Systems and methods for duty cycle measurement, analysis and compensation

Abstract

Circuit (100) containing a data path (610, 710), wherein the circuit further contains: a first measuring circuit (630A) which contains a first resistor-capacitor circuit, RC circuit, and is designed to acquire first duty cycle measurements (141A) from the data path (610, 710); and a second measuring circuit (630N) which contains a second RC circuit and is designed to acquire second duty cycle measurements (141N) from the data path (610, 710); wherein the first RC circuit and the second RC circuit share a capacitor (660); wherein the first measuring circuit (630A) and the second measuring circuit (630N) are coupled communication-wise with different positions (612A, 612N, 712A, 712N) along the data path (610, 710), so that a difference between the first duty cycle measurements (141A) and the second duty cycle measurements (141N) corresponds to a duty cycle deterioration along the data path (610, 710); wherein the first duty cycle measurements (141A) include voltage potentials at the first RC circuit, while the first RC circuit is coupled communication-wise to a first position (612A, 712A) along the data path (610, 710), and wherein the second duty cycle measurements (141N) include voltage potentials at the second RC circuit, while the second RC circuit is communicatively coupled to a second position (612N) along the data path (610, 710), the second position (612N, 712N) being different from the first position (612A, 712A); and wherein the circuit further includes a control circuit arrangement (632A, 632N) designed to selectively connect the shared capacitor (660) to one of the first positions (612A, 712A) along the data path (610, 710) and the second position (612N, 712N) along the data path (610, 710).

Description

Technical field

[0001] This disclosure relates to the reduction of duty cycle errors and in particular to systems and methods for duty cycle measurement, analysis and / or compensation. background

[0002] Memory interface circuits can be susceptible to duty cycle distortion. As used here, "duty cycle distortion" refers to a change in the duty cycle of a signal as the signal propagates through the circuit (for example, as the signal travels along a path). Duty cycle distortion can lead to input / output errors. For example, duty cycle distortion can cause input / output errors such as pulse widths of a high and / or low pulse signal that do not meet the timing requirements of a high pulse width (tQSH) and / or low pulse width (tQSL). Increasing input / output clock speeds (I / O clock speeds) and lower input / output voltage potentials and / or currents can lead to lower tolerances, so that even small duty cycle distortions can result in I / O errors.

[0003] Conventional duty cycle calibration circuits may be unable to scale down to operate at required clock frequencies and may be unable to detect internal duty cycle distortion introduced by the circuitry itself. Furthermore, a conventional duty cycle calibration circuit may require periodic recalibration, which can adversely affect performance. Internal duty cycle distortion can be caused by a number of different factors that may not be known at design time (e.g., manufacturing defects, process variations, and the like). Therefore, internal duty cycle distortion may need to be measured by field testing the manufactured device at frequencies exceeding the capabilities of conventional built-in test circuits.Measuring internal duty cycle distortion can be even more complex, as duty cycle distortion in input signals can be reflected in such measurements. Therefore, systems and methods for duty cycle measurement, analysis, and / or compensation are needed to accurately quantify and compensate for duty cycle distortion resulting from internal signal propagation. These systems and methods must be unaffected by input signal distortion, not adversely impact high-speed timing requirements, and require minimal additional effort in terms of size, performance, and / or energy consumption.

[0004] US 2009 / 0177457A1 concerns a method and a system for modeling and calibrating duty cycle distortions. Brief description of the drawings Fig. Figure 1A is a schematic block diagram of an embodiment of a duty cycle measurement circuit. Fig. Figure 1B is a schematic block diagram of an embodiment of an interface circuit arrangement that includes a duty cycle measurement circuit arrangement. Fig. 2A shows timing diagrams of exemplary timing and data output signals. Fig. 2B shows timing diagrams of exemplary timing and data output signals. Fig. Figure 3 is a simplified schematic block of an embodiment of a duty cycle measurement circuit arrangement. Fig. Figure 4A is a schematic block diagram of another embodiment of the duty cycle measurement circuit arrangement. Fig. Figure 4B is a schematic block diagram of an embodiment of a signal generator for duty cycle measurement and / or analysis. Fig. Figure 5A is a schematic block diagram of an embodiment of a duty cycle measurement circuit arrangement. Fig. Figure 5B is a schematic block diagram of another embodiment of a duty cycle measurement circuit arrangement. Fig. Figure 5C is a schematic block diagram of another embodiment of a duty cycle measurement circuit arrangement. Fig. Figure 5D is a schematic block diagram of another embodiment of a duty cycle measurement circuit arrangement. Fig. Figure 6A is a schematic block diagram of an embodiment of a data path that includes a duty cycle measurement circuit. Fig. Figure 6B is a schematic block diagram of an embodiment of a duty cycle measurement circuit arrangement designed to acquire differential duty cycle measurements. Fig. Figure 7 is a schematic block diagram of another embodiment of a data path that includes a duty cycle measurement circuit arrangement. Fig. Figure 8A is a schematic block diagram of another embodiment of a data path that includes a duty cycle measurement circuit arrangement. Fig. Figure 8B is a schematic block diagram of another embodiment of a duty cycle measurement circuit arrangement designed to acquire differential duty cycle measurements. Fig. Figure 9 is a schematic block diagram of an embodiment of a system for duty cycle measurement, analysis and / or compensation. Fig. Figure 10 is a flowchart of an embodiment of a method for duty cycle measurement, analysis and / or compensation. Fig. Figure 11 is a flowchart of a further embodiment of a method for duty cycle measurement, analysis and / or compensation. Fig. Figure 12 is a flowchart of a further embodiment of a method for duty cycle measurement, analysis and / or compensation. Detailed description

[0005] According to the invention, a circuit, semiconductor devices, a method and a system with the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0006] This document discloses embodiments of systems, methods, circuits, devices, and arrangements for duty cycle measurement, analysis, and / or compensation. It also discloses embodiments of a circuit containing a data path. The circuit may include a first measuring circuit designed to acquire initial duty cycle measurements from the data path and a second measuring circuit designed to acquire subsequent duty cycle measurements. The first and second measuring circuits may be communicatively coupled at different positions along the data path, such that a difference between the initial and subsequent duty cycle measurements corresponds to a duty cycle degradation along the data path.The first measuring circuit can be communicatively connected to a first position along the data path, where the first position is designed such that the first duty cycle measurements correspond to an input duty cycle. The second measuring circuit can be communicatively connected to a second position along the data path, where the second position is designed such that the second duty cycle measurements correspond to an output duty cycle. The data path can include an input circuit arrangement, and the first measuring circuit can be communicatively connected to the input circuit arrangement. The data path can also include a data output circuit arrangement, and the second measuring circuit can be communicatively connected to the data output circuit arrangement.

[0007] The circuit may further include a control circuit arrangement designed to connect either the first or the second measurement circuit to an output array. A test device may receive the duty cycle measurements through the output array, including first and second duty cycle measurements. The test device may further include a duty cycle degradation measurement along the data path using the received duty cycle measurements and a duty cycle matching parameter for the data path based on the duty cycle degradation measurement. The circuit may further include a duty cycle matching circuit arrangement designed to adjust the duty cycle of an oscillating signal propagating through the data path based on the determined duty cycle matching parameter.

[0008] The first measurement circuit can contain a first resistor-capacitor circuit (RC circuit), and the measurement circuit can contain a second RC circuit. The first duty cycle measurements can include voltage potentials across the first RC circuit, which is communicatively coupled to a first position along the data path. The second duty cycle measurements can include voltage potentials across the second RC circuit, which is communicatively coupled to a second position along the data path. The first and second RC circuits can share a capacitor.The circuit may further include a control circuit arrangement designed to selectively connect the shared capacitor to either the first position along the data path or the second position along the data path. The control circuit arrangement may include a first switch comprising a metal-oxide-semiconductor transistor (MOS transistor) with a source terminal connected to the first position along the data path, a drain terminal connected to the shared capacitor via a first resistor, and a gate terminal coupled to a first enable signal.The control circuit arrangement may include a second switch containing a metal oxide semiconductor transistor (MOS transistor) with a source terminal connected to the second position along the data path, a drain terminal connected to the shared capacitor via a second resistor, and a gate terminal coupled to a first enable signal.

[0009] This document discloses embodiments of a semiconductor device comprising a data output circuit arrangement with a timing path, wherein the data output circuit arrangement is configured to transmit a clock signal along the timing path from an input region to an output region. The semiconductor device may further comprise a duty cycle measurement circuit arrangement configured to measure a duty cycle error associated with the timing path. The duty cycle measurement circuit arrangement may be configured to determine an input duty cycle metric corresponding to a duty cycle of the timing signal in the input region of the timing path and an output duty cycle metric corresponding to a duty cycle of the timing signal in the output region of the timing path.A difference between the input duty cycle metric and the output duty cycle metric can contain a measure of the duty cycle error associated with the time setpoint path.

[0010] The duty cycle measurement circuit arrangement can be configured to acquire differential duty cycle measurements, which may include an input duty cycle metric and an output duty cycle metric, and to supply the differential duty cycle measurements to a diagnostic device. The diagnostic device can be configured to determine a duty cycle adjustment to correct the degree of duty cycle error associated with the timing path using the differential duty cycle measurements. The diagnostic device can be configured to write the determined duty cycle adjustment to a memory location in the semiconductor device. The semiconductor device can further include a duty cycle correction circuit configured to implement the determined duty cycle adjustment written to the memory location.

[0011] The duty cycle measurement circuit arrangement can include an accumulator circuit with an input node and an output node. The input duty cycle metric can correspond to the charge accumulated at the output node while the input node is coupled to the input range of the time-delay path, and the output duty cycle metric can correspond to the charge accumulated at the output node while the input node is coupled to the output range of the time-delay path.

[0012] In some embodiments, the duty cycle measurement circuitry includes an RC circuitry with an input connected to a capacitive element of the RC circuitry via a resistive element of the RC circuitry, and a control circuitry for selectively connecting the input of the RC circuitry to either the input region of the timer path or the output region of the timer path. The input duty cycle metric can correspond to a voltage potential across the capacitive element while the input of the RC circuitry is connected to the input region of the timer path. The output duty cycle metric can correspond to a voltage potential across the capacitive element of the RC circuitry while the input of the RC circuitry is connected to the output region of the timer path.The capacitive element may contain a node connected to a generator, and the duty cycle measurement circuit arrangement may be designed to selectively disable the generator.

[0013] Embodiments of the duty cycle measurement circuit arrangement may include a first capacitor and a second capacitor. The input duty cycle metric may correspond to a voltage potential across the first capacitor, while the first capacitor is connected via a first control circuit arrangement to a first digit on the time set path, the first digit being within the input range of the time set path. The output duty cycle metric may correspond to a voltage potential across the second capacitor, while the second capacitor is coupled to a second digit on the time set path, the second digit being within the output range of the time set path. In some embodiments, the first capacitor and the second capacitor may include a common capacitive element.The first control circuit arrangement can be configured to selectively connect the first location on the timing path to the common capacitive element, and the second control circuit arrangement can be configured to selectively connect the second location on the timing path to the common capacitive element. The input duty cycle metric can correspond to a voltage potential across the common capacitive element while the common capacitive element is connected to the first location of the timing path and disconnected from the second location of the timing path. The output duty cycle metric can correspond to a voltage potential across the common capacitive element while the common capacitive element is connected to the second location of the timing path and disconnected from the first location of the timing path.

[0014] Embodiments of methods for duty cycle measurement, analysis, and / or compensation are disclosed herein. Embodiments of the disclosed methods may include acquiring first measurements corresponding to the duty cycle of an input signal propagating along a data path. Acquiring the first measurements may include connecting an input of an RC circuit arrangement at a first propagation distance within the data path, wherein the input is connected to receive a first time-varying signal corresponding to the propagation of the input signal along the first propagation distance within the data path, and acquiring first voltage potential measurements at an output of the RC circuit arrangement while the input of the RC circuit arrangement is connected at the first propagation distance along the data path.

[0015] The method may further include acquiring second measurements corresponding to the duty cycle of the input signal as it propagates along the data path. Acquiring the second measurements may involve connecting the input of the RC circuit arrangement at a second propagation distance along the data path, the input being connected to receive a second time-varying signal corresponding to the propagation of the input signal over the second propagation distance within the data path, the second propagation distance being greater than the first, and acquiring second voltage potential measurements at the output of the RC circuit arrangement while the input of the RC circuit arrangement is connected at the second propagation distance along the data path.Embodiments of the method may further include determining a duty cycle correction for the data path based on differences between the first voltage potential measurements and the second voltage potential measurements.

[0016] Herein are disclosed embodiments of a system for duty cycle measurement, analysis and / or compensation.Embodiments of the disclosed systems may include: means for measuring a first voltage potential across a capacitor while an input of the capacitor is connected to a first point along a data path of the data output circuit arrangement, wherein the first point has a first oscillating signal that is generated in response to the propagation of a signal from an input into the data path to the first point along the data path; and means for measuring a second voltage potential across the capacitor while the input of the capacitor is connected to a second point along the data path of the data output circuit arrangement, wherein the second point has a second oscillating signal that is generated in response to the propagation of the signal from the input into the data path to the second point along the data path, the second point being different from the first point.The disclosed system may further include means for determining a duty cycle correction for the data path, wherein the duty cycle correction corresponds to a difference between the first voltage potential and the second voltage potential.

[0017] Fig. Figure 1A is a simplified schematic representation of a circuit 100 containing an interface circuit arrangement 101. The interface circuit arrangement 101 can be implemented on a semiconductor 102, which may contain a chip, a bare chip, a package, and / or the like. The interface circuit arrangement 101 can be communicatively connected to a memory circuit arrangement, which may be designed, among other things, to write data to non-volatile memory cells, read data from the non-volatile memory cells, and / or the like (in Fig. (Figure 1A not shown to avoid obscuring details of the illustrated embodiments). The interface circuit arrangement 101 may include a data input / output circuit, a data input / output path circuit, a data output path circuit, a data output path, a signal path, a timing path, and / or the like. The interface circuit arrangement 101 may have a path 110 comprising an input area 111 and an output area 117.

[0018] The input section 111 of path 110 may contain a circuit arrangement designed, among other things, to receive external input signals that may contain one or more time-varying and / or oscillating signals, including, but not limited to: timing signals, clock signals, read enable signals, differential signals, inverse timing signals, data strobe signals, and / or the like. The input section 111 may further contain a circuit arrangement designed to propagate a signal 114 corresponding to the inputs through path 110 (through the input section 111 towards the output section 117). Signal 114 can correspond to an external input signal (e.g., a timing signal, a clock signal, a read enable signal, an inverse or differential timing signal, an inverse or differential clock signal, and / or the like), a test stimulus (e.g., test signals), and / or the like.The interface circuit arrangement 101 can use the signal 114 to generate an output signal 118 (at the output region 117 of path 110). As used here, the "propagation" of a signal 114 can include: a) transmitting the signal 114 along path 110 (so that the signal 114 flows from the input region 111 towards the output region 117), b) processing and / or manipulating the signal 114, c) deriving one or more other signals from the signal 114, and / or the like. Accordingly, the propagation of a signal 114 can, without limitation, include: amplifying the signal 114, filtering the signal 114, buffering the signal 114, splitting the signal 114, trimming the input signal 114, adjusting a duty cycle of the signal 114, shifting the signal 114, delaying the signal 114, repeating the signal 114 and / or the like.The interface circuit arrangement 101 can include any suitable means for propagating a signal 114 along the path 110, which may, without restriction, include: traces, semiconductor traces, signal traces, conductors, semiconductor layers, conductive and / or insulating layers, conductor tracks, signal traces, vias, contact points, wires, channels, buses, intermediate connections and / or the like.The path 110 may further include means for manipulating, processing and / or deriving signals from the signal 114, which may, without limitation, include: an amplifier circuit arrangement, a differential circuit arrangement, a differential amplifier circuit arrangement, a delay circuit arrangement, a repeater circuit arrangement, a driver circuit arrangement, a buffer circuit arrangement, an intermediate interconnect circuit arrangement, a switching circuit arrangement, a routing circuit arrangement, an on-chip termination (ODT) circuit arrangement, a signal generator circuit arrangement, an oscillator circuit arrangement and / or the like.

[0019] As disclosed above, the signal 114 may contain a time-varying and / or oscillating signal with a duty cycle 115. As used here, the “duty cycle” 115 of a signal 114 refers to the fraction of time during which the signal 114 is in a particular state. The “state” of a signal 114 may refer to a voltage potential of the signal 114 and / or a logical interpretation of the signal 114 (e.g., the fraction of time for which a signal is interpreted as a logical “1” compared to a logical “0”). Alternatively or additionally, the state of the signal 114 may refer to a threshold voltage potential (e.g., the fraction of time for which a signal is above a certain voltage potential threshold compared to the time for which the signal is below the threshold). In the embodiment of Fig. 1A can refer to the duty cycle of signal 114 as the time during which the input signal 114 is in a high state (t) during a specific cycle. H ) compared to a low state (t L ). As used here, t refers to H the time during which a signal is interpreted as high (e.g., as a logical "1") during a cycle, and t L refers to the time during which the signal is interpreted as disabled (e.g., as a logical "0") during the cycle. As used here, t can therefore H refer to the width of the high pulse of a signal and t L can refer to a width of the low pulse of the signal, such that t H + t L of period t p of the signal corresponds to (t H + t L = t p ).

[0020] In the input area 111 of path 110, the signal 114 can be an input signal 114IN with an input duty cycle (D IN ) and an input duty cycle distortion (ΔT IN ) contain and / or correspond to it. The input signal 114IN can correspond to an external input signal received at the input range 111 and / or a test signal generated within the circuit 110 (as disclosed in more detail here). The input signal 114IN can be substantially free of duty-rate distortion, such that t H ≥ t L during their respective cycles (and ΔT) IN near zero). Alternatively, and as in Fig. Figure 1A shows that the input signal 114IN can have an initial input duty cycle distortion (ΔT). IN exhibit.

[0021] As disclosed above, the interface circuit arrangement 101 can be configured to propagate the signal 114 along the path 110. The duty cycle of the signal 114 can be distorted when the interface circuit arrangement 101 propagates the signal 114 along the path 110. At points near the input region 111, the signal 114 may be essentially unchanged. At points further along the path 110, the signal 114 may be distorted, resulting in a degradation of the duty cycle 115 and / or an increased duty cycle distortion 116. Fig. Figure 1A shows exemplary signals 114 at various propagation points and / or positions 112 within the interface circuit arrangement 101 (along the path 110). The propagation points 112 can correspond to respective propagation distances and / or offsets 113 within the path 110. As used here, a "propagation point", "path point", "location", "propagation position", "path position", and / or "position" 112 refers to a specific location along and / or within the path 110 of the interface circuit arrangement 101 (e.g., a circuit arrangement that includes and / or lies between the input region 111 and the output region 117 of the path 110).A path location 112 can refer to a specific position along and / or within signal communication means of path 110, such as a cable, a signal trace, an intermediate linking circuit arrangement, a switching circuit arrangement, a routing circuit arrangement, a driver circuit arrangement, a read circuit arrangement, and / or the like. Alternatively or additionally, a path location 112 can refer to the propagation of the signal 114 by signal processing and / or signal manipulation means of path 110, which may include, without limitation: buffer circuit arrangement, ODT circuit arrangement, signal processing circuit arrangement (e.g., differential amplifier circuit arrangement), duty cycle matching circuit arrangement 108, data output circuit arrangement, and / or the like.As used herein, a “propagation distance”, “path distance”, “distance”, “propagation offset”, “path offset”, and / or “offset” 113 refers to the propagation of a signal 114 over a certain distance along or within, or through, the path 110. A propagation distance 113 may refer to the communication of a signal 114 between two different positions or locations 112 along and / or within the path 110 as disclosed herein (e.g., transmission of the signal 114 by a signal communication and / or signal processing means of the path 110). Accordingly, a propagation distance 113 may refer to the communication of a signal 114 as well as to the processing and / or manipulation of the signal 114 (and / or the derivation of one or more other signals 114 from it) within the path 110.

[0022] Fig. 1A shows a signal 114A at a location 112A along path 110. Location 112A may be near the input region 111 of the interface circuit arrangement 101. In some embodiments, the signal 114A may include the signal 114IN (e.g., an input signal such as an external input signal received via an ODT circuit arrangement, a test input signal, and / or the like). Location 112A may be configured such that the duty cycle of the signal 114A at location 112A is substantially equal to the duty cycle of the input signal 104 (has not degraded during propagation along path 110 of the interface circuit arrangement 101). Location 112A may lie within a propagation distance threshold that may correspond to a propagation distance 113, which does not lead to significant changes in the duty cycle of signal 114. Fig. 1A can have a duty cycle of 115 (D A) of signal 114A at point 112A essentially equal to the duty cycle (D IN ) of the signal 114IN (e.g., a nominal duty cycle distortion of 116 ΔT may be A containing values ​​that are essentially equivalent to ΔT IN is).

[0023] Fig. Figure 1A further shows an exemplary signal 114B, which represents the signal 114 after propagation to a position 112B along the path 110 of the interface circuit arrangement 101. The duty cycle distortion 116 (ΔT) B The intensity of signal 114B increased during propagation along the reproductive distance 113B (e.g., ΔT). B > ΔT A and ΔT IN ). The additional duty cycle distortion (ΔT) B - ΔT A) can occur during the propagation of signal 114 from location 112A to location 112B along path 110 of the interconnection circuit arrangement. The exemplary signal 114N represents signal 114 after propagation to location 112N (propagation distance 113N). Location 112N can be within and / or near the output area 117 of path 110, and therefore the duty cycle 115 (D N ) and / or the duty cycle distortion 116 (ΔT N ) of signal 114N are essentially equal to the duty cycle 115 and / or the duty cycle distortion 116 of signal 114, which is used to generate the one or more output data signals 118. Therefore, the duty cycle 115 (D N ) and the duty cycle distortion 116 (ΔT N ) of signal 114N at position 112N as the output duty cycle (D OUT ) and the output duty cycle distortion (ΔT OUT) of path 110 and / or interface circuit arrangement 101. The output duty cycle distortion 116 ΔT OUT can correspond to the propagation of signal 114 to a propagation offset 113N (e.g. from the input area 111 and / or position 112A to the output area 117 and / or position 112N along the data path 110).

[0024] As revealed above, signal 114N can be used to generate data output signals 118 through the interface circuit arrangement 101. The interface circuit arrangement 101 can use signal 114N as an output timing signal (e.g., an output clock) to generate a data strobe output (DQS and / or an inverse signal such as #DQS or BDQS) and / or the like. The duty cycle distortion 116 (D N and / or D OUTHowever, a change at position 114N can cause the data output signal 118 to fail to meet time constraints (e.g., tQSH and / or tQSL). Fig. Figure 2A is a graph 200A representing an example time-delay signal 114A (and an inverse time-delay signal #114A) used to generate data strobe output signals DQS 218A and BDQS #218A. The time-delay signal 114A can be equal to the initial input signal 114IN (before additional duty cycle distortion occurs during propagation along path 110). As shown in graph 200A, the duty cycle 215A of signal 114A (D A ) D IN correspond and the duty cycle distortion 216A (ΔT A ) can ΔT IN correspond (and are essentially 0). Thus, t H and t Lof signal 114A would be essentially the same. If the interface circuit arrangement 101 were to use signal 114A (and #114A) to generate data output signals 118 (DQS and BDQS), the minimum duty cycle distortion 116 (ΔT) would be A ≥ ΔT IN ≥ 0) enable DQS 218A and BDQS #218A, which result, to satisfy time constraints such as tQSMin 230, which provide a minimum pulse width for t H or t L can define. As shown in Graph 200A, the widths of the high and low pulses tQSH 228A and tQSL 229A respectively of DQS 218A and BDQS #218A, corresponding to signal 114A, are essentially equivalent and satisfy the constraint 230 tQSMin.

[0025] Graph 200B of Fig. 2B shows signal 114N, which can correspond to the propagation of signal 114 to location 112N (along the propagation distance 113N). The duty cycle 215N (D N ≈ ΔT OUTThe signal 114N can be distorted during propagation from point 112A to point 112N (propagation distance 113N) along path 110 of the interface circuit arrangement 101. The duty cycle distortion 216N (ΔT N ≈ ΔT OUT ) can lead to t H significantly shorter than t L The signal 114N can be used to generate data output signals DQS 218N and BDQS #218N using a circuit arrangement embodied in the output area 117 of path 110. The duty cycle distortion 116N (ΔT N The deviation of signal 114N (and #114N) can cause the tQSH and / or tQSL of the resulting DQS signals 218A and / or BDQS signals #218N to violate the tQSMin 230 constraint. As in Fig. 2B at 231 shows that tQSH 228N of DQS 218N and tQSL of #DQS 218N at 231 do not satisfy the constraint parameter tQSMin 230, which can lead to data input / output errors.

[0026] With renewed reference to Fig. 1A The interface circuit arrangement 101 can include a duty cycle matching circuit arrangement 108, which may be designed, among other things, to adjust and / or trim the duty cycle of the signals 114 during the propagation of such signals 114 within the interface circuit arrangement 101 (e.g., along the path 110). As disclosed above, the extent of duty cycle adjustment and / or trimming required to compensate for duty cycle degradation along the path 110 may vary based on factors not known at design time (e.g., process variations, manufacturing variations, defects, and / or the like). Although the duty cycle calibration circuit arrangement may be able to adjust for duty cycle distortion in external input signals, such a circuit arrangement may not be able to detect and / or compensate for duty cycle distortion that occurs during the propagation of signal 114 (e.g.,along path 110 of the interface circuit arrangement 101 itself). In addition, the duty cycle calibration circuit arrangement can be costly, may have operating frequency limitations (e.g., it may not be scaled down to operate at sufficiently high clock rates), may cause significant additional design and performance effort, and may adversely affect performance (due to the need for periodic recalibration).

[0027] The circuit 100 may include a duty cycle measurement circuit 130, which may be designed to obtain duty cycle measurements within the path 110. These measurements can be used to quantify the extent of duty cycle degradation experienced by the signal 114 as it propagates through the interconnection circuit arrangement 101 (along the path 110). The duty cycle measurements can be used to determine a duty cycle matching factor and / or trim factor, which can be used to compensate for the actual measured duty cycle degradation that occurs in the manufactured circuit 100 (after duty cycle testing and analysis of the circuit 100). The circuit 100 may further include a duty cycle matching circuit arrangement 108, which may be designed to implement one or more duty cycle matching operations based, among other things, on the duty cycle matching and / or duty factor determined for the circuit 100.The duty cycle matching parameter can be stored and / or recorded in the circuit 100. In some embodiments, the duty cycle matching factor and / or trim factor can be recorded in a read-only memory (ROM) of the interconnection circuit arrangement 101 (e.g., in a ROM fuse of the duty cycle matching circuit arrangement 108).

[0028] The duty cycle measurement circuit 130 can be configured to a) obtain duty cycle measurements 141 corresponding to the duty cycle of the signal 114 at various points 112 along the path 110, and b) supply the duty cycle measurements 141 to a diagnostic device 160. The diagnostic device 160 can use the duty cycle measurements 141, among other things, to determine the duty cycle degradation occurring in the circuit 100 and / or to configure the duty cycle matching circuit arrangement 108 of the circuit for compensation. The diagnostic device 160 can include a computing device with a processor, storage memory, non-transient memory, human-machine interface components (e.g., display, input devices), communication interface(s), and / or the like.The diagnostic device 160 can be connected to the circuit 100 via any suitable means of communication, including but not limited to a data bus, a memory interface, a dedicated test interface, one or more probes, one or more input / output fields, one or more input / output pins and / or the like.

[0029] In some embodiments, the duty cycle measuring circuit 130 is designed to obtain duty cycle measurements 141 from two (or more) different locations 112 and / or propagation distances 113 along the path 110. Fig. In 1A, the duty cycle circuit 130 is designed to obtain duty cycle measurements 141A and 141N. The duty cycle measurements 141A can correspond to the duty cycle of the signal 114A at location 112A (after propagation distance 113A along path 110). The duty cycle measurements 141N can correspond to the duty cycle of the signal 114N at location 112N (after propagation distance 113N along path 110). As disclosed above, location 112A can be at and / or near the input region 111, and location 112N can be at and / or near the output region 117 of the interconnection circuit arrangement 101. Therefore, the duty cycle (D A ) and / or the duty cycle degradation (ΔT) A ) of the input signal 114A (if present) essentially equivalent to the input duty cycle (D IN ) and / or the input duty cycle degradation (ΔT IN ) be, so that D A ≈ D IN and ΔT A ≈ ΔT INThe duty cycle (D) N ) and / or the duty cycle degradation (ΔT) N ) of signal 114N at position 112N can determine the output duty cycle (D OUT ) and / or the initial duty cycle degradation (ΔT) OUT ) contain and / or correspond to this, so that D N ≈ D OUT and ΔT N ≈ ΔT OUT .

[0030] As in Fig. Figure 1A shows that the differential duty cycle measurements 151 (measurements 141A and 141N) can be compared to obtain a measure of a) the duty cycle error (ΔD). E_PATH ), which is assigned to path 110, and / or b) the duty cycle distortion error (ΔT) E_PATH ), which is assigned to path 110. The duty cycle error (ΔD) E_PATH ) can represent a measure of the change in the duty cycle of signal 114 as signal 114 propagates through the input region 111 to the output region. The duty cycle distortion error (ΔT) E_PATH) can represent a measure of the change in duty cycle distortion in signal 114 as signal 114 propagates through the input region 111 to the output region. The measures of ΔD E_PATH and Δ TE_PATH can therefore result in a difference and / or a comparison between a) duty cycle measurements corresponding to input range 111 (where D IN ≈ D A and ΔT IN ≈ ΔT A ), and b) duty cycle measurements corresponding to output range 117 (where D OUT ≈ D N and ΔT OUT ≈ ΔT N ) correspond to, correspond to. Accordingly, ΔD can E_PATH and ΔT E_PATH as follows: ΔDE_PATH=DOUT−DIN≈DN−DA≈fD(141N)−fD(141A) ΔTE_PATH=ΔTOUT−ΔTIN≈ΔTOUT−ΔTIN≈fΔT(141N)−fΔT(141A)

[0031] In Eq. 1, f D and f ΔTConversion functions between the duty cycle measurements 141 of duty cycle (D) and duty cycle distortion (ΔT), respectively. As disclosed in further detail herein, in some embodiments the duty cycle measurements 141 may include measurements of a voltage potential (VM) corresponding to a voltage potential that contains: accumulated voltage potential while the signal 114 is in a high state (while the signal 114 is at the high voltage potential V). H lies), and is discharged while signal 114 is in a low state (while signal 114 is at the low voltage potential V) H lies). In such embodiments, f D and f ΔT Functions are included to measure the voltage potential (V). M ) to convert into duty cycle and duty cycle distortion measurements as follows: D=VREF−VMVREF ΔT=|tp2−(D∗tp)|or|tp2−((VREF−VMVREF)∗tp)|

[0032] In equation 2, VREF a difference between V H and V L and t p The period of signal 114 is [missing value]. Although certain techniques for acquiring duty cycle measurements are disclosed herein, the disclosure is not limited in this respect and could be adapted to acquire duty cycle measurements using any suitable measurement technique and / or methodology.

[0033] As disclosed above, the duty cycle error within path 110 can be characterized by differences and / or comparisons between duty cycle measurements 141A and 141N, corresponding to different respective path locations 112 and / or propagation distances 113. Accordingly, the duty cycle measurements 141A and 141N can be referred to as differential duty cycle measurements 151. As used here, “differential duty cycle measurements” and / or “differential duty cycle metrics” refer to duty cycle measurements 141 and / or metrics corresponding to different path locations 112 and / or propagation distances 113. Differential duty cycle measurements 151 (e.g., measurements 141A and 141N) can be used to measure the internal duty cycle error (ΔD). E_PATH ) and / or the internal duty cycle distortion error (ΔT) E_PATH) to determine which are characterized as being substantially independent of the distortion, variance, and / or instability of the input duty cycle (the distortion, variance, and / or instability of the duty cycle in the one or more signals 114 used to acquire the duty cycle measurements 141). As disclosed above, the signal 114 may contain an initial and / or input duty cycle distortion (denoted in this example as X). The differential duty cycle measurements 151 both contain this initial duty cycle distortion X. The duty cycle measurements 141A corresponding to digit 112A will contain a duty cycle distortion (ΔT). A) exhibit approximately X and / or correspond to it (e.g., due to the fact that location 112A lies within and / or near the input region 111 of path 110). The propagation of signal 114 to output region 117 (e.g., to path location 112N via propagation distance 110) introduces an additional duty-rate distortion in signal 114. As disclosed above, this additional duty-rate distortion is the duty-rate distortion error of path 110 (ΔT). E_PATH ). Accordingly, the duty cycle measurements 114N, which are recorded at location 112N, will show a duty cycle distortion (ΔT). N ) exhibit and / or correspond to this, which is a sum of the input duty cycle distortion X and the path duty cycle distortion error (ΔT) E _ PATH ) contains such that ΔT N ≈ ΔT OUT = X + ΔT E_PATH If only one set of duty cycle measurements were used to determine ΔT E_PATHTo characterize it, the resulting characterization would be inaccurate (e.g., it would incorrectly assign the initial duty cycle distortion X to path 110, so that ΔT E_PATH = ΔT E_PATH + X). The use of such a characteristic during operation can lead to data input / output errors if this characteristic is applied to signals 114 that are not distorted (e.g., do not have the initial distortion X). The use of differential duty cycle measurements 151 can avoid such inaccuracies. As disclosed above, the measure of ΔT E_PATH for path 110 using differential duty cycle measurements 151 (e.g. a difference and / or a comparison between measurements 141A and 141N) such that ΔT E_PATH ≈ ΔT OUT - ΔT IN , where ΔT IN ≈ ΔT A and ΔT OUT ≈ ΔT INThe differential duty cycle measurements 151 (measurements 141A and 141N) both include the initial duty cycle distortion X, such that ΔT IN ≈ ΔT A = X and ΔT OUT ≈ ΔT N = ΔT E_PATH + X. Therefore, the initial duty cycle X is determined from the characterization of ΔT. E_PATH for route 110 away; ΔT E_PATH ≈ (ΔT N + X) - X, such that ΔT E_PATH ≈ ΔT N .

[0034] The duty cycle measurement circuit 160 can transmit the measurements 141A and 141N to the diagnostic device 160, which can use the duty cycle measurements 141A and 141N to configure the interface circuit arrangement 101 to compensate for the duty cycle degradation measured along path 110. In some embodiments, the diagnostic device 160 determines a duty cycle fault characteristic (DCDC) 164 of the interface circuit arrangement 101. The DCDC 164 can quantify the extent of duty cycle degradation in the signal 114, while the interface circuit arrangement 101 forwards the signal 114 along path 110 (e.g., from the input region 111 to the output region 117). The DCDC 164 can calculate a difference and / or compare duty cycle measurements 141A, which are located at point 112A (where D A ≥ D IN and ΔT A ≥ ΔT IN) are obtained, and duty cycle measurements 141N, which are located at point 112N (where D N ≥ D OUT and ΔT N ≥ ΔT OUT ) are obtained, contained. Alternatively or additionally, the DCDC 164 can change the duty cycle of signal 114 during propagation along path 110 (e.g., ΔD). E_PATH ) and / or a change in the duty cycle deterioration during reproduction along path 110 (ΔT E_PATH ) quantify, as revealed above.

[0035] In some embodiments, the diagnostic device 160 is designed to measure duty cycle metrics DCM. A 162A and DCM N 162N to be determined according to the duty cycle measurements 141A and 141N, respectively. The DCM A 162A may contain and / or correspond to the following: the duty cycle measurements 141A, which are recorded at location 112A, duty cycle measurements (D A) of signal 114A at position 112A, a high duty cycle pulse of signal 114A at position 112A (D A_H or t A_H ), a low duty cycle pulse of signal 114A at position 112A (D A_L or t A_L ), a duty cycle degradation measured at point 112A, (ΔT A ) and / or the like. The DCM N 162N may contain and / or correspond to the following: the duty cycle measurements 141N, which are recorded at location 112N, a duty cycle (D N ) of signal 114N at position 112N, a high duty cycle pulse at position 112N (D N_H , or t N_H ), a low duty cycle pulse at position 112A (D N_L or t N_L ), a duty cycle degradation of signal 114N at location 112N (ΔT N ) and / or the like.

[0036] The DCDC 164 intended for the interface circuit arrangement 101 can be based on a difference and / or a comparison between the DCM A 162A and the DCM N 162N is based on the DCDC 164, which can detect a difference between the duty cycle measurements 141A and 141N, a duty cycle change along the path 110 of the intermediate connection circuit arrangement 101 (e.g., Δ DE_PATH , where ΔD E_PATH ≈ ΔD A-N = D A -D N is), an error of the high duty cycle pulse (e.g. ΔD H_PATH , where ΔD H_PATH ≈ ΔD H_A-N = D H_A- D H_N is), a low duty cycle pulse error (e.g. ΔD L_PATH , where ΔD L_PATH ≈ ΔD L_A-N = D L_A -D L_N is) or a duty cycle degradation along the path 110 of the intermediate connection arrangement 101 (e.g. ΔT E_PATH , where ΔT E_PATH ≈ ΔT A-N = ΔT N -ΔT A is).

[0037] The diagnostic device 160 can further be configured to determine duty cycle correction data 166 for the path 110. The duty cycle correction data 166 can be adapted to configure the duty cycle matching circuit arrangement 108 to correct a specific duty cycle error (ΔD). E_PATH ) and / or duty cycle distortion error (ΔT) E_PATH ) of path 110 (as characterized by the DCDC 164 designated for path 110) is compensated. The duty cycle correction data 166 may contain configuration data designed to configure the duty cycle matching circuit arrangement 108 to implement duty cycle corrections during operation of the circuit. The duty cycle correction data 166 may be designed to configure the duty cycle matching circuit arrangement 108 to process and / or manipulate signals 114 during propagation within path 110 (e.g., adjusting and / or trimming the duty cycle of the signals 114 to achieve ΔDE_PATH and / or ΔT E_PATH to compensate for the effects that occur when the signals 114 propagate along the path 110). The duty cycle correction data 166 may, without limitation, include: a duty cycle matching setting, a duty cycle matching parameter, duty cycle matching rules, a lookup table, firmware, configuration data, code and / or other information designed to configure the duty cycle matching circuit arrangement 108 to implement duty cycle corrections within the path 110.

[0038] The duty cycle correction data 166 can contain one or more duty cycle codes corresponding to discrete duty cycle adjustment settings and / or trim settings that can be implemented by the duty cycle adjustment circuit arrangement 108. In some embodiments, the duty cycle adjustment circuit arrangement 108 can be configured to implement duty cycle trim operations with a specific granularity (e.g., in 10 ps steps or the like). The duty cycle correction data 166 can indicate a number of such adjustments to be applied to the signals 114 during propagation through path 110 (e.g., N settings such that the duty cycle is adjusted by N*10 ps). The duty cycle correction data 166 can define a range of duty cycle correction operations, with each operation corresponding to respective operating conditions (e.g., respective operating temperatures, wear levels and / or the like).The duty cycle correction data 166 can be designed to configure the duty cycle matching circuit arrangement 108 to compensate for the measured DCDC 164 of the circuit 100 under each of the specified operating conditions.

[0039] The diagnostic device 160 can be configured to program, store, and / or record the duty cycle correction data 166 within the circuit, the semiconductor 102, the duty cycle matching circuit arrangement 108, the duty cycle measurement circuit arrangement 130, the memory (not shown), and / or the like. In some embodiments, the diagnostic device 160 is configured to record the duty cycle correction data 166 in a register, a ROM fuse, and / or another memory location accessible to the duty cycle matching circuit arrangement 108.

[0040] As revealed above, the differential duty cycle measurements 151 (including measurements 141N and / or 141A), the duty cycle metrics DCM A 162A, DCM N162N, DCDC 164, and the duty cycle correction data 166 correspond to field testing of the interface circuit arrangement 101 as manufactured on the semiconductor 102 and can therefore account for process variations (and / or other factors) that cause duty cycle distortion in the interface circuit arrangement 101. Accordingly, the duty cycle measurement circuit 130 can provide accurate duty cycle analysis and compensation without requiring a complex, costly duty cycle calibration circuit arrangement that can interfere with high-speed signal timing.Using a difference and / or comparison between duty cycle measurements 141 obtained at different locations and / or positions 112 along the path 110 of the interface circuit arrangement 101 to determine the DCDC 164 and / or the duty cycle correction data 166, in contrast to deriving these quantities from duty cycle measurements 114 acquired at a single location 112 along the path 110, can ensure that the DCDC 164 and / or duty cycle correction data 166 are accurate regardless of noise and / or duty cycle degradation (ΔTIN), variance and / or instability in the signal 114.

[0041] In some embodiments, the duty cycle measurement circuit arrangement 130 acquires the duty cycle measurements 141A and 141N, among other things, by providing test inputs to the interface circuit arrangement 101. The test inputs may include a test input, a data signal, and / or the like. The test input signal may be generated by a signal generator 131. The signal generator 131 may include an oscillator, an ODT circuit arrangement, an external oscillator, and / or the like. The test inputs may also include test output data, which may be designed to enable accurate duty cycle measurements (e.g., a data pattern designed to minimize jitter, such as an "FF" data pattern). The duty cycle circuit arrangement 130 can further be designed to acquire duty cycle measurements 141A and 141N while the test inputs are applied to the interface circuit 101, and the acquired duty cycle measurements 141 (e.g.141A and 141N) to transmit to the diagnostic device 160. The duty cycle circuit arrangement 130 can transmit the duty cycle measurements 141A and 141N using any suitable communication mechanism, including, without limitation, an input / output field, input / output pins, a communication bus, a register (or other memory location), a bus register, and / or the like.

[0042] In some embodiments, the diagnostic device 160 may be configured to perform duty cycle analysis operations. These duty cycle analysis operations may be performed during the initial testing and / or validation of the manufactured duty cycle circuit assembly 101 (e.g., during chip sorting tests). The diagnostic device 160 may include a chip sorting test device (DS test device). The diagnostic device 160 may be equipped with one or more probes, input / output fields, input / output pins, a dedicated test interface, and / or the like (in Fig. (1A not shown to avoid confusion of the details of the illustrated embodiments) be coupled to the circuit 100 in terms of communication technology. The diagnostic device 160 can implement a duty cycle analysis operation by, among other things: a) supplying test input signals to the circuit 100 and / or configuring the circuit 100 to generate the test input signals, b) configuring the duty cycle circuit 130 to obtain duty cycle measurements 141 (including duty cycle measurements 141A corresponding to position 112A and duty cycle measurements 141N corresponding to position 112N), and c) comparing the duty cycle measurements 141A and 141N to determine a DCDC 164 for path 110 of the interface circuit arrangement 101. If the DCDC 164 is above a threshold, the duty cycle analysis operation can further include configuring the duty cycle matching circuit arrangement 108 to compensate for the determined DCDC 164.The diagnostic device 160 can provide test input signals by configuring the signal generator 131 to generate a test input signal for propagation along the path 110 and configuring the duty cycle measurement circuit arrangement 130 to acquire duty cycle measurements 141A and 141N while the test input signal is being generated. The threshold can be based, among other things, on timing constraints of the interface circuit arrangement 101, matching and / or trimming capabilities of the duty cycle matching circuit arrangement 108 (e.g., a matching and / or trimming granularity), and / or the like.

[0043] The duty cycle measuring circuit 130 can be configured to acquire the duty cycle measurements 141, among other things, by selectively coupling the measuring circuit arrangement with the path 110 of the intermediate connection circuit arrangement 101 (e.g., connecting the duty cycle measuring circuit arrangement to locations 112A and / or 112N along the path 110). When connected to location 112A, the duty cycle measuring circuit 130 can acquire duty cycle measurements 141A corresponding to the duty cycle (DA) of the signal 114A at location 112A, and when connected to location 112N, the duty cycle measuring circuit 130 can acquire duty cycle measurements 141N corresponding to the duty cycle (DN) of the signal 114N at location 112N. In some embodiments, the duty cycle measuring circuit 130 is designed to obtain duty cycle measurements 141A and 141N simultaneously.In such embodiments, the duty cycle measuring circuit 130 can have a duty cycle measuring circuit arrangement designed to acquire duty cycle measurements 141A and 141N at locations 112A and 112N in parallel (e.g., containing separate independent connections to locations 112A and 112N respectively within the path 110). Alternatively, the duty cycle measurement circuit 130 can be configured to obtain duty cycle measurements 141A and 141N separately (e.g., to obtain duty cycle measurements 141A while connected to path 110 at location 112A and disconnected from location 112N, and to obtain duty cycle measurements 141N while connected to path 110 at location 112N and disconnected from location 112A). The duty cycle measurement circuit 130 can be configured to obtain multiple duty cycle measurements 141 at each location 112A and 112N (e.g., multiple duty cycle measurements 141A and 141N, respectively).

[0044] In some embodiments, the duty cycle measurement circuit 130 may be configured to perform one or more duty cycle measurement operations, each of which may include: a) applying a specified input signal 104 to the input area 111 of the interconnection circuit arrangement 101, b) acquiring a specified number of duty cycle measurements 141 from each of one or more designated positions 112 along the path 110 of the interconnection circuit arrangement 101 while the specified input signal 104 is applied (e.g., positions 112A and 112N), c) determining one or more characteristics of the duty cycle measurements 141 (e.g., an average, a deviation, a variance, and / or the like), and so on. The duty cycle measurement operations can be encoded in one or more logic circuits, state machine circuits, firmware, configuration data and / or the like.Alternatively or additionally, the duty cycle measurement operations and / or the operation of the duty cycle circuit arrangement 130 can be carried out by separate test and / or diagnostic circuits (in . Fig. 1A not shown to avoid obscuring the details of the embodiments shown) and / or the diagnostic device 160 is managed.

[0045] Fig. Figure 1B is a schematic block diagram of another embodiment of a circuit 100, which includes an intermediate connection circuit arrangement 101 with a path 110. In the embodiment of Fig. 1B includes the interface circuit arrangement 101 and an ODT circuit 122, which can be configured for external input signals. The ODT circuit 122 can further be configured to generate a test input signal 105. The test input signal 105 can be generated by an oscillator and / or another circuit arrangement embodied on the semiconductor 102. The ODT circuit 122 can be configured to generate the test input signal 105 with a specific frequency, period, and duty cycle (D). OSC ), duty cycle degradation (ΔT OSC ) and / or the like. The characteristics of the test input signal 105 generated by the interface circuit arrangement 101 can be known and / or verified (e.g., by testing the manufactured interface circuit arrangement 101). Therefore, D OSC and / or ΔT OSC The test input signal 105 must be known.

[0046] The circuit 100 may further include a duty cycle measurement circuit 130, which may be designed to acquire duty cycle measurements 141 at one or more locations 112 within the path 110. The duty cycle measurement circuit 130 may be designed to acquire the duty cycle measurements 141N while the ODT 122 generates the test input signal 105 and / or while the test input signal 105 is coupled to the input area 111 of the path 110. The duty cycle measurements 141N may be obtained from the location 112N, which may have a signal 114N. The signal 114N may propagate the test input signal 105 (with known D OSC and / or ΔT OSC ) to point 112N within data path 110 (around reproductive distance 113N). Accordingly, the duty cycle measurements 141N can correspond to the duty cycle metrics DCM. N 162N, which without restriction correspond to and / or may contain the following: the duty cycle of signal 114N (D N≈ D OUT ), a high duty cycle pulse of signal 114N (D H_N ≈ D H_OUT ), a low duty cycle pulse of signal 114N (D L_N ≈ D L_OUT ), a duty cycle degradation of signal 114N (ΔT N ≈ ΔT OUT ) and / or the like. The duty cycle degradation characteristics of the interface circuit arrangement 101 can be determined by comparing the known characteristics of the test input signal 105 with the duty cycle measurements 141N (and / or the corresponding DCM). N 162N). As in Fig. Figure 1B shows a duty cycle error characteristic for the interface circuit arrangement 101 (ΔD E_PATH ) by comparing the duty cycle (D N ) of signal 114N with the known duty cycle (D OSC ) of the test input signal 105 can be determined (e.g. ΔD E_PATH ≈ D OSC-N = D N -D OSC). A duty cycle degradation for the interface circuit arrangement 101 (ΔT E_PATH ) can be determined by comparing duty cycle degradation (ΔT) N ) of signal 114N at location 112N with the known duty cycle degradation (ΔT OSC ) of the test input signal 105 can be determined (e.g. ΔT E_PATH ≈ ΔT OSC-N = ΔT N - ΔT OSC ).

[0047] The duty cycle measurement circuit 130 can be configured to supply the duty cycle measurements 141N to a diagnostic device 160, which can use the duty cycle measurements 141N to determine a DC-DC converter 164 and / or duty cycle correction data 166 for the interface circuit arrangement 101. The DC-DC converter 164 can be determined, as disclosed herein, by comparing the duty cycle measurements 141N with known characteristics of the test input signal 105. The duty cycle correction data 166 can be determined to configure the duty cycle matching circuit arrangement 108 to compensate for the determined DC-DC converter 164, as disclosed herein. The duty cycle correction data 166 can be designed to configure the duty cycle matching circuit arrangement 108 such that the measured DCDC 164 is compensated within the path 110 (e.g. the determined measurements of ΔD). E_PATH and / or ΔT E_PATH as revealed here).

[0048] The duty cycle measurement circuit 130 disclosed herein can be configured to acquire duty cycle measurements 141 using any suitable circuit, mechanism, and / or technique. The duty cycle measurement circuit 130 can be configured to measure the duty cycle of signals propagating within the interface circuit arrangement 101 using a duty cycle-to-voltage (DCV) circuit arrangement. Fig. Figure 3 is a schematic block diagram of an embodiment of a simplified DCV circuit 330. The in Fig. The DVC circuit 330 shown in Figure 3 can include an input circuit arrangement 332 and an accumulator circuit arrangement 340. The input circuit arrangement 332 can be configured to selectively connect the DVC circuit 330 to a location and / or position 112 within the interface circuit arrangement 101 (e.g., at a specific distance and / or offset 113 along the path 110). In some embodiments, the input circuit arrangement 332 can include a switching and / or routing circuit arrangement configured to communicatively couple and / or decouple the accumulator circuit arrangement 340 with selected locations 112 along the path 110 of the interface circuit arrangement 101.The input circuit arrangement 332 can be configured to selectively connect the accumulator circuit arrangement 340 to the data path 110 at positions 112 located at respective ends of the path 110. The input circuit arrangement 332 can be configured to couple the accumulator circuit arrangement 340 to a first position 112 located at, in, and / or near the input region 111 of the path 110 (e.g., position 112A) and / or a second position 112 located at, in, and / or near the output region 117 of the path 110 (e.g., position 112N). The input circuit arrangement 332 can include a switch. Connecting the DVC circuit 330 to path 110 may involve activating and / or closing the switch, and disconnecting the DVC circuit 330 from path 110 may involve deactivating and / or opening the switch.

[0049] The accumulator circuit arrangement 340 can include any suitable circuit arrangement for accumulating a charge and / or voltage potential corresponding to the duty cycle of a time-varying and / or oscillating signal 314. The signal 314 can include a time-specified signal (e.g., signal 114) with a high state at an input / output voltage potential (VCCQ) and a low state at V0. VCCQ can be between approximately 1.2 V and 1.8 V. In the embodiment of Fig. The accumulator circuit arrangement 340 contains a resistor 350 and a capacitor 360 (a resistor-capacitor circuit (RC circuit)). The signal 314 can contain a signal 114 at a selected location 112 along the path 110 (e.g., signal 114A at location 112A, signal 114N at location 112N, or the like). Accordingly, the signal 314 can have a duty cycle 315 (D or t). H +t L) and a corresponding duty cycle distortion 316 (ΔT, t H -1 / 2t p exhibit.

[0050] Fig. Figure 3 further contains a graph 301 showing exemplary voltage potentials at the accumulator circuit arrangement 340 in response to the signal 314 (e.g., charge at the capacitor 360 when coupled to a selected point 112 along the data path 110). Graph 302 shows a corresponding current flow into and out of the accumulator circuit arrangement 340 during t H or t L of signal 314 (I H and I L The accumulator circuit arrangement 340 can have an RC characteristic that can correspond to a settling time of the signal. The accumulator circuit arrangement 340 can be configured such that its RC characteristic is significantly larger than the period of the signal 314 (e.g., RC >> t). H + t LWhen connected to a receiving signal 314, the accumulator circuit arrangement 340 stabilizes itself such that the time t H corresponding charge Q H essentially the time t L corresponding charge Q L corresponds to (e.g. Q) H = |Q L | as shown in Graph 302). Accordingly, the current flow into and out of the accumulator circuit arrangement 340 will be essentially balanced: QH=lH∗tH=|QL|=|lL∗tL|

[0051] Based on Eq. 3, the voltage potential VDU 341 at the output node 349 of the DVC 330 can be expressed as a function of t. H and t L of signal 314 (the duty cycle 315 of signal 314) can be expressed as follows: VDUR*tH=VCCQ−VDUR*tL

[0052] According to Eq. 4, the duty cycle characteristics of signal 314 can be determined from the voltage potential VDU 341 at output node 349 as follows: DH=tH(tH+tL)=VCCQ−VDUVCCQ;DL=1−DH,tH=DH∗tp;tL=tp−tH,ΔTH=tp2−tH;ΔTL=tp2−tL

[0053] As illustrated above, the duty cycle 315 of signal 314 can be determined by: a) supplying signal 314 to the accumulator circuit arrangement 340 (via the input circuit arrangement 332) and b) measuring the voltage potential VDU 341 at an output node 349 (after a stabilization time, which may correspond to the RC value of the accumulator circuit arrangement 340 and / or the period of signal 314). As shown in Fig. As shown in Figure 3, the voltage potential VDU 341 at the output node 349 can exhibit a certain degree of variance after the stabilization time (due, among other things, to the oscillation of signal 314, jitter, noise, variability of the input signal, and / or the like). Accordingly, determining the duty cycle of signal 314 may involve implementing one or more error reduction techniques, which, without limitation, include: acquiring multiple voltage measurements VDU 341 corresponding to signal 314 (e.g., N measurements of V). DU 341); Determining an average, mean and / or median of the voltage potential of the N measurements; Determining a variance and / or deviation of the N measurements; Discarding outlier measurements of the N measurements; and / or the like.

[0054] The stabilization time of the accumulator circuit arrangement 340 can correspond to its RC characteristic (e.g., the product of the resistance value of resistor 350 and the capacitance of capacitor 360). The accumulator circuit arrangement 340 can be designed such that the RC characteristic is significantly larger than the period of signal 314 (RC >> t). H + t L ). Signal 114 (received at signal 314 in Fig. 3) can correspond to a timing signal with a period of approximately 1.875 ns. The accumulator circuit arrangement 340 can provide an RC value of approximately 1.518 × 10 -6 have, which can correspond to a resistance of 134.4 kOhms and a capacitance of 11.3 pF (and is significantly larger than 1.875 × 10 -9Although certain examples of the accumulator circuit arrangement 340 and corresponding RC characteristics are described here, the disclosure is not limited in this respect and could be adapted to use any suitable accumulator circuit arrangement 340 with any suitable RC characteristic (using suitably dimensioned resistive and / or capacitive elements) that may be suitable for measuring the duty cycle of signals 314 with any suitable frequency and / or period.

[0055] The duty cycle measuring circuit 130, which is in Fig. The device shown in 1A and / or 1B may contain one or more DVC circuits 330. The diagnostic device 160 can configure the duty cycle measurement circuit 130 to acquire differential duty cycle measurements 151, which may include acquiring duty cycle measurements relating to the output range 117 (e.g., duty cycle measurements 141N corresponding to position 112N) and / or acquiring duty cycle measurements relating to the input range 111 (e.g., duty cycle measurements 114A corresponding to position 112A). Configuring the duty cycle measurement circuit arrangement 130 to acquire duty cycle measurements 141N may include configuring the duty cycle measurement circuit arrangement 130 for the following: a) connecting the DVC circuit 330 to location 112N along path 110 and b) measuring V DU341 at the output node 349 of the DVC 330, while one or more test input signals are driven along path 110. Configuring the duty cycle measurement circuit arrangement 130 to acquire the duty cycle measurements 141a may include configuring the duty cycle measurement circuit arrangement 130 for the following: a) connecting the DVC circuit 330 to point 112A along path 110 and b) measuring V DU 341 at the output node 349 of the DVC 330, while one or more test input signals are driven along path 110. The diagnostic device 160 can further configure the duty cycle measurement circuit arrangement 130 to transmit the duty cycle measurements 141A and 141N to it, as disclosed herein. In some embodiments, the diagnostic device 160 can directly acquire the measurements (e.g., the output node 349, which V DU341, which is connected to an input / output field and / or channel accessible by the diagnostic device 160). The diagnostic device 160 can analyze the duty cycle measurements 141A and / or 141N to determine if duty cycle degradation occurs during signal propagation along path 110. The diagnostic device 160 can compare the duty cycle measurements 141A and 141N to determine if path 110 has duty cycle errors. As disclosed above, duty cycle degradation can be caused by a number of different variable factors, such as manufacturing defects, process variations, and / or the like. Therefore, the duty cycle degradation along path 110 can vary in different manufacturing and / or fabrication processes of path 110. In some cases, path 110 within the manufactured circuit 100 may not exhibit any significant deterioration in duty cycle.If the duty cycle measurements (and / or the corresponding metrics 162A and / or 162N) differ by more than a threshold, the diagnostic device 160 can determine that path 110 exhibits duty cycle degradation. Otherwise, path 110 can be considered to have no duty cycle degradation. As disclosed above, the granularity threshold of the duty cycle adjustment operations and / or trimming operations that can be performed by the duty cycle adjustment circuit arrangement 108 can correspond to the timing requirements of the interface circuit arrangement 101 and / or the like. The diagnostic device 160 can use the duty cycle measurements 141A and 141N to determine a DCDC 164 for the interface circuit arrangement 101 and / or duty cycle correction data 166 to correct the determined DCDC 164.The diagnostic device 160 can further be designed to record the duty cycle correction data 166 as disclosed herein on the circuit, the semiconductor 102 and / or the duty cycle matching circuit arrangement 108.

[0056] Fig. Figure 4A is a schematic block diagram of another embodiment of a circuit 100, which includes a data output circuit arrangement 401 with a signal path 410. The data output circuit arrangement 401 can be embodied in a circuit structure 102, which may include a semiconductor structure, a semiconductor wafer, a chip, a bare chip, a package, a storage device, a memory chip, a memory assembly, and / or the like. The signal path 410 can include a circuit arrangement designed to pass a signal 114, such as a timing signal, through the data output circuit 401 (e.g., from the input area 111 to the output area 117).

[0057] In the embodiment of Fig. The signal path 410 can contain several sections 420, each containing an input section 420A and an output section 420N. The data output circuit arrangement 401 can be configured to propagate a signal 114 along a signal path 410 in response to receiving an input 104 (at the input section 420A) and can use the signal 114 to generate data output signals 118 (at the output section 420N). The input section 420a can contain an ODT circuit arrangement 422 and an input receiver circuit arrangement 424. The ODT circuit arrangement 422 can be configured to receive external input signals 404 (e.g., input signals 104 originating from outside the circuit structure 102). Alternatively or additionally, the ODT circuit arrangement 422 can be configured to receive and / or generate the test input signal 105. in the embodiment of Fig. 4A the ODT circuit arrangement 422 includes a signal generator 131 which, as disclosed here, can be designed to generate test input signals 105 for use in analyzing the duty cycle characteristics of the data output circuit 401.

[0058] The input area 420a may further include an input receiver circuit arrangement 424, which may be configured to receive an input signal 104 from the ODT circuit arrangement 422 and propagate a corresponding signal 114 along the signal path 410. The input receiver circuit arrangement 424 may be configured to process and / or manipulate the signal 114 (e.g., buffering the signal 114, filtering the signal 114, amplifying the signal 114, and / or the like). Alternatively or additionally, the input receiver circuit arrangement 424 may derive one or more internal signals from the signal 114 (e.g., it may include a differential circuit to derive an inverse of the signal 114).

[0059] The data output area 420N can include a circuit arrangement designed to generate a data output signal 118 using signal 114 (e.g., signal 414N within the output area 420N). The data output area 420N can also include a data strobe circuit arrangement 462, which can be designed to generate data output signals 118 containing output data. The output data can correspond to data stored in memory and / or data that can be accessed using memory circuitry (not shown to avoid obscuring the details of the disclosed embodiments). Alternatively or additionally, the output data can include test output data, for example, a "FF" data pattern.The data output section 420N may include a data sampling circuit designed to encode the output data as one or more data strobe signals (DQS signals) and / or inverted or differential data strobe signals (BDQS signals). Generating the DQS and / or BDQS signals may involve combining the output data with signal 114 (e.g., signal 114N propagating to output section 420N). A DQS and / or BDQS data signal can contain a combination of the output data and signal 114 (and / or an inversion thereof), such that the output data is encoded as respective data and strobe signals with the property that only either the data signal or the strobe signal can change its state during a given cycle of the timing signal (e.g., signal 114N).A logical combination of the resulting data and strobe signals can lead to the reconstruction of the time signal used to generate the strobe signals (e.g., to the reconstruction of signal 414N by a logical XOR combination of the data and strobe signals). Accordingly, the duty cycle (D. N ) and / or the duty cycle distortion (ΔT) N ) of signal 114N at path point 112A or propagation distance 113N determine the timing characteristics of the output data 118. Therefore, the duty cycle (D N ) and / or the duty cycle distortion (ΔT) N ) of signal 114N at path point 112A or propagation distance 113N the output duty cycle (D OUT ) and / or the output duty cycle distortion (ΔT) OUT ) of signal path 410 and / or correspond to it.

[0060] The circuit 400 can include a duty cycle measurement circuit 130, which can be configured to acquire differential duty cycle measurements 151, including duty cycle measurements 141A and 141N at respective locations 412A and 412N along the signal path 410 (and / or propagation offsets 413A and 413N) as disclosed herein. The duty cycle measurement circuit 130 of the embodiment of Fig. 4A can contain a test controller 440, a first measurement circuit 430A, and a second measurement circuit 430N, and / or be communicatively coupled to them. The first measurement circuit 430A can be configured to acquire duty cycle measurements 141A corresponding to location 412A along the signal path 410. Location 412A can be located within the input area 420A of the signal path 414 (and at a propagation distance 413A from the input area 111 of the signal path 410). Location 412A can correspond to the input receiver circuit arrangement 424 (and / or an output thereof). Accordingly, the duty cycle (D A ) and / or the duty cycle distortion (ΔT) A ) of signal 414A at position 412A of an initial or input duty cycle (D IN ) and / or duty cycle distortion (ΔT) IN ) for duty cycle measurement operations on signal path 410.

[0061] The second measuring circuit 430N can be configured to acquire duty cycle measurements 141N corresponding to location 412N along the signal path 410. Location 412N can be located within the output range 420N of the signal path 410 (at the propagation distance 413N along the signal path 410). Location 412N can correspond to the data strobe circuit arrangement 462 (and / or an output thereof). Accordingly, the duty cycle (D N ) and / or the duty cycle distortion (ΔT) N ) of signal 414N at position 412N the output duty cycle (D OUT ) and / or the output duty cycle distortion (ΔT) OUT ) for duty cycle measurement operations on signal path 410.

[0062] The test controller 440 can be communicatively coupled to a diagnostic device 160. The test controller 440 can be communicatively coupled to the diagnostic device 160 using any suitable means disclosed herein. In the embodiment of Fig. 4A The test controller 440 can be communicatively coupled to the diagnostic device 160 via a test interface 443, among other things. The test interface 443 can contain a circuit arrangement for transmitting signals to and / or from the semiconductor 102 and / or the circuit 100. The test interface 443 can contain, without limitation: one or more ODT circuits, one or more probes, one or more input / output fields, one or more input / output pins, one or more input / output wires, one or more semiconductor vias, and / or the like. The test interface 443 can be configured to receive command signals 161 from the diagnostic device 160 and / or to transmit the differential duty cycle measurements 151 (e.g., the duty cycle measurements 141A, 141N, and / or other information) to the diagnostic device 160.The command signals 161 can configure the duty cycle measurement circuit 130 for the following: acquiring duty cycle measurements 141 (e.g., differential duty cycle measurements 151 including measurements 141A and 141N); performing duty cycle measurement operations; coupling the first measurement circuit 430A and / or the second measurement circuit 430N to the signal path 410 to acquire duty cycle measurements 141 from it; coupling the output node 349, which is the V. DU -voltage potential 341, with one or more input / output fields (e.g. probe 443) to enable, among other things, the diagnostic device 160 to obtain duty cycle measurements 141 directly from an output node 349 from the first measuring circuit 430A and / or the second measuring circuit 430N; configuring the signal generator 131 to generate test input signals 105; and / or the like.

[0063] The test interface circuit arrangement 443 can be configured to route and / or control internal signals 445 corresponding to the command signals 161. The internal signals 445 can include enable signals, disable signals, configuration signals (e.g., duty cycle correction data 166), and / or the like. The internal signals 445 can be used to configure elements of the circuit 100 to perform duty cycle measurement operations and / or analysis operations, as disclosed herein.

[0064] The command signals 161 can configure the circuit 100 to perform a duty cycle measurement and / or analysis operation, which may include: a) applying a test stimulus to signal path 410, b) configuring the first measurement circuit 430A to obtain first duty cycle measurements 141A corresponding to location 412A (and / or propagation distance 413A) while the test stimulus is applied to signal path 410 (and / or after a settling time since the applied stimulus), c) configuring the second measurement circuit 430N to obtain second duty cycle measurements 141N corresponding to location 412N (and / or propagation distance 413N) while the test stimulus is applied to signal path 410 (and / or after a settling time since the applied test stimulus), and / or the like.Applying the test stimulus to signal path 410 may involve configuring the ODT circuit arrangement 422 for the following: a) generating a test input signal 105, which may include forming internal signals 445 designed to cause the signal generator 131 to generate the test input signal 105; b) configuring the ODT circuit arrangement 422 to use the test input signal 105 as an input 104 for the signal path (and / or to isolate signal path 410 from one or more external input signals 404); c) configuring the output circuit arrangement to supply test output data to the output area 420N (e.g., a "FF" data pattern); and so on.Configuring the first measuring circuit 430A to acquire the first duty cycle measurements 141a may include generating internal signals 445 designed to: a) cause the first measuring circuit 430A to be connected to the path point 412A, b) route the signal 414A at the path point 412A to the accumulator circuit arrangement 340 thereof, and / or c) acquire one or more measurements 141A of the voltage potential V. DU341 at the output node 349 thereof (and / or supplying one or more measurements 141A to the diagnostic device, including by sending the measurements 141A to the diagnostic device, coupling a probe circuit arrangement to the output node 349 of the first measuring circuit 430A and / or the like).Configuring the second measuring circuit 430A to acquire the second duty cycle measurements 141N may include generating internal signals 445 designed to: a) cause the second measuring circuit 430N to be connected to the path point 412N, b) route the signal 414N at the path point 412N to the accumulator circuit arrangement 340, and / or c) acquire one or more measurements 141N of the voltage potential VDU 341 at the output node 349 thereof (and / or supply the one or more measurements 141N to the diagnostic device, including by sending the measurements 141A to the diagnostic device, coupling a probe circuit arrangement to the output node 349 of the first measuring circuit 430N, and / or the like).

[0065] Alternatively or additionally, the Testcontroller 440 can be designed to manage duty cycle measurement operations and / or analysis operations. The test controller 440 can be configured to activate internal signals 445 to configure the circuit 100 for the following: acquiring first duty cycle measurements 141A (using the first measuring circuit 430A), acquiring second duty cycle measurements 141N (using the second measuring circuit 430N), and transmitting the acquired duty cycle measurements 141 (e.g., 141A and 141N) to the diagnostic device 160. The test controller 440 can be configured to obtain a predetermined number of duty cycle measurements 141 at specific points 112 along the signal path 410, to process the duty cycle measurements 141 (e.g., to determine statistical properties of the duty cycle measurements 141), and so on.In these embodiments, the test controller 440 may contain a control circuit, a logic circuit, a state machine circuit arrangement, firmware, configuration data and / or the like.

[0066] The first measurement circuit 430A may include a DVC circuit 330 as disclosed herein. Acquiring the first duty cycle measurements 141a may therefore include: a) configuring the input circuit arrangement 332 of the first measurement circuit 430A to connect the accumulator circuit arrangement 340 to the path node 412A such that the accumulator circuit arrangement 340 receives the signal 414A, which propagates within the input area 420a of the signal path 410; and b) acquiring measurements 141A, which may include measurements of the voltage potential (VDU) 341 at the output node 349 of the accumulator circuit arrangement 340 (after stabilization of the accumulator circuit arrangement 340). The test controller 440 may be configured to take multiple duty cycle measurements 141A (five or more measurements of V). DU341) to obtain, to determine characteristics of the recorded measurements 141A, to process the recorded measurements 141A (e.g. to discard outliers of the recorded measurements 141A) and so forth, as disclosed herein.

[0067] The second measuring circuit 430N can include a DVC circuit 330, as disclosed herein. Acquiring the second duty cycle measurements 141N can therefore include: a) configuring the input circuit arrangement 332 of the second measuring circuit 430N to connect the accumulator circuit arrangement 340 to the path node 412N, so that the accumulator circuit arrangement 340 receives the signal 414N, which propagates within the output area 420b of the signal path 410; and b) acquiring measurements 141N, which may include measurements of the voltage potential (VDU) 341 at the output node 349 of the accumulator circuit arrangement 340 (after stabilization of the accumulator circuit arrangement 340). The test controller 440 can be designed to perform multiple duty cycle measurements 141N (e.g., five or more measurements 141N of U). DU341) to obtain, to determine characteristics of the recorded duty cycle measurements 141N, to process the recorded measurements 141N (e.g. to discard outliers of the recorded measurements 141N) and so forth, as disclosed herein.

[0068] In some embodiments, the first measuring circuit 430A and the second measuring circuit 430N are designed to obtain duty cycle measurements 141A and 141N essentially simultaneously (e.g., the first measuring circuit 430A can be communicatively coupled to the signal path 410 at point 412A to obtain duty cycle measurements 141A, while the second measuring circuit 430N is communicatively coupled to the signal path 410 at point 412N to obtain duty cycle measurements 141N). Alternatively, the first measuring circuit 430A and the second measuring circuit 430N can be designed to obtain duty cycle measurements separately (e.g., the first measuring circuit 430A can be disconnected from the signal path 410, while the second measuring circuit 430N is connected to the signal path 410 to obtain duty cycle measurements 141N, and vice versa).In some embodiments, the first measuring circuit 430A and the second measuring circuit 430N share one or more resistive and / or capacitive elements (e.g., they are designed as a single DVC circuit 330, sharing a capacitive element and / or the like).

[0069] In some embodiments, the test controller 440 may be configured to analyze the measurements 141A and 141N, which may include: comparing the measurements 141A and 141N and using the measurements 141A and 141N to determine a measure of the DCDC 164 of the signal path 410, determining duty cycle correction data 166 for the measured DCDC 164, and / or configuring the duty cycle matching circuit arrangement 108 to compensate for the measured DCDC 164 (e.g., by generating duty cycle correction data 166 to configure the circuit 100 to compensate for the measured duty cycle errors within the path 410). Alternatively or additionally, the duty cycle measurements 141 may be analyzed in the diagnostic device 160.The test controller 440 can transmit the duty cycle measurements 141 to the diagnostic device 160, which can use the duty cycle measurements to determine the DC-DC converter 164 of the signal path 410 and / or derive corresponding duty cycle correction data 166, as disclosed herein. The test controller 440 can further be configured to receive duty cycle correction data 166 from the diagnostic device 160 and / or to configure the duty cycle matching circuit arrangement 108 to use the duty cycle correction data 166 during operation of the circuit 100.

[0070] As disclosed above, acquiring the duty cycle measurements 141 and / or the differential duty cycle measurements 151 (measurements 141A and 141N) may involve configuring the ODT circuit arrangement 422 to generate a test input signal 105 and / or coupling the test input signal 105 to the signal path 410 (using one or more internal signals 445). Fig. Figure 4B is a schematic block diagram showing an embodiment of a signal generator 131, which can be configured to selectively generate test input signals 105 and / or to couple such test input signals 105 to the signal path 410 as disclosed herein. The signal generator 131 can be used in the ODT circuit arrangement 422 of Fig. 4A (and / or the ODT circuit arrangement 122 of Fig. 1B). Alternatively, the signal generator 131 can be embodied separately (e.g., as a component of the duty cycle test circuit 130, as shown in Fig. (as shown in Figure 1A). The signal generator 131 can include an oscillator circuit 431, which can be configured to generate a test input signal 105. The test input signal 105 can have a duty cycle 115 (D OSC ) and a duty cycle distortion (ΔT) OSCThe output of the oscillator circuit 431 can flow to a logic circuit arrangement 432, which can configure the drive circuit arrangement 434 to selectively drive the output node 439 of the generator 131 with the test input signal 105, among other things, based on internal signals 445, including a MON_EN signal 435 and an ODT_EN signal 436. When the MON_EN signal 435 is activated, the logic circuit arrangement 432 causes the drive circuit arrangement 434 to drive the output node 439 with the test input signal 105 (using PMOS and NMOS transistors connected between VCCQ and V0 via resistors R1 and R2). When the MON_EN signal 435 is activated, the ODT circuit arrangement 422 may further be configured to output the test output signal 105 for propagation along the data path 410 instead of the one or more external signals 404 thereby received.

[0071] With renewed reference to Fig. 4A can contain the first measuring circuit arrangement 430A and / or the second measuring circuit 430N a DVC circuit 330. The in Fig. The DVC circuit 330 shown in Figure 3 may be prone to measurement errors, including those caused by voltage fluctuations, inconsistent source current and / or voltage, and / or the like. Fig. Figure 5A shows another embodiment of a DVC circuit 330, which can be designed to acquire very accurate duty cycle measurements 141. The DVC circuit 330 of Fig. 5A can include a control circuit arrangement 532 and an accumulator circuit arrangement 534. In some embodiments, the control circuit arrangement 532 includes the routing circuit arrangement 534 and / or is communicatively coupled to it. The routing circuit arrangement 534 can be configured to selectively route a signal 314 to the input node 531 of the DVC 330, which, as disclosed herein, can include selectively connecting the input node 531 to one or more designated path points 112 within the intermediate connection circuit arrangement 101 and / or the data output circuit arrangement 401. Alternatively, the connection to the path point 112 can be controlled by transistors 535 and 536.

[0072] The control circuit arrangement 532 can include a control circuit arrangement for selectively connecting (and disconnecting) the input node 531 and the accumulator circuit arrangement 540 with a designated path point 112 based on internal signals 445, including a MON_EN signal 435 (and its inverse, the #MON_EN signal 436). The control circuit arrangement 532 can connect the input node 531 to the accumulator circuit arrangement 540 via transistors 535 and 536. The gate of the first transistor 535 can be coupled to the MON_EN signal 435, and the gate of the second transistor 536 can be coupled to the #MON_EN signal 436. When the MON_EN signal 435 is enabled (and the #MON_EN signal 436 is disabled), the input node 531 can be connected to waypoint 112 to receive the signal 314 on it (through the routing circuit arrangement 534).The signal 314 can flow to the accumulator circuit arrangement 540 and generate a voltage potential V. DU 341 generate at the output node 349. The accumulator circuit arrangement 540 can include an RC circuit comprising resistive and capacitive circuits. In the embodiment of Fig. In 5A, the accumulator circuit arrangement 540 comprises a resistor 550 and a capacitor 560. A first terminal of the capacitor 560 can be coupled to the voltage potential V0 (e.g., via a common node, a ground node, a VDD node, and / or the like). A second terminal of the capacitor 560 can be coupled to the output node 349 of the DVC 330 and the resistor 550. Accordingly, when the MON_EN signal 435 is enabled (and the #MON_EN signal 436 is disabled), the signal 314 can be received at the second terminal of the capacitor 560 via the resistor 550.

[0073] As revealed above, when the accumulator circuit arrangement 540 receives the signal 314, the voltage potential V DUThe duty cycle of signal 314 at output node 349 corresponds to a duty cycle of signal 314. Duty cycle measurements corresponding to signal 314 can therefore be obtained by accumulating the voltage potential VDU 341 at output node 349, while the accumulator circuit arrangement 540 is communicatively coupled to path 112 to receive signal 314 (e.g., communicatively coupled to path 110, data path, signal path 410, and / or the like, as disclosed herein). The accumulator circuit arrangement 540 can have an RC characteristic that may correspond to its resistance and / or capacitance (e.g., the resistance value of resistor 550 and the capacitance of capacitor 560). The accumulator circuit arrangement 540 can be designed such that its RC value is greater than the period of the signal 314 received thereby (e.g., significantly greater than the period of the signal 314, so that RC >> t p or tH +t L Signal 314 can correspond to signal 114 within path 110, signal path 410, and / or the like. Therefore, signal 314 can contain a time-delay signal, a clock signal, a read-enable signal, a difference signal, an inverse time-delay signal, an inverse clock signal, an inverted read-enable signal, and / or the like. Signal 314 can have one period (t). p ) of approximately 1.875 ns (e.g. t p = t H +t L = 1.875 ns). The accumulator circuit arrangement 540 of the DVC 330 can be designed such that its RC value is significantly larger than t p (e.g., significantly larger than 1.875 ns). In the embodiment of Fig. At 5A, the 550 resistor can have a resistance value of approximately 134.4 kOhms and the capacitor can have a capacitance of approximately 11.3 pF, which corresponds to an RC value of approximately 1.518 × 10 -6 This corresponds to something significantly larger than 1.875 × 10 -9 (the tp of signal 314). The use of a high resistance value in resistor 550 can allow the size of transistors 535 and 536 to be reduced (partly due to the relatively low currents flowing within DVC 330), which can reduce the additional effort in design, power consumption, and / or latency of the duty cycle measurement circuit 130. In the embodiments of Fig. 5A and Fig. 5B, the transistors 535 and / or 536 can have a design size of approximately 5 to 10 µm, and the duty cycle circuit 130 can have a design size of approximately 25 × 10 µm.

[0074] Although specific examples of DVC circuits 330 incorporating an accumulator circuit arrangement 340 with specific RC values ​​are described here, the disclosure is not limited in this respect and could be adapted to use any suitable type of accumulator circuit arrangement 340 for acquiring duty cycle measurements 141 corresponding to signals with any suitable frequency and / or period (having any suitable RC value, including, but not limited to, using suitably configured resistive and / or capacitive elements).

[0075] As revealed here, the voltage potential at output node 349 can correspond to the duty cycle of signal 314. Accordingly, duty cycle measurements 141, corresponding to the duty cycle of signal 314, can be obtained by measuring the voltage potential V DU341 is acquired at the output node 349, while the signal 314 is received in the accumulator circuit arrangement 540 (via the control circuit arrangement 532 and / or the routing circuit arrangement 534). As disclosed above, acquiring the duty cycle measurements 141 can be acquiring one of several measurements of the voltage potential V DU 341 is included, while the signal 314 is received in the accumulator circuit arrangement 540 (e.g. N measurements of the voltage potential V). DU 341 at the output node) 349). The duty cycle measurements 141 can be performed after a settling time (t s ) are recorded. The settling time (t s) can correspond to the RC value of the accumulator circuit arrangement 540 and / or the period of the signal 314, as disclosed herein. The acquisition of the duty cycle measurements 141 can further include processing and / or analyzing the measurements 141, which includes, but is not limited to: acquiring a certain number of measurements of the voltage potential V DU 341 at the output node 349 (e.g., N measurements, where N is five or more); determining one or more statistical characteristics of the N measurements (e.g., determining an average, mean, median, variance, and / or deviation of the N measurements); identifying and / or removing outliers of the N measurements (e.g., based on statistical characteristics of the N measurements); and / or the like. The duty cycle measurements 141, which are obtained using the duty cycle circuit 330 of Fig. 5A can lead to a minimal duty cycle measurement error (e.g. less than about 15 ps).

[0076] Fig. Figure 5B shows another embodiment of the DVC circuit 330 disclosed herein. In the embodiment of Fig. The control circuit arrangement 532 receives internal signals 445, including the MON_EN signal 435, which flows through inverters 537 and 538. The output of inverter 537 is an inverse of the MON_EN signal 435 (e.g., #MON_EN) and is coupled to the gate of transistor 536. The output of inverter 538 is the same as the MON_EN signal 435 and is coupled to the gate of transistor 535. Transistor 535 may be a PMOS transistor, and transistor 536 may be an NMOS transistor.

[0077] The input node 531 of the DVC circuit 330 can be coupled to a specific point 512X within a timer path 510. The timer path 510 can be the path 110 of the intermediate connection circuit 101 (as in Fig. 1A and Fig. 1B shown), path 410 of the data output circuit 401, a data output path (e.g. data path 610, 710 and / or 810 of Fig. 6A, Fig. 7 and / or 8A) and / or the like, and / or correspond to them. The timing path 510 can be configured to transmit timing signals within the circuit 100, the control circuit arrangement 101, the data path circuit arrangement, and / or the like. The timing signals transmitted along the timing path 510 can include the signal 114 as disclosed herein, which can include a clock signal, an inverted clock signal, a read enable signal, an inverse read enable signal, a data strobe signal, an inverted data strobe signal, and / or the like.

[0078] The location 512X within the time-delay path 510 can correspond to a propagation distance 513X along the time-delay path 510. The location 512X can correspond to any suitable location along the time-delay path 510 (e.g., a location at or near an input region 511), such as location 112A and / or 414A, a location at or near an output region 517 of the time-delay path 510, such as location 112N and / or 414N, and / or the like. The location 512X can have a signal 514X. Signal 514X can correspond to a propagation of signal 114 within the time-specified path 510 as disclosed herein (e.g., propagation of signal 114 to location 512X within the time-specified path 510 and / or propagation of signal 114 along the propagation distance 513X within the time-specified path 510). Signal 514X can represent a duty cycle D x and a duty cycle degradation ΔT x exhibit (which t H and tL can correspond, where t H +t L the period t p of the signal 514X).

[0079] When the MON_EN signal 435 is deactivated, the accumulator circuit assembly 540 can be disconnected and / or isolated from the timing path 510 (and the signal 514X). When the MON_EN signal 435 is activated, the control circuit assembly 532 (e.g., transistors 556 and 536) can connect the accumulator circuit assembly 540 to point 512X within the timing path 510. When connected to point 512X, the signal 514X corresponding to point 512X can be received in the accumulator circuit assembly 540 (e.g., the signal 514X flows via resistor 550 to the second terminal of capacitor 560). When the MON_EN signal 435 is activated, the voltage potential V DU 341 at the output terminal 349 according to the duty cycle D x and / or the duty cycle degradation ΔT xof signal 514X at location 512X (and / or propagation distance 513X) along the time-specified path 510. Duty cycle measurements 141X corresponding to signal 514X can be acquired by taking one or more measurements of the voltage potential V DU 341 can be obtained at output terminal 349 (while the MON_EN signal 435 is activated), as revealed here. Acquiring the duty cycle measurements 141X can involve obtaining one or more measurements of the voltage potential V. DU 341 (e.g. N measurements) and / or performing one or more error reduction operations on the measurements as disclosed herein.

[0080] Fig. Figure 5C shows another embodiment of a DVC circuit 330. In the embodiment of Fig. The DVC circuit 330 can be connected to position 512X of the timing path 510 via a transistor 570. The gate of transistor 570 can be coupled to input node 531 (and / or position 512X of the timing path 510). The signal 314 received at the DVC circuit 330 can contain a signal 514X, which, as disclosed above, can correspond to the propagation of signal 114 to position 512X (and / or the propagation distance 513X) along the timing path 510. A drain terminal of transistor 570 can be coupled to V0. A source terminal of the transistor can be coupled to node 545, which is connected to VCCQ via resistor 553 and to capacitor 560 via resistor 552. When signal 314 is activated (during t H (of signal 514X), charge can accumulate on capacitor 560 (from VCCQ and via resistors 553 and 552), and when signal 314 is deactivated (during t L(of the signal 514X), capacitor 560 can discharge. The voltage potential V DU 341 at the output node 349 can therefore have a duty cycle of signal 314 (duty cycle D). x of the 514X signal).

[0081] Fig. Figure 5D shows another embodiment of a DVC circuit 330. In the embodiment of Fig. In 5D, input node 531 can be connected to position 512X within the timing path 510. Input node 531 can be connected to the gate of transistor 571 and the gate of transistor 572. As shown in Fig. In the 5D diagram, the source terminal of transistor 571 can be coupled to VCCQ via resistor 555. The drain terminal of transistor 571 can be connected to node 547. The source terminal of transistor 572 can be coupled to node 547. The drain terminal of transistor 572 can be coupled to voltage V0. The drain terminal of transistor 573 can be coupled to node 547. The gate of transistor 573 can be connected to a reference voltage V. REF be coupled. The source terminal of transistor 573 can be coupled to node 549. Node 549 can be coupled to VCCQ via resistor 556 and to capacitor 560 via resistor 554. As in DVC circuit 330 of embodiment of Fig. 5C can then, when the input signal 314 is activated (during t H of the signal 514X), charge accumulates on the capacitor 560, and when the input signal 314 is deactivated (during tL (of the signal 514X), capacitor 560 can discharge. The voltage potential V DU 341 at the output node 349 can therefore have a duty cycle of signal 314 (duty cycle D). x of the 514X signal).

[0082] Fig. Figure 6A is a schematic block diagram of an embodiment of a data path 610, which includes a duty cycle measurement and duty cycle compensation circuit arrangement. In the embodiment of Fig. Circuit 6A contains a data path 610, which includes a sequence of stages 620 from an input stage 620A to an output stage 620N. The data path 610 can be configured to propagate signals 114 from the input stage 620A to the output stage 620N. The circuit containing the data path 610 can be implemented on a semiconductor 102, as shown here.

[0083] The input stage 620A of the data path 610 can be configured to receive external inputs 604, which may include an external read enable input (RE input) 634 and an external inverse and / or differential read enable input (BRE input) 644. The RE input circuit arrangement 622A can be configured to receive the external RE input 634, and the BRE input circuit 622B can be configured to receive the external BRE input 644. The RE input circuit arrangement 622A and / or BRE input circuit arrangement 622B can include a corresponding input / output circuit arrangement, such as an ODT circuit arrangement, a buffer circuit arrangement, a capture circuit arrangement, a driver circuit arrangement, and / or the like. The RE input circuit arrangement 622A and / or BRE input circuit arrangement 622B may further be configured to receive the test stimulus 605, as disclosed in more detail herein.

[0084] The input stage 620A can further be configured to propagate a signal 114 along the data path 610 (through the stages 620A of the data path 610) in response to one or more inputs received at the RE input circuit arrangement 622A and / or the BRE input circuit arrangement 622B. The input receiver circuit arrangement 624 can be configured to process, manipulate, and / or derive the signal 114 for communication within the data path 610. The signal 114 can contain and / or correspond to inputs received at the input of the RE input circuit arrangement 622A and / or BRE input circuit arrangement 622B. In the embodiment of Fig. In 6A, signal 114 includes a RE signal 614 and a BRE signal 664. The RE signal 614 can contain and / or correspond to a voltage signal, a probe signal, or a timing signal such as a clock signal or an RE timing signal, an RE clock signal, and / or the like. The BRE signal 664 can contain and / or correspond to a voltage signal, a probe signal, an inverse and / or differential RE signal, an inverse and / or differential timing signal, a BRE timing signal, a BRE clock signal, and / or the like. The RE signal 614 and the BRE signal 664 can be separate signals. In some embodiments, the RE signal 614 and the BRE signal 664 can propagate through separate sections, stages, circuits, and / or channels of the data path 610.The RE signal 614 can propagate through RE areas, stages, circuits, and / or channels of the data path 610, and the BRE signal 664 can propagate through separate BRE areas, stages, circuits, and / or channels of the data path 610. Alternatively or additionally, the RE signal 614 and the BRE signal 664 can propagate through one or more identical areas, stages, circuits, and / or channels of the data path 610.

[0085] The input stage 620N can include a duty cycle matching circuit arrangement 108, which can be configured to match and / or trim the signals 114 propagating within the data path 610, including matching and / or trimming the RE signal 614 and matching / or trimming the BRE signal 664. The duty cycle matching circuit arrangement 108 can be configured to implement duty cycle matching and / or trimming operations according to the duty cycle correction data 166. The duty cycle correction data 166 can, among other things, define an amount of duty cycle adjustment and / or trim to be applied to signal 114 including RE signal 614 and BRE signal 664 to compensate for the duty cycle error measured within path 610 (e.g. by means of the DCDC 164 intended for path 610).

[0086] The data path 610 may further include a repetition stage 620B, which may contain one or more repetition circuits 642A-N. The repetition circuits 642A-N may be configured to process and / or manipulate the signal 114 (including the RE signal 614 and / or BRE signal 664), which may include buffering the signal 114, delaying the signal 114, repeating the signal 114 and / or other processing and / or manipulation of the signal 114.

[0087] The output stage 620N of the data path 610 can include a data output circuit arrangement 672, which is designed to generate data output signals 118 using the signal 114 transmitted to the output stage 620N via the data path 610 (e.g., signal 114N). The data output signals 118 can include DQS signals 618A and BDQS signals 618B. The DQS signals 618A can include DQS data signals and DQS strobe signals. The BDQS signals 618B can include BDQS data signals and BDQS strobe signals. The data output circuit 672 can include a DQS generator 673A and a BDQS generator 673B. The DQS generator 673A can be configured to generate the DQS signals 618A, and the BDQS generator 673B can be configured to generate the BDQS signals 618B. Generating the DQS signals 618A can include generating DQS data signals and DQS strobe signals.The DQS data signals can be generated by combining the RE signal 614 received at the output stage 620N (e.g., the RE signal 614N) with output data. Accordingly, the DQS data signal and the DQS strobe signal can contain and / or correspond to the RE signal 614N (e.g., the DQS data signal and the DQS strobe signal can contain a logical combination of the RE signal 614N and the output data). The RE signal 614N, which is used to generate the DQS signals 618A, can be reconstructed by logically combining the DQS data signal with the DQS strobe signal (in a logical XOR operation). The BDQS signals 618B can be generated by combining the BRE signal 664 received at the output stage 620N (e.g., the BRE signal 664N) with output data. Accordingly, the BDQS data signal and the BDQS strobe signal can contain and / or correspond to the BRE signal 664N (e.g.,The BDQS data signal and the BDQS strobe signal can contain a logical combination of the BRE signal 664N and the output data. The BRE signal 664N used to generate the BDQS signals 618B can be reconstructed by logically combining the BDQS data signal with the BQDS strobe signal (in a logical XOR operation).

[0088] The output stage 620N may include a memory circuit arrangement and / or be communicatively coupled to it. The memory circuit arrangement may be designed to acquire the output data used to generate the DQS signals 618A and / or BDQS signals 618B, as disclosed herein. The memory circuit arrangement may include a memory address circuit arrangement, a memory read circuit arrangement, a memory write circuit arrangement, an acquisition circuit arrangement, a memory interface circuit arrangement, a memory bus, a memory link, a memory buffer circuit arrangement (first-in-first-out buffer circuit arrangement), and / or the like (in Fig. 1A, Fig. 1B, Fig. 4A, Fig. 6A, Fig. 7 and Fig. Figure 8A is not shown to avoid obscuring the details of the embodiments shown. As disclosed herein, the memory circuit arrangement can be configured during duty cycle measurement and / or analysis operations to provide test data for use in generating the data output signals 118 (e.g., an "FF" data pattern for use in generating the DQS signals 618A and / or BDQS signals 618B).

[0089] The output stage 620N can further include a DQS data output buffer 674A and a corresponding DQS output circuit arrangement 676A, and a BDQS data output buffer 674B and a corresponding BDQS output circuit arrangement 676B. The DQS data output buffer 674A can be configured to buffer the DQS signals 618A generated by the data output circuit arrangement 672. The BDQS data output buffer 674B can be configured to buffer the BDQS signals 618B generated by the data output circuit arrangement 672. The DQS output circuit arrangement 676A can be configured to output the DQS signals 618B that are buffered in the DQS data output buffer 674A, and the BDQS output circuit arrangement 676B can be configured to output the BDQS output signals 618B that are buffered in the BDQS data output buffer 674B.The DQS output circuit assembly 676A and / or BDQS output circuit assembly 676B may include a corresponding ODT circuit assembly, input / output circuit assembly, input / output fields, input / output pins, a driver circuit assembly, a buffer control circuit assembly, an output control circuit assembly and / or the like.

[0090] In the embodiment of Fig. 6A The circuit 100 may further include a duty cycle measurement circuit 130, which may contain communication interface circuits 643 and / or be communicatively coupled to them. The interface circuit arrangement 643 may include means for communicatively coupling the circuit 100 with the diagnostic device 160 (for example, means for transmitting command signals 161 (and / or other information) from the diagnostic device 160 to the circuit 100 and / or means for communicating duty cycle measurements 141, differential duty cycle measurements 151 (and / or other information) from the circuit 100 to the diagnostic device 160).The interface circuit arrangement 643 can, without limitation, include: an ODT circuit arrangement, an input / output circuit arrangement, input / output fields, input / output pins, probes, a dedicated test and / or diagnostic interface, a configuration interface, and / or the like. In some embodiments, the interface circuit arrangement 643 can include a test controller 440 and / or be communicatively coupled to it, as described in [reference]. Fig. 4A is shown.

[0091] The interface circuit arrangement 643 can be configured to receive, generate, and / or propagate internal signals 445 within the circuit 100 (e.g., within the duty cycle circuit 130, the data path 610, and / or the like). The internal signals 445 can configure the circuit 100 to perform duty cycle measurement operations, analysis operations, and / or compensation operations as disclosed herein. The interface circuit arrangement 643 can be configured to perform duty cycle measurement operations in response to command signals 161 from the diagnostic device 160 (and / or as part of a built-in self-test and / or other diagnostic operations). Performing a duty cycle measurement operation can involve acquiring duty cycle measurements 141 and / or differential duty cycle measurements 151 (e.g.,Measurements 141A and 141N, corresponding to the respective path points 612A and 612N, are included while the test stimulus 605 is delivered there. The test stimulus 605 may include a time-varying, oscillating test input signal 105 generated by the signal generator 131, a probe signal 607, test output data (such as an "FF" data pattern for use within the output stage 620N and / or generated by a memory circuit arrangement as disclosed above), and / or the like.

[0092] In the embodiment of Fig. The RE-ODT circuit assembly 622A may be coupled to a probe 633, and the BRE-ODT circuit assembly 622B may contain and / or be coupled to the signal generator 131. The coupling between the RE-ODT circuit assembly 622A and the probe 633 may prevent the RE-ODT circuit assembly 622A from receiving and / or propagating the test input signal 105, due to, among other things, the capacitance of the probe 633, capacitive grounding, limitations of the probe 633, and / or the like. The BRE-ODT circuit assembly 622b may not be coupled to a probe and / or may be decoupled and / or isolated from such a circuit assembly during duty cycle measurement and / or analysis operations.Thus, the test stimulus 605 for duty cycle measurement and / or analysis operations can include: a) a probe signal 607 to be applied to the RE-ODT circuit arrangement 622A (from the probe 633), b) a test input signal 105 to be applied to the BRE-ODT circuit arrangement 622B (and generated, as disclosed herein, by the signal generator 131), and c) test output data for use in generating BDQS signals 618B at the data output circuit arrangement 672 of the output stage 620N of the data path. The probe signal 607 can include a substantially constant voltage signal at approximately 1 / 2 VCCQ (half the input / output voltage VCCQ).

[0093] Performing a duty cycle measurement and / or analysis operation on the circuit 100 may include, among other things: a) supplying a test stimulus 605 to the data path 610, b) configuring the first measurement circuit 630A to obtain first duty cycle measurements 141A corresponding to the first path location 612A and / or propagation distance 613A (while the test stimulus 605 is applied), and c) configuring the first measurement circuit 630A to obtain second duty cycle measurements 141N corresponding to the second path location 612N and / or propagation distance 613N (while the test stimulus is applied). The circuit 100 may be configured to use internal signals 445, as disclosed herein.

[0094] Applying the test stimulus 605 can include: a) configuring the RE input circuit arrangement 622A to receive the probe signal 607 and to deliver the probe signal 607 to the input receiver circuit arrangement 624 for propagation within the data path 610 as RE signal 614, b) configuring the signal generator 131 to generate the test input signal 105, c) configuring the BRE input circuit arrangement 622B to receive the test input signal 105 and to deliver the test input signal 105 to the input receiver circuit arrangement 624 for propagation within the data path 610 as BRE signal 664, and / or d) configuring the output stage 620N and / or the memory circuit arrangement to generate DQS signals 618A and / or BDQS signals. 618B using a test data pattern (e.g. the “FF” data pattern).

[0095] As shown above, applying the test stimulus 605 can involve coupling the RE signal 614 with the probe signal 607, which may contain an essentially constant voltage signal (e.g., 1 / 2 VCCQ). In contrast, the BRE signal 664 may contain and / or correspond to the test input signal 105, which may contain an oscillating time-specified signal. Thus, the duty cycle measurement circuit 130 can be configured to obtain differential duty cycle measurements 151, corresponding to the propagation of the BRE signal 664 along the data path 610 (as opposed to the propagation of the RE signal 614). The duty cycle circuit 130 can acquire first duty cycle measurements 141A as disclosed, which involves connecting a first measuring circuit 630A to the location 612A within the data path 610 and obtaining one or more measurements of the voltage potential V DU341 at the output node 349 of the first measurement circuit 630A, as disclosed here. The path location 612A can contain the BRE signal 664A. The signal 664A can correspond to the propagation of the BRE signal 664 to location 612A (and / or the propagation distance 613A). Location 612A can be within the input stage 620A of the data path 610, so that the BRE signal 612A is essentially the same as the test input signal 105. Accordingly, the duty cycle ( DA ) and / or the duty cycle distortion (ΔT) A ) of the BRE signal 664A at position 612A the input duty cycle (D IN ) and / or the input duty cycle distortion (ΔT) IN) for the duty cycle measurement operation and / or analysis operation. The duty cycle circuit 130 can further be designed to acquire second duty cycle measurements 141N, as disclosed herein, which involves connecting a second measurement circuit 630N to the location 612N within the data path 610 (at the propagation distance 613N) and obtaining one or more measurements of the voltage potential V DU 341 at the output node 349 of the second measuring circuit 630N, as disclosed here. Location 612N can correspond to the propagation of the BRE signal 664 along the data path 610 to location 612N (and / or the propagation distance 613N). Location 612N can lie within the output stage 620N of the data path 610. Accordingly, the duty cycle (D) N ) and / or the duty cycle distortion (ΔT) N ) of the BRE signal 664N at position 612A the output duty cycle (D OUT) and / or the output duty cycle distortion (ΔT) OUT ) for the duty cycle measurement operation and / or analysis operation. The duty cycle measurements 141A and 141N may include differential duty cycle measurements 151, which can be used to determine a measure of the DCDC 164 of the data path 610 and / or to determine duty cycle correction data 166 to compensate for the measured DCDC 164, as disclosed herein.

[0096] In some embodiments, the first measuring circuit 630A and the second measuring circuit 630N contain separate independent DVC circuits 330 (e.g., the DVC circuits 330 that are in Fig. 5B are shown). In the embodiment of Fig. The duty cycle measurement circuit 130 can contain a shared capacitive element used by both the first measurement circuit 630A and the second measurement circuit 630N. The shared capacitive element can contain a node 662 with a capacitance 660. The node 662 can be coupled to a generator unit 663, which can be selectively configured to generate a pseudo-VCCQ voltage potential at the node 662. As disclosed in more detail here, the node 662 can contain a shared capacitive element for use by both the first measurement circuit 630A and the second measurement circuit 630N.

[0097] Fig. Figure 6B is a schematic block diagram of an embodiment of a duty cycle measurement circuit 130 designed to acquire differential duty cycle measurements 151. The duty cycle measurement circuit 130 of Fig. 6B can contain a first measuring circuit 630A and a second measuring circuit 630N. The first measuring circuit 630A and the second measuring circuit 630N can be controlled by internal signals 445, including a MON_A_EN signal 655A and a MON_N_EN signal 655N. The MON_A_EN signal 655A can configure the first measuring circuit 630A to obtain first duty cycle measurements 141A corresponding to the path point 612A, and the MON_N_EN signal 655N can configure the second measuring circuit 630N to obtain second duty cycle measurements 141N corresponding to the path point 612N.

[0098] The input node 631A of the first measurement circuit 630A can be coupled to the accumulator circuit arrangement 640A via the control circuit arrangement 632A, which contains transistors 635A and 636A. The gate of transistor 635A can be coupled to the MON_A_EN signal 655A (via inverters 637A and 638A), and the gate of transistor 636A can be coupled to a MON_A_EN signal generated by inverter 637A. Accordingly, when the MON_A_EN signal 655A is activated, the input node 631A can be connected to point 612A within the data path 610. When connected, the BRE signal 664A can be coupled at point 612A to the accumulator circuit arrangement 640A, which may involve coupling the BRE signal 664A to a node 662 (and a capacitor 660) via a resistor 650A. When connected to point 612A to receive the BRE signal 664A, the voltage potential V DU 641 at node 662 the duty cycle (DA ) of the BRE signal 664A at path point 612A. Accordingly, duty cycle measurements 141A, which correspond to the BRE signal 664A at path point 612A, can be a measurement of the voltage potential V. DU 641 is included, while node 662 receives the BRE signal 664A (from point 612A) via resistor 650A, as revealed here.

[0099] The second measuring circuit 630N can be selectively connected to the path location 612N by the control circuit arrangement 632N according to the MON_N_EN signal 655N. The MON_N_EN signal 655N and an inverse MON_N_EN signal can flow through the inverters 637N and 638N to the gate terminals of transistors 635N and 636N of the control circuit arrangement 632N. When the MON_N_EN signal 655N is activated, the input node 631N of the second measuring circuit 630N can be connected to the location 612N of the data path 610. In some embodiments, the input node 631N can be connected to the location 612N via the circuit arrangement 643. The circuit arrangement 643 may include a dummy gate and / or the like. In some embodiments, the circuit arrangement 643 may be designed to disconnect and / or isolate the second measuring circuit 630N from the data path 610 when no duty cycle measurement operations are performed (e.g., when MON_N_EN 655N is deactivated).

[0100] When the MON_N_EN signal 655N is activated, the accumulator circuit 640N of the second measuring circuit can receive the BRE signal 664N at the path point 612N. The BRE signal 664N can be coupled to node 662 (and capacitor 660) via resistor 650N. When connected to receive the BRE signal 664N at path point 612N, the voltage potential V DU 641 at node 662 the duty cycle (D N ) of the BRE signal 664N. Accordingly, the duty cycle measurements 141N can correspond to one or more measurements of the voltage potential V. DU 641 is included at node 662, while the accumulator circuit arrangement 640N is connected to receive the BRE signal 664N at location 612N, as revealed here.

[0101] The accumulator circuit assemblies 640A and 640N can each have RC values. The RC values ​​can correspond to the capacitance 660 of node 662 and the resistance values ​​of resistors 650A and 650N, respectively. The RC values ​​of the accumulator circuit assemblies 640A and 640N can be configured according to the period of the BRE signal 664 and / or the test input signal 105 (e.g., to be significantly larger than its period). The period of the BRE signal 664 can be approximately 1.875 ns. The capacitance 660 of node 662 can be approximately 11.3 pF, and the resistance of each resistor 650A and 650N can be approximately 134.4 kΩ. As revealed above, the use of high resistance values ​​in the 650A and 650N resistors can make it possible to reduce the size of the 635A, 636A, 635N and / or 636N transistors (e.g., to about 5 to 10 µm).Utilizing the capacity 660 of the existing node 662 can further reduce the size and / or additional complexity of the duty cycle measurement circuit 130. The duty cycle measurement circuit 130 of... Fig. 6B can have a design size of approximately 25 by 10 µm. Although certain embodiments of the duty cycle measurement circuit arrangement are disclosed herein, which have specific resistance and capacitance values, the disclosure is not limited in this respect and could be adapted to include any suitable duty cycle measurement circuit arrangement, which has an accumulator circuit arrangement with any suitable RC values ​​corresponding to any suitable signal period.

[0102] As disclosed above, the diagnostic device 160 and / or the interface circuit arrangement 643 can be configured to generate internal signals 445 to configure the circuit 100 to perform duty cycle measurement and / or analysis operations. The internal signals 445 can include the MON_A_EN signal 655A and / or the MON_N_EN signal 655N. The internal signals 445 can be controlled so that the signals 655A and 655N are not activated simultaneously. The signals 655A and 655N can be used to selectively disable the generator unit 663, preventing the generator unit 663 from driving (and / or disconnecting from) the node 662 when either the MON_A_EN signal 655A or the MON_N_EN signal 655N is activated (e.g.,The logic that forms a release signal for generator unit 663, the GEN_EN signal 657, can deactivate generator unit 663 if one of the signals 655A or 655N is activated).

[0103] With renewed reference to Fig. 6A may include the implementation of a duty cycle measurement operation and / or analysis operation, generating internal signals 445 to configure the circuit 100 for the following: a) applying a test stimulus 605 and b) acquiring differential duty cycle measurements 151 including first duty cycle measurements 141A and second duty cycle measurements 141N by activating the MON_A_EN signal 655A (and deactivating the MON_N_EN signal 655N) and / or activating the MON_N_EN signal 655N (and deactivating the MON_A_EN signal 655A). The acquisition of the differential duty cycle measurements 151 can include receiving multiple duty cycle measurements 141A and 141N, corresponding to the respective positions 612A and 612N, processing the duty cycle measurements 141A and 141N, etc., as disclosed herein. The differential duty cycle measurements 141 can be transmitted to the diagnostic device 160 as disclosed herein.In some embodiments, the diagnostic device 160 can be communicatively coupled to the node 662 (using an interface circuit arrangement 643 such as a probe, an input / output field, and / or the like). Accordingly, the diagnostic device 160 can be configured to acquire duty cycle measurements 141A and 141N directly from the circuit 100. The diagnostic device 160 can acquire initial duty cycle measurements 141A by, among other things: a) generating command signals 161 designed to apply the test stimulus 605 to the data path 610 and activate the MON_A_EN signal 655A, and b) receiving one or more voltage potential measurements at the node 662 (via the interface circuit arrangement 643).The diagnostic device can acquire second duty cycle measurements 141N by, among other things: a) generating command signals 161 designed to apply the test stimulus 605 to the data path 610 and activate the MON_N_EN signal 655N, and b) receiving one or more voltage potential measurements at the node 662 (via the interface circuit arrangement 643).

[0104] The diagnostic device 160 can use the duty cycle measurements 141 (e.g., the differential duty cycle measurements 151, including measurements 141A and 141N) to determine a measure of the DCDC 164 within the data path 610 and / or to generate duty cycle correction data 166 designed to compensate for the measured DCDC 164 of the data path 610. The duty cycle correction data 166 can be recorded in the circuit 100 as disclosed herein. The duty cycle matching circuit arrangement 108 can be configured to adjust and / or trim the duty cycle of the RE signals 614 and / or BRE signals 664 according to the duty cycle correction data 166, as disclosed herein.

[0105] Fig. Figure 7 is a schematic block diagram of a further embodiment of a circuit 100, which includes a data path 710 and a duty cycle measurement circuit 130. A circuit arrangement containing the data path 710 and / or the duty cycle measurement circuit 130 can be implemented on a semiconductor 102, as disclosed herein. The data path 710 can be configured to propagate signals 114 from an input region 111 to an output region 117. The signals 114 can correspond to a) external input signals 704 and / or b) a test stimulus 605, which may include a test input signal 105 generated by the signal generator 131 and / or a probe signal 607, as disclosed herein. The data output path 710 can further be configured to receive external inputs 704, including an external RE input and an external BRE input.The data output path 710 can contain a RE-ODT circuit arrangement 722A designed to receive external RE inputs and a BRE-ODT circuit arrangement 722B designed to receive external BRE inputs.

[0106] The data path 710 may further include a transfer switch 731 and a level converter 733. The transfer switch 731 may be configured to couple the RE-ODT circuit arrangement 722A and the probe 633 to the data path 717, such that the RE signals 714 propagated in the data path 710 correspond to: a) an external RE input received at the RE circuit arrangement 722A, or b) the probe signal 607 received by the probe 633 (e.g., a reference input / output voltage signal V). REFThe level converter 733 can be configured to couple the BRE-ODT circuit arrangement 722B or the signal generator 131 to the data path 710, such that the BRE signals 764 propagating within the data path 710 correspond to: a) an external BRE input received at the BRE-ODT circuit arrangement 722B, or b) the test input signal 105 generated by the signal generator 131. The data path 710 can further include a data output circuit arrangement 672, which, as disclosed herein, is configured to generate DQS signals 618A and / or BDQS signals 618B using the RE signal 714 and / or the BRE signal 764 propagating along the data path 710.

[0107] The duty cycle measurement circuit 130 can be configured, as disclosed herein, to perform duty cycle measurement and / or analysis operations on the circuit 100. Performing a duty cycle measurement and / or analysis operation can include: a) configuring the data path 710 to receive test input signals, such as the test input signal 105 generated by the signal generator 131, and / or a reference input / output voltage of the probe 633, and b) acquiring differential duty cycle measurements 151, including duty cycle measurements 141 corresponding to two different locations and / or propagation distances along the data output path 710. In the embodiment of Fig. 7. The duty cycle measuring circuit 130 can be designed to acquire duty cycle measurements 141A corresponding to a duty cycle ( DA ) and / or duty cycle distortion (ΔT) A) of the BRE signal 764A at path point 712A (and / or at propagation offset 713A along data path 710), as disclosed herein. The duty cycle measuring circuit 130 can further be configured to obtain duty cycle measurements 141N corresponding to a duty cycle (D N ) and / or duty cycle distortion (ΔT) N ) of the BRE signal 764N at path point 712N (and / or at propagation offset 713N along data path 710), as disclosed herein. The second point 712N can correspond to the BDQS data output buffer 674B, which is located along data path 710 at a further propagation distance 713N than the propagation distance 613N of Fig. The duty cycle measurement circuit 130 can supply the differential duty cycle measurements 151 (including duty cycle measurements 141A and 141N) to the diagnostic device 160, which can use the differential duty cycle measurements 151 to determine a DC-DC converter 164 for the data path 710 and / or to direct corresponding duty cycle correction data 166 for the data path 710, as disclosed herein. The diagnostic device 160 can further be configured to record the duty cycle correction data 166 in the circuit 100. The duty cycle matching circuit arrangement 108 of the data path 710 can use the duty cycle correction data 166 to compensate for the measured DCDC 164, as disclosed herein (e.g., it can adjust and / or trim the duty cycle of signals 114 propagating within the data path 710 during the operation of the circuit 100, including the RE signals 714 and BRE signals 764).

[0108] In the embodiment of Fig. 7. The diagnostic device 160 can configure the duty cycle measurement circuit 130 and / or the data path 710 to implement duty cycle measurement operations. As disclosed herein, the diagnostic device 160 can supply command signals 161 to the circuit 100 via one or more communication buses, input / output fields, diagnostic input / output fields, and / or the like.The command signals 161 can configure the data path 710 to receive test input signals corresponding to a duty cycle measurement operation, which may include: supplying a reference voltage signal to the probe 633; ​​configuring the transfer switch 731 to propagate the sampling signal 607 within the data path 710 (as RE signal 714) instead of external RE input signals received at the RE-ODT circuit assembly 722A; configuring the signal generator 131 to generate the test input signal 105; configuring the level shifter 733 to propagate the test input signal 105 within the data path 710 (as BRE signal 764) instead of external BRE inputs received at the BRE ODT circuit assembly 722B; and configuring the memory circuit arrangement to provide an "FF" data pattern for output as DQS signals 618A and / or BDQS signals 618B.The command signals 161 can further configure the duty cycle circuit 130 to acquire differential duty cycle measurements 151, including duty cycle measurements 141A and duty cycle measurements 141N. The command signals 161 for acquiring first duty cycle measurements 141A can include command signals 161 for connecting the first measuring circuit 630A to location 712A within data path 710 and node 662 (e.g., by activating the MON_A_EN signal 655A and / or deactivating the MON_N_EN signal 655N). The command signals 161 for acquiring the second duty cycle measurements 141N can include command signals 161 for connecting the second measuring circuit 630N to location 712N within data path 710 and node 662 (e.g., by activating the MON_N_EN signal 655N and / or deactivating the MON_A_EN signal 655A). The command signals 161 can also contain requests to obtain duty cycle measurements 141 (e.g.,to transmit the differential duty cycle measurements 151 (including measurements 141A and 141N) to the diagnostic device 160, among other things, via the input / output circuit 760. The input / output circuit 760 may include a probe, an input / output field, an input / output pen, a dedicated test and / or diagnostic interface, and / or the like. In the embodiment of . Fig. 7. The input / output circuit 760 can be coupled to node 662 via communication technology (in order to obtain voltage potential measurements V). DUto obtain). The diagnostic device 160 can therefore obtain the differential duty cycle measurements 151 directly by reading voltage potential measurements from the input / output circuit arrangement 733 during the duty cycle measurement operations disclosed herein (e.g., while test inputs are supplied to the data path 710 and / or one of the first measuring circuit 630A and the second measuring circuit 630N is connected to the node 662 and a respective location 712A or 712N within the data path 710).

[0109] Fig. Figure 8A is a schematic block diagram of another embodiment of a circuit 100, which includes a data path 810 and a duty cycle measurement circuit 830. In the embodiment of Fig. Data path 810 can receive input signals 704 and propagate corresponding signals 114 within data path 810 (to generate data output signals 118, which may include data strobe signals, including DQS data output signals 618A and BDQS data output signals 618B). The RE-ODT circuit arrangement 622A can be configured to receive external RE input signals and / or a probe signal 607 (e.g., a voltage reference signal (VDS(on)). REF ) via probe 633). The BRE-ODT circuit arrangement 822B can be configured to receive external BRE input signals. The BRE-ODT circuit arrangement 822B can be configured to generate a test input signal 105 (e.g., it can be configured as in Fig. 4B shows an oscillator and / or control logic).

[0110] The RE-ODT circuit arrangement 622a can be configured to output: a) external RE input signals received by it, or b) the probe signal 607 for propagation as an RE signal 814 along the data path 810. The BRE-ODT circuit arrangement 822B can be configured to output: a) one or more external BRE input signals received by it, or b) a test input signal 105 generated by it. The input receiver 624 can be configured to propagate signals 114 within the data path 810 (from the input area 111 to the output area 117 thereof), which may include propagating an RE signal 814 105 corresponding to a) an external RE input signal or b) the probe signal 607, and a BRE signal 864 corresponding to a) an external BRE input signal or b) a test input signal.

[0111] The duty cycle measuring circuit 830 can be configured to be selectively connected to one or more locations, positions, and / or propagation distances along the data path 810. In the embodiment of Fig. The duty cycle measuring circuit 830 is designed to be connected to either a path point 812A or a path point 812N. Path points 812A and 812N can correspond to the propagation of the BRE signals 864 within the data path 810 (over respective propagation distances 813A and 813N). Path point 812A can have the BRE signal 864A, which can correspond to the propagation of the BRE signal 864 to point 812A along the data path 810 (and / or the propagation distance 813A through the data path 810). The path point 812A can contain the BRE signal 864N, which can correspond to a propagation of the BRE signal 864 to point 812N along data path 810 (and / or the propagation distance 813N through data path 810). Point 812N can correspond to, be located within, and / or be positioned within a near-range threshold of the output area 117 of data path 810.The near-field threshold can correspond to a propagation distance, one or more processing operations performed within data path 810, one or more manipulation operations performed within data path 810, and / or the like. The near-field threshold corresponding to position 812A can be selected such that a duty cycle ( DA ) of signal 864A at position 812A the duty cycle (D IN ) for the duty cycle measurement operation. The near-range threshold, corresponding to position 812N, can be selected such that a duty cycle (D N ) of signal 864N at position 812N essentially equal to the duty cycle (D OUT ) is, which is used to generate the data output signals 118 (e.g. clock signals used to manufacture BQDS 618B).

[0112] The circuit 100 of the embodiment of Fig. 8A can include a duty cycle measuring circuit 830 designed to acquire differential duty cycle measurements 151, which include duty cycle measurements 141 corresponding to the various respective path points 812A and 812N and / or the reproduction distances 813A and 813N. Fig. Figure 8B is a schematic block diagram of an embodiment of a duty cycle measurement circuit 830. The duty cycle measurement circuit 830 can include a DVC circuit arrangement comprising a control circuit arrangement 832 and an accumulator circuit arrangement 840. The control circuit arrangement 832 can receive a MON_A_EN signal 855A (to enable duty cycle monitoring at location 812A) and a MON_N_EN signal 855N (to enable duty cycle monitoring at location 812N). The input circuit 832 can include a selection circuit arrangement 834, which can be configured to connect the input node 831 of the DVC circuit 830 to either location 812A or location 812N (based on the signals 855A and 855N).When the MON_A_EN signal 855A is enabled, the selector circuit 834 can connect input node 831 to position 812A, and when the MON_N_EN signal 855N is enabled, the selector circuit 834 can connect input node 831 to position 812N. A logic OR combination of signals 855A and 855N can include a MON_EN signal that can be enabled when either the MON_A_EN signal 855A or the MON_N_EN signal 855N is enabled. The MON_EN signal can be connected to the gate of NMOS transistor 835 (via inverters 837 and 838), and an inverting MON_EN signal can be connected to the gate of PMOS transistor 836. When the MON_A_EN signal 855A is activated, the input node 831 is connected to the location 812A such that the accumulator circuit arrangement 840 receives the BRE signal 864A and the voltage potential V. DU 841 at the output node 849 of the DVC circuit 830 the duty cycle ( DA) of the BRE signal 864A corresponds (where D A ≈ D IN When the MON_N_EN signal 855N is activated, the input node 831 is connected to the point 812N such that the accumulator circuit arrangement 840 receives the BRE signal 864N and the voltage potential V DU 841 at the output node 849 a measure of the duty cycle (D N ) of the BRE signal 864N contains (where D N ≈ D OUT The output node 849 can be connected via communication technology to an input / output circuit arrangement 760, which can enable the diagnostic device 160 to perform measurements of the voltage potential measurements V, as disclosed here. DU to obtain 841 at the output node 849.

[0113] The accumulator circuit arrangement 840 can have an RC value corresponding to the resistance value of resistor 850 and the capacitance of capacitor 860. The accumulator circuit arrangement 840 can be designed such that its RC value is substantially larger than the period of the BRE signal 864A and / or 864N (e.g., about 1.875 ns). In one embodiment, the capacitance of capacitor 860 is 11.3 pF and the resistance value of resistor 850 is 134.4 kΩ. The DVC circuit 830 could be adapted to have any suitable RC value for use with any signal period. Using a large resistance value for resistor 850 may allow the size of transistors 835 and 836 to be reduced, which can reduce the size and / or complexity of the DVC circuit 830.The size and / or complexity of the DVC circuit 830 can be further reduced, as disclosed herein, by using existing capacitance elements of the circuit 100, such as node 662 with capacitance 660. In such embodiments, the design size of the DVC circuit 830 can be approximately 25 by 10 µm.

[0114] With renewed reference to Fig. 8A The diagnostic device 160 can be configured to perform duty cycle measurement operations using the duty cycle circuit 830. Performing a duty cycle operation can include: a) Configuring the circuit 100 to supply test input signals as disclosed herein to the data path 810 (e.g.,by issuing command signals 161 to configure the RE-ODT circuit arrangement 622A to output the probe signal 733 for propagation as RE signal 814, and to configure the BRE-ODT circuit arrangement 822A to generate the test input signal 105 for propagation as BRE signal 864 along the data path 810); b) Configuring the duty cycle measurement circuit 830 to obtain the differential duty cycle measurements 151, which include the duty cycle measurements 141 corresponding to the respective path points 812A and 812N, which may include command signals 161 (and / or internal signals 445) to activate the MON_A_EN signal 855A or the MON_N_EN signal 855N as disclosed herein. The diagnostic device 160 can also be designed to perform one or more measurements of the voltage potential V. DUat the output node 839 of the duty cycle measurement circuit 830 using the input / output circuit arrangement 760 as disclosed herein. When the duty cycle measurement circuit 830 is connected to the data path 810 at location 812A, the duty cycle measurements 141A of the duty cycle distortion (ΔT) can be obtained. A ) corresponding to the propagation to position 812A along data path 810, which is essentially equal to an input duty cycle (D IN ) and / or an input duty cycle distortion (ΔT) IN ) may be. If the duty cycle measurement circuit 830 is connected to the data path 810 at position 812N, the duty cycle measurements 812N of the duty cycle distortion (ΔT) can be N ) corresponding to the propagation to position 812N along data path 810, which is essentially equal to an output duty cycle (D OUT) of data path 810. Accordingly, the duty cycle distortion corresponding to the signal propagation through data path 810 can be determined by comparing and / or differentiating the duty cycle measurements 141N-141A (and / or ΔT). OUT ΔT IN ) can be determined, which may correspond to a duty cycle change in the signals during propagation through data path 810 (e.g., the DCDC 164 for data path 810). The diagnostic device 160 can therefore determine a measure of the DCDC 164 of data path 810 and / or derive corresponding duty cycle correction data 166 for data path 810 based on the duty cycle measurements 141A and 141N acquired using the duty cycle circuit 830. The diagnostic device 160 can further be configured to record the duty cycle correction data 166 in the circuit 100 for use by the duty cycle matching circuit arrangement 108 to compensate for the measured duty cycle error within data path 810.

[0115] Fig. Figure 9 is a simplified block diagram of a system 900 for duty cycle measurement, analysis, and / or compensation. The system 900 may include means 930 for obtaining duty cycle measurements corresponding to one or more path locations 112 and / or propagation distances 113 within the path 910. The means 930 may be configured to obtain duty cycle measurements corresponding to a first path location 912A and a second path location 912N. The first path location 912A may correspond to an input area 111, and the second location 912N may correspond to an output area 117. The means 930 may include a duty cycle measurement arrangement as disclosed herein (e.g., a duty cycle measurement circuit 130, 630, and / or 830, duty cycle measurement circuit arrangement, DCV circuit arrangement, and / or the like). The measuring instruments 930 may contain an accumulator circuit arrangement 340 and / or 540, which may contain an RC circuit arrangement as disclosed herein.The system 900 may further include means 960 for analyzing the duty cycle measurements acquired by means 930 in order to determine a measure of the DCDC 164 for path 910, derive corresponding duty cycle correction data 166, configure the duty cycle matching circuit arrangement 108 to compensate for the measured duty cycle errors (e.g., to store the duty cycle correction data 166 in the circuit 100), and so forth, as disclosed herein. The analysis means may, as disclosed herein, include a duty cycle measurement circuit arrangement, a test controller, the test interface, and / or the diagnostic device 160.

[0116] Fig. Figure 10 is a flowchart of an embodiment of a method 1000 for duty cycle measurement, analysis, and / or compensation. Step 1010 may include supplying one or more test input signals to path 110. Path 110 may be implemented as a circuit 100 on a semiconductor chip 102 and may consist of an interconnection circuit arrangement 101, a data output circuit arrangement 401, and / or the like. Path 110 may include one or more data paths 410, a timing path 510, a signal path, and / or the like. The test input signal(s) of step 1010 may contain an oscillating signal that is to be propagated along path 110 and / or used to generate data output signals 118. The test input signal(s) can contain a test input signal 105, which is generated by a signal generator 131.The test input signal 105 can be propagated as a signal 114 and / or BRE signal 664 within path 110. The test input signal(s) can further contain a probe signal 733 (e.g., a reference voltage signal) for propagation as an RE signal 614 within path 110, test output data (e.g., a "FF" data pattern), and / or the like.

[0117] Step 1020 may include connecting a duty cycle measurement circuit to a location along path 110. Step 1020 may include connecting a DVC circuit 330 to path 110. Step 1020 may include connecting an input node 531 of the DVC circuit 330 to a selected location along path 110, such that the signal 114 is received at the selected location on the accumulator circuit arrangement 340 of the DVC circuit 330. In some embodiments, the measurement circuit includes an input circuit arrangement 332 containing a switch configured to selectively connect the DVC circuit 330 to a designated path location 112. In such embodiments, step 1020 can include activating and / or closing the switch so that the accumulator circuit arrangement 340 of the DVC 330 is electrically coupled to the path 110 in order to receive a signal 314 there.In some embodiments, the measuring circuit includes the DVC circuit 330 from . Fig. Step 5A and step 1020 contain a configuration of the routing circuit arrangement 534 to connect the input node 531 to the selected location along path 110. Alternatively or additionally, the measuring circuit can use the DVC circuit 330. Fig. 5B includes an input node 531 connected to the selected location within path 110 (e.g., location 512X) by the control circuit arrangement 532, and step 1020 may include activating a MON_EN signal 435 to configure the control circuit arrangement 532 to connect location 512X to the accumulator circuit arrangement 540 via transistors 535 and 546 (e.g., connecting the selected location along path 110 to capacitor 560 via resistor 550). In some embodiments, the measuring circuit includes the duty cycle measuring circuit 130. Fig. Step 6B and step 1020 involve activating: the MON_A_EN signal 655A to configure the control circuit arrangement 632A to connect the input node 631A to a first waypoint (waypoint 612A), or the MON_N_EN signal 655N to configure the control circuit arrangement 632N to connect the input node 631N to a second waypoint (waypoint 612N). In some embodiments, the measuring circuit includes the duty cycle measuring circuit 830. Fig. Step 8B and step 1020 includes activating the MON_A_EN signal 655A or the MON_N_EN signal 655N to configure the selection circuit arrangement 834 and / or the control circuit arrangement 832 thereof to connect the input node 831 to the first waypoint (812A) or the second waypoint (812N).

[0118] Step 1030 may include the acquisition of duty cycle measurements 141. The duty cycle measurements 141 correspond to the duty cycle of the signal 114 at the selected location. Acquiring the duty cycle measurements 141 may involve obtaining measurements of a voltage potential V. DU at a node of the measurement circuit, while the test input signal(s) from step 1010 are supplied to path 110 and the measurement circuit remains connected to the selected location (via step 1020). Step 1030 may include receiving a signal from path 110, so that signal 114 flows to the accumulator circuit arrangement 340, 540, 640A, 640N and / or 840. The accumulator circuit arrangement may include an RC characteristic corresponding to a resistance and / or capacitance thereof. The accumulator circuit arrangement may be designed such that the RC characteristic is significantly larger than the period of signal 114 (e.g., RC >> t). P or t H+t L The period of signal 114 can be approximately 1.875 ns. The accumulator circuit of the measuring circuit can be designed such that its RC characteristic is greater than 1.875 ns. The capacitance of the accumulator circuit can be approximately 11.3 pF and the resistance can be approximately 13.4 kΩ, resulting in an RC characteristic of approximately 1.518 × 10 -6 This may correspond to the disclosure. However, the disclosure is not limited in this respect and could be interpreted to include the use of a measurement circuit arrangement having an RC characteristic adapted for use with signals 114 with any suitable period.

[0119] Step 1030 may further include disconnecting the measurement circuit arrangement from path 110 in response to the acquisition of duty cycle measurements 141. Step 1030 may include: disconnecting and / or disabling a switch connecting the DVC circuit 330 to path 110, configuring the routing circuit arrangement 534 to disconnect the DVC circuit 330 from path 110. Fig. 5A to disconnect from path 110, withdraw the MON_EN signal 435 to configure the control circuit arrangement 532 to disconnect the input node 531 from path 110, disable the MON_A_EN signal 655A and / or the MON_N_EN signal 655N to disconnect the measuring circuits 632A and / or 632N from path 110, disable the MON_A_EN signal 655A and / or the MON_B_EN signal 655N to configure the control circuit arrangement 832 to disconnect the measurement 830 from path 110, and / or the like.

[0120] The duty cycle measurements from step 1030 can be used to measure a voltage potential V DU at a node of the measuring circuit (e.g. V DU 341 at the exit node 349, V DU 641 at node 662, V DU 841 at the output node 849 and / or the like). Acquiring the duty cycle measurements 141 can provide multiple measurements of the voltage potential V. DU (e.g., N measurements) and / or include performing error reduction processing on the N measurements, which may include, but is not limited to: determining an average, mean, and / or median of the voltage potential of the N measurements; discarding outlier measurements of the N measurements; and / or the like.

[0121] Step 1030 can involve transmitting the duty cycle measurements 141 by, among other things, recording the duty cycle measurements in a memory, sending the duty cycle measurements on a bus and / or an intermediate connection, outputting the duty cycle measurements via an input / output field and / or a probe, connecting the output nodes 349, 662, and / or 849 to a probe (e.g., probe 760), and / or the like. The duty cycle measurements 141 can be used to determine a DCDC 164 for path 110 and / or to derive corresponding duty cycle correction data 166 for path 110 to compensate for the determined DCDC 164 as disclosed herein.

[0122] Fig. Figure 11 is a flowchart of a further embodiment of a method 1100 for duty cycle measurement, analysis, and / or compensation. Step 1110 may include acquiring differential duty cycle measurements 151 corresponding to a path 110, as disclosed herein. Step 1100 may include a first acquiring of duty cycle measurements 141A corresponding to a first propagation offset within the path 110. The first propagation offset may correspond to an entry region of the path 110 (e.g., located in or near the entry region 111 of the path 110). The first propagation offset may include and / or correspond to one or more propagation offsets 113A, 413A, 613A, 713A, and / or 813A disclosed herein.Acquiring the duty cycle measurements 141A corresponding to the first propagation offset may include, among other things, supplying one or more test input signals into path 110, connecting a measuring circuit to a selected position and / or location within path 110 (where the selected position and / or location corresponds to the first propagation offset, e.g., position 112A, 412A, 612A, 712A and / or 812A), and acquiring duty cycle measurements using the measuring circuit as disclosed herein (e.g., according to steps 1010, 1020 and / or 1030 of method 1000).

[0123] The acquisition of the differential duty cycle measurements 151 in step 1110 may further include a second acquisition of duty cycle measurements 141N, corresponding to a second propagation offset within the path 110. The second propagation offset may correspond to an exit region of the path 110 (e.g., located in or near the exit region 117 of the path 110). The second propagation offset may include and / or correspond to one or more propagation offsets 113N, 413N, 613N, 713N, and / or 813N disclosed herein. The acquisition of the second duty cycle measurements 141N can, among other things, involve supplying one or more test input signals into path 110, connecting a measuring circuit to a selected position and / or location within path 110 (where the selected position and / or location corresponds to the second propagation offset, e.g.Position 112N, 412N, 612N, 712N and / or 812N) and a recording of duty cycle measurements using the measuring circuit as disclosed herein (e.g. according to steps 1010, 1020 and / or 1030 of method 1000).

[0124] Step 1130 may include determining a duty cycle degradation of path 110 based on the duty cycle measurements corresponding to the first and second propagation offsets within the path. Step 1130 may include comparing and / or differentiating the duty cycle measurements 141A with the duty cycle measurements 141N as disclosed herein. Step 1130 may further include calculating a duty cycle error of path 110 (ΔD). E_PATH ) a duty cycle degradation (ΔT E_PATH) during propagation through path 110 and / or the like. Step 1130 may include determining a DCDC 164 for path 110 and / or deriving according to the duty cycle correction data 166 to compensate for the determined DCDC 164. Step 1130 may further include configuring circuit 100 to compensate for ΔD E_PATH and ΔT E­_PATH included, which includes deriving the duty cycle correction data 166 corresponding to the DCDC 164 and storing the duty cycle correction data 166 within the circuit 100 (e.g. recording the duty cycle correction data 166 in a ROM backup memory of the duty cycle matching circuit arrangement 108).

[0125] Fig.Figure 12 is a flowchart of an embodiment of a further method 1200 for duty cycle measurement, analysis, and / or compensation. Step 1210 may include acquiring duty cycle measurements 141A corresponding to an input area 111 of the path 110. The duty cycle measurements 141A may be acquired from a first path location 112 and / or propagation distance 113 (e.g., path location 112A, 412A, 612A, 712A, and / or 812A as disclosed herein). The duty cycle measurements 141A may be acquired according to step 1110 of method 1100 and / or steps 1010, 1020, and 1030 of method 1000 as disclosed above.

[0126] Step 1220 may include the acquisition of duty cycle measurements 141N corresponding to an output area 117 of the path 110. The duty cycle measurements 141N may be acquired at the second path location 112 and / or a propagation distance 113 along the path (e.g., path locations 112N, 412N, 612N, 712N, and / or 812N as disclosed herein). The duty cycle measurements 141N may be acquired as disclosed above according to step 1110 of procedure 1100 and / or steps 1010, 1020, and 1030 of procedure 1000.

[0127] The duty cycle measurements acquired in steps 1210 and 1220 may include differential duty cycle measurements 151, as disclosed herein. Step 1230 may include a comparison of the duty cycle measurements 141A with the duty cycle measurements 141N to determine whether the measurements 141A and 141N (and / or corresponding duty cycle metrics) differ by more than a threshold. As disclosed above, the threshold may correspond to a duty cycle matching granularity of the duty cycle matching circuit arrangement 108 (e.g., the matching and / or trim size of the duty cycle matching circuit arrangement 108). If the duty cycle measurements 141A and 141N differ by more than the threshold, the process may proceed to step 1240; otherwise, the process may terminate at step 1250.

[0128] Step 1240, as disclosed herein, may include determining a DCDC 164 for path 110 using measurements 141A and 141N. Step 1240 may further include, as disclosed herein, determining duty cycle correction data 166 corresponding to the DCDC 164. The duty cycle correction data 166 may be configured to configure the duty cycle matching circuit arrangement 108 to compensate for the DCDC 164 measured within path 110. Step 1240 may further include recording the duty cycle correction data 166 on the circuit, the semiconductor 102, the duty cycle matching circuit arrangement 108 and / or the like, so that the duty cycle matching circuit arrangement 108 is configured to implement the specified duty cycle corrections during operation of the circuit 100.

[0129] The device described here can be implemented in any suitable NAND flash memory, including 20- or 30-NAND flash memory. Semiconductor memory devices include volatile memory devices such as dynamic random-access memory (DRAM) or static random-access memory (SRAM), non-volatile memory devices such as resistive random-access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random-access memory (FRAM), magnetoresistive random-access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations.For example, flash memory devices can be configured in a NAND or a NOR configuration.

[0130] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory devices include ReRAM device elements, which in some embodiments contain a resistance-switching memory element such as an anti-fuse, a phase-change material, etc., and optionally a control element such as a diode, etc. As another non-limiting example, active semiconductor memory devices include EEPROM and flash memory device elements, which in some embodiments contain elements that include a charge storage region such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0131] Multiple memory elements can be configured to be connected in series or to allow individual access to each element. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array can be configured to consist of multiple memory strands, where each strand contains multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured to allow individual access to each element, such as in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured differently.

[0132] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, for example, in a two-dimensional or three-dimensional memory structure. In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, memory elements in a two-dimensional memory structure are arranged in a plane (e.g., in an xz-direction plane) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate can be a wafer on which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can contain a semiconductor such as silicon.

[0133] The memory elements can be arranged in an ordered configuration within a single memory device level, for example, in multiple rows and / or columns. However, the memory elements can also be arranged in non-regular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0134] A three-dimensional storage arrangement is arranged such that storage elements occupy multiple levels or multiple storage facility levels, thereby forming a structure in three dimensions (i.e. in the x, y, and z directions, with the y direction being essentially perpendicular and the x and z directions being essentially parallel to the main surface of the substrate).

[0135] As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-restrictive example, a three-dimensional storage arrangement can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple storage elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional storage arrangement with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions can also form a three-dimensional storage arrangement.

[0136] As a non-restrictive example, the memory elements in a three-dimensional NAND memory array can be coupled to form a NAND chain within a single horizontal (e.g., xz) memory device plane. Alternatively, the memory elements can be coupled to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations are possible, with some NAND chains containing memory elements within a single memory plane, while others containing memory elements spanning multiple memory planes. Three-dimensional memory arrays can also be configured in a NOR configuration and in a ReRAM configuration.

[0137] Typically, in a monolithic three-dimensional memory arrangement, one or more memory device layers are formed on a single substrate. Optionally, the monolithic three-dimensional memory arrangement can also contain one or more memory layers, at least partially, within the single substrate. As a non-restrictive example, the substrate can contain a semiconductor material such as silicon. In a monolithic three-dimensional arrangement, the layers that form the respective memory device layers of the arrangement are typically formed on top of the layers of the underlying memory device layers of the arrangement. However, layers of adjacent memory device layers in a monolithic three-dimensional memory arrangement can be shared, or layers can be located between memory device layers.

[0138] Furthermore, two-dimensional arrays can be fabricated separately and then packed together to form a non-monolithic, multi-layer memory device. For example, non-monolithic stacked memories can be built by fabricating memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory array layers prior to stacking, but because the memory array layers are initially fabricated over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Additionally, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be fabricated on separate chips and then packed together to form a stacked-chip memory device.

[0139] Associated circuitry is typically used to operate and communicate with the memory elements. As non-restrictive examples, memory devices may include circuitry used to control and manipulate memory elements to perform functions such as programming and reading. This associated circuitry may reside on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read / write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0140] Experts will recognize that this disclosure is not limited to the two-dimensional and three-dimensional illustrative structures described, but covers all relevant storage structures within the scope of protection of the disclosure as described herein and understood by experts in the field.

[0141] The subject matter described herein may be implemented in hardware, software, firmware, or any combination thereof. The terms "function," "node," or "module," as used herein, refer to hardware, which may also include software and / or firmware components to implement the described feature. In an exemplary implementation, the subject matter described herein may be implemented using a computer-readable medium on which computer-executable instructions are stored. When executed by a computer's processor, these instructions control the computer to perform actions. Exemplary computer-readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media such as disk storage devices, chip storage devices, programmable logic devices, and application-specific integrated circuits.Furthermore, a computer-readable medium implementing the item described herein may be located on a single device or computing platform, or it may be distributed across multiple devices or computing platforms.

[0142] Naturally, various details of the subject matter described here may be changed without altering the overall scope of the subject matter described. Furthermore, the foregoing description serves only for illustrative purposes and not as a limitation.

Claims

[1] A circuit (100) including a data path (610, 710), the circuit further including: a first measurement circuit (630A) including a first resistor-capacitor circuit, RC circuit, and configured to acquire first duty cycle measurements (141A) from the data path (610, 710); and a second measurement circuit (630N) including a second RC circuit and configured to acquire second duty cycle measurements (141N) from the data path (610, 710); wherein the first RC circuit and the second RC circuit share a capacitor (660); wherein the first measurement circuit (630A) and the second measurement circuit (630N) are communicatively coupled to different positions (612A, 612N, 712A, 712N) along the data path (610, 710) such that a difference between the first duty cycle measurements (141A) and the second duty cycle measurements (141N) corresponds to a duty cycle degradation along the data path (610, 710); wherein the first duty cycle measurements (141A) include voltage potentials at the first RC circuit while the first RC circuit is communicatively coupled to a first position (612A, 712A) along the data path (610, 710), and wherein the second duty cycle measurements (141N) include voltage potentials at the second RC circuit while the second RC circuit is communicatively coupled to a second position (612N) along the data path (610, 710), the second position (612N, 712N) being different from the first position (612A, 712A); and wherein the circuit further includes control circuitry (632A, 632N) configured to selectively connect the shared capacitor (660) to one of the first position (612A, 712A) along the data path (610, 710) and the second position (612N, 712N) along the data path (610, 710). [2] Circuit according to claim 1, wherein the first measurement circuit (630A) is communicatively coupled to the first position (612A, 712A) along the data path (610, 710), the first position (612A, 712A) being configured such that the first duty cycle measurements (141A) correspond to an input duty cycle, and the second measurement circuit (630N) is communicatively coupled to the second position (612N, 712N) along the data path (610, 710), wherein the second position (612N, 712N) is configured such that the second duty cycle measurements (141N) correspond to an output duty cycle. [3] The circuit of claim 1, wherein the data path (610) includes input circuitry (622A, 622B) and wherein the first measurement circuitry (630A) is communicatively coupled to the input circuitry (622A, 622B). [4] The circuit of claim 3, wherein the data path (610) includes data output circuitry (672) and wherein the second measurement circuit (630N) is communicatively coupled to the data output circuitry (672) of the data path (610, 710). [5] Circuit according to claim 1, wherein the control circuitry (632A, 632N) is configured to selectively connect one of the first measuring circuit (630A) and the second measuring circuit (630N) to an output field, wherein a test device is configured to receive duty cycle measurements through the output array, the received duty cycle measurements including first duty cycle measurements (141A) and second duty cycle measurements (141N), the test device further configured to determine a measure of duty cycle degradation along the data path (610, 710) using the received duty cycle measurements (141A, 141N) and to determine a duty cycle adjustment factor for the data path based on the measure of duty cycle degradation. [6] A circuit according to claim 5, further comprising: duty cycle adjustment circuitry (108) configured to adjust a duty cycle of a signal propagating through the data path (610) based on the determined duty cycle adjustment factor. [7] The circuit of claim 1, wherein the control circuitry (632A) includes a first switch including: a metal-oxide-semiconductor transistor (MOS transistor) (635A) having a source terminal connected to the first position (612A, 712A) along the data path (610, 710), a drain terminal connected to the shared capacitor (660) via a first resistor (650A), and a gate terminal coupled to a first enable signal (665A); and a second transistor (636A) having a source terminal connected to the first position (612A) along the data path (610), a drain terminal connected to the shared capacitor (660) via the first resistor (650A), and a gate terminal coupled to an inversion of the first enable signal. [8] The circuit of claim 7, wherein the control circuitry (632N) includes a second switch including: a MOS transistor (635N) having a source terminal connected to the second position (612N) along the data path (610), a drain terminal connected to the shared capacitor (660) via a second resistor (650N), and a gate terminal connected to a second enable signal (655N); and a second transistor (636N) having a source terminal connected to the second position (612N) along the data path (610), a drain terminal connected to the shared capacitor (660) via the second resistor (650N), and a gate terminal coupled to an inversion of the second enable signal. [9] A semiconductor device (100) comprising: a data output circuitry (401) having a timing path, the data output circuitry being configured to transmit a timing signal along the timing path (510) from an input portion (111) to an output portion (117); and duty cycle measurement circuitry (130) configured to measure a duty cycle error associated with the timing path, the duty cycle measurement circuitry configured to: Determining an input duty cycle metric corresponding to a duty cycle of the timing signal in the input portion (111) of the timing path, and Determining an output duty cycle metric corresponding to a duty cycle of the timing signal in the output portion (117) of the timing path, wherein a difference between the input duty cycle metric and the output duty cycle metric contains a measure of the duty cycle error associated with the timing path, wherein the duty cycle measurement circuitry includes an accumulator circuitry (340) having an input node and an output node (349), and wherein: the input duty cycle metric corresponds to the charge accumulated at the output node (349) while the input node is coupled to the input portion of the timing path, and the output duty cycle metric corresponds to the charge accumulated at the output node (349) while the input node is coupled to the output portion of the timing path. [10] Semiconductor device comprising: a data output circuitry having a timing path (610, 710, 810), the data output circuitry being configured to transmit a timing signal (114) along the timing path (610, 710, 810) from an input portion (111) to an output portion (117); and duty cycle measurement circuitry (130, 830) configured to measure a duty cycle error associated with the timing path (610, 710, 810), the duty cycle measurement circuitry (130, 830) configured to: Determining an input duty cycle metric corresponding to a duty cycle of the timing signal in the input portion (111) of the timing path (610, 710, 810), and Determining an output duty cycle metric corresponding to a duty cycle of the timing signal in the output portion (117) of the timing path (610, 710, 810), wherein a difference between the input duty cycle metric and the output duty cycle metric contains a measure of the duty cycle error associated with the timing path (610, 710, 810), wherein the duty cycle measurement circuit (130, 830) is configured to acquire differential duty cycle measurements (151) corresponding to the input duty cycle metric and the output duty cycle metric, and to provide the differential duty cycle measurements (151) to a diagnostic device (160), wherein the diagnostic device (160) determines a duty cycle adjustment (166) using the differential duty cycle measurements (151) to correct the amount of duty cycle error associated with the timing path, wherein the diagnostic device (160) writes the determined duty cycle adjustment (166) to a memory location of the semiconductor device, wherein the data output circuitry further includes: a duty cycle correction circuit (108) configured to implement the determined duty cycle adjustment (166) written to the memory location within the timing path (610, 710, 810). [11] A semiconductor device according to claim 10, wherein the duty cycle measurement circuitry (830) includes an accumulator circuitry (840) having an input node and an output node (849), and wherein: the input duty cycle metric corresponds to the charge accumulated at the output node (849) while the input node (831) is coupled to the input portion (111) of the timing path, and the output duty cycle metric corresponds to the charge accumulated at the output node (849) while the input node (831) is coupled to the output portion (117) of the timing path. [12] A semiconductor device according to claim 10, wherein the duty cycle measurement circuitry (830) includes: a resistor-capacitor circuit (RC circuit) having an input connected to a capacitive element (860) of the RC circuit via a resistive element (850) of the RC circuit; and a control circuit arrangement (832) adapted to selectively connect the input of the RC circuit arrangement to one of the input portion (111) of the timing path (810) and the output portion (117) of the timing path (810), wherein: the input duty cycle metric corresponds to a voltage potential (841) on the capacitive element (850), while the input of the RC circuit is connected to the input region (111) of the timing path (810), and the output duty cycle metric corresponds to a voltage potential (841) on the capacitive element (860) of the RC circuit, while the input of the RC circuit is connected to the output portion (117) of the timing path (810). [13] The semiconductor device of claim 12, wherein the capacitive element (860) includes a node connected to a generator, and wherein the duty cycle measurement circuitry (830) is configured to selectively disable the generator. [14] A semiconductor device according to claim 10, wherein the duty cycle measurement circuitry (130) includes: a first capacitor; and a second capacitor, where: the input duty cycle metric corresponds to a voltage potential on the first capacitor, while the first capacitor is connected to a first location (612A, 712A) on the timing path (610, 710), the first location (612A, 712A) being within the input range (111) of the timing path (610, 710), and the output duty cycle metric corresponds to a voltage potential on the second capacitor, while the second capacitor is coupled to a second location (612N, 712N) on the timing path (610, 710), the second location (612N, 712N) being within the output region (117) of the timing path (610, 710). [15] A semiconductor device according to claim 14, wherein: the first capacitor and the second capacitor include a shared capacitive element (660), a first control circuit arrangement (632A) is designed to selectively connect the first location (612A, 712A) on the timing path (610, 710) to the shared capacitive element (660), a second control circuit arrangement (632N) is designed to selectively connect the second location (612N, 712N) on the timing path (610, 710) to the shared capacitive element (660), the input duty cycle metric corresponds to a voltage potential on the shared capacitive element (660) while the shared capacitive element (660) is connected to the first position (612A, 712A) of the timing path (610, 710) and is disconnected from the second position (612N, 712N) of the timing path, and the output duty cycle metric corresponds to a voltage potential across the shared capacitive element (660), while the shared capacitive element (660) is connected to the second position (612N, 712N) of the timing path (610, 710) and is disconnected from the first position (612A, 712A) of the timing path (610, 710). [16] Procedure comprising: Acquiring (1210) first measurements (141A) corresponding to a duty cycle of an input signal propagating through a data path (110), wherein the acquiring of the first measurements (141A) includes: Connecting an input of a resistor-capacitor circuit (RC circuit) to a first propagation distance (113) within the data path (110), the input being connected to receive a first time-varying signal, the first time-varying signal corresponding to the propagation of the input signal over the first propagation distance (113) within the data path (110), and Acquiring first voltage potential measurements at an output of the RC circuit while the input of the RC circuit is connected at the first propagation distance (113) along the data path (110); Acquiring (1220) second measurements (141N) corresponding to the duty cycle of the input signal propagating through the data path (110), wherein the acquiring of the second measurements (141N) includes: Connecting the input of the RC circuit to a second propagation distance (113) along the data path (110), wherein the input is connected to receive a second time-varying signal, wherein the second time-varying signal corresponds to the propagation of the input signal over the second propagation distance (113) within the data path (110), wherein the second propagation distance (113) is greater than the first propagation distance (113), and Acquiring second voltage potential measurements at the output of the RC circuit while the input of the RC circuit is connected at the second propagation distance (113) along the data path (110); and Determining (1240) a duty cycle correction (166) for the data path (110) based on a comparison (1230) between the first voltage potential measurements and the second voltage potential measurements. [17] System that contains: Means (930, 630, 830) for measuring a first voltage potential across a capacitor (660) while an input of the capacitor is connected to a first location (912A) along a data path (910) of data output circuitry, the first location (912A) having a first oscillating signal formed in response to propagation of a signal from an input to the data path to the first location along the data path; Means (930, 630, 830) for measuring a second voltage potential across the capacitor (660) while the input of the capacitor (660) is connected to a second location (912N) along the data path (910) of the data output circuitry, the second location (912N) having a second oscillating signal formed in response to propagation of the signal from the input to the data path (910) to the second location (912N) along the data path (910), the second location (912N) being different from the first location (912A); and Means (960) for determining a duty cycle correction (166) for the data path (910), wherein the duty cycle correction (166) corresponds to a difference between the first voltage potential and the second voltage potential.

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