TECHNIQUES FOR MRAM MTJ TOP ELECTRODE ON METAL LAYER INTERFACE WITH A SPACER

Abstract

Integrated circuit comprising: a semiconductor substrate (206); an interconnect structure (204) disposed over the semiconductor substrate (206) and comprising a plurality of dielectric layers (226, 228, 230) and a plurality of stacked metal layers (232, 234, 236), the plurality of metal layers (232, 234, 236) including a lower metal layer (114, 240) and an upper metal layer (116, 242) over the lower metal layer (114, 240); a lower electrode (254) disposed above and in electrical and physical contact with the lower metal layer (114, 240); a magnetic tunnel junction, MTJ (258), disposed over a top surface of the bottom electrode (254); a top electrode (256) disposed over a top surface of the MTJ (258), the top electrode (254) having an electrode top in direct electrical contact with a bottom surface of the top metal layer (116, 242); a sidewall spacer (126, 260) surrounding an outer periphery of the upper electrode (256), the spacer (126, 260) having a top surface of the spacer (126, 260); an etch stop layer (142a) disposed on top of an outer periphery of the upper surface of the spacer (126, 260) and surrounding an outer periphery of the lower surface of the upper metal layer (116, 242); and further wherein the etch stop layer (142a) has a lateral extension overhanging the outer periphery of the upper surface of the spacer (126, 260), wherein a portion of the etch stop layer (142a) extending beyond the outer periphery of the upper surface of the spacer (126, 260) is angled slightly downward toward the lower metal layer (114, 240).

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory can retain its stored data when power is lost, whereas volatile memory loses its stored data when the power is interrupted. Magnetoresistive random-access memory (MRAM) is a promising candidate for next-generation non-volatile electronic memory due to its advantages over current electronic memory. Compared with current non-volatile storage, such as flash random-access memory, MRAM is typically faster and has a longer endurance.Compared to current volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), MRAM typically has similar performance and density but lower power consumption.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2018 / 0 040 817 A1, DE 10 2016 114 870 A1, US 2017 / 0 117 467 A1, DE 10 2014 119 172 A1, DE 10 2015 117 872 A1, US 2017 / 0 207 387 A1, US 2016 / 0 308 119 A1 and US 10 038 137 B2.

[0003] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1A shows a cross-sectional view of a portion of an electronic memory with some embodiments of an MRAM cell including a magnetic tunnel junction (MTJ). Fig. Figure 1B shows a cross-sectional view of an MRAM cell illustrating the geometry of a stop layer deposited during MRAM cell fabrication. Fig. Figure 1C shows a cross-sectional view of an MRAM cell exhibiting unwanted metal overflow. Fig. 2 shows a cross-sectional view of some embodiments of an integrated circuit including MRAM cells. Fig. Figure 3 shows a plan view of some embodiments of the integrated circuit of Fig. 2 with MRAM cells. Fig. 4 shows an enlarged cross-sectional view of an MRAM cell of the integrated circuit of Fig. 2. Fig. Figures 5 to 11 illustrate a series of incremental manufacturing steps as a series of cross-sectional views. Fig. 12 illustrates a methodology in flowchart format illustrating some embodiments of the present concept. DETAILED DESCRIPTION

[0005] The present disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0007] A magnetoresistive random access memory (MRAM) cell contains top and bottom electrodes and a magnetic tunnel junction (MTJ) disposed between the top and bottom electrodes. In conventional MRAM cells, the top electrode is connected to an overlying metal layer (e.g., Metal 1, Metal 2, Metal 3, etc.) through a contact or via. Although the use of this coupling contact or via is widespread, the total height of this MRAM cell plus this contact or across it is large compared to a typical vertical distance between adjacent metal layers (e.g., between a Metal 2 layer and a Metal 3 layer).To make this height consistent with the vertical distance between adjacent metal layers, the present disclosure provides techniques for directly coupling the top electrode to an overlying metal line without via or contact therebetween, while avoiding a possible MRAM short circuit due to metal line overflow beyond a top surface of the MRAM cell and a bottom electrode of the MRAM cell.

[0008] Referring to Fig. Figure 1A illustrates a cross-sectional view of a portion of a memory device 100 including a memory array region and a peripheral region. The memory array region includes a metal layer-to-metal layer interconnect arrangement 103 for an MRAM cell 101, according to some embodiments. Two MRAM cells 100 (Cell 1 and Cell 2) are illustrated, although for simplicity, like reference numerals are used to describe the MRAM cells 101. The MRAM cells 101 include a bottom electrode 102 and a top electrode 104 separated by a magnetic tunnel junction (MTJ) 106. In some embodiments, the bottom electrode 102 uses a multi-layer structure (e.g., three layers) including a barrier layer of tantalum nitride or tantalum and two additional layers of tantalum nitride or titanium nitride.The top electrode 104, the MTJ 106, and a portion of the bottom electrode 102 are surrounded by a sidewall spacer 126. The bottom and top electrodes 102, 104 are disposed between a bottom metal layer 114 and a top metal layer 116. The sidewall spacer 126 is surrounded by a protective layer 125, which may be made of silicon oxynitride (e.g., SiON), for example, and a dielectric material, such as an interlayer dielectric (ILD) or intermetallic dielectric (IMO) layer 128, surrounds the protective layer 125. A dielectric liner 138, such as a silicon dioxide liner or a silicon nitride liner, may conformally overlie a protective dielectric layer 140. The dielectric protection layer 140 electrically isolates the bottom electrode 102 from other active circuits and provides mechanical and chemical protection for the bottom electrode.In some embodiments, the dielectric protective layer is made of silicon dioxide (SiO2) or silicon nitride (Si3O4).

[0009] The MTJ 106 includes a lower ferromagnetic electrode 108 and an upper ferromagnetic electrode 110 separated from each other by a tunnel barrier layer. In some embodiments, the lower ferromagnetic electrode 108 may have a fixed or "pinned" magnetic orientation, while the upper ferromagnetic electrode 110 has a variable or "free" magnetic orientation that can be switched between two or more different magnetic polarities, each representing a different data state, such as a different binary state. However, in other implementations, the MTJ 106 may be vertically "flipped" so that the lower ferromagnetic electrode 108 has a "free" magnetic orientation, while the upper ferromagnetic electrode 110 has a "pinned" magnetic orientation.

[0010] In some embodiments, the sidewall spacer 126 includes a top spacer surface 126a having approximately the same height as an upper electrode surface 104a of the top electrode. A portion of an etch stop layer 142a remains above the top surface 126 of the spacer and disposed around an outer perimeter of the top metal layer 116. The etch stop layer 142a has a width d1, which is a factor that defines the width d2 of a bottom surface of the top metal layer 116. The width d1 of the etch stop layer 142a is partially controlled by a width of the top spacer surface 126a, which supports the etch stop layer 142a when deposited. A lower portion of the etch stop layer 142a may be seen extending outwardly from a bottom surface of the sidewall spacer 126.

[0011] Fig. 1B schematically illustrates how the width of the top spacer surface 126a controls the width of the etch stop layer 142a in an MRAM cell 150 in some embodiments. The etch stop layer 142a' may be made of silicon carbide (SiC) in some embodiments. The upper portion of the etch stop layer 142a' may include a central region directly above (and in some cases in direct contact with) the top electrode 104 and a peripheral region that tapers or slopes downwards beyond the spacer 126. It can be seen that the etch stop layer 142a' extends slightly beyond the edges of the sidewall spacer 126. The etch stop layer 142a' has a "beret"-like shape because the etch stop layer has a lateral extent that significantly overhangs the spacer 126.The portion of the etch stop layer 142a' that extends beyond the outer perimeter of the top surface of the spacer angles slightly downward toward the lower metal layer. For the purposes of this description, the term "overhanging etch stop layer" is used as shorthand to describe a beret-shaped etch stop layer formed as shown in FIG. Fig. 1B. The protruding etch stop layer 142a' may prevent inadvertent etching of the protective layer 125 in a region extending beyond an outer periphery of the sidewall spacer 126. When the etch stop layer 142a' is etched to form an opening for a top metal layer, the opening will not extend beyond the etch stop layer 142, thereby containing the top metal layer in the opening and enclosing the top metal layer in the region above the MRAM cell, as shown in Fig. 1A can be seen.

[0012] In some MRAM manufacturing processes, a titanium / titanium nitride layer is deposited on top of the top electrode 104 to prevent oxidation during manufacturing. This titanium / titanium nitride layer is removed by a subsequent photo / etch step. One advantage of depositing the stop layer 142a' on the top electrode 104 is that the complete coverage of the stop layer 142a' over the top electrode 104 can serve as sufficient oxidation prevention, thus making the titanium / titanium nitride layer unnecessary. Accordingly, using the etch stop layer 142a' to prevent oxidation instead of the titanium / titanium nitride layer can save processing steps and costs.

[0013] Fig. Figure 1C shows an exemplary MRAM cell 160 that has a potential difficulty represented by direct contact between the top electrode 104' and the overlying metal layer 116' without a sufficiently wide sidewall spacer or stop layer. The sidewall spacer 126' is narrower than the sidewall spacer 126 of Fig. 1B. This means that the etch stop layer 142a lacks lateral coverage (e.g., width) and may not provide sufficient protection against inadvertent etching of the protective layer 125. It is possible that during the etching to form the opening for the overlying metal layer 116a, an inadvertent void may be formed if the etch extends slightly beyond the sidewall spacer 126'. When this void is filled with the overlying metal layer, a "tooth" 116x is formed, and a weak point may be created (indicated by the dashed arrow labeled X), offering the possibility of a short circuit between the tooth 116x and a bottom electrode 102' of the MRAM cell 160.

[0014] Returning to Fig. 1A, the MRAM cells 100 include a wider sidewall spacer 126 and an etch stop layer 142a that have a sufficient width so that the connection between the metal layer 116 and the MRAM cell 100 does not extend beyond the top surface 126a of the sidewall spacer 126. This means that the risk of a short circuit developing between the bottom electrode 102 and the overlying metal layer 116 is reduced. As can be seen, the features of Fig. 1A provide a reduced distance between the lower and upper metal layers 114, 116 due to direct contact between the upper electrode 104 and the upper metal layer 116 without an intermediate via and can also be exploited for streamlined manufacturing techniques.

[0015] In particular, the top electrode 104 itself is in direct electrical contact with the overlying metal layer 116, rather than contact or connection of the top electrode 104 to an overlying metal layer 116. In some embodiments, the overlying metal layer 116 is a metal line or a metal layer bridge. In some embodiments, a bottom surface of the overlying metal layer 116 meets at a planar interface with a top surface 104a of the top electrode 104 and also with a portion of a top surface 126a of the sidewall spacer 126. Because there is no via or contact between the top electrode 104 and the overlying metal layer 116, the overall height of the MRAM cell 100 is more easily compatible with back-end-of-line (BEOL) process flows.

[0016] Fig. 2 shows a cross-sectional view of some embodiments of an integrated circuit 200 including MRAM cells 202a, 202b arranged in an interconnect structure 204 of the integrated circuit 200. The integrated circuit 200 includes a substrate 206. The substrate 206 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The illustrated embodiment shows one or more shallow trench isolation (STI) regions 208, which may include a dielectrically filled trench within the substrate 206.

[0017] Two wordline transistors 210, 212 are disposed between the STI regions 208. The wordline transistors 210, 212 each include wordline gate electrodes 214, 216; wordline gate dielectrics 218, 220; wordline sidewall spacers 222; and source / drain regions 224. The source / drain regions 224 are disposed within the substrate 206 between the wordline gate electrodes 214, 216 and the STI regions 208 and are doped to have a first conductivity type opposite a second conductivity type of a channel region beneath the respective gate dielectrics 218, 220. The wordline gate electrodes 214, 216 may be, for example, doped polysilicon or a metal such as aluminum, copper, or combinations thereof. The wordline gate dielectrics 218, 220 may be, for example, an oxide such as silicon dioxide or a high-K dielectric material.The wordline sidewall spacers 222 may be made of, for example, silicon nitride (e.g., Si3N4).

[0018] The interconnect structure 204 is disposed above the substrate 206 and couples components (e.g., transistors 210, 212) to one another. The interconnect structure 204 includes a plurality of IMD layers 226, 228, 230 and a plurality of metallization layers 232, 234, 236 that are alternately layered one above the other. The IMD layers 226, 228, 230 may, for example, be made of a low-K dielectric such as undoped silicate glass or an oxide such as silicon dioxide or an ultra-low-K dielectric layer. The metallization layers 232, 234, 236 include metal lines 238, 240, 241, 242 formed within trenches and may be made of a metal such as copper or aluminum.Contacts 244 extend from the lower metallization layer 232 to the source / drain regions 224 and / or gate electrodes 214, 216; and vias 246 extend between the metallization layers 232, 234, 236. The contacts 244 and the vias 246 extend through dielectric protection layers 250, 252 (which may be made of dielectric material and may act as etch stop layers during manufacturing). The dielectric protection layers 250, 252 may be made of an ultra-low-K dielectric material, such as SiC. The contacts 244 and the vias 246, 248 may be made of a metal, such as copper or tungsten.

[0019] MRAM cells 202a, 202b, configured to store respective data states, are disposed within the interconnect structure 204 between adjacent metal layers. The MRAM cell 202a includes a bottom electrode 254 and a top electrode 256 made of a conductive material. Between its top and bottom electrodes 256, 254, the MRAM cell 202a includes an MTJ 258. The MRAM cell 202a also includes a sidewall spacer 260. The metal line 242 has a bottom surface that is coplanar with, and in direct electrical contact (e.g., ohmically coupled) with, a top surface of the top electrode 256 and a portion of a top surface of the sidewall spacer 260.

[0020] Fig. 3 shows some embodiments of a top view of the integrated circuit 200 of the Fig. 2, as in the Fig. 2-3. As can be seen, in some embodiments, the MRAM cells 202a, 202b may have a square, rectangular, or circular shape when viewed from above. However, in other embodiments, for example, due to the practicality of many etching processes, the corners of the illustrated square shape may be rounded, resulting in MRAM cells 202a, 202b having a square or rectangular shape with rounded corners, or shaped as a circle or an oval. The MRAM cells 202a, 202b are each disposed over metal lines 240, 241 and have top electrodes 256 in direct electrical connection with the metal lines 242 without vias or contacts therebetween.

[0021] Referring to Fig. 4 is an enlarged cross-sectional view of the MRAM cell 202a of Fig. 2. As shown, MRAM cell 202a includes bottom electrode 254 and top electrode 256 with MTJ 258 between bottom electrode 254 and top electrode 256. Bottom electrode 254 extends downwardly into an opening in protective dielectric layer 252 to make electrical contact with underlying metal line 240.

[0022] In the illustrated embodiment, the MTJ 258 includes a lower ferromagnetic electrode 266 (which may have a fixed magnetic orientation) and an upper ferromagnetic electrode 268 (which may have a free magnetic orientation). A tunnel barrier layer 270 is disposed between the lower and upper ferromagnetic electrodes 266, 268; and a cap layer 272 is disposed over the upper ferromagnetic electrode 268. The lower ferromagnetic electrode 266 may be a synthetic antiferromagnetic (SAF) structure including an upper pinned ferromagnetic layer 274, a lower pinned ferromagnetic layer 276, and a metal layer 278 sandwiched between the upper and lower pinned ferromagnetic layers 274, 276.

[0023] In some embodiments, the upper ferromagnetic electrode 268 comprises Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd, or the like. In some embodiments, the cap layer 272 comprises WO2, NiO, MgO, Al2O3, Ta2O5, MoO2, TiO2, GdO, Al, Mg, Ta, Ru, or the like. In some embodiments, the tunnel barrier layer 270 provides electrical isolation between the upper ferromagnetic electrode 268 and the lower ferromagnetic electrode 266 while still allowing electrons to tunnel through the tunnel barrier layer 270 under suitable conditions. The tunnel barrier layer 270 may comprise, for example, magnesium oxide (MgO), aluminum oxide (e.g., Al2O3), NiO, GdO, Ta2O5, MoO2, TiO2, WO2, or the like.

[0024] During operation, the variable magnetic polarity of the upper (e.g., free) ferromagnetic electrode 268 is typically read by measuring the resistance of the MTJ 258. Due to the magnetic tunneling effect, the resistance of the MTJ 258 changes with the variable magnetic polarity. Further, the variable magnetic polarity is typically changed or switched during operation using the spin transfer torque (STT) effect. According to the STT effect, current is passed across the MTJ 258 to induce a flow of electrons from the lower (e.g., pinned) ferromagnetic electrode 266 to the upper (e.g., free) ferromagnetic electrode 268. When electrons pass through the lower ferromagnetic electrode 266, the spins of the electrons are polarized.When the spin-polarized electrons reach the top ferromagnetic electrode 268, the spin-polarized electrons apply a torque to the variable magnetic polarity and switch the state of the free ferromagnetic electrode (e.g., the top electrode 268). Alternative approaches for reading or changing the variable magnetic polarity are also possible. For example, in some alternative approaches, magnetization polarities of the pinned and / or free ferromagnetic electrodes 266 / 268 are perpendicular to an interface between the tunnel barrier layer 270 and the pinned and / or free ferromagnetic electrode 266 / 268, making the MTJ 258a a perpendicular MTJ.

[0025] Because, in the illustrated embodiment, the top electrode 256 itself (as well as a portion of the sidewall spacer 260) is in direct contact with the overlying metal line 242, the overall height of the MRAM cells 202a, 202b can be reduced relative to previous approaches. This reduced height makes the MRAM cells 202a, 202b more easily compatible with BEOL process flows. Thus, the formation of MRAM cells 202a, 202b provides better MRAM operations with reduced manufacturing costs. Furthermore, because a bottom surface of the metal line is not as wide as the top surface of the spacer 260, the possibility of a short circuit of the metal line to the bottom electrode 254 is reduced.

[0026] With reference to Fig. 5 to 11 show cross-sectional views of some embodiments of a semiconductor structure with an MRAM cell in various stages of manufacture. Although Fig. 5 to 20 are described as a series of operations, it should be understood that these operations are not limiting in that the order of operations may be changed in other embodiments and the disclosed methods are also applicable to other structures. In other embodiments, some of the illustrated and / or described operations may be omitted in whole or in part.

[0027] Fig. Figure 5 shows a cross-sectional view of some embodiments illustrating a portion of an interconnect structure 204 disposed over a substrate (in Fig. 5 not shown, but previously in Fig. 2). The interconnect structure 204 includes an IMD layer 228 and a metal line 240 extending horizontally through the IMD layer 228. The IMD layer 228 may be an oxide such as silicon dioxide, a low-K dielectric material, or an extremely low-K dielectric material. The metal line 240 may be made of a metal such as aluminum, copper, or combinations thereof. In some embodiments, the substrate may be a bulk silicon substrate or a semiconductor-on-insulator (SOI) substrate (e.g., silicon-on-insulator substrate). The substrate may also be a binary semiconductor substrate (e.g., GaAs), a tertiary semiconductor substrate (e.g., AlGaAs), or a higher-order semiconductor substrate.In many cases, the substrate manifests as a semiconductor wafer and can have a diameter of 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); 450 mm (17.7 inches, commonly referred to as "18 inches"). After processing is complete, for example, after MRAM cells have been formed, such a wafer can optionally be stacked with other wafers or dies and is then singulated into individual dies corresponding to individual ICs.

[0028] A first dielectric protection layer 252 is formed over the IMD layer 228 and over the metal line 240. In some embodiments, the first dielectric protection layer 252 comprises SiC (silicon carbide) with a thickness of approximately 250 angstroms. A second dielectric protection layer 253 is formed over the first dielectric protection layer 252. In some embodiments, the second dielectric protection layer has a different chemical composition than the first dielectric protection layer 252 and may, for example, comprise SRO (silicon-rich oxide) with a thickness of approximately 200 angstroms. A bottom electrode layer 254 is formed over the dielectric protection layers 252, 253 and extends downward through an opening in the dielectric protection layers 252, 253 to make electrical contact with an upper portion of the metal line 240.The bottom electrode layer 254 may be a conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, or a combination of one or more of the foregoing. Furthermore, in some embodiments, the bottom electrode layer 254 may be, for example, about 10-100 nanometers thick.

[0029] A magnetic tunnel junction stack (MTJ) 258 is formed over a top surface of the bottom electrode layer 254, and a top electrode layer 256 is formed over the MTJ stack 258. The top electrode layer 256 may be a conductive material, such as titanium nitride, tantalum nitride, titanium, tantalum, tungsten, or a combination of one or more of the foregoing. Further, the top electrode layer 256 may be, for example, about 10-100 nanometers thick. A mask 502 is disposed over a top surface of the top electrode layer 256. In some embodiments, the mask 502 includes a photoresist mask, but it may also be a hard mask, such as a nitride mask. In some embodiments, the mask 502 may be a different conductive material than the top electrode layer 256, such as titanium nitride, tantalum nitride, titanium, tantalum, or a combination of one or more of the foregoing.Sidewalls of the MTJ 258 and / or the upper electrode 256 may be angled at an angle other than 90 degrees as measured with respect to a normal line passing through a top surface of the lower electrode 254.

[0030] A sidewall spacer precursor layer 260' is formed over lateral portions of the bottom electrode 254, the sidewalls of the MTJ 258, and the sidewalls of the top electrode 256, and extends over the sidewalls and the top surface of the mask 502. In some embodiments, the sidewall spacer precursor layer 260' may be formed by any suitable deposition technique and is typically formed conformally. Further, the sidewall spacer precursor layer 260' may be formed, for example, from silicon nitride, silicon carbide, Si3N4, SiON, or a combination of one or more of the foregoing. Moreover, the sidewall spacer precursor layer 260' may be formed to a thickness of, for example, about 150-600 angstroms. A dielectric coating 602, such as a conformal oxide, is then formed over the sidewall spacer precursor layer 260'.The dielectric lining 602 facilitates the in . Fig. 6 performed spacer etching process.

[0031] In Fig. 6, a spacer etch process 600 (e.g., anisotropic etch) was performed into the sidewall spacer precursor layer 260' to etch back the sidewall spacer precursor layer 260' to remove lateral portions of the sidewall spacer precursor layer 260 and the top electrode mask layer 502 to expose a top surface 256 of the top electrode 256 surrounded by the remaining sidewall spacer 260. In some embodiments, a top sidewall spacer surface and the top electrode surface have a combined width that is significantly wider than the expected width of a metal recess or trench formed in Fig. 10 will be formed to create the metal line (e.g., greater than 154 nm). Therefore, in some embodiments, the width of the sidewall spacer is selected based on the width of the metal line to which the top electrode will be connected. Additionally, the spacer etch process cuts the bottom electrode 254 to its final dimension. In some embodiments, this spacer etch 600 is a unidirectional or vertical etch.

[0032] In Fig. 7, an etch stop layer is deposited to create a first portion of the stop layer 142a covering the upper electrode surface and the upper surface of the spacer. An additional portion 142a of the etch stop layer, which may be discontinuous with respect to the first portion 142a, borders a perimeter of the lower electrode 254. This discontinuity in the stop layer is due to the step-like coverage characteristic of the stop layer material (e.g., silicon nitride, silicon carbide, Si3H4, SiON, or combinations thereof), which typically does not deposit on the lateral surface of the MTJ. Furthermore, the first portion 142a projects beyond the upper surface of the spacer and, in some embodiments, has the Fig. 1B to provide additional lateral protection against inadvertent etching beyond the top surface of the spacer.

[0033] In Fig. 8, a protection layer 230, such as a silicon oxynitride (SiON) layer or an extremely low-k dielectric layer, is then formed over the etch stop layer 142, for example, by chemical vapor deposition (CVD), plasma vapor deposition (PVD), spin-on techniques, or thermal oxidation. The protection layer 230 electrically isolates the MRAM cell from other active circuitry and provides mechanical and chemical protection for the MRAM cell. In some embodiments, a top surface of the protection layer 230 is approximately 1080 angstroms above a surface of the second protection dielectric layer 253. In some embodiments, chemical mechanical planarization (CMP) is then performed on the protection layer 230 to planarize a top surface of the protection layer 230.After CMP, a photomask (not shown) is formed over the protective layer 230, and etching is performed so that the protective layer 230 covers the memory array region and not the peripheral region, as shown in FIG. Fig. 8 shown.

[0034] Next, an IMD or ILD layer 801 made of a dielectric material such as an oxide or ELK dielectric is deposited on top of the protection layer 230 in the memory array area and on top of the second protection dielectric layer 253 in the peripheral region. In some embodiments, the IMD or ILD layer 801 has a thickness of approximately 400 angstroms in the memory array region and approximately 1700 angstroms in the peripheral region. An etch stop layer 803 is deposited on the IMD or ILD layer 801. In some embodiments, the etch stop layer 803 comprises tetraethyl orthosilicate (TEOS). A nitrogen-free anti-reflective layer (NFARL) 805 is deposited on the etch stop layer 803. In some embodiments, the NFARL 805 is approximately 200 angstroms thick. A hard mask layer 807 is applied to the NFARL 805.Photolithography is used to pattern the hard mask layer 807 with trench openings used in a dual-damascene process to form trenches or openings intended to hold a top metal layer. In some embodiments, these openings may be dual-damascene openings. In some embodiments, the hard mask layer 807 comprises titanium nitride (TiN) and is approximately 350 angstroms thick.

[0035] In Fig. 9, a photoresist layer 909 is applied over the hard mask layer 807. A first trench 915 is etched in the peripheral region.

[0036] In Fig. 10, the photoresist layer 909 was removed. One or more etches are then performed to form trench openings 242' and 243'. In some embodiments, the one or more etchants comprise a dual damascene process.

[0037] In Fig. 11, a metal such as aluminum or copper is used to fill the trenches and openings. Thus, in a memory array region, the trench is filled with a metal line 242 having a bottom surface in direct contact with the top surface of the top electrode 256, thereby providing an ohmic connection without a contact or via between the metal lines. The bottom surface of the metal line is also in contact with a portion of the stop layer 142a, reducing the risk of metal spillover beyond the MRAM cell. In some embodiments, the bottom surface of the metal line is in contact with less than an entirety of the stop layer. Then, a CMP operation is performed (as indicated by the dashed line) to planarize a top surface of the metal lines and a top surface of the dielectric protection layer 801, resulting in the structure of the Fig. 1A and / or 4.

[0038] In another area of ​​the integrated circuit, such as the peripheral region where CMOS logic devices are formed, a metal line 242 is connected to an underlying metal line 240 via a via 243. Compared to the direct connection between the metal line 242 and the top electrode 256, the interposition of the via 243 between the metal layer 242 and the underlying metal line 240 consumes a similar amount of space in the vertical direction as the MRAM cell. Thus, the direct connection between the metal line 242 and the top electrode 256 in the memory array region enables a reduced cell height in the memory array region, so that the cell height in the memory array region is similar to the cell height in the peripheral region.

[0039] Fig. 12 illustrates a methodology 1200 for forming an MRAM cell with an etch stop layer of sufficient width to protect against inadvertent etching over the sidewall spacer, according to some embodiments. While this method and other methods illustrated and / or described herein are illustrated as a series of acts or events, it should be appreciated that the present disclosure is not limited to the illustrated arrangement or acts. Thus, in some embodiments, the acts may be performed in different orders than illustrated and / or may be performed concurrently. Further, in some embodiments, the illustrated acts or events may be divided into multiple acts or events that may be performed at separate times or concurrently with other acts or sub-acts.In some embodiments, some illustrated acts or events may be omitted and other, non-illustrated acts or events may be included.

[0040] For example, acts 1202 to 1208 may correspond to the structure previously described in Fig. 5 in some embodiments. At 1202, an etch stop layer is formed over a top surface of a dielectric layer. The etch stop layer has an opening exposing at least a portion of a top surface of an underlying metal line. At 1204, a bottom electrode layer is formed over the etch stop layer. The bottom electrode layer extends downward through the opening to make physical and electrical contact with the underlying metal layer. At 1206, a magnetic tunnel junction (MTJ) layer is formed over the bottom electrode layer. At 1208, a top electrode layer is formed over the magnetic tunnel junction layer. At 1210, which corresponds to the previously described Fig. 5, a wide spacer layer is formed surrounding at least the MTJ layer and the top electrode. The wide spacer layer is sufficiently wide to support an etch stop layer that protects against inadvertent etching beyond a top surface of the spacer. At 1212, which corresponds to the previously described Fig. 6, the spacer layer is etched to expose an upper surface of the upper electrode and an upper surface of the spacer. At 1213, which corresponds to the previously Fig. 7, an etch stop layer is formed covering the upper surface of the upper electrode and the upper surface of the spacer. The etch stop layer projects beyond an outer periphery of the upper surface of the spacer. At 1214, which corresponds to the previously Fig.11, an upper metal layer is formed to be in direct physical and electrical contact with the upper electrode surface and the upper surface of the spacer.

[0041] Some embodiments relate to an integrated circuit including a magnetoresistive random access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers alternately stacked one above the other. The plurality of metal layers includes a bottom metal layer and a top metal layer disposed over the bottom metal layer. A bottom electrode is disposed over and in electrical contact with the bottom metal layer. A magnetic tunnel junction (MTJ) is disposed over a top surface of the bottom electrode. A top electrode is disposed over a top surface of the MTJ and has an electrode top in direct electrical contact with the top metal layer.A sidewall spacer surrounds an outer perimeter of the upper electrode and has a top surface of the spacer. An etch stop layer is disposed on top of an outer perimeter of the top surface of the spacer and surrounds an outer perimeter of the bottom surface of the upper metal layer. The etch stop layer projects beyond the outer perimeter of the top surface of the spacer.

[0042] Other embodiments relate to an MRAM cell disposed on a semiconductor substrate. The MRAM cell includes a bottom electrode disposed over the semiconductor substrate and a magnetic tunnel junction (MTJ) disposed on the bottom electrode. A top electrode is disposed over a top surface of the MTJ, the top electrode having a top electrode surface. A sidewall spacer surrounds an outer periphery of the top electrode, the spacer having a top surface of the spacer. A metal line is disposed over the top electrode and has a bottom surface in direct physical and electrical contact with the top electrode surface and with at least a portion of the top surface of the spacer.

[0043] Other embodiments relate to a method of fabricating an MRAM cell. In this method, an etch stop layer is formed over a top surface of a dielectric layer, the etch stop layer having an opening exposing at least a portion of a top surface of an underlying metal line. A bottom electrode layer is formed over the etch stop layer. The bottom electrode layer extends downward through the opening to physically and electrically connect to the underlying metal line. A magnetic tunnel junction (MTJ) layer is formed over the bottom electrode layer. A top electrode is formed over the magnetic tunnel junction layer. A spacer layer is formed surrounding at least the MTJ layer and the top electrode. The spacer layer is etched to expose a top surface of the top electrode and a top surface of the spacer.A top metal layer is formed in direct electrical and physical contact with the top surface of the electrode and the top surface of the spacer.

[0044] It should be understood that in this written description, as well as in the following claims, the terms "first," "second," "third," etc., are merely generic identifiers used for convenience of description to distinguish between various elements of a figure or series of figures, which, by themselves, do not imply a chronological order or structural proximity for those elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, "a first dielectric layer" described in connection with a first figure may not necessarily correspond to a "first dielectric layer" described in connection with another figure, and may not necessarily correspond to a "first dielectric layer" in an unillustrated embodiment.

Claims

[1] Integrated circuit comprising: a semiconductor substrate (206); an interconnect structure (204) disposed over the semiconductor substrate (206) and comprising a plurality of dielectric layers (226, 228, 230) and a plurality of stacked metal layers (232, 234, 236), the plurality of metal layers (232, 234, 236) including a lower metal layer (114, 240) and an upper metal layer (116, 242) over the lower metal layer (114, 240); a lower electrode (254) disposed above and in electrical and physical contact with the lower metal layer (114, 240); a magnetic tunnel junction, MTJ (258), disposed over a top surface of the bottom electrode (254); a top electrode (256) disposed over a top surface of the MTJ (258), the top electrode (254) having an electrode top in direct electrical contact with a bottom surface of the top metal layer (116, 242); a sidewall spacer (126, 260) surrounding an outer periphery of the upper electrode (256), the spacer (126, 260) having a top surface of the spacer (126, 260); an etch stop layer (142a) disposed on top of an outer periphery of the upper surface of the spacer (126, 260) and surrounding an outer periphery of the lower surface of the upper metal layer (116, 242); and further wherein the etch stop layer (142a) has a lateral extension overhanging the outer periphery of the upper surface of the spacer (126, 260), wherein a portion of the etch stop layer (142a) extending beyond the outer periphery of the upper surface of the spacer (126, 260) is angled slightly downward toward the lower metal layer (114, 240). [2] The integrated circuit of claim 1, wherein the lower surface of the upper metal layer (116, 242) is in contact with the upper spacer surface (126, 260). [3] The integrated circuit of claim 1 or 2, wherein a width of the lower surface of the upper metal layer (116, 242) is less than a width of the upper spacer surface (126, 260). [4] The integrated circuit of any preceding claim, wherein the MTJ (258) has sidewalls angled at an angle other than 90 degrees as measured relative to a normal passing through a top surface of the bottom electrode (254). [5] The integrated circuit of any preceding claim, further comprising an additional portion of the etch stop layer (142b) disposed at an outer periphery of the lower electrode (254). [6] A magnetoresistive random access memory cell, MRAM, disposed on a semiconductor substrate (206), the MRAM cell comprising: a lower electrode (254) disposed above the semiconductor substrate (206); a magnetic tunnel junction, MTJ (258), disposed on the lower electrode (254); a top electrode (256) disposed over a top surface of the MTJ (258), the top electrode (256) having a top electrode surface; a sidewall spacer (260) surrounding an outer periphery of the upper electrode (256), the spacer (260) having a top surface of the spacer (260); an etch stop layer (142a) disposed on top of an outer periphery of the upper surface of the spacer (260), the etch stop layer (142a) overhanging the outer periphery of the upper surface of the spacer (260); and a metal line (242) disposed above the upper electrode (256) and having a lower surface in direct physical and electrical contact with the upper surface of the electrode (256), wherein a portion of the etch stop layer (142a) extending beyond the outer periphery of the upper surface of the spacer (260) is angled slightly downward toward the lower electrode (254). [7] The MRAM cell of claim 6, wherein the bottom surface of the metal line (242) is in contact with the top spacer surface. [8] The MRAM cell of claim 6 or 7, wherein the MTJ (258) has sidewalls angled at an angle different from 90 degrees, measured relative to a normal passing through a top surface of the bottom electrode (254). [9] The MRAM cell of any one of the preceding claims 6 to 8, wherein a width of the lower surface of the metal line (242) is less than a width of the upper spacer surface. [10] The MRAM cell of any one of the preceding claims 6 to 9, comprising an additional portion of the etch stop layer (142b) disposed at an outer periphery of the lower electrode (254). [11] A method of manufacturing a magnetoresistive random access memory cell, MRAM, the method comprising: Forming an etch stop layer (253) disposed over a top surface of a dielectric layer (252), the etch stop layer (253) having an opening exposing at least a portion of a top surface of an underlying metal line (240); Forming a lower electrode layer (254) over the etch stop layer (253), the lower electrode layer (254) extending downward through the opening to physically and electrically connect to the underlying metal line (240); Forming a magnetic tunnel junction, MTJ, layer (258) over the bottom electrode layer (254); Forming an upper electrode (256) over the magnetic tunnel junction layer (258); Forming a spacer layer (260') surrounding at least the MTJ layer (258) and the top electrode (256); Etching the spacer layer (260') to expose a top surface of the top electrode (256) and a top surface of the spacer (260); Forming an upper etch stop layer (142a) over the upper surface of the upper electrode (256) and the upper surface of the spacer (260), the upper etch stop layer (142a) overhanging an outer periphery of the upper surface of the spacer (260); and Forming an upper metal layer (242) in contact with the upper surface of the upper electrode (256), wherein a portion of the etch stop layer (142a) extending beyond the outer periphery of the upper surface of the spacer (260) is angled slightly downward toward the lower electrode (254). [12] The method of claim 11, wherein a width of the upper etch stop layer (142a) is greater than a width of a lower surface of the upper metal layer (242). [13] The method of claim 12, wherein the upper etch stop layer (142a) comprises silicon nitride, Si3N4. [14] The method of any one of the preceding claims 11 to 13, wherein a width of the top surface of the spacer (260) combined with a width of the top electrode surface is greater than about 154 nanometers. [15] The method of any one of the preceding claims 11 to 14, wherein the spacer layer (260') comprises silicon carbide, SiC. [16] Method according to one of the preceding claims 11 to 15, further comprising: Forming a further dielectric layer over the upper surface of the spacer (260) and the upper electrode surface; and Forming a trench and an opening in the further dielectric layer, wherein a trench opening exposes the electrode top and a portion of the upper surface of the spacer (260); and Filling the trench and via openings with a conductive material directly adjacent to the top electrode surface and a portion of the top surface of the spacer (260). [17] The method of claim 16, wherein the trench opening exposes less than the entirety of the top surface of the spacer (260).

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