Structure and method for exposing memory cells of different sizes

Abstract

Storage device (100a) comprising: a lower electrode via (110) surrounded by a lower dielectric layer (108) and disposed over a substrate (102); a lower electrode (112) disposed on the lower electrode via (110); a switching dielectric (116) disposed over the lower electrode (112) and having a variable resistance; an upper electrode (118) disposed above the switching dielectric (116); a sidewall spacer layer (126) extending upwardly along sidewalls of the lower electrode (112), the switching dielectric (116), and the upper electrode (118); a lower etch stop layer (120) disposed over the lower dielectric layer (108) and lining an outer sidewall of the sidewall spacer layer (126); an upper dielectric layer (136) disposed on the lower etch stop layer (120) and surrounding an upper portion of the sidewall spacer layer (126); and an upper interlayer dielectric layer (138) adjacent to upper surfaces of the lower etch stop layer (120) and the upper dielectric layer (136); wherein the lower etch stop layer (120) is made of a material different from that of the sidewall spacer layer (126); the upper surfaces of the lower etch stop layer (120) and the upper dielectric layer (136) are coplanar; and the lower etch stop layer (120) extends continuously from the lower dielectric layer (108) to the upper interlayer dielectric layer (138).

Description

BACKGROUND

[0001] Many modern electronic devices contain non-volatile memory capable of storing data without a power supply. Non-volatile memories such as magnetoresistive random access memory (MRAM) and resistive random access memory (RRAM) are promising candidates for next-generation non-volatile memory technology due to their relatively simple structures and compatibility with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes.

[0002] US 2014 / 0 252 295 A1 describes an RRAM cell and its fabrication. A first spacer surrounds an upper electrode of the RRAM cell. Furthermore, a second spacer surrounds the lower electrode and the resistive material layer of the RRAM cell, as well as the first spacer.

[0003] US 2017 / 0 117 467 A1 describes an integrated circuit with an RRAM cell. A sidewall spacer surrounds an upper electrode of the RRAM cell. Furthermore, a dielectric cap layer surrounds the lower electrode and the resistive layer of the RRAM cell, as well as the sidewall spacer.

[0004] US 9,431,603 B1 describes an integrated circuit device with an RRAM cell. The integrated circuit arrangement has a spacer surrounding sidewalls of a lower electrode, a resistive switching layer, and an upper electrode of the RRAM cell. Furthermore, the integrated circuit arrangement has an upper etch stop layer adjacent to the sidewalls of the spacer and overlying the upper electrode.

[0005] DE 10 2016 117 034 A1 describes a semiconductor structure with a magnetic tunnel contact layer and a spacer surrounding this layer.

[0006] Furthermore, DE 10 2016 100 136 A1 describes a magnetic random access memory structure with a recap layer on a bottom via, wherein the material of the recap layer differs from that of the bottom via.

[0007] US 2014 / 0 070 162 A1 describes a memory device having a lower electrode, a resistance changing element, an upper electrode, and a sidewall insulating film on a side surface of the resistance changing element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1A shows a cross-sectional view of some embodiments of a memory device with an etch stop layer. Fig. 1B shows a cross-sectional view of some alternative embodiments of a memory device with an etch stop layer. Fig. 2 shows a cross-sectional view of some embodiments of an integrated circuit with the memory device of Fig. 1A or Fig. 1B. The Fig. 3 - 7 show a series of cross-sectional views of some embodiments of a memory device at various stages of manufacture. Fig. 8 shows a flowchart of some embodiments of a method for manufacturing a memory device. The Fig. 9-13 show a series of cross-sectional views of some alternative embodiments of a memory device at various stages of manufacture. Fig. 14 shows a flowchart of some alternative embodiments of a method for manufacturing a memory device. DETAILED DESCRIPTION

[0009] The present disclosure contemplates many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0010] Furthermore, spatially relative terms such as "upper," "lowermost," "below," "beneath," "lower," "above," "above," and the like may be used herein for convenience of description to describe the relationship of one feature or device to one or more other features or devices, as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be differently oriented (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0011] Furthermore, "first," "second," "third," etc., may be used herein for convenience of description to distinguish between different elements of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding element. Therefore, "a first dielectric layer" described in connection with a first figure may not necessarily correspond to a "first dielectric layer" described in connection with another figure.

[0012] A non-volatile memory device includes a memory cell array having a plurality of memory cells. Each of the memory cells includes a top electrode and a bottom electrode separated by a switching dielectric. Depending on a voltage applied to the electrode pair, the switching dielectric undergoes a reversible change between a high resistance state associated with a first data state (e.g., "0" or "RESET") and a low resistance state associated with a second data state (e.g., "1" or "SET"). The memory cell is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes and can be inserted between a bottom metallization line and a top metallization line for data storage and transfer. In some applications, the memory device can include memory cells of different sizes.The memory cells can have different lateral dimensions as well as different vertical thicknesses. Thus, the height from the bottom metallization line to a top electrode of a memory cell can vary depending on the memory cell size. The variation in vertical heights makes it challenging to expose the top electrodes of memory cells of different sizes during manufacturing: A top electrode of a smaller memory cell may not be properly exposed before damaging another top electrode of a larger memory cell.

[0013] The present application relates to an improved memory device having an etch stop layer lining a memory cell and related fabrication methods. In some embodiments, for example, with reference to Fig. 1A or Fig. 1B, a memory device includes a first memory cell 114a and a second memory cell 114b disposed over a substrate 102. Each of the memory cells 114a, 114b includes a bottom electrode 112, a switching dielectric 116 disposed over the bottom electrode 112 and having a variable resistance, and an upper electrode 118 disposed over the switching dielectric 116. The bottom electrode 112 is connected to a bottom electrode via 110 surrounded by a bottom dielectric layer 108. A sidewall spacer layer 126 is disposed over the bottom electrode via 110 and the bottom dielectric layer 108 and extends upward along sidewalls of the bottom electrode 112, the switching dielectric 116, and the top electrode 118.A lower etch stop layer 120 is disposed over the lower dielectric layer 108 and lines an outer sidewall of the sidewall spacer layer 126. An upper dielectric layer 136 is disposed on the lower etch stop layer 120 and surrounds an upper portion of the sidewall spacer layer 126. The lower etch stop layer 120 is composed of a dielectric that may protect the memory cell 114a, 114b during polishing and etching processes for exposing the upper electrode. For example, the lower etch stop layer 120 and the upper dielectric layer 136 may be disposed over the memory cell 114a, 114b (see, for example, FIG. Fig. 4) and then subjected to an etch-back process to expose the upper electrode 118 (see, for example, Fig. 6). The lower etch stop layer 120 may comprise a dielectric having a different etch selectivity than the upper dielectric layer 136 with respect to the etchant of the etch-back process, so that the lower etch stop layer 120 can be preserved and protects the upper electrode from damage. This allows for better control of the polishing and etching processes, and the upper electrode 118 of the memory cell 114a, 114b can be well exposed after a more precisely controlled removal of the lower etch stop layer 120.

[0014] The bottom electrode 112 of the memory cell 114a, 114b is made of a conductive material such as titanium nitride. The bottom electrode 112 may also comprise, for example, titanium, tantalum, tantalum nitride, platinum, iridium, tungsten, ruthenium, or the like. In some embodiments, the memory cell 114a, 114b is a magnetoresistive random access memory (MRAM) cell, and the resistive switching dielectric 116 may comprise a magnetic tunnel junction (MTJ) structure with a bottom ferromagnetic layer and an top ferromagnetic layer separated by a tunnel barrier layer. In some further embodiments, the memory cell 114a, 114b is a resistive random access memory (RRAM) cell, and the resistive switching dielectric 116 may comprise an RRAM dielectric layer. The switching dielectric 116 may comprise a high-k layer (ieThe bottom electrode via 110 may be a layer having a dielectric constant k greater than 3.9, for example tantalum oxide, tantalum hafnium oxide, tantalum aluminum oxide, or another material comprising tantalum, oxygen, and one or more other elements. The bottom electrode via 110 is made of a conductive material such as platinum, iridium, ruthenium, or tungsten. The bottom dielectric layer 108 surrounds the bottom electrode via 110 and includes one or more layers of dielectrics. The bottom dielectric layer 108 may include silicon carbide, silicon nitride, silicon oxide, or one or more layers of composite dielectric films. For example, the bottom dielectric layer 108 may include a silicon-rich oxide layer 108b disposed on a silicon carbide layer 108a. The bottom electrode via 110 may connect to the memory cell 114a, 114b shown in FIGS. Fig. 1A or Fig. 1B, may be connected to a lower metallization line 106 disposed in a lower interlayer dielectric layer 104. The lower electrode via 110 may also serve as a diffusion barrier layer to prevent the material of the lower metallization lines 106 from diffusing into the lower electrode 112. The lower metallization line 106 may, for example, be made of a metal such as copper. The lower interlayer dielectric layer 104 may, for example, be made of an oxide, a low-k dielectric (i.e., a dielectric with a lower dielectric constant k than silicon dioxide), or an extreme-low-k dielectric (a dielectric with a dielectric constant k of less than about 2).

[0015] In some embodiments, the top electrode 118 may include one or more metal or metal interconnect layers, including, for example, titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the top electrode 118 is electrically connected to the top metallization line 134 of the top interconnect structure 142 via a top electrode via 132 disposed between the top electrode 118 and the top metallization line 134. The top electrode via 132 may be made of, for example, a conductive material such as copper, aluminum, or tungsten. During operation of the memory cell 114a, 114b, voltages are applied between the top electrode 118 and the bottom electrode 112 to read, set, or erase the memory cell 114a, 114b by forming or breaking one or more conductive filaments of the switching dielectric 116.Thus, the memory cell 114a, 114b may have a variable resistance in a comparatively low or high resistance state, so that it represents, for example, a low or high bit state.

[0016] As in Fig. 1A, in some embodiments, the sidewall spacer layer 126 is disposed directly on the bottom dielectric layer 108 and contacts sidewalls of the bottom electrode 112, the switching dielectric 116, and the top electrode 118. The sidewall spacer layer 126 protects the bottom electrode 112, the switching dielectric 116, and the top electrode 118 from short circuits. In some embodiments, the top surface of the sidewall spacer layer 126 is lower than that of the top electrode 118, such that a topmost point of the sidewall spacer layer 126 is disposed on the sidewall surface of the top electrode 118. The bottom etch stop layer 120 is disposed adjacent to the sidewall spacer layer 126 and directly on the bottom dielectric layer 108.In some embodiments, the lower etch stop layer 120 extends laterally between the memory cells 114a, 114b and extends upward to cover sidewall and top surfaces of the sidewall spacer layer 126. The upper dielectric layer 136 may be disposed directly on the lower etch stop layer 120. In some embodiments, the sidewall spacer layer 126 is separated from the upper dielectric layer 136 by the lower etch stop layer 120. The upper dielectric layer 136 may have a lower surface that is separated from an upper surface of the lower dielectric layer 108 by the lower etch stop layer 120. The lower etch stop layer 120 and the upper electrode 118 may have upper surfaces that are aligned or coplanar and may further be coplanar with an upper surface of the upper dielectric layer 136.The upper electrode 118 may be connected to an upper metallization line 134 through an upper electrode via 132. The upper metallization line 134 and the upper electrode via 132 are surrounded by an upper interlayer dielectric layer 138. In some embodiments, the lower surfaces of the upper metallization line 134 and the upper interlayer dielectric layer 138 and the upper surfaces of the upper electrode 118 and the lower etch stop layer 120 are coplanar. The lower etch stop layer 120 is composed of a dielectric different from that of the sidewall spacer layer 126. The sidewall spacer layer 126 may, for example, comprise silicon nitride. The upper dielectric layer 136 may, for example, comprise silicon dioxide. The lower etch stop layer 120 may be composed of silicon oxynitride.During the manufacturing process, the lower etch stop layer 120 is more resistant to the etchant (compared to the upper dielectric layer 136 or the sidewall spacer layer 126) when the upper electrode 118 is exposed, thereby providing additional support and protection from damage to the upper electrode 118. For example, the lower etch stop layer 120 may have an etchant etch rate that is approximately ten times lower than that of the upper dielectric layer 136 or the sidewall spacer layer 126.

[0017] As in Fig. 1B, in some alternative embodiments, the sidewall spacer layer 126 is disposed directly on the lower dielectric layer 108 and extends in a lateral direction continuously between the memory cells 114a, 114b, while the sidewall spacer layer 126 in the embodiments shown in Fig. 1A, has separate sections that respectively surround the memory cells 114a, 114b. The lower etch stop layer 120 is disposed directly on the sidewall spacer layer 126. Thus, the sidewall spacer layer 126 may separate the lower etch stop layer 120 from the lower dielectric layer 108. The sidewall spacer layer 126 extends upward and contacts sidewalls of the lower electrode 112, the switching dielectric 116, and the upper electrode 118. In some embodiments, the upper surface of the sidewall spacer layer 126 is coplanar with upper surfaces of the upper electrode 118 and the lower etch stop layer 120. The upper dielectric layer 136 may be disposed directly on the lower etch stop layer 120 and has an upper surface that is coplanar with that of the lower etch stop layer 120. Similar to the embodiments shown in Fig. 1A, the sidewall spacer layer 126 protects the bottom electrode 112, the switching dielectric 116, and the top electrode 118 from short circuits. The top electrode 118 may be connected to an upper metallization line 134 through a top electrode via 132 surrounded by an upper interlayer dielectric layer 138. In some embodiments, the bottom surfaces of the top metallization line 134 and the upper interlayer dielectric layer 138 and the top surfaces of the top electrode 118, the sidewall spacer layer 126, and the bottom etch stop layer 120 are coplanar. The bottom etch stop layer 120 is composed of a dielectric different from that of the sidewall spacer layer 126. The sidewall spacer layer 126 may, for example, comprise silicon nitride. The upper dielectric layer 136 may comprise, for example, silicon dioxide.The lower etch stop layer 120 may be made of silicon oxynitride. During the manufacturing process, the lower etch stop layer 120 is more resistant to the etchant (compared to the upper dielectric layer 136 or the sidewall spacer layer 126) when the upper electrode 118 is exposed, thereby providing additional support and protection from damage to the upper electrode 118.

[0018] Fig. Figure 2 shows a cross-sectional view of an integrated circuit device 200 including a memory cell 201 according to some additional embodiments. The memory cell 201 may have the same structure as the memory cell 114a, 114b shown in Figures Fig. 1A or Fig. 1B and described above. As shown in Fig. As shown in Figure 2, the memory cell 201 may be disposed over a substrate 202. The substrate 202 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. One or more shallow trench isolation (STI) regions 204 or oxide-filled trenches are disposed in the substrate 202. A pair of wordline transistors 206, 208 are spaced between the STI regions 204. The wordline transistors 206, 208 extend parallel to each other and include wordline gates 210, which are separated from the substrate 202 by wordline dielectric layers 212, and source / drain regions 214, 216. The source / drain regions 214, 216 are embedded in the surface of the substrate 202 between the wordline gates 210 and the STI regions 204. The wordline gates 210 can be made of, for example, doped polysilicon or a metal such as titanium nitride or tantalum nitride.The wordline dielectric layers 212 may be made of an oxide, such as silicon dioxide, for example. A bottom ILD layer 238 is disposed above the wordline transistors 206, 208. The bottom ILD layer 238 may be made of an oxide.

[0019] A back-end-of-line (BEOL) metallization stack 218 is disposed over the wordline transistors 206, 208. The BEOL metallization stack 218 includes a plurality of metallization layers 222, 224, 226 disposed within the interlayer dielectric layers 220, 228, 230, respectively. The metallization layers 222, 224, 226 may be made of a metal such as copper or aluminum, for example. The interlayer dielectric layers 220, 228, 230 may be made of a low-k dielectric such as porous undoped silicate glass or an oxide such as silicon dioxide, for example. Dielectric layers 108, 242 may be arranged to separate the interlayer dielectric layers 220, 228, 230. The metallization layers 222, 224, 226 include a source line 232 coupled to the source / drain region 214 shared by the word line transistors 206, 208.Furthermore, the metallization layers 222, 224, 226 include a bit line 134 connected to the memory cell 201 and further connected to the source / drain region 216 of the wordline transistor 206 or the wordline transistor 208 via a plurality of metallization lines, such as the metallization lines 106, 234, and a plurality of vias, such as the vias 132, 110, 240. A contact 236 extends from the metallization line 234 through the bottommost ILD layer 238 to reach the source / drain region 216. The vias 132, 110, 240 and the contact 236 may be made of a metal such as copper, gold, or tungsten, for example.

[0020] The memory cell 201 is inserted between an upper metallization line 134 and a lower metallization line 106. Similar to the above in connection with the Fig. 1A or Fig. 1B, the memory cell 201 includes a bottom electrode 112 connected to or seamlessly contacting a bottom electrode via 110. A switching dielectric 116 is disposed over the bottom electrode 112. An upper electrode 118 is disposed over the switching dielectric 116. A sidewall spacer layer 126 extends upward along sidewalls of the bottom electrode 112, the switching dielectric 116, and the upper electrode 118. A bottom etch stop layer 120 is disposed on the sidewall spacer layer 126. An upper dielectric layer 136 is disposed on the bottom etch stop layer and over the memory cell 201. The upper dielectric layer 136 may be comprised of an oxide.The lower etch stop layer 120 has an etch selectivity that is different from that of the upper dielectric layer 136 and / or the sidewall spacer layer 126, such that the lower etch stop layer 120 covers and protects the upper electrode 118 when the precursor materials of the upper dielectric layer 136 and / or the sidewall spacer layer 126 are etched back to expose the upper electrode 118. A top electrode via 132 connects the top electrode 118 to the top metallization line 134. Although the memory cell 201 in . Fig. 2 as being inserted between the upper metallization layer 226 and the lower metallization layer 224, it should be noted that the memory cell 201 may be inserted between any two of the metallization layers of the BEOL metallization stack 218.

[0021] The Fig. 3 - 7 show a series of cross-sectional views of some embodiments of a memory device at various stages of manufacture.

[0022] As shown in cross-sectional view 300 of Fig. 3, a first memory cell stack 302a and a second memory cell stack 302b are formed side by side over a substrate 102 by depositing a multilayer stack using a variety of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.), followed by one or more patterning processes. The first memory cell stack 302a and the second memory cell stack 302b can be formed with different sizes. Both the first and second memory cell stacks 302a, 302b include a bottom electrode 112, a switching dielectric 116 over the bottom electrode 112, an top electrode 118 over the switching dielectric 116, and a sidewall spacer layer 126 adjacent to sidewalls of the bottom electrode 112, the switching dielectric 116, and the top electrode 118.The sidewall spacer layer 126 may be formed by depositing a dielectric spacer layer on a top surface of the lower dielectric layer 108, extending along sidewall surfaces of the lower electrode 112, the switching dielectric 116, and the upper electrode 118, and covering a top surface of the upper electrode 118. Then, an anisotropic etch (e.g., a vertical etch) may be performed on the dielectric spacer layer to remove lateral portions of the dielectric spacer layer, resulting in the sidewall spacer layer 126. As a result, the sidewall spacer layer 126 may have a top surface lower than that of the upper electrode 118. The top surface of the sidewall spacer layer 126 may also be aligned with or lower than a top surface of the upper electrode 118.The dielectric spacer layer may comprise silicon nitride, tetraethyl orthosilicate (TEOS), silicon-rich oxide (SRO), or a similar dielectric composite film. In some embodiments, the dielectric spacer layer may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0023] As shown in cross-sectional view 400 of Fig. 4, a plurality of dielectric layers are formed above and between the first memory cell stack 302a and the second memory cell stack 302b. The plurality of dielectric layers may include a lower etch stop layer 120 formed above and lining the substrate 102 between the first and second memory cell stacks 302a, 302b, an upper dielectric layer 136 formed above the lower etch stop layer 120, an upper etch stop layer 402 formed above the upper dielectric layer 136, and a polish precursor layer 404 formed above the upper etch stop layer 402. The lower etch stop layer 120 may be comprised of a dielectric different from that of the sidewall spacer layer 126 and the upper dielectric layer 136. The lower etch stop layer 120 may, for example, consist of silicon oxynitride (SiON).The upper dielectric layer 136 may, for example, be made of a low-k or an extremely low-k dielectric. In some embodiments, the upper etch stop layer 402 and the lower etch stop layer 120 are made of the same material. The upper dielectric layer 136 and the polish precursor layer 404 may be made of silicon dioxide and may be formed by plasma-enhanced atomic layer deposition (PEALD).

[0024] As shown in cross-sectional view 500 of Fig. 5, a first planarization / recess process is performed to partially remove the upper etch stop layer 402 and the polish precursor layer 404. In some embodiments, the first planarization / recess process is a chemical mechanical polishing (CMP) process. The first planarization / recess process may be substantially non-selective for the upper etch stop layer 402 and the polish precursor layer 404, such that the upper etch stop layer 402 and the polish precursor layer 404 may have coplanar upper surfaces as an etch result. After the first etch, a portion of the polish precursor layer 404 and a portion of the upper etch stop layer 402 directly above the first memory cell stack 302a and the second memory cell stack 302b are removed by the first planarization / recess process.A remaining portion of the polish precursor layer 404 between the first memory cell stack 302a and the second memory cell stack 302b has sidewall and bottom surfaces surrounded by the remaining portion of the upper etch stop layer 402. A portion of the upper dielectric layer 136 directly above the memory cell stacks 302a, 302b is exposed. The exposed portion of the upper dielectric layer 136 may have a top surface that is substantially coplanar with the top surface of the etch stop layer 402 or the polish precursor layer 404.

[0025] As shown in cross-sectional view 600 of Fig. 6, a second planarization / recess process is performed to further lower the plurality of dielectric layers. The polish precursor layer 404 may be removed, and the upper etch stop layer 402 may be exposed in an edge region of the memory cell stacks 302a, 302b. A portion of the lower etch stop layer 120 directly above the memory cell stacks 302a, 302b is exposed. In some embodiments, the second planarization / recess process is a chemical mechanical polishing (CMP) process. The second planarization / recess process may be highly selective for the upper dielectric layer 136 over the upper etch stop layer 402 and the lower etch stop layer 120. For example, the upper dielectric layer 136 (e.g., a PEALD oxide layer) may have a removal rate that is approximately ten times greater than that of the lower etch stop layer 120 (e.g.,a SiON layer) and the upper etch stop layer 402 (e.g., a SiON layer). The lower etch stop layer 120 is more resistant to the etchant (compared to the upper dielectric layer 136), thereby providing additional support and protection from damage to the upper electrode 118. The lower etch stop layer 120 may be made of a material with an etch rate that is lower (e.g., about 50% lower) than that of the sidewall spacer layer 126 (e.g., a SiN layer), so that more support for the memory cell stacks 302a, 302b and the edge region may be provided by the lower etch stop layer 120 and the upper etch stop layer 402 during the first and second planarization / recess processes.

[0026] As shown in cross-sectional view 700 of Fig. 7, a full-surface etch is performed to form the upper etch stop layer 402 (in Fig. 6) and to further lower the lower etch stop layer 120 and the upper dielectric layer 136. As a result of the etching, the upper electrodes 118 of the first and second memory cell stacks 302a, 302b are exposed. In some embodiments, for example with respect to Fig. 2, after performing the full-area etch, an interlayer dielectric layer 230 is formed over the top electrode 118, the sidewall spacer layer 126, and the top dielectric layer 136. A top electrode via 132 is formed to extend through the interlayer dielectric layer 230 to reach the top electrode 118.

[0027] Fig. 8 shows some embodiments of a flowchart of a method 800 for forming a memory device. Although the method 800 is similar to the Fig. 3 - 7, it should be noted that the method 800 is not limited to those structures described in the Fig. 3 - 7, but instead independent of the ones in the Fig. 3 - 7 can stand alone. Similarly, it is understood that the structures disclosed in the Fig. 3-7 are not limited to the method 800, but instead may stand alone as structures independent of the method 800. Although disclosed methods (e.g., the method 800) are shown and described below as a sequence of acts or events, it should be understood that the shown order of such acts or events is not to be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. In addition, not all acts shown may be required to implement one or more aspects or embodiments of the present description. Further, one or more of the acts shown herein may be performed in one or more separate steps and / or phases.

[0028] At 802, a first memory cell stack and a second memory cell stack are formed adjacent to each other over a substrate by depositing a multilayer stack followed by one or more patterning processes. A sidewall spacer layer is formed adjacent to sidewalls of a bottom electrode, a switching dielectric, and a top electrode of the memory cell stack. The sidewall spacer layer may be formed to have a top surface lower than that of the top electrode. The top surface of the sidewall spacer layer may also be aligned with or lower than a top surface of the top electrode. Fig. 3 shows some embodiments of a cross-sectional view 300 corresponding to operation 802.

[0029] At 804, a plurality of dielectric layers are formed above and between the first memory cell stack and the second memory cell stack. The plurality of dielectric layers may include a lower etch stop layer formed above the substrate and between the first and second memory cell stacks, an upper dielectric layer formed above the lower etch stop layer, an upper etch stop layer formed above the upper dielectric layer, and a polish precursor layer formed above the upper etch stop layer. The lower etch stop layer may be made of silicon oxynitride (SiON), for example. Fig. 4 shows some embodiments of a cross-sectional view 400 corresponding to operation 804.

[0030] At 806, a first planarization / recess process is performed to partially remove the upper etch stop layer and the polish precursor layer. In some embodiments, the first planarization / recess process is a chemical mechanical polishing (CMP) process. The first planarization / recess process may be substantially non-selective to the upper etch stop layer and the polish precursor layer. A portion of the polish precursor layer and a portion of the upper etch stop layer directly above the first and second memory cell stacks are removed by the first planarization / recess process. A remaining portion of the polish precursor layer between the first memory cell stack and the second memory cell stack includes sidewall and bottom surfaces surrounded by the remaining portion of the upper etch stop layer.A portion of the upper dielectric layer directly above the memory cell stacks is exposed. Fig. 5 shows some embodiments of a cross-sectional view 500 corresponding to operation 806.

[0031] At 808, a second planarization / recess process is performed to further lower the plurality of dielectric layers. The polish precursor layer may be removed, and the upper etch stop layer may be exposed in an edge region of the memory cell stacks. A portion of the lower etch stop layer directly above the memory cell stacks is exposed. In some embodiments, the second planarization / recess process is a chemical mechanical polishing (CMP) process. Fig. 6 shows some embodiments of a cross-sectional view 600 corresponding to operation 808.

[0032] At 810, a full-surface etch is performed to remove the upper etch stop layer and further lower the lower etch stop layer and the upper dielectric layer. The upper electrodes of the first and second memory cell stacks are exposed. Fig. 7 shows some embodiments of a cross-sectional view 700 corresponding to operation 810.

[0033] The Fig. 9-13 show a series of cross-sectional views of some embodiments of a memory device at various stages of manufacture.

[0034] As shown in cross-sectional view 900 of Fig. 9, a first memory cell stack 302a and a second memory cell stack 302b are formed side by side over a substrate 102 by depositing a multilayer stack through a variety of vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.), followed by one or more patterning processes. The first memory cell stack 302a and the second memory cell stack 302b may be formed with different sizes. Both the first and second memory cell stacks 302a, 302b include a bottom electrode 112, a switching dielectric 116 over the bottom electrode 112, and a top electrode 118 over the switching dielectric 116. In some embodiments, the bottom electrode 112 is connected to a bottom electrode via 110 surrounded by a bottom dielectric layer 108.A sidewall spacer layer 126 is formed by depositing a dielectric spacer layer conformally and directly onto the bottom dielectric layer 108 and extending upward along sidewalls of the bottom electrode 112, the switching dielectric 116, and the top electrode 118. The dielectric spacer layer may comprise silicon nitride, tetraethyl orthosilicate (TEOS), silicon-rich oxide (SRO), or a similar dielectric composite film. In some embodiments, the dielectric spacer layer may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0035] As shown in the cross-sectional view 1000 of Fig. 10, a plurality of dielectric layers are formed above and between the first memory cell stack 302a and the second memory cell stack 302b and following the curvature of the memory cell stacks 302a, 302b. The plurality of dielectric layers may include a lower etch stop layer 120 formed directly on the sidewall spacer layer 126, an upper dielectric layer 136 formed on the lower etch stop layer 120, an upper etch stop layer 1002 formed over the upper dielectric layer 136, an oxygen-containing dielectric layer 1004 formed over the upper etch stop layer 1002, and a polish precursor layer 1006 formed over the oxygen-containing dielectric layer 1004. The lower etch stop layer 120 may be comprised of a dielectric different from that of the sidewall spacer layer 126 and the upper dielectric layer 136.The lower etch stop layer 120 may be made of silicon oxynitride (SiON), for example. The upper dielectric layer 136 may be made of a low-k or an extreme-low-k dielectric, for example. In some embodiments, the upper etch stop layer 1002 and the lower etch stop layer 120 are made of the same material. The upper dielectric layer 136 may be made of silicon dioxide and may be formed by plasma-enhanced atomic layer deposition (PEALD). The oxygen-containing dielectric layer 1004 may comprise tetraethyl orthosilicate (TEOS). The polish precursor layer 1006 may comprise an anti-reflective coating material (e.g., a carbon-containing BARC material).

[0036] As shown in cross-sectional view 1100 of Fig. 11, a first planarization / recess process is performed to partially remove the upper etch stop layer 1002, the oxygen-containing dielectric layer 1004, and the polish precursor layer 1006. In some embodiments, the first planarization / recess process includes a dry etch process that is selective for the polish precursor layer 1006 compared to the upper etch stop layer 1002. For example, the dry etch process has a ratio of the etch rate of the polish precursor layer 1006 to that of the upper etch stop layer 1002 of greater than 6:1. The dry etch is stopped on the upper etch stop layer 1002 once oxygen of the oxygen-containing dielectric layer 1004 is detected.Then, an overetch is performed to remove the oxygen-containing dielectric layer 1004 and the upper etch stop layer 1002 and to expose the upper dielectric layer 136 above the first memory cell stack 302a and the second memory cell stack 302b.

[0037] As shown in the cross-sectional view 1200 of Fig. 12, a second planarization / recess process is performed to further lower the plurality of dielectric layers. The polish precursor layer 1006 may be removed, and the upper etch stop layer 1002 may be exposed in an edge region of the memory cell stacks 302a, 302b. A portion of the lower etch stop layer 120 directly above the memory cell stacks 302a, 302b is exposed. In some embodiments, the second planarization / recess process is a chemical mechanical polishing (CMP) process. The second planarization / recess process may be highly selective for the upper dielectric layer 136 over the upper etch stop layer 1002 and the lower etch stop layer 120. For example, the upper dielectric layer 136 (e.g., a PEALD oxide layer) may have a removal rate that is approximately ten times greater than that of the lower etch stop layer 120 (e.g.,a SiON layer) and the upper etch stop layer 402 (e.g., a SiON layer). The lower etch stop layer 120 is more resistant to the etchant (compared to the upper dielectric layer 136), thereby providing additional support and protection from damage to the upper electrode 118. The lower etch stop layer 120 may be made of a material with an etch rate that is lower (e.g., about 50% lower) than that of the sidewall spacer layer 126 (e.g., a SiN layer), so that more support for the memory cell stacks 302a, 302b and the edge region may be provided by the lower etch stop layer 120 and the upper etch stop layer 1002 during the first and second planarization / recess processes.

[0038] As shown in cross-sectional view 1300 of Fig. 13, a full-surface etching is performed to form the upper etch stop layer 1002 (in Fig. 12) and to further lower the lower etch stop layer 120 and the upper dielectric layer 136. As a result of the etching, the upper electrodes 118 of the first and second memory cell stacks 302a, 302b are exposed. In some embodiments, for example with respect to Fig. 2, after performing the full-area etch, an interlayer dielectric layer 230 is formed over the top electrode 118, the sidewall spacer layer 126, and the top dielectric layer 136. A top electrode via 132 is formed to extend through the interlayer dielectric layer 230 to reach the top electrode 118.

[0039] Fig. 14 shows some embodiments of a flowchart of a method 1400 for forming a memory device. Although the method 1400 is similar to the Fig. 9 - 13, it should be noted that the method 1400 is not limited to those structures described in the Fig. 9 - 13, but instead independent of the ones revealed in the Fig. 9 - 13. Similarly, it is understood that the structures disclosed in the Fig. 9-13 are not limited to the method 1400, but instead may stand alone as structures independent of the method 1400. Although disclosed methods (e.g., the method 1400) are shown and described below as a sequence of acts or events, it should be understood that the shown order of such acts or events is not to be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. In addition, not all acts shown may be required to implement one or more aspects or embodiments of the present description. Further, one or more of the acts shown herein may be performed in one or more separate steps and / or phases.

[0040] At 1402, a first memory cell stack and a second memory cell stack are formed adjacent to each other over a substrate by depositing a multilayer stack followed by one or more patterning processes. A sidewall spacer layer is formed on a lower dielectric layer adjacent to sidewalls of the memory cell stack. The sidewall spacer layer may be conformally formed. Fig. 9 shows some embodiments of a cross-sectional view 900 corresponding to operation 1402.

[0041] At 1404, a plurality of dielectric layers are formed above and between the first memory cell stack and the second memory cell stack. The plurality of dielectric layers may include a lower etch stop layer formed above the substrate and between the first and second memory cell stacks, an upper dielectric layer formed above the lower etch stop layer, an upper etch stop layer formed above the upper dielectric layer, and an oxygen-containing dielectric layer and a polish precursor layer formed above the upper etch stop layer. The lower etch stop layer may be made of silicon oxynitride (SiON), for example. Fig. 10 shows some embodiments of a cross-sectional view 1000 corresponding to operation 1404.

[0042] At 1406, a first planarization / recess process is performed to partially remove the upper etch stop layer and the polish precursor layer. In some embodiments, the first planarization / recess process includes a dry etch process selective for the polish precursor layer. The dry etch process stops on the oxygen-containing dielectric layer and is followed by a more precisely controlled etch to achieve a planar surface after etching. After the first planarization / recess process, a portion of the upper dielectric layer is exposed directly above the memory cell stacks. Fig. 11 shows some embodiments of a cross-sectional view 1100 corresponding to operation 1406.

[0043] At 1408, a second planarization / recess process is performed to further lower the plurality of dielectric layers. The polish precursor layer may be removed, and the upper etch stop layer may be exposed in an edge region of the memory cell stacks. A portion of the lower etch stop layer directly above the memory cell stacks is exposed. In some embodiments, the second planarization / recess process is a chemical mechanical polishing (CMP) process. Fig. 12 shows some embodiments of a cross-sectional view 1200 corresponding to operation 1408.

[0044] At 1410, a full-surface etch is performed to remove the upper etch stop layer and further lower the lower etch stop layer and the upper dielectric layer. The upper electrodes of the first and second memory cell stacks are exposed. Fig.13 shows some embodiments of a cross-sectional view 1300 corresponding to operation 1410.

[0045] It should be noted that in describing aspects of the methodologies described herein, reference is made to exemplary structures. The methodologies (and structures) are to be considered independent of each other and capable of standing alone, and can be practiced independently of the specific aspects shown in the figures. Additionally, layers described herein can be formed in any suitable manner, such as spin-coating, sputtering, growth, and / or deposition techniques, etc.

[0046] The invention is defined by the main claim and the subordinate claims. The subclaims further describe embodiments of the invention.

Claims

[1] A storage device (100a) comprising: a lower electrode via (110) surrounded by a lower dielectric layer (108) and disposed over a substrate (102); a lower electrode (112) disposed on the lower electrode via (110); a switching dielectric (116) disposed over the lower electrode (112) and having a variable resistance; an upper electrode (118) disposed above the switching dielectric (116); a sidewall spacer layer (126) extending upwardly along sidewalls of the lower electrode (112), the switching dielectric (116), and the upper electrode (118); a lower etch stop layer (120) disposed over the lower dielectric layer (108) and lining an outer sidewall of the sidewall spacer layer (126); an upper dielectric layer (136) disposed on the lower etch stop layer (120) and surrounding an upper portion of the sidewall spacer layer (126); and an upper interlayer dielectric layer (138) adjacent to upper surfaces of the lower etch stop layer (120) and the upper dielectric layer (136); wherein the lower etch stop layer (120) is made of a material different from that of the sidewall spacer layer (126); the upper surfaces of the lower etch stop layer (120) and the upper dielectric layer (136) are coplanar; and the lower etch stop layer (120) extends continuously from the lower dielectric layer (108) to the upper interlayer dielectric layer (138). [2] The memory device (100a) of claim 1, wherein the lower etch stop layer (120) is made of silicon oxynitride and the sidewall spacer layer (126) is made of silicon nitride. [3] The memory device (100a) of any preceding claim, wherein an upper surface of the sidewall spacer layer (126) directly contacts and is covered by the lower etch stop layer (120) and is lower than an upper surface of the upper electrode (118). [4] A memory device (100a) according to any one of the preceding claims, wherein the lower electrode (112) is made of titanium nitride. [5] The memory device (100a) of any preceding claim, wherein the lower etch stop layer (120) directly contacts the upper dielectric layer (136). [6] The memory device (100a) of any preceding claim, wherein the sidewall spacer layer (126) is separated from the upper dielectric layer (136) by the lower etch stop layer (120). [7] The memory device (100a) of any preceding claim, wherein the lower etch stop layer (120) is made of silicon oxynitride and the upper dielectric layer (136) is made of silicon oxide. [8] Storage device (100a) according to one of the preceding claims, further comprising: a lower metallization line (106) surrounded by a lower interlayer dielectric layer (104) and connected to the lower electrode (112) through the lower electrode via (110); and an upper metallization line (134) surrounded by the upper interlayer dielectric layer (138) and directly contacting the upper electrode (118). [9] The memory device (100a) of claim 8, wherein lower surfaces of the upper metallization line (134) and the upper interlayer dielectric layer (138) and upper surfaces of the upper electrode (118) and the lower etch stop layer (120) are coplanar. [10] A method (800) for manufacturing a memory device, comprising: Forming (802) and patterning a first memory cell stack (302a) and a second memory cell stack (302b) of different sizes next to each other over a substrate (102), each of the memory cell stacks comprising a bottom electrode (112), a switching dielectric (116) over the bottom electrode (112), a top electrode (118) over the switching dielectric (116), and a sidewall spacer layer (126) adjacent to sidewalls of the first memory cell stack (302a) and the second memory cell stack (302b); Forming (804) a lower etch stop layer (120) over the substrate (102) between and lining the first and second memory cell stacks (302a, 302b); after forming (804) the lower etch stop layer (120), forming (804) an upper dielectric layer (136) over the substrate (102) between and lining the first and second memory cell stacks; Forming (804) an upper etch stop layer (402) over the upper dielectric layer (136); Performing (806) a first chemical mechanical polishing (CMP) process to expose the upper dielectric layer (136) directly above the memory cell stacks; after performing (806) the first CMP process, performing (808) a second CMP process to further lower the upper etch stop layer (402) and expose the lower etch stop layer (120) directly above the memory cell stacks (302a, 302b); and Performing (810) a full-area etch to remove the upper etch stop layer (402) and further lower the upper dielectric layer (136) and expose the upper electrodes (118) of the first and second memory cell stacks. [11] The method (800) of claim 10, further comprising, prior to performing the first CMP process: Forming (804) a polishing precursor layer (404) over the upper etch stop layer (402); wherein a portion of the polishing precursor layer (404) directly above the first memory cell stack (302a) and the second memory cell stack (302b) is removed by the first CMP process, and a remaining portion of the polishing precursor layer between the first memory cell stack and the second memory cell stack has sidewall and bottom surfaces surrounded by the upper etch stop layer (402). [12] The method (800) of claim 11, further comprising: performing (1406) a dry etch-back process on the polishing precursor layer (404) before performing the first CMP process; wherein the dry etch-back process has a ratio of the etch rate of the polishing precursor layer (404) to that of the upper dielectric layer (136) of greater than 6:

1. [13] The method (800) of claim 11 or 12, wherein the upper dielectric layer (136) and the polishing precursor layer (404) are formed by plasma enhanced atomic layer deposition. [14] The method (800) of any one of claims 11 to 13, wherein the first CMP process (806) has a substantially equal etch rate for the upper etch stop layer (402) and the polish precursor layer (404). [15] The method (800) of any one of claims 10 to 14, wherein the sidewall spacer layer (126) comprises silicon nitride. [16] The method (800) of claim 15, wherein the upper etch stop layer (402) and the lower etch stop layer (120) are made of the same material. [17] The method of claim 15 or 16, wherein the upper etch stop layer (402) and the lower etch stop layer (120) are made of silicon oxynitride. [18] The method of any one of claims 10 to 17, further comprising, after performing (810) the full-surface etching: Forming an interlayer dielectric layer (138) over the top electrode (118), the sidewall spacer layer (126) and the top dielectric layer (136); and Forming a top electrode via (132) extending through the dielectric layer (138) to reach the top electrode (118). [19] A method (1400) for manufacturing a memory device, comprising: Forming (1402) and patterning a first memory cell stack (302a) and a second memory cell stack (302b) of different sizes side by side over a substrate (102), each of the memory cell stacks comprising a bottom electrode (112), a switching dielectric (116) over the bottom electrode (112), an top electrode (118) over the switching dielectric (116), and a sidewall spacer layer (126) adjacent to sidewalls of the bottom electrode (112), the switching dielectric (116), and the top electrode (118); Forming (1404) a lower etch stop layer (120) over the substrate (102) between and lining the first and second memory cell stacks (302a, 302b); Forming (1404) an upper dielectric layer (136) over the lower etch stop layer (120); Forming (1404) an upper etch stop layer (1002) over the upper dielectric layer (136); Forming (1404) a polishing precursor layer (1006) over the upper etch stop layer (1002); Performing (1406) a first chemical mechanical polishing process to expose the upper dielectric layer (136) directly above the memory cell stacks (302a, 302b); Performing (1408) a second chemical-mechanical polishing process to lower the upper etch stop layer (1002) between the memory cell stacks (302a, 302b) and expose the lower etch stop layer (120) directly above the memory cell stacks; and Performing (1401) a full-area etch to remove the upper etch stop layer (1002) and partially remove the lower etch stop layer (120) and expose the upper electrodes (118) of the first and second memory cell stacks (302a, 302b).

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