MOS power transistors in parallel channel configuration

Abstract

Circuit that features: a first MOS power transistor (111) with a first gate terminal, a first drain terminal and a first source terminal, a second MOS power transistor (121) with a second gate terminal, a second drain terminal and a second source terminal, a first control circuit (115) configured to output a control signal to the first gate terminal, a second control circuit (125) configured to output a control signal to the second gate terminal, a switch (301) which is connected between the first gate terminal and the second gate terminal and is configured to selectively couple the first gate terminal and the second gate terminal.

Description

[0001] Several examples involve a circuit containing multiple metal-oxide-semiconductor power transistors. Several examples specifically involve a switch connected between the gate terminals of multiple metal-oxide-semiconductor power transistors.

[0002] Circuit breakers are typically used to selectively couple a load to a supply voltage. In recent years, "smart" circuit breaker devices have been developed, equipped with one or more diagnostic capabilities and protective features against fault conditions such as overload and short circuit. For example, a MOS power transistor can be used as the switching element in such circuit breaker devices. In the event of a fault condition, the MOS power transistor can operate in a defined state, such as a high-resistance state.

[0003] Certain applications require driving higher loads and / or reducing power losses. To achieve such goals, it is possible to implement multiple MOS power transistors in the circuit and equip it with the capability to support a parallel-channel configuration: In this configuration, the load is connected in series with the multiple MOS power transistors, and the MOS power transistors are connected in parallel. In the parallel-channel configuration, the current through each of the multiple MOS power transistors is reduced when the power switches are in a low-resistance state; this can increase the total current drawn by the load—which is the sum of the currents through the multiple MOS power transistors. A lower current through a single power transistor also reduces the power dissipated by that power transistor.

[0004] German patent DE 10 2014 106 294 A1 describes a semiconductor device with a first transistor element and a second transistor element, wherein a gate of the first transistor element is directly connected to a control terminal (gate terminal) of the semiconductor device and a gate of the second transistor element is connected to the control terminal via a control element. The control element switches on or off, for example, depending on a common drain-source voltage of the two transistor elements or depending on a drain-gate voltage of the first transistor element.

[0005] DE 10 2015 105 158 A1 describes an electronic circuit with a first and a second transistor, whose load paths are connected in parallel and whose gate terminals are coupled to each other via a switch in order to activate the second transistor when a drain-source voltage of the first transistor reaches a predetermined threshold.

[0006] German patent application DE 10 2005 051 004 A1 describes an electronic circuit with two transistors connected in parallel, the gate terminals of which are each connected to a control circuit via a gate resistor, so that the gate terminals are tightly coupled to each other. Each of the transistors also includes a clamping circuit between drain and source, which is designed to switch the transistor on during a transient of the drain-source voltage in order to protect the transistor from overvoltage.

[0007] WO 97 / 45957 A1 describes a transistor circuit with several MOSFETs, each with a gate terminal. The gate terminal of each MOSFET is connected via a separate transistor to a control terminal of the transistor circuit.

[0008] It has been observed that protecting MOS power transistors against fault conditions in a parallel channel configuration can be difficult.

[0009] Exemplary embodiments of the invention relate to a circuit according to claim 1 and a method according to claim 14.

[0010] It is understood that the features mentioned above and those to be explained below can be used not only in the respective combinations specified, but also in other combinations or in isolation, without deviating from the field of the invention. Fig. Figure 1 schematically illustrates a system according to various examples, in which the system includes a circuit with a first MOS power transistor and a second MOS power transistor, and in which the system further connects a load to the source terminals of both the first MOS power transistor and the second MOS power transistor, which are in a parallel channel configuration. Fig. Figure 2 schematically shows a circuit according to various examples. Fig. Figure 3 schematically shows a switch that selectively couples a gate terminal of a first MOS power transistor and a gate terminal of a second MOS power transistor, according to various examples. Fig. Figure 4 is a flowchart of a procedure according to various examples. Fig. Figure 5 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor, the circuit further including a control circuit for the first MOS power transistor and for the second MOS power transistor, according to various examples. Fig. 6A is a flowchart of a procedure according to various examples. Fig. 6B is a flowchart of a procedure according to various examples. Fig. Figure 7 is a flowchart of a procedure according to various examples. Fig. Figure 8 schematically shows the time evolution of the voltage across a MOS power transistor according to various examples. Fig. Figure 9 schematically shows the time evolution of currents through MOS power transistors according to various examples. Fig. Figure 10 schematically shows the integrated dissipated energy for MOS power transistors according to various examples. Fig. Figure 11 schematically shows the time evolution of the voltage across a MOS power transistor according to various examples. Fig. Figure 12 schematically shows a time evolution of currents through MOS power transistors according to various examples. Fig. Figure 13 schematically shows the integrated dissipated energy for MOS power transistors according to various examples. Fig. Figure 14 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor. Fig. Figure 15 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor. Fig. Figure 16 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor. Fig. Figure 17 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor. Fig. Figure 18 schematically shows a circuit containing a first MOS power transistor and a second MOS power transistor and a switch between the gate terminals of the first MOS power transistor and the second MOS power transistor.

[0011] The following section describes embodiments of the invention in detail with reference to the accompanying drawings. It is understood that the following description of embodiments is not to be understood in a limiting sense. The scope of the invention is not intended to be limited by the embodiments described below or by the drawings, which are to be understood as illustrative only.

[0012] The drawings are to be regarded as schematic representations, and the elements depicted in the drawings are not necessarily shown to scale. Rather, the various elements are represented in such a way that their function and general purpose are clear to a person skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. Coupling between elements may also be established via a wireless connection. Functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

[0013] The following describes techniques related to MOS power transistors. For example, the MOS power transistors can be implemented as field-effect transistors (FETs). Specifically, the MOS power transistors described herein could be implemented as double-diffused MOSFETs. The MOS power transistors can be implemented using a vertical source-drain channel or a horizontal source-drain channel. A gate terminal can be insulated using polyoxide or oxide. Each of the MOS power transistors can have an active area of ​​not less than 0.15 mm². 2 , optionally of not less than 0.25 mm 2These techniques simplify the switching of relatively high currents by operating the MOS power transistors in a high-resistance or low-resistance state. The channel resistance between the source and drain terminals can vary by orders of magnitude depending on whether the MOS power transistor is operated in a high-resistance or low-resistance state. The MOS power transistors are typically designed to exhibit relatively low resistance in the low-resistance state. This reduces losses when operating the MOS power transistors in the low-resistance state. Sometimes the high-resistance state is referred to as the OFF state, while the low-resistance state is referred to as the ON state. For example, currents of up to 5 A or even 50 A can be switched.The MOS power transistors can be integrated on a die or chip. It is possible for the MOS power transistors to occupy at least 5%, or optionally at least 10%, or optionally at least 50% of the active chip area. Typically, the chip area covered by the MOS power transistors also increases when higher currents need to be switched.

[0014] In general, MOS power transistors can have a gate terminal, a drain terminal, and a source terminal. A load current flows through the MOS power transistor between the drain and source terminals when the MOS power transistor is operated in a low-resistance state. In a stable state, there is no significant load current between the drain and source terminals when the MOS power transistor is operated in a high-resistance state. By applying a suitable control signal to the gate terminal, the MOS power transistor can be selectively operated in either a low-resistance or a high-resistance state.

[0015] During an emergency shutdown of the MOS power transistors—e.g., in response to the detection of a fault condition—and before reaching a stable state, significant discharge currents may flow through the MOS power transistors, even when operating in a high-resistance state. These inductive discharge currents, also known as inductive commutation currents, result from parasitic line inductances.

[0016] The techniques described herein facilitate the parallel-channel configuration of multiple MOS power transistors. In particular, these techniques simplify parallel-channel configuration by providing protection for the MOS power transistors against fault conditions. Damage to the MOS power transistors in the event of a fault condition can be avoided.

[0017] In particular, protection against a wide variety of fault conditions can be provided. Example fault conditions include overcurrent through the MOS power transistors – e.g., due to a short-circuited load – overtemperature, a spatial and / or temporal temperature gradient exceeding a threshold (differential temperature), overvoltage, etc.

[0018] Several techniques are based on the understanding that, in the event of a fault, terminals connected to different MOS power transistors or different channels may exhibit differing operating characteristics. Specifically, the terminal voltage may vary for different terminals. This can be due to different breakdown voltages of the Zener diodes used to implement the terminals. Furthermore, when the terminal voltages differ for various MOS power transistors, any symmetry between them is lifted, and the currents through them can vary—for example, due to the discharge of inductors or capacitors. Therefore, one or more MOS power transistors may be subject to increased wear compared to one or more other MOS power transistors.

[0019] Several other techniques are based on the understanding that control circuits belonging to different MOS power transistors of different channels can exhibit different response times in the event of a fault condition. Therefore, if a suitable sensor detects a fault condition, the response time required to change the operating state of different MOS power transistors from low to high resistance can vary from transistor to transistor. This, in turn, eliminates any symmetry between different MOS power transistors, and the currents through them—for example, the discharge currents due to inductor discharge—can vary. Consequently, one or more MOS power transistors may be subject to increased wear compared to one or more others.

[0020] This paper describes techniques that make it possible to mitigate such increased wear of MOS power transistors. This is achieved by avoiding asymmetries in the operation of the various MOS power transistors.

[0021] As shown in the examples, a switch is connected between the gate terminals of various MOS power transistors. The switch is designed to selectively couple the gate terminals. This helps to synchronize the gate terminals of the MOS power transistors.

[0022] This can mitigate negative effects associated with different clamping voltages. In particular, it may be possible to selectively couple the gate terminals in response to the detection of a fault condition. When the various MOS power transistors are clamped—that is, when the clamp between the relevant gate terminal and a source terminal and / or the clamp between the relevant gate terminal and a drain terminal is in a low-resistance state—shifts in the voltage levels of the various gate terminals—which would otherwise be observed due to variations in the clamping voltages—can be avoided by coupling these gate terminals. This prevents differences in the currents through the various MOS power transistors. Asymmetries between the MOS transistors are avoided by synchronizing the gate terminals of the MOS power transistors.Selective wear is avoided.

[0023] According to examples, a control circuit is configured to detect a fault condition in at least one of a first MOS power transistor and a second MOS power transistor. Then, in response to the detection of the fault condition, both the first and second MOS power transistors can be operated in a high-resistance state. Therefore, the gate drivers of the gate terminals of the MOS power transistors can be synchronized.

[0024] Therefore, it is possible to influence the operating state of multiple MOS power transistors, even if a fault condition is detected for only one of them. This simplifies synchronized emergency shutdown of multiple MOS power transistors. Differences in currents through the various MOS power transistors, particularly differences in discharge currents before reaching a stable state, can be avoided. Asymmetries between the MOS power transistors are prevented, and selective wear is avoided.

[0025] Fig. Figure 1 illustrates aspects relating to a System 100. The System 100 comprises a circuit 101, a load 102, and a voltage source 103 that provides a supply voltage Vbat. The supply voltage Vbat can be provided by a battery. The supply voltage Vbat can drive the load 102. The circuit 101 contains a MOS power transistor 111 belonging to channel 110; and it further contains a MOS power transistor 121 belonging to another channel 120.

[0026] The use of Fig. Figure 1 illustrates that of the MOS power transistors 111, 121 each has a drain terminal 91 and a source terminal 92 - in the scenario of Fig. 1 connected to a body connector 94 - and has a gate connector 93.

[0027] As in Fig. As shown in Figure 1, channel 110 contains an input pin 112 and an output pin 113. Channel 120 contains an input pin 122 and an output pin 123. The load 102 is connected to the output pins 113 and 123 of both channels 110 and 120. This is a parallel channel configuration. In the parallel channel configuration, the current 180 through the load 102 is equal to the sum of the currents 181 and 182 of channels 110 and 120, respectively.

[0028] Furthermore in Fig. Figure 1 shows an inductance 105 and a resistance 106. The inductance 105 and the resistance 106 may be present due to parasitic effects and / or the finite length of electrical conductor paths between the MOS power transistors 111, 121 and the load 102. Energy is stored in the inductance 105 when the current 180 flows through the inductance 105. Although in Fig. If 1 is not shown, it would also be possible that a capacitance is observed - e.g. due to parasitic effects and / or the finite length of the electric paths.

[0029] In Fig. Channel 110 is assigned to a control circuit 115; and channel 120 is assigned to a control circuit 125. The control circuits 115 and 125 can include gate drivers configured to supply control signals to the gate terminals 93 of the MOS power transistors 111 and 121. In particular, the control circuit 115 can be operated independently of the control circuit 125. Therefore, it is conceivable that the MOS power transistor 111 is operated in a low-resistance state while the MOS transistor 121 is simultaneously operated in a high-resistance state. This results in an asymmetry in the currents 181 and 182.

[0030] Fig. Figure 1 also illustrates aspects of clamping circuits 116, 126, which belong to the MOS power transistors 111, 121. These clamping circuits are referred to below simply as terminals 116, 126. Terminal 116 contains a Zener diode 117, which is connected in reverse bias between the drain terminal 91 and the gate terminal 93; and it further contains a Zener diode 118, which is connected in reverse bias between the gate terminal 93 and the source terminal 92 of the MOS transistor 111. Terminal 126, belonging to the MOS power transistor 121, is similarly configured with Zener diodes 127, 128. Terminals 116, 126 provide overvoltage protection. The voltage between terminals 91, 92 is limited according to the clamping voltage. For example, techniques of active “Zenering” can be used.In this process, the Zener diode 117 can pull the voltage at the gate terminal 93 of the MOS power transistor 111 upwards when it is clamped. The MOS power transistor 111 can then be switched on to allow a specific current flow.

[0031] It is possible that the terminal voltages of terminals 116 and 126 are not matched, i.e., they exhibit a voltage difference of a few mV or even V. This can occur due to manufacturing tolerances. The mismatched terminal voltages can result in an asymmetry between the inductive discharge currents through the MOS power transistors 111 and 121. This asymmetry is particularly noticeable when a switch 301, connected between the gate terminals 93 of the MOS power transistors 111 and 121, is operated in a high-resistance state, as shown. According to various examples, to mitigate such asymmetries, the switch 301 can be operated in a low-resistance state.When the switch 301 is operated in the low-resistance state, the gate terminals 93 of the MOS power transistors 111, 121 are coupled; whereas the gate terminals 93 of the MOS power transistors 111, 121 are not coupled when the switch 301 is operated in the high-resistance state.

[0032] Different implementations of the 301 switch can be used in the various examples described herein. For example, the 301 switch can be implemented using high-voltage (HV) FETs of type n or type p, or both.

[0033] Fig. 2 illustrates aspects relating to System 100. In particular, it illustrates Fig. 2 aspects relating to the control circuits 115, 125.

[0034] The control circuit 115 contains a driver logic 201. The driver logic 201 controls a gate driver 204, which contains a charge pump. The gate driver 204 is configured to output a control signal to the gate terminal 93 of the MOS power transistor 111. The gate driver 204 is configured to output the control signal depending on the control input provided by the driver logic 201.

[0035] The control circuit 115 also includes a current sensor 202 and a temperature sensor 203. The current sensor 202 is configured to detect the current 181. If the current 181 exceeds a predetermined threshold, the overcurrent fault condition of the driver logic 201 can be signaled by a suitable sensor signal. The driver logic 201 can then control the gate driver 201 to output a control signal that operates the MOS power transistor 111 in a high-resistance state. The temperature sensor 203 is configured to monitor the temperature in the vicinity of the MOS power transistor 111. Alternatively or additionally, the temperature sensor 203 can be configured to monitor the temperature relative to the environment of the MOS power transistor 111; such a fault condition can be referred to as a delta-temperature fault condition. In this case, the temperature difference on the chip can exceed a threshold value.Based on this monitoring, the temperature sensor 203 is configured to signal a delta or overtemperature fault condition to the driver logic 201. The driver logic 201 can then control the gate driver 204 to output a control signal that operates the MOS power transistor in a high-resistance state.

[0036] The control circuit 125 is designed in a similar way to the control circuit 115.

[0037] The control signals 191, 192, which are supplied to the gate terminals 93 by the corresponding control circuits 115, 125, are in Fig. 2 also shown.

[0038] Fig. Figure 2 further illustrates a control circuit 251, 252. The control circuit 252 provides protection against electrostatic discharge. The control circuit 251 allows configuration of an operating mode of the device 110 via a serial peripheral interface 271. A corresponding memory 272 is provided. Likewise in Fig. Figure 2 shows a benefit provision 261.

[0039] Fig. 3 illustrates aspects relating to circuit 101. Fig. Figure 3 illustrates in particular aspects relating to the selective coupling of the gate terminals of the MOS power transistors 111, 121.

[0040] Circuit 101 includes a switch 301 connected between the gate terminal 93 of the MOS power transistor 111 and the gate terminal 93 of the MOS power transistor 121. The switch 301 is configured to selectively couple the gate terminals 93 of the MOS power transistors 111 and 121; that is, the switch 301 is configured to couple or discouple the gate terminals 93, for example, depending on certain triggering criteria.

[0041] In the scenario of Fig. 3 One such trigger criterion is the voltage difference between the gate terminals 93 of the MOS power transistors 111, 121 and the corresponding drain terminals 91.

[0042] Specifically, one possible implementation of switch 301, as shown in Fig. Figure 3 shows MOS transistors 311 and 321. The body terminal 94 of MOS transistor 311 is coupled to the source terminal 92 of MOS power transistor 111; meanwhile, the body terminal 94 of MOS transistor 321 is coupled to the source terminal 92 of MOS power transistor 121. The drain terminal 91 of MOS transistor 311 is coupled to the gate terminal 93 of MOS power transistor 111; meanwhile, the drain terminal 91 of MOS transistor 321 is coupled to the gate terminal 93 of MOS power transistor 121. If there is a large voltage difference between the drain terminal 91 and the gate terminal 93 of the MOS power transistor 111, the same large voltage difference exists between the source terminal 92 and the gate terminal 94 of the MOS transistor 311.For example, if the voltage difference between the drain terminal 91 and the gate terminal 93 of the MOS power transistor 111 exceeds 3 V, this voltage difference can exceed the gate-source threshold voltage of the MOS transistor 311; then the MOS transistor 311 is operated in a low-resistance state. Similar considerations apply to the MOS transistor 321. If both the MOS transistor 311 and the MOS transistor 321 are operated in a low-resistance state, the gate terminals 93 of the MOS power transistors 111 and 121 are coupled together.Therefore, in other words, the switch 301 is configured to selectively couple the gate terminals 93 of the MOS power transistors 111, 121 when the voltage difference between the drain terminal 91 and the gate terminal 93 of the MOS power transistor 111 exceeds a certain threshold, and when the voltage difference between the drain terminal 91 and the gate terminal 93 of the MOS power transistor 121 also exceeds a certain threshold. Typically, the resistivity of the MOS transistors 311, 321 is lower than the resistivity of the clamped Zener diodes 117, 127; this facilitates the synchronization of the voltage levels at the gate terminals 93 of the MOS power transistors 111, 121 by means of a current flowing through the switch 301.

[0043] The MOS power transistors 111 and 121 can be configured to switch larger currents compared to the MOS transistors 311 and 321. Each of the MOS power transistors 111 and 121 can have an active area that is at least twice, and optionally at least ten times, larger than the active area of ​​the MOS transistors 311 and 321.

[0044] In Fig. Zener diodes 315 and 325 are provided to limit the gate-source voltage difference of MOS transistors 311 and 321. Current sources 316 and 326 are provided to charge the gate terminals 93 of MOS transistors 311 and 321.

[0045] In particular, this trigger criterion, namely that the voltage difference between the drain terminal 91 and the gate terminal 93 exceeds a certain threshold, can be met when the relevant MOS power transistor 111, 121 experiences a voltage drop defined by the clamping voltage of the relevant terminal 116, 126. That is, the switch 301 can operate in a low-resistance state when both MOS power transistors 111, 121 are clamped by terminals 116, 126. This clamping of the MOS power transistors 111, 121 can occur, in particular, when the MOS power transistors 111, 121 are operated in a high-resistance state, if an emergency shutdown occurs in response to the detection of a fault condition.

[0046] Therefore, another trigger criterion is the operation of both MOS power transistors 111, 121 in a high-resistance state. For example, the operation of the MOS power transistors 111, 121 can in turn be triggered by the detection of a fault condition by the relevant control logic 115, 125.

[0047] Another triggering criterion can be implemented using switches 317 and 327. Switches 317 and 327 are selectively operated in a low-resistance state depending on the operating mode of circuit 101. An operating mode control signal 370, provided by control circuits 115 and 125, is used to control the operation of switches 317 and 327 in the low-resistance or high-resistance state, respectively. Switches 317 and 327 operate synchronously in the low-resistance or high-resistance state because both switches receive the same operating mode control signal 370.

[0048] At the in Fig. In the scenario shown, switches 317 and 327 are operated in a high-resistance state. This means that MOS transistors 311 and 321 are permanently operated in a high-resistance state. Therefore, the control of switch 301 between low-resistance and high-resistance operation is permanently disabled. Even if, for example, the voltage differences between the source terminals 92 and the gate terminals 93 of the MOS power transistors 111 and 121 both exceed a certain threshold, switch 301 remains in a high-resistance state. When switches 317 and 327 are operated in a low-resistance state, i.e., when the operating mode control signal 370 is set accordingly, a gate-source voltage difference can be present across MOS transistors 311 and 321.This is the case because the voltage at the gate terminals 93 of the MOS power transistors 111, 121 can then drop below the supply voltage Vbat (whereas the voltage at the gate terminal 93 of the respective MOS power transistor 111, 121 is above the supply voltage Vbat during normal operation, when the MOS power transistor 111, 121 is operated in a low-resistance state by means of a gate driver). From the above, it follows that the control circuit 115, 125 is configured to selectively activate the control of the switch 301 between the low-resistance state and the high-resistance state based on an operating mode of the circuit 101.

[0049] For example, the operating state could be indicated by a command received via serial peripheral interface 271 and / or a value stored in memory 272. For example, the operating mode could indicate whether a parallel channel configuration—as in Fig. 3 is represented by the connection of output pins 113 and 123. Therefore, the operating state can be inferred from the parallel channel configuration.

[0050] In Fig. Figure 3 depicts a scenario in which the MOS transistors 311 and 321, as well as the MOS power transistors 111 and 121, are all of type n. This simplifies the integration of transistors 311, 321, 111, and 121 on a common substrate. Furthermore, a comparatively simple manufacturing technology can be used.

[0051] Fig. Figure 4 is a flowchart of a procedure according to various examples. In block 1001, a first gate terminal of the first MOS power transistor and a second gate terminal of a second MOS power transistor are selectively coupled.

[0052] For example, selective coupling can depend on one or more trigger criteria, such as the operating mode of the relevant device and / or a voltage difference between the first and / or a second MOS power transistor. Another trigger criterion can be the detection of a fault condition and / or a corresponding emergency shutdown. A further trigger criterion can be the clamping of the first and / or second MOS power transistor.

[0053] For example, the procedure could follow the flowchart of Fig. 4 through circuit 101 as above in connection with Fig. 3 will be implemented as described.

[0054] Fig. Section 5 illustrates aspects relating to circuit 101. Circuit 101 according to the example of Fig. 5 generally corresponds to circuit 101 according to the example of Fig. 3. Fig. Figure 5 further illustrates aspects relating to an emergency shutdown of both MOS power transistors 111, 121 in response to the detection of a fault condition of at least one of the MOS power transistors 111, 121. Thus, it illustrates Fig. 5 aspects of synchronized control of the MOS power transistors 111, 121 to avoid asymmetries between the MOS power transistors 111, 121.

[0055] Fig. Section 5 illustrates in particular aspects relating to the control circuits 115 and 125. In the scenario of Fig. Each control circuit 115, 125 contains sensors 202, 203 configured to detect fault conditions—e.g., overcurrent, overtemperature, or differential temperature—of the respective MOS power transistors 111, 121. The sensors 202, 203 assigned to channel 110 are configured to output a sensor signal 471. This sensor signal 471 indicates a detected fault condition of the MOS power transistor 111. Similarly, the sensors 202, 203 assigned to channel 120 are configured to output a sensor signal 472. This sensor signal 472 indicates a detected fault condition of the MOS power transistor 121. Both sensor signals 471, 472 are fed to an OR logic element 402 via corresponding level shifters 450. The OR logic element 402 is configured to output a combined sensor signal 475 based on the sensor signals 471, 472.For example, if at least one of the sensor signals 471, 472 indicates the relevant fault condition, the combined sensor signal will also indicate the fault condition.

[0056] Signals 471, 472, and 475 can encode the error state digitally or analogously.

[0057] The combined sensor signal 475 is fed to the driver logic 201 and the gate control 204 of both channels 110 and 120. Therefore, the control circuits 115 and 125 are configured to determine the respective control signals 191 and 192 based on the combined sensor signal 475. This enables both MOS power transistors 111 and 121 to operate in a high-resistance state when a fault condition is detected in at least one of the MOS power transistors 111 and 121. This is particularly relevant in the scenario of a parallel channel configuration (as in Fig. 4 shown) this has the effect of a synchronized emergency shutdown to avoid asymmetric currents 181, 182.

[0058] Using switches 412 and 422, the control circuit 115 and 125 can be implemented in such a way that it selectively determines the relevant control signal 191 or 192 depending on the operating state of the circuit 101. In particular, the combined sensor signal 475 is only passed to the driver logic 201 and the gate control 204 if the operating mode control signal 370 indicates the operating mode corresponding to the parallel channel configuration. Otherwise, a fault condition detected for channel 110 does not affect an emergency shutdown of the MOS power transistor 121 of channel 120 – and vice versa. This facilitates flexible applications of the circuit 101 in both parallel and non-parallel channel configurations.

[0059] Furthermore, shown in Fig. 5 is the optional feature of directly forwarding the relevant sensor signals 471, 472 to the relevant driver logic 201 and gate control 204 via the branches 491, 492 and the OR logic elements 401. This facilitates a quick emergency shutdown.

[0060] In the scenario of Fig. In section 5, the control circuit 115 of channel 110 contains a counter 411; and the control circuit 125 of channel 120 contains a counter 421. Each of the counters 411 and 421 maintains a counter value. The counter values ​​of counters 411 and 421 are incremented based on the combined sensor signal 475 when the operating mode signal 370 indicates the parallel channel configuration. Therefore, counters 411 and 421 are incremented synchronously. This is particularly relevant in the scenario of a parallel channel configuration (as in section 5). Fig. 4 shown) this has the effect of a synchronized emergency shutdown to avoid asymmetric currents 181, 182.

[0061] For example, if the counter value of counter 411 of channel 110 exceeds a certain predefined threshold, counter 411 outputs a latch control signal 475. This latch control signal 475 indicates a latch fault condition. The optional AND logic gate 404 feeds the latch control signal 475 to the driver logic 201 and the gate controller 204 of channel 110. When the latch fault condition is communicated to the driver logic 201 and the gate controller 204 of channel 110, the MOS power transistor 111 of channel 110 is operated in a permanently high-resistance state until counter 411 is reset.

[0062] As in Fig. As shown in Figure 5, the latch control signal 475 output by the counter 411 of channel 110, if the operating mode control signal 370 indicates the parallel channel configuration, also leads to a latch error state of channel 120.

[0063] Therefore, the control signal 191 for operating the MOS power transistor 111 in the low-resistance or high-resistance state is determined based on the counter value of both counter 411 of channel 110 and counter 421 of channel 120. Similarly, the control signal 192 for operating the MOS power transistor 121 in the low-resistance or high-resistance state is determined based on the counter value of both counter 411 of channel 110 and counter 421 of channel 120. The OR logic gate 403 is provided for this purpose. This, in turn, helps to synchronize the operation of the MOS power transistors 111 and 121 of channels 110 and 120 when the parallel channel configuration is used.

[0064] How to use the above in conjunction with Fig. As will be seen in the explanation given in section 4, the control signal 191, to operate the MOS power transistor 111 in a high-resistance state, and the control signal 192, to operate the MOS power transistor 121 in a high-resistance state, are provided by the control circuits 115 and 125 in response to the detection of a fault condition in at least one of the MOS power transistors 111 and 121. This synchronized emergency shutdown can be implemented by one or more layers, for example, via the OR logic element 402 and / or the OR logic element 403. All of this helps to avoid asymmetries in the operation of the MOS power transistors 111 and 121; this prevents isolated wear of individual MOS power transistors 111 and 121.

[0065] Fig. Figure 6A is a flowchart of a procedure according to various examples. In block 1601, a fault condition of at least one of at least two MOS power transistors is detected. For example, the fault condition could involve overtemperature and overcurrent and / or a differential temperature.

[0066] Then, in block 1602, in response to the aforementioned detection of the fault condition, the gate terminals of the at least two MOS power transistors are synchronized. Synchronizing the gate terminals reduces asymmetries between the at least two MOS power transistors. This avoids asymmetries in currents 181 and 182, such as inductive commutation currents. Selective wear of one or a few of the at least two MOS power transistors can be reduced.

[0067] Synchronizing the at least two MOS power transistors can be implemented using one or more measures. For example, it would be possible to connect the gate terminals of the at least two MOS power transistors, e.g., using switch 301, according to various examples described herein. For example, the switch can be implemented using one or more MOS transistors. Then, the said connection can involve operating a first MOS transistor in a low-resistance state and operating a second MOS transistor in a low-resistance state. Another example measure for synchronizing the at least two MOS power transistors can involve synchronizing the gate drivers of the gate terminals of the at least two MOS power transistors. For example, techniques such as those described in conjunction with Fig. 5 is discussed, will be used.

[0068] The execution of block 1602 can be selectively enabled, i.e., it may be possible to disable the execution of block 1602. The method may involve selectively enabling the aforementioned connection of the gate terminals depending on the operating state of a circuit comprising at least two MOS power transistors, the operating state optionally being indicated by at least one peripheral interface instruction and a control memory value. Techniques such as those explained in connection with control signal 370 may be employed in this context.

[0069] Fig. Figure 6B is a flowchart of a procedure according to various examples. In block 1011, a fault condition of a first MOS power transistor and / or a second MOS power transistor is detected. For example, the fault condition may involve overtemperature and overcurrent and / or a differential temperature.

[0070] Then, in block 1012, a first control signal is applied to the first gate terminal of the first MOS power transistor in response to the detection of at least one fault condition in block 1011, in order to operate the first MOS power transistor in a high-resistance state. This corresponds to an emergency shutdown of the first MOS power transistor.

[0071] Next, in block 1013, again in response to the aforementioned detection of at least one fault condition in block 1011, a second control signal is applied to the second gate terminal of the second MOS power transistor to operate the second MOS power transistor in a high-resistance state. This corresponds to an emergency shutdown of the second MOS power transistor.

[0072] For example, it would be possible for blocks 1012 and 1013 to be executed essentially in parallel or at least partially in parallel.

[0073] For example, the procedure could follow the example of Fig. 6B through circuit 101 according to the example of Fig. 5 will be executed.

[0074] Fig. Figure 7 is a flowchart of a procedure according to various examples. For example, the procedure according to the flowchart of Fig. 7 by circuit 101 according to the example of Fig. 5. The operation of circuit 101 according to the example of Fig. 5 is used in conjunction with the procedure according to the flowchart of Fig. 7 explained in more detail.

[0075] In Fig. In block 1021, a fault condition for channel 110 is detected. For example, this could correspond to an overcurrent, e.g., because the load 102, connected to both output pins 113 and 123, is short-circuited. The current 181 then increases through the MOS power transistor 111 and eventually crosses a threshold value. This is detected by the corresponding sensor 202.

[0076] When the current 181 through the MOS power transistor 111 increases, the current 182 through the MOS power transistor 121 of channel 120 generally also increases. However, due to manufacturing variations or other differences, it is possible that the control circuit 115 of channel 110 detects the fault condition earlier than the control circuit 125 of channel 120. For this reason, in block 1021, the fault condition is detected only for the MOS power transistor 111 of channel 110, but not for the MOS power transistor 121 of channel 120.

[0077] Then, in block 1022, an emergency shutdown is performed for the MOS power transistor 111 of channel 110. This can be implemented by feeding the sensor signal 471 directly to the driver logic 201 and the gate controller 204 via branch 491. Due to this direct feedback from sensor 202 to the driver logic 201 and the gate controller 204, the emergency shutdown for the MOS power transistor 111 of channel 110, where the fault condition is detected, tends to be executed faster than for the MOS power transistor 121 of the other channel 120.

[0078] Finally, an emergency shutdown is also performed in block 1023 for the MOS transistor 121 of channel 120. This is achieved using the combined sensor signal 475 received from the OR logic element 402. Because the circuit 101 operates in the mode corresponding to the parallel channel configuration, the combined sensor signal 471, which indicates the fault condition, is forwarded via switch 422 to the driver logic 201 and a gate control 204 of channel 120.

[0079] Then both the MOS power transistor 111 and the MOS power transistor 121 are operated in a high-resistance state. However, the inductor 105 stores energy, and consequently the voltage difference between the source terminals 92 and the drain terminals 91 of the MOS power transistors 111 and 121 increases until the clamping voltage is reached.

[0080] Finally, the voltage difference between the drain terminals 91 and the gate terminals 93 of both MOS power transistors 111 and 121 crosses a voltage threshold. This causes switch 301 to couple the gate terminals 93 of both MOS power transistors 111 and 121, block 1024.

[0081] The voltage difference continues to increase, and then one of the two voltage differences between the source terminals 92 and the gate terminals 93 of the MOS power transistors 111, 121 crosses the relevant clamping voltage of the relevant terminal 116, 126. In the scenario of Fig. 7. Due to a difference between the clamping voltages of terminals 116 and 126, the MOS power transistor 111 is first clamped in block 1025, i.e., a fixed voltage difference is set and maintained between the source terminal 92 and the gate terminal 93; only then is the MOS power transistor 121 clamped in block 1026.

[0082] Even though the terminal voltages of terminals 116 and 126 may differ, the voltage difference across both MOS power transistors 111 and 121 is the same due to the coupling of the gate terminals 93. Therefore, the discharge currents used to discharge the inductor 105 show a comparatively small or no difference. This prevents isolated wear of either of the MOS power transistors 111 or 121.

[0083] This functionality is also used in connection with the Fig. 8-13 illustrated.

[0084] Fig. Figure 8 illustrates the time evolution of the voltage 870 between the drain terminal 91 and the source terminal 92 of the MOS power transistor 111 of channel 110. In the scenario of Fig. 8. Switch 301 is permanently operated in a high-resistance state; e.g., because the operating mode signal 370 is appropriately set, i.e., it detects the non-parallel channel configuration. Nevertheless, in the scenario of Fig. 8 the load is connected to both output pins 113, 123, i.e. in reality a parallel channel configuration is implemented, even if it is indicated differently by the operating mode signal 370.

[0085] At a specific time, a fault condition 801 occurs. This fault condition is then detected by the corresponding sensor 202, 203, and an emergency shutdown 802 is executed. Since the MOS power transistor 111 is operating in a high-resistance state, the voltage 870 increases. At 803, the voltage 870 is clamped to the terminal voltage 850. At 804, the energy stored in the inductor 105 is completely dissipated. The voltage 870 then decreases again.

[0086] The voltage 870 between the drain terminal 91 and the source terminal 92 is approximately proportional to the gate-drain voltage.

[0087] Fig. Figure 9 illustrates the current 181 through the MOS power transistor 111 (dashed line in Fig. 9) and the current 182 through the MOS power transistor 121 (dotted line) for the scenario of Fig. 8. Therefore, also in Fig. 9 of the switches 301 are permanently operated in a high-resistance state. The total current 183 is also shown (solid line).

[0088] The terminal voltages 850 differ for terminals 116 and 126. Therefore, there is a large difference between the currents 181 and 182. This corresponds to an asymmetrical operation of the MOS power transistors 111 and 121 and can lead to increased wear of the MOS power transistor 121, which experiences the larger current 182.

[0089] Fig. Figure 10 illustrates the integrated dissipated energy 871 at the MOS power transistor 111 (dashed line) and at the MOS power transistor 121 (dotted line) due to the respective currents 181, 182. As shown in Fig. As shown in Figure 10, the integrated dissipated energy 871 at the MOS power transistor 121 is much larger than the integrated dissipated energy 871 at the MOS power transistor 111 due to the larger current 182 through the MOS power transistor 121. This asymmetry can lead to a malfunction of the MOS power transistor 121 due to increased wear.

[0090] The Fig. 11-13 generally correspond to the Fig. 8 - 10. Also in the scenarios of Fig. 11-13: The load is connected to both output pins 113 and 123, meaning a parallel channel configuration is implemented. In the Fig. 11 - 12 the operation of switch 301 in the low resistance state is activated; e.g. because the operating mode signal 370 is set accordingly and the parallel channel configuration can be detected.

[0091] When the voltage crosses the threshold value 850, switch 301 of 809 begins operating in a low-resistance state. Therefore, the difference between currents 181 and 182 of 809 is reduced (cf. Fig. 12). Therefore, the difference between the integrated dissipated energy 871 at the MOS power transistor 111 and the MOS power transistor 121 (cf. Fig. 13) in the scenario compared to the scenario of Fig. 8-10 significantly lower. This prevents damage to the MOS power transistor 121 because the dissipated energy is evenly distributed between the two MOS power transistors 121 and 111. Symmetrical wear is achieved. Asymmetries are avoided through synchronized operation.

[0092] Now, with reference to the Fig. Sections 14-18 describe aspects relating to switch 301. Different implementations of switch 301 may be used in the various examples described herein.

[0093] For example, according to the scenario of Fig. 3 and Fig. 5 MOS transistors 311, 321; this can simplify the fabrication and integration with the MOS power transistors 111, 121, because all transistors 111, 121, 311, 321 are of type n.

[0094] Furthermore, in the scenario of Fig. The switch 301 – and thus the MOS transistors 311 and 321 – only operate in a low-resistance state when the voltage between gate terminal 93 and drain terminal 91 exceeds the threshold value 851. For example, in a typical implementation, this threshold value 851 could be in the range of 3 to 5 volts. This is based on the understanding that the low-resistance state of switch 301 is only required during clamping to ensure short-circuit withstand capability. Therefore, the implementation of switch 301, according to the scenarios of Fig. 3 and Fig. 5. The advantage is that it is also compatible with a non-parallel channel configuration: Here, the control signals 191, 192 of the gate terminals 93 are operated independently by the control circuit 115 of channel 110 and the control circuit 125 of channel 120, respectively. Such independent operation in the non-parallel channel configuration can lead to a scenario in which one gate terminal is directly above Vbat (MOS power transistor in a low-resistance state), while the other gate terminal is at ground (MOS power transistor clamped). Such large voltage differences between the gate terminals 93 of the MOS power transistors 111, 121 are compensated for by the configuration of switch 301 according to the examples in the Fig. 3 and Fig. 5 is tolerated. Therefore, the 301 switch flexibly supports both parallel and non-parallel channel configurations. A similar effect can be achieved with the 301 switch implementations according to the scenarios of Fig. 14 - 18 can be achieved.

[0095] In Fig. In section 14, a charge pump 501 connected to Vbat is used. The charge pump is designed to provide a voltage independent of, and thus directly above, Vbat. This allows the N-channel gate connection switches 311, 321 to be activated at any output voltage / voltage drop across the MOS power transistors 111, 121. That is, this enables the operation of switch 301 in a low-resistance state, independent of the voltage difference across the MOS power transistors 111, 121. This eliminates the limitation that the gates of the MOS power transistors 111, 121 can only be connected via switch 301 when the voltage at the output terminals 113, 123 is significantly below the supply voltage Vbat.

[0096] In the example of Fig. In some scenarios, a multi-stage charge pump 501 can be used to ensure a sufficiently large voltage difference between the control terminal 93 and the source terminal 92 of the MOS transistors 311 and 321. This is because a positive voltage difference already exists between the gate terminal 93 and the drain terminal 91 of the MOS power transistors 111 and 121 when the MOS power transistors 111 and 121 are operated in a low-resistance state. Therefore, a multi-stage charge pump 501 can be used to provide an even larger positive voltage difference between the gate terminal 93 and the source terminal 92 of the MOS transistors 311 and 321.

[0097] In Fig. 14 The charge pump 501 is designed to control the switch 301 based on the voltage at the drain terminal 91 of the MOS power transistors 111, 121.

[0098] Fig. 15 generally corresponds to Fig. 14. However, instead of using switches 317, 327, the charge pumps 502 are operated according to the operating mode control signal 370. Furthermore, the charge pumps 502 are located at the voltage level of the source terminals 92 of the respective power transistors 111, 121. Thus, the charge pumps 502 are configured to control the switch 301 based on the voltage at the source terminals 92 of the MOS power transistors 111, 121. This eliminates the need for the high-voltage current sources 316 and could be preferred in some manufacturing technologies.

[0099] In Fig. 16. The charge pumps 503 are located at the voltage level of the gate terminal 93 of the respective MOS power transistors 111, 121. Therefore, the charge pumps 503 are configured to control the switch 301 based on the voltage at the gate terminals 93 of the MOS power transistors 111, 121. In contrast to Fig. 15. The charge pumps 503 only need to pump the gate-source voltage difference for switches 311 and 321, while the pumps 502 in Fig. 15 must supply a voltage that is as high as the gate-source voltage difference of the MOS power transistors 111, 121 plus the gate-source voltage difference of the switches 311, 321. Therefore, it is possible that in Fig. 16. There is no requirement to provide multi-stage charging pumps 503.

[0100] In Fig. In Figure 17, a transmission gate formed by the N-type MOS transistor 512 and the P-type MOS transistor 511 is used as switch 301. If suitable features are available in the manufacturing technology, this concept allows the MOS power transistors to be connected at any output voltage level without the need for a charge pump. Care must be taken to bias the bulk and the gates of transistors 511 and 512 of the transmission gate. Additional transistors may be required to implement this concept.

[0101] In Fig. In section 18, two isolated high-voltage MOS transistors 513 and 514 of type P are used. To ensure the connection of the gates 93 of the MOS power transistors 111 and 121 in every operating state except the off state, the threshold voltage of the isolated high-voltage MOS transistors 513 and 514 of type P is significantly lower than the threshold voltages of the MOS power transistors of type N.

[0102] A scenario that mirrors the scenario of Fig. 18 corresponds to could also be implemented using MOS power transistors of type p and transistors of type n of switch 301.

[0103] In summary, the above techniques for synchronizing the gate terminals of power transistors in a parallel-channel configuration are described. Synchronization can be achieved by selectively coupling the gate terminals in a clamped state of the power transistors. Alternatively or additionally, synchronization can be achieved by using a fault condition detected for one of the two power transistors to also trigger an emergency shutdown of the other. Therefore, the following examples were described: Example 1.

[0104] Circuit (101) which features: - a first MOS power transistor (111, 121) with a first gate terminal (93), a first drain terminal (91) and a first source terminal (92), - a second MOS power transistor (111, 121) with a second gate terminal (93), a second drain terminal (91) and a second source terminal (92), - a switch (301) which is connected between the first gate terminal (93) and the second gate terminal (93) and is configured to selectively couple the first gate terminal (93) and the second gate terminal (93). Example 2.

[0105] Circuit (101) according to Example 1, which further exhibits: - a first terminal (116, 126) between the first drain terminal and the first gate terminal (93), wherein the first terminal (116, 126) has a first terminal voltage (850), - a second terminal (116, 126) between the second drain terminal (91) and the second gate terminal (93), wherein the second terminal (116, 126) has a second terminal voltage (850), the second terminal voltage (850) being different from the first terminal voltage (850). Example 3.

[0106] Circuit (101) according to example 1 or 2, wherein the switch (301) is configured to selectively couple the first gate terminal (93) and the second gate terminal (93) depending on a voltage difference between at least one of: (i) the first drain terminal (91) and the first gate terminal (93) and (ii) the second drain terminal (91) and the second gate terminal (93). Example 4.

[0107] Circuit (101) according to Example 3, wherein the switch (301) is configured to couple the first gate terminal (93) and the second gate terminal (93) when the voltage difference between the first drain terminal and the first gate terminal (93) exceeds a first threshold (851) and when the voltage difference between the second drain terminal and the second gate terminal (93) exceeds a second threshold (851). Example 5.

[0108] Circuit (101) according to one of the preceding examples, wherein the switch (301) is configured to couple the first gate terminal (93) and the second gate terminal (93) when at least one or both of the (i) first MOS power transistor and the (ii) second MOS power transistor are operated in a high-resistance state. Example 6.

[0109] Circuit (101) according to one of the preceding examples, wherein the switch (301) is configured to couple the first gate terminal (93) and the second gate terminal (93) when at least one of the first MOS power transistor and the second MOS power transistor is clamped by a corresponding terminal (116, 126). Example 7.

[0110] Circuit (101) according to one of the preceding examples, which further exhibits: a control circuit (115, 125, 201-204, 251, 252) which is configured to selectively activate the control of the switch (301) depending on an operating mode of the circuit (101) between operation in a low-resistance state and a high-resistance state, where the operating mode is optionally indicated by at least one peripheral interface instruction and a control memory value. Example 8.

[0111] Circuit (101) according to one of the preceding examples, wherein the switch (301) has at least one further MOS transistor (311, 321), wherein the first MOS power transistor (111, 121), the second MOS power transistor (111, 121) and at least one further MOS transistor (311, 321) are all of type n or all of type p and are all optionally integrated on a common die. Example 9.

[0112] Circuit (101) according to one of the preceding examples, wherein the switch (301) has a first further MOS transistor (311, 321) and a second further MOS transistor (311, 321), wherein a body terminal of the first further MOS transistor (311, 321) is coupled to the first source terminal (92), wherein a body terminal of the second further MOS transistor (311, 321) is coupled to the second source terminal (92), wherein a source terminal (92) of the first further MOS transistor (311, 321) is coupled to the first gate terminal (93), wherein a source terminal (92) of the second further MOS transistor (311, 321) is coupled to the second gate terminal (93), wherein a drain terminal (91) of the first further MOS transistor (311, 321) is coupled to the drain terminal (91) of the second further MOS transistor (311, 321). Example 10.

[0113] Circuit (101) according to one of examples 1 - 7, wherein the switch (301) has a transmission gate. Example 11.

[0114] Circuit (101) according to one of examples 1 - 7, wherein the switch (301) is controlled by at least one charge pump (501, 502, 503). Example 12.

[0115] Circuit (101) according to Example 11, wherein the at least one charge pump (501) is configured to supply to the switch a voltage based on at least one of a voltage at the first drain terminal and a voltage at the second drain terminal. Example 13.

[0116] Circuit (101) according to Example 11, wherein at least one charge pump is configured to supply the switch with a voltage based on at least one voltage of the first source terminal and a voltage of the second source terminal. Example 14.

[0117] Circuit (101) according to Example 11, wherein at least one charge pump is configured to supply the switch with a voltage based on at least one voltage at the first gate terminal and a voltage at the second gate terminal. Example 15.

[0118] Circuit (101) according to one of examples 1 - 7, where the first MOS power transistor (111, 121) and the second MOS power transistor (111, 121) are of type n, wherein the switch (301) has MOS transistors of type p (513, 514). Example 16.

[0119] Circuit (101) according to Example 15, wherein the threshold voltage of at least one further MOS transistor of type p (513, 514) is smaller than the threshold voltages of the first MOS power transistor and the second MOS power transistor. Example 17.

[0120] Circuit (101) which features: - a first MOS power transistor (111, 121) with a first gate terminal (93), a first drain terminal (91) and a first source terminal (92), - a second MOS power transistor (111, 121) with a second gate terminal (93), a second drain terminal (91) and a second source terminal (92), and - a control circuit (115, 125, 201-204, 251, 252) designed to detect a fault condition (801) of at least one of the first MOS power transistor (111, 121) and the second MOS power transistor (111, 121), - wherein the control circuit (115, 125, 201-204, 251, 252) is configured to supply a first control signal (191, 192) to the first gate terminal (93) in response to the aforementioned detection of the fault condition, in order to operate the first MOS power transistor (111, 121) in a high-resistance state, and to supply a second control signal (191, 192) to the second gate terminal (93) in order to operate the second MOS power transistor (111, 121) in a high-resistance state. Example 18.

[0121] Circuit (101) according to Example 17, wherein the control circuit (115, 125, 201-204, 251, 252) has a first sensor (202, 203) which is configured to detect the fault state (801) of the first MOS power transistor (111, 121) and to output a first sensor signal (471, 472) which allows the detected fault state (801) of the first MOS power transistor (111, 121) to be recognized, wherein the control circuit (115, 125, 201-204, 251, 252) has a second sensor (202, 203) which is configured to detect the fault state (801) of the second MOS power transistor (111, 121) and to output a second sensor signal (471, 472) which allows the detected fault state (801) of the second MOS power transistor (111, 121) to be recognized, wherein the control circuit (115, 125, 201-204, 251, 252) has an OR logic element (402, 403) configured to output a combined sensor signal (475) based on the first sensor signal (471, 472) and the second sensor signal (471, 472), wherein the control circuit (115, 125, 201-204, 251, 252) is configured to determine the first control signal (191, 192) based on the combined sensor signal (475) and to determine the second control signal (191, 192) based on the combined sensor signal (475). Example 19.

[0122] Circuit (101) according to Example 18, wherein the control circuit (115, 125, 201-204, 251, 252) is configured to selectively determine the first control signal (191, 192) based on the combined sensor signal (475) depending on an operating state of the circuit (101), wherein the control circuit (115, 125, 201-204, 251, 252) is configured to selectively determine the second control signal (191, 192) based on the combined sensor signal (475) depending on the operating state of the circuit (10). Example 20.

[0123] Circuit (101) of Examples 18 or 19, wherein the control circuit (115, 125, 201-204, 251, 252) also has an error counter (411, 421), wherein the control circuit (115, 125, 201-204, 251, 252) is configured to increment the fault counter (411, 421) based on the first sensor signal (471, 472) or the combined sensor signal (475). Example 21.

[0124] Circuit (101) according to Example 20, wherein the control circuit (115, 125, 201-204, 251, 252) is configured to determine the first control signal (191, 192) based on a counter value of the error counter (411, 421), wherein the control circuit (115, 125, 201-204, 251, 252) is configured to determine the second control signal (191, 192) based on the counter value of the error counter (411, 421). Example 22.

[0125] Circuit (101) according to one of examples 18 - 21, wherein the control circuit (115, 125, 201-204, 251, 252) further comprises a first level converter (450) which is connected between the first sensor (202, 203) and the OR logic element (402, 403) and is configured to convert the level of the first sensor signal (471, 472), wherein the control circuit (115, 125, 201-204, 251, 252) further comprises a second level converter which is connected between the second sensor (202, 203) and the OR logic element (402, 403) and is configured to convert the level of the second sensor signal (471, 472). Example 23.

[0126] Circuit (101) according to one of examples 17 - 22, wherein the control circuit (115, 125, 201-204, 251, 252) has a first driver configured to generate the first control signal (191, 192) depending on a first state signal, wherein the control circuit (115, 125, 201-204, 251, 252) has a second driver configured to generate the second control signal (191, 192) depending on a second state signal which differs from the first state signal, wherein the control circuit is configured to determine the first state signal and the second state signal based on the combined sensor signal (475). Example 24.

[0127] System that features: - the circuit (101) according to one of the examples 1-16, and - an electrical load connected to the first source terminal (92) and the second source terminal (92). Example 25.

[0128] System that features: - Circuit (101) according to one of Examples 17-23, and - an electrical load connected to the first source terminal (92) and the second source terminal (92). Example 26.

[0129] A process that exhibits: - Detecting a fault condition of at least one of at least two MOS power transistors, and - in response to the detection of the fault condition: synchronizing the gate connections of at least two MOS power transistors. Example 27.

[0130] The procedure according to Example 26, which further shows: - in response to the detection of the fault condition: connecting the gate terminals of at least two MOS power transistors. Example 28.

[0131] The procedure according to Example 27, which further shows: - selective activation of the aforementioned connection of the gate terminals depending on an operating state of the circuit which has at least two MOS power transistors, wherein the operating state is optionally indicated by at least one peripheral interface instruction and a control memory value. Example 29.

[0132] A method according to one of Examples 26-28, which further exhibits: - in response to the detection of the fault condition: operating a first MOS transistor in a low-resistance state and operating a second MOS transistor in a low-resistance state. Example 30.

[0133] A method according to one of Examples 26-29, which further exhibits: - in response to the detection of the fault condition: synchronizing gate drivers of the gate terminals of at least two MOS power transistors. Example 31.

[0134] A process that exhibits: - selective coupling of a first gate terminal (93) of a first MOS power transistor (111, 121) and a second gate terminal (93) of a second MOS power transistor (111, 121). Example 32.

[0135] The procedure according to Example 31, which further shows: - Detecting a trigger criterion; - in response to the aforementioned detection of the trigger criterion: Operating a switch (301) to couple the first gate terminal and the second gate terminal, where the trigger criterion is at least one of the following: - a voltage difference between the first gate terminal and a first drain terminal of the first MOS power transistor; - a voltage difference between the second gate terminal and a second drain terminal of the second MOS power transistor; - that the first MOS power transistor is operated in a high-resistance state; - that the second MOS power transistor is operated in a high-resistance state; - that the first MOS power transistor is clamped by an associated first terminal; - that the second MOS power transistor is clamped by an associated second terminal; - an overvoltage fault condition detected for the first MOS power transistor; - an overvoltage fault condition detected for the second MOS power transistor; - an overtemperature fault condition detected for the first MOS power transistor; - an overtemperature fault condition detected for the second MOS power transistor; - a differential temperature fault condition detected for the first MOS power transistor; - a differential temperature fault condition detected for the second MOS power transistor; - an overcurrent fault condition detected for the first MOS power transistor; and - an overcurrent fault condition detected for the second MOS power transistor. Example 33.

[0136] The procedure according to Example 31 or 32, which further exhibits: - selective activation of the control of the switch (301) between operation in a low-resistance state and a high-resistance state depending on an operating mode of the circuit (101), - where the operating state is optionally indicated at least by a peripheral interface instruction and a control memory value. Example 34.

[0137] A method according to one of Examples 31-33, which further exhibits: - Supplying a first current through the first MOS power transistor to a load and simultaneously supplying a second current through the second MOS power transistor to the load. Example 35.

[0138] A process that exhibits: - Detecting a fault condition (801) of at least one of a first MOS power transistor (111, 121) and a second MOS power transistor (111, 121), - in response to the aforementioned detection of the fault condition (801): Supplying a first control signal (191, 192) to a first gate terminal (93) of the first MOS power transistor (111, 121) to operate the first MOS power transistor (111, 121) in a high-resistance state, and supplying a second control signal (191, 192) to a second gate terminal (93) of the second MOS power transistor (111, 121) to operate the second MOS power transistor (111, 121) in a high-resistance state. Example 36.

[0139] The procedure according to Example 35, which further shows: - Detecting the fault condition (801) of the first MOS power transistor (111, 121), - Determining a first sensor signal (471, 472) that reveals the detected fault condition (801) of the first MOS power transistor (111, 121), - Detecting the fault condition (801) of the second MOS power transistor (111, 121), and - Determining a second sensor signal (471, 472) that allows the detected fault condition (801) of the second MOS power transistor (111, 121) to be identified, - Determining a combined sensor signal (475) based on the first sensor signal (471, 472) and the second sensor signal (471, 472), - Determining the first control signal (191, 192) based on the combined sensor signal (475), and - Determining the second control signal (191, 192) based on the combined sensor signal (475). Example 37.

[0140] The procedure according to Example 36, which further shows: - depending on an operating state of the circuit (101): selective determination of the first control signal (191, 192) based on the combined sensor signal (475), and / or - depending on the operating state of the circuit (101): selective determination of the second control signal (191, 192) based on the combined sensor signal (475). Example 38.

[0141] The method according to Examples 36 or 37, which further exhibits: - Incrementing an error counter (411, 421) based on the first sensor signal (471, 472) or the combined sensor signal (475). Example 39.

[0142] The procedure according to Example 38, which further shows: - Determining the first control signal (191, 192) based on a counter value of the error counter (411, 421), and - Determining the second control signal (191, 192) based on the counter value of the error counter (411, 421).

[0143] To illustrate, while different scenarios involving two power transistors contributing to a parallel channel configuration have been described above, other scenarios could involve a larger number of power transistors contributing to a parallel channel configuration. Even when three, four, or more power transistors contribute to a parallel channel configuration, it is possible to use the techniques described herein to couple the gate terminals of this number of power transistors; and / or to trigger emergency shutdowns on all power transistors if a fault condition is detected for at least one of them.

[0144] To further illustrate, while the above various scenarios have been described in relation to MOS power transistors, similar techniques can also be used for other types and kinds of power transistors.

Claims

[1] Circuit which features: a first MOS power transistor (111) with a first gate terminal, a first drain terminal and a first source terminal, a second MOS power transistor (121) with a second gate terminal, a second drain terminal and a second source terminal, a first control circuit (115) configured to output a control signal to the first gate terminal, a second control circuit (125) configured to output a control signal to the second gate terminal, a switch (301) which is connected between the first gate terminal and the second gate terminal and is configured to selectively couple the first gate terminal and the second gate terminal. [2] Circuit according to claim 1, further comprising: a first clamping circuit (116) which is coupled between the first drain terminal and the first gate terminal, wherein the first clamping circuit (116) has a first clamping voltage, a second clamping circuit (126) which is coupled between the second drain terminal and the second gate terminal, wherein the second clamping circuit (126) has a second clamping voltage, where the second clamping voltage does not match the first clamping voltage. [3] Circuit according to claim 1 or 2, wherein the switch (301) is configured to selectively couple the first gate terminal and the second gate terminal depending on a voltage difference between the first drain terminal and the first gate terminal and a voltage difference between the second drain terminal and the second gate terminal. [4] Circuit according to claim 3, wherein the switch (301) is configured to couple the first gate terminal and the second gate terminal when the voltage difference between the first drain terminal and the first gate terminal exceeds a first threshold and when the voltage difference between the second drain terminal and the second gate terminal exceeds a second threshold. [5] Circuit according to claim 1 or 2, wherein the switch (301) is configured to couple the first gate terminal and the second gate terminal when both the first MOS power transistor (111) and the second MOS power transistor (121) are operated in a high-resistance state. [6] Circuit according to claim 2, wherein the switch (301) is configured to couple the first gate terminal and the second gate terminal when at least one of the first MOS power transistor (111) and the second MOS power transistor is clamped by a corresponding clamping circuit (116, 126). [7] Circuit according to claim 1, further comprising: a control circuit designed to operate the switch (301) in a low-resistance state or a high-resistance state depending on an operating mode of the circuit, where the operating mode is optionally indicated by at least one peripheral interface instruction and a control memory value. [8] Circuit according to any one of claims 1 to 7, wherein the switch (301) has at least one further MOS transistor (311, 321), wherein the first MOS power transistor (111), the second MOS power transistor (121) and at least one further MOS transistor (311, 321) are all n-type transistors or all p-type transistors and are all optionally integrated on a common die. [9] Circuit according to any one of claims 1 to 7, wherein the switch (301) has a first further MOS transistor (311) and a second further MOS transistor (321), wherein a body terminal of the first further MOS transistor (311) is coupled to the first source terminal, wherein a body terminal of the second further MOS transistor (321) is coupled to the second source terminal, where a source terminal of the first further MOS transistor is coupled to the first gate terminal, wherein a source terminal of the second further MOS transistor (321) is coupled to the second gate terminal, wherein a drain terminal of the first further MOS transistor (311) is coupled to the drain terminal of the second further MOS transistor. [10] Circuit according to any one of claims 1 to 7, wherein the switch (301) comprises a transmission gate. [11] Circuit according to any one of claims 1 to 7, wherein the switch (301) is controlled by at least one charge pump (501). [12] Circuit according to any one of claims 1 to 7, wherein the first MOS power transistor (111) and the second MOS power transistor (121) are type n transistors, wherein the switch (301) has a MOS transistor of type p. [13] Circuit according to claim 12, where the MOS transistor of type p has a threshold voltage, where the threshold voltage of the type p MOS transistor is smaller than the threshold voltages of the first MOS power transistor (111) and the second MOS power transistor (121). [14] Method which features: Controlling a first MOS power transistor (111) by a control signal provided by a first control circuit (115), Controlling a second MOS power transistor (121) by a control signal provided by a second control circuit (125), Detecting a fault condition of at least one of the two MOS power transistors (111, 121), and in response to the aforementioned detection of the fault condition: Synchronizing the gate terminals of the two MOS power transistors (111, 121) by connecting the gate terminals of the two MOS power transistors (111, 121). [15] The method of claim 14, further comprising: Selective activation of the aforementioned connection of the gate terminals depending on an operating state of the circuit, which has at least two MOS power transistors (111, 121), where the operating state is optionally indicated by at least one peripheral interface instruction and a control memory value. [16] The method of claim 14, further comprising: in response to the aforementioned detection of the fault condition: Operating the first MOS power transistor (111) in a low resistance state and operating the second MOS power transistor (121) in a low resistance state. [17] The method of claim 14, further comprising: In response to the aforementioned detection of the fault: Synchronizing the gate drivers of the first and second control circuits (115, 125).

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