Dynamic multi-stage decoding

Abstract

Machine-implemented method comprising: Determining (400) a sequence of a plurality of read-level voltages (C, LL, RR, L, R, LLL, RRR) based on prior decode data, wherein the prior decode data contains information about which stages and corresponding read-level voltages were successful in decoding raw data read from a flash memory device (118) during prior multi-stage decoding operations; Performing (405) a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages (C, LL, RR, L, R, LLL, RRR), wherein each stage of the multi-stage decoding operation comprises performing one or more decoding operations to decode raw data read from the plurality of memory cells.wherein a corresponding read level voltage from the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is used according to the stage, and wherein the stages of the multi-stage decoding operation are executed sequentially until one of the one or more decoding operations at one of the stages successfully decodes the raw data read from the plurality of memory cells, wherein the one or more decoding operations of each stage include a hard decoding operation (305) and, if the hard decoding operation is unsuccessful, include up to several soft decoding operations (325), wherein raw data buffered from the previous hard decoding operation,used for soft decoding operations; returning (315) decoded data from the multi-stage decoding operation after completion of the multi-stage decoding operation; and updating (410) the previous decoded data based on the results of the multi-stage decoding operation.

Description

BACKGROUNDFlash memories may result in data errors in data stored therein due to variations in the memory cells that arise at the time of manufacture or due to changes in performance as the memory cells age. Error correction codes may be used to correct data errors during read operations. For example, low density parity check codes (LDPC) may provide robust error correction capabilities. However, LDPC algorithm codes may contribute to undesirable latency in read operations.US 2015 / 0 085 571 A1 relates to the determination, in particular updating, of read voltages in a data storage device. US 2017 / 0 242 748 A1 relates to decoding methods for data storage devices. US 2015 / 0 095 736 A1 relates to recovery or retrying in read operations in nonvolatile data storage devices.SUMMARYAccording to the invention, there is provided a machine-implemented method, data storage systems and a processor-readable medium having the features of the independent claims; dependent claims relate to preferred embodiments.According to aspects of the present technology, a machine-implemented method is provided that includes determining a sequence of a plurality of read level voltages based on previous decoding data and performing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. Decoded data is returned from the multistage decoding operation after completion of the multistage decoding operation, and the past decoding data is updated based on results of the multistage decoding operation.According to aspects of the present technology, a data storage system is provided that includes a non-volatile memory device and a controller. The controller is configured to determine a sequence of a plurality of read level voltages based on previous decoding data and perform a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. Each stage of the multi-stage decoding operation includes performing one or more decoding operations to decode raw data read from the plurality of memory cells using a corresponding read level voltage from the sequence of the plurality of read level voltages corresponding to the stage. The stages of the multi-stage decoding operation are sequentially performed until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells. Decoded data is returned from the multistage decoding operation after completion of the multistage decoding operation, and the past decoding data is updated based on results of the multistage decoding operation.According to aspects of the present technology, a processor readable medium is encoded with executable instructions that, when executed by a processor, perform a method. The method includes determining a sequence of a plurality of read level voltages based on previous decoding data and performing a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. Decoded data is returned from the multistage decoding operation after completion of the multistage decoding operation, and the past decoding data is updated based on results of the multistage decoding operation by increasing a counter value corresponding to a read level voltage of the plurality of read level voltages used for reading the successfully decoded raw data. The sequence of the plurality of read level voltages is determined based on the counter value.According to aspects of the present technology, a data storage system is provided that includes non-volatile memory and means for determining a sequence of a plurality of read level voltages based on prior decoding data. The data storage system further includes means for executing a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages, and means for returning decoded data from the multi-level decoding operation after completion of the multi-level decoding operation. The data storage system further includes means for updating the past decoding data based on results of the multi-level decoding operation.It is to be understood that other configurations of the present disclosure will become readily apparent to those skilled in the art from the following detailed description, with various configurations of the present disclosure being shown and described for illustrative purposes. It will be apparent that the present disclosure enables other and different configurations, and its various details enable various other relationships to be modified without departing from the scope of the present disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram illustrating example components of a data storage system in accordance with aspects of the present technology. FIG. 2 shows an example graph illustrating / four possible cell program distributions in multi-level cell flash memory according to aspects of the present technology. FIG. 3 shows a flowchart of a multi-level decoding operation in accordance with aspects of the present technology. FIG. 4 shows a flowchart of a process for adjusting a multi-level decoding operation in accordance with aspects of the present technology.DETAILED DESCRIPTIONThe detailed description set forth below is intended as a description of various configurations of the present disclosure and is not intended to represent the only configurations in which the present disclosure may be practiced. The accompanying drawings are incorporated in and constitute a part of the detailed description. The detailed description includes specific details to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the present disclosure. Like components are identified with identical element numbers for ease of understanding.LDPC decoding may use a multi-level decoding operation to decode raw data read from a group of memory cells in a non-volatile memory, such as a NAND flash memory. The raw data processed at each stage of the decoding operation may be read from the memory cells using a respective read level voltage from a sequence of different read level voltages. Each stage may perform a hard decoding operation on the raw data and / or one or more soft decoding operations on the raw data. The multi-level decoding operation may each perform one level in a sequence until the raw data read from the memory cells is successfully decoded.Memory cells in the same block, group of blocks, module, or module batch may have common features that lead to similarities in read errors occurring when reading data from the block, group of blocks, module, or module batch. Read errors occurring in reading data from memory cells of a similar age may also have similarities. The present technology uses these similarities to improve the multi-level decoding operation by tracking the level and corresponding read level voltage at which previous decoding operations successfully decoded the raw data read from memory cells. Read errors occurring in other similarly configured memory cells may be recovered using a sequence of read level voltages based on previous successful decoding operations that may shorten the multi-level decoding operation. As discussed in more detail below, the present technology modifies the multi-level decoding operation by determining a sequence of read level voltages based on previous decoding data indicating which read level voltages were used to successfully decode raw data in previous reads. Arranging the read level voltages in a sequence based on previous successful read operations allows read level voltages with a higher probability of successful decoding to be arranged earlier in the sequence, while read level voltages with a lower probability of successful decoding are moved to a more backward location of the sequence. In this way, the sequence of read level voltages is optimized based on read operations as the memory cells age or the operating conditions change.FIG. 1 is a block diagram illustrating example components of a data storage system 100, in accordance with aspects of the present technology. The data storage system 100 includes a controller 102, a low density parity check (LDPC) engine 104, a storage medium 106, and a flash memory device array 108. As shown in FIG. 1, the data storage system 100 may be connected to a host device 110 via a host interface 112.The controller 102 may include multiple internal components, such as one or more processors 103, a read-only memory, a flash component interface (e.g., a multiplexer for managing command and data transport along a connection to the flash memory device array 108), an I / O interface, an error correction circuit, and the like. The processor 103 of the controller 102 may monitor and control the operation of the components in the data storage controller 102. The processor 103 and / or the controller 102 may be a multi-core processor, a general purpose microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD), a controller, a state machine, a logic gate, discrete hardware components, or a combination of the foregoing. One or more elements of the controller 102 may be integrated into a single chip. In other aspects, the elements may be implemented in two or more discrete components.The controller 102 may be configured to execute code or instructions to perform the operations and functions described herein. For example, the controller 102 may be configured to perform operations for managing request flow and address maps, and to perform computations and generate commands. One or more sequences of instructions may be stored as firmware in memory in the controller 102. One or more sequences of instructions may be stored software read from the storage medium 106 and the flash storage device array 108 or received from the host device 110 (e.g., via the host interface 112). Storage medium 106 and flash storage device array 108 represent examples of machine- or computer-readable media on which instructions / code executable by controller 102 may be stored. The terms machine- or computer-readable media may generally refer to any tangible and non-transitory medium or medium used to provide instructions to the controller 102, including both transitory media such as dynamic memory used for storage media 102 or for buffers in the controller 102, and non-transitory media such as electronic media, optical media, and magnetic media. The operations and functions described herein may also be implemented using, for example, logic circuitry in hardware or a combination of hardware and software / firmware.In some aspects, storage medium 106 represents volatile memory used to temporarily store data and information that serves to manage data storage system 100. According to aspects of the present disclosure, storage medium 106 is random access memory (RAM), such as double data rate RAM (DDR). Other types of RAM may also be used to implement storage medium 106. The storage medium 106 may be implemented using a single RAM module or multiple RAM modules. While storage medium 106 is shown as being distinct from controller 102, it should be appreciated that storage medium 106 may be incorporated into controller 102 without departing from the scope of the present disclosure. Alternatively, the storage medium 106 may be a nonvolatile memory such as a magnetic disk, a flash memory, a peripheral SSD, and the like.The host interface 112 is configured to be coupled to the host device 110 to receive data from and send data to the host device 110. The host interface 112 may include both electrical and physical connections to operatively couple the host device 110 to the controller 102. The host interface 112 is configured to communicate data, addresses, and control signals between the host device 110 and the controller 102. In this way, the controller 102 is configured to store data received from the host device 102 in the flash memory device array 108 in response to a write command from the host device 110, and read data stored in the flash memory device array 108, and transmit the read data to the host device 110 via the host interface 112 in response to a read command from the host device 110.The host device 110 is any device configured to be coupled to the data storage system 110 and store data in the data storage system 100. The host device 110 may be a computing system such as a personal computer, a server, a workstation, a laptop computer, a PDA, a smart phone, and the like. Alternatively, the host device 110 may be an electronic device such as a digital camera, a digital audio player, a digital video recorder, and the like.As further shown in FIG. 1, the host device 110 and the data storage system 100 may communicate with each other via a bus 114. The bus 114 and the interface 112 may use suitable interface standards including, but not limited to, serial advanced technology attachment (SATA), advanced technology attachment (ATA), small computer system interface (SCSI), PCI-extended (PCI-X), fibre channel, serial attached SCSI (SAS), secure digital (SD), embedded multi-media card (EMC), universal flash storage (UFS), and peripheral component interconnect express (PCIe).The data storage system 100 may include an internal system bus 115. The system bus 115 may include a combination of a control bus, address bus, and data bus and may connect the components of the controller 102 (e.g., a processor and / or memory therein) to other components of the data storage system 100, including the memory LDPC engine 104, the storage medium 106, the flash memory device array 108, and the host interface 112. Data may be transferred between the various components over the system bus 115. The system bus 115 may be located partially outside and partially inside the controller 102.The host device 110 and the data storage system 100 may communicate with each other via a wired or wireless connection and may be local or remote to each other. In one or more other aspects, the data storage system 100 (or host interface 112) includes a wireless transceiver to place the host device 110 and the data storage system 100 in wireless communication with each other.The controller 102 may be configured to receive data and / or memory access commands from a memory interface module 116 (e.g., a device driver) of the host device 110. Memory access commands communicated from the memory interface 116 may include write and read commands issued by the host system 110. Read and write commands may specify a logical address (e.g., logical block addresses or LBAs) used to access data stored in the data storage system 100. The controller 102 may execute instructions in the flash memory device array 108 in response to instructions received from the memory interface module 116.The flash memory device array 108 may include multiple flash memory devices 118. A flash memory device 118 is a non-volatile memory device for storing data. According to aspects of the present technology, flash memory device 118 includes, for example, NAND flash memory. Each flash memory device 118 may include a single flash memory chip or module, or may include multiple flash memory chips or modules. For example, in a flash memory device array 108, some of the flash memory devices 118 may include one flash module, while others may include more than one flash module. The flash memory device 118 is not limited to any particular capacity or configuration. For example, the number of physical blocks, the number of physical pages per physical block, the number of sectors per physical page, and the size of the sectors may vary within the scope of the present technology.The flash memory device array 108 may be arranged in multiple channels, each channel including one or more flash memory devices 118. A flash memory device 118 may include one or more flash memory interfaces (not shown). Each flash memory interface connects the controller 102 to one of the flash memory devices via a corresponding channel. Each of the channels (not shown) may be implemented using one or more physical I / O buses coupled between one of the flash memory interfaces and the corresponding flash device(s). Each channel allows the corresponding flash memory interface to send read, write, and / or erase commands to the corresponding flash memory device. Each flash memory interface may include a register (e.g., first-in-first-out (FIFO) registers) that queues read, write, and / or erase commands from the controller 102 for the corresponding flash memory device. Although the term "channel" as used above refers to the bus coupled between a flash memory interface and the corresponding flash memory device, the term "channel" may also refer to the corresponding flash memory device addressable by a bus (e.g., system bus 115).The flash memory devices 118 may have a standard interface specification. This standard ensures that chips from several manufacturers can be used interchangeably (at least to a high degree). The interface of flash memory devices 118 may be used to access internal registers 120 and an internal flash controller 122. In some aspects, registers 120 may include address, command, and / or data registers that internally fetch and issue the necessary data to and from a NAND memory cell array 124. For example, the memory cell array 124 may include a single level cell memory (SLC), a multi-level cell memory (MLC), a three level cell memory device (TLC), etc., and in some aspects, the flash memory device array 108 may include one or more hybrid memory devices that may operate in one or more of an SLC, MLC, or TLC mode. Other types of flash memories, such as 3D NAND flash memory, are also contemplated in the present technology.A data register (e.g., register 120) may include data to be stored in memory cell array 124, or data after a fetch from memory cell array 124, and may also be used for temporary data storage and / or act like a buffer. An address register may store the memory address from which data is retrieved to the host device 110 or the address to which data is sent and stored. In some aspects, an instruction register is included to control parity, interrupt control, and the like. In some aspects, the internal flash controller 122 is accessible via a control register to control the general behavior of the flash memory device 118. The internal flash controller 122 and / or control register may control the number of stop bits, word length, receiver clock source, and may also control the switching of addressing mode, paging control, coprocessor control, and the like.The LDPC engine 104 is one or more components configured to encode and / or decode codewords to be stored in and / or read from the flash memory device array 108. The LDPC engine 104 may include an encoder and a decoder. The decoder may include a hard decoder and a soft decision ECC decoder. The LDPC engine 104 may encode the data received from the host device 100 into codewords and decode codewords from the flash memory array 118 prior to sending the decoded data to the host. In some implementations, the LDPC engine 104 may include one or more memory device(s) and / or one or more processing units used to perform error correction (e.g., using LDPC or turbo codes). The LDPC engine 104 may also include a soft information module that determines and / or maintains soft metric inputs for encoding and decoding operations. While the LDPC engine 104 is shown as being distinct from the controller 102, it should be appreciated that the LDPC engine 104 may be incorporated into the controller 102 without departing from the scope of the present disclosure.FIG. 2 shows an example graph illustrating / four possible cell program distributions in multi-level cell (MLC) flash memory according to aspects of the present technology. As shown, MLC NAND cells may be programmed to one(s) of four different states or program levels L0, L1, L2 and L3, yielding two logical information bits per cell: the most significant bit (MSB) and the least significant bit (LSB). When memory cells are read or programmed, these two bits may form corresponding MSB and LSB pages of a wordline in a memory block. Program levels L 0 and L 1 may correspond to an LSB logic bit value of "one", and program levels L 2 and L 3 may correspond to an LSB logic bit value of "zero". Although not indicated in FIG. 2, program levels L 0 and L 3 may correspond to an MSB logic bit value of "one", and program levels L 1 and L 2 may correspond to an MSB logic bit value of "zero".To read raw data from the memory cells, a read level voltage is applied to the memory cells and memory cells having a threshold voltage (Vt) at or below the applied read level voltage, which therefore activate or conduct, are considered to be part of a program distribution below the read level voltage; and such memory cells having a threshold voltage above the read level voltage, which therefore do not activate or conduct, are considered to be in a program distribution above the read level voltage. For example, FIG. 2 shows a read level voltage C that can be applied to a group of memory cells to determine which cells are programmed at either the L0 or L1 program level corresponding to an LSB logic bit value of "one" or the L2 or L3 program level corresponding to an LSB logic bit value of "zero".When the flash memory is cycled (i.e., repeatedly programmed and erased), its physical qualities change. For example, the repeated placement and removal of electrons on the floating gate during program and erase operations may cause some electrons to be trapped in the floating gate of the device. The threshold voltages of these memory cells may eventually take values different (higher or lower) than expected values, causing the cell programming distributions to eventually begin to overlap and cause read errors when reading the data.To determine a probability that the memory cells have actually been programmed (i.e., read raw data) to the observed putative program levels, multiple read operations may be initiated as part of a multi-level decode operation. For example, the memory cells may be read at a first stage with the read level voltage C, at a second stage with the read level voltage LL, at a third stage with the read level RR, and so on. The sequence of read level voltages establishes a plurality of program ranges that can be used to categorize the raw data values read from the memory cells for soft decoding if the hard decoding of the raw data fails.At a first stage of the multi-stage decoding operation, two program areas may be defined. A first program area includes cells having a programmed value at or below the read level voltage C and a second program area includes cells having a programmed value above the read level voltage C. At the second stage of the multi-stage decoding operation, three program areas may be defined by aggregating the raw data read using the read level voltage C with raw data read using the read level voltage LL. In particular, a first program region may include cells having a programmed value at or below read level voltage LL, a second program region may include cells having a programmed value above read level voltage LL and at or below read level voltage C, and a third program region may include cells having a programmed value above read level voltage C. Each subsequent stage in the multi-stage decoding operation aggregates raw data read using the read level voltage corresponding to the stage, wherein the raw data read in the preceding stages to define additional program ranges correspond to the ranges of program values between the different read level voltages. The present technology is not limited to the number of read level voltages shown in FIG. 2 or the read order indicated in FIG. 2 for applying the read level voltages to the respective stages of the multistage decoding operation. In addition, similar sequences of read level voltages may be used to read the MSB bit values in the regions between the L0 and L1 program levels and between the L2 and L3 program levels.According to aspects of the present technology, confidence values may be assigned to the respective program regions or "bins" for use in soft decoding operations. Confidence values may include log likelihood ratios (LLRs). In low density parity check (LDPC) applications, a binary LLR may include the logarithm of a ratio between the probability that a bit is "0" or "1.". A positive LLR may indicate that a signal read from the memory cell may likely be a 0-bit, and a negative LLR may indicate that the signal read from the memory cell may likely be a 1-bit. In some examples, a bit value having an assigned LLR equal to five may be more likely to be a first predetermined value (e.g., binary "0") than a bit value having an assigned LLR equal to a second predetermined value (e.g., binary "1"). A bit value with an assigned LLR equal to zero may be equally likely to be either of the predetermined values. An LLR may also be represented by a non-binary confidence vector having a set of component values.As introduced above, each stage of the multi-stage decoding process defines a set of program areas or bins. Each set of program regions or bins has a set of confidence values (e.g., LLR values) corresponding to the respective program regions or bins of the set. These confidence values may be referred to as decoding information and may be stored in respective tables or other data structures that are retrieved when soft decoding operations are performed on each of the stages.According to various implementations, when performing decoding operations, the LDPC engine 104 may use different sets of decoding information and different arrangements of the sets of decoding information for each decoding stage. Further, different sets of decoding information may be used based on the age of a respective block(s) of the storage device. For example, the age of a block(s) may be based on a number of program / erase cycles associated with the block, and there may be another group of sets for decoding information for each predetermined range of program / erase cycles (and / or each read level). According to aspects of the present technology, each stage of decoding may use multiple sets of decoding information (e.g., three), with separate soft decoding operations performed using corresponding sets of decoding information.FIG. 3 shows a flowchart of a multi-level decoding operation in accordance with aspects of the present technology. The multi-level decode operation may be initiated in response to a read command received from the host system 110 or in response to an internal data management operation performed by the controller 102. Upon initiation of the multi-level decoding operation, a read level voltage for the flash memory device 118 from which requested data is to be read is set after a sequence of read level voltages (block 300). Initially, the read level voltage may be set to the read level voltage C. The read level voltage may be set by programming a register in the flash memory device with a value corresponding to the read level voltage C.After setting the read level voltage value, raw data is read from a group of memory cells using the set read level voltage, and the raw data is passed to a hard decoder in the LDPC engine 104 to perform a hard decoding operation on the raw data (block 305). If the hard decode operation successfully decoded the raw data (block 310), the decoded data is returned to the requesting process (block 315). If the hard decoding operation is not successful, soft decoding information is selected (block 320) and the raw data is passed along with the soft decoding information to a soft decision decoder in the LDPC engine 104 to perform a soft decoding operation using the raw data and the selected soft decoding information (block 325).If the soft decoding operation successfully decoded the raw data (block 330), the decoded data is returned to the requesting process (block 315). If the soft decoding operation is not successful, the process determines whether another soft step or soft decoding operation remains at the current stage of the multi-stage decoding operation (block 335). According to aspects of the present technology, each stage of the multi-stage decoding operation may include a hard decoding operation and up to multiple soft decoding operations. Each of the soft decoding operations uses a corresponding set of soft decoding information corresponding to the current stage. Each set of soft decoding information may be determined or calculated using test or simulation data based on different conditions and assumptions. If the soft decoding using a first set of soft decoding information is not successful, the soft decoding operation may be repeated using the same raw data but with a second selected set of soft decoding information (block 320). This soft decoding operation loop may be repeated until either the raw data is successfully decoded or all sets of soft decoding information associated with the current stage have been used in soft decoding attempts. According to aspects of the present technology, each stage may have three sets of soft decoding information that are used to attempt soft decoding of raw data. However, the present technology may be implemented using more or less than three sets of soft decoding information for each stage.If no soft steps or soft decoding operations remain for the current stage (block 335), the operation determines whether another stage remains in the multistage decoding operation (block 340). The multi-level decoding operation may include up to seven levels, corresponding to the sequence of seven read level voltages, for example, shown in FIG. 2. If another stage remains in the operation, the next read level voltage in the sequence is set (block 300) and the above-described stage operations repeat. This control loop of hard and soft decoding operations repeats until either the raw data is successfully decoded and returned to the requesting process (block 315) or all hard and soft decoding operations on each of the stages are unsuccessful. If the decoding is not successful, a read error is returned to the requesting process (block 345).FIG. 4 shows a flowchart of dynamic adaptation of a multi-level decoding operation according to aspects of the present technology. Analogous to the process described above with reference to FIG. 3, the operation illustrated in FIG. 4 may be initiated in response to a read command received from the host system 110 or in response to an internal data management operation performed by the controller 102.In accordance with aspects of the present technology, a sequence of read level voltages is determined based on previous decode data (block 400). The prior decoding data contains information about which stages and corresponding read level voltages have succeeded in decoding the raw data read from the flash memory device 118 during prior decoding operations. The prior decoding data may comprise an array of counters corresponding to the read level voltages, each counter including a counter value indicative of a number of decoding operations successfully performed using the respective read level voltage. For example, the array of counters may include seven counters corresponding to the seven read level voltages illustrated in FIG. 2 (e.g., C, LL, RR, L, R, LLL, RRR). The read order indicated in FIG. 2 represents a standard sequence of read level voltages used at the beginning of the lifetime for the data storage device 100 or some other stages of initialization.To determine the sequence of read level voltages, the controller 102 may sort or order the array of counters from the largest value to the smallest value according to the counter values in the array. The sorted array of counters indicates an order of read level voltages corresponding to which read level voltages were more successful in decoding operations. For example, read level voltage L may have the highest corresponding counter value, followed by read level voltages RR, C, LL, R, LLL, and RRR. Accordingly, the particular sequence of read level voltages L, RR, C, LL, R, LLL, and RRR that is subsequently applied in the multi-level decoding operation described above with reference to FIG. 2 would be (block 405). In sorting the counter array, counters that contain the same counter value may remain in the same order relative to each other as in the standard sequence of read level voltages.After completion of the multi-level decoding operation, the previous decoding data is updated to reflect the read level voltage of the decoding level that successfully decoded the raw data (block 410). For example, the counter in the counter array corresponding to the read level voltage used at the successful decode stage is incremented by one.Sorting or ordering the counter array and determining the sequence of read level voltages based on the ordered counter array in response to each read command or management operation that includes reading data may represent a large processing burden on the controller 102 and minimally impact the performance of the data storage device 100. According to aspects of the present technology, the determining of the sequence of read level voltages may be performed after completion of a predetermined number of read operations since performing the last determination. For example, the sequence may be determined after 256 read operations are completed each (block 415). If the number of read operations since the last determination of the sequence does not meet the read count threshold of 256, the multi-state decode operation is performed using the last determined sequence of read level voltages (block 415). Due to the use of 256 read operations as a read count threshold to determine when to make the determination, the counter array may have a data byte for each element of the array. The present technology is not limited to this number of read operations as a read count threshold, and may be implemented using other numbers that may be selected or programmed to balance the processor load for this background operation with processor loads for other operations performed by the controller 102.A counter array may be maintained for the flash memory device array 108. Alternatively, a counter array may be maintained for respective blocks, groups of blocks, modules, groups of modules, or individual flash memory devices 118. Maintaining separate counter arrays and determining sequences of read level voltages for the respective blocks, groups of blocks, modules, groups of modules, flash memory devices 118, etc., enables the sequences of read level voltages to better align with the features and conditions of each block, group of blocks, module, group of modules, or flash memory device 118.In the examples discussed above, the particular sequence of read level voltages may include any order of the read level voltages depending on the prior decoding data used to determine the sequence. The present technology is not limited to this configuration. According to other aspects of the present technology, the possible sequences of read level voltages may be limited to different orders of groups of read level voltages or predetermined sequences, rather than to different orders of the individual read level voltages. For example, the counter array may include two counters: one corresponding to the group of read level voltages R, RR, and RRR, and a second corresponding to the group of read level voltages L, LL, and LLL. With this configuration, the determined sequence of read level voltages for the multi-state decoding operation can switch between the read level voltages R-, RR-, and RRR used first in the sequence or the read level voltages L-, LL-, and LLL used first based on the counter values in the past decoding data. Other groupings and orders within the groupings are contemplated in the present technology.According to aspects of the present technology, the multi-level decoding operation illustrated in FIG. 3 may be performed using the determined sequence of read level voltages. However, the multi-level decoding operation may be modified in other ways according to the determined sequence of read level voltages. For example, only the hard decoding operations may be performed using the determined sequence of read level voltages, while the soft decoding operations may be performed in the default order. This configuration reduces the number of sets of decoding information maintained and stored for the soft decoding operations. The raw data read prior to each of the hard decoding operations may be buffered for use in the later soft decoding operations to avoid having to reread data using a read level voltage already used in the operation. For example, using the sequence L, RR, C, LL, R, LLL, and RRR, hard decoding operations may be performed on read raw data using the read voltage levels L and RR before transitioning to the multi-state operation with both hard and soft decoding operations using the default sequence C, LL, RR, L, R, LLL, and RRR if none of the initial hard decoding operations are unsuccessful in decoding the raw data. If the multi-level decoding operation reaches a level corresponding to one of the early hard decoding operations (e.g., L and RR), the operation would proceed directly to the soft decoding operation control loop because hard decoding was previously attempted using raw data read at read levels L and RR. The raw data buffered from the previous hard decoding operation can be used for the soft decoding operations at these stages without having to reread the raw data.The above dynamic adjustment of the sequence of read level voltages causes the automatic adjustment of the sequence as the flash memory devices age and / or the operating conditions change. Adjusting the sequence of read level voltages potentially reduces the number of stages of the multi-stage decoding operation that must be performed prior to successfully decoding raw data read from the flash memory devices.According to aspects of the present technology, a machine-implemented method is provided that includes determining a sequence of a plurality of read level voltages based on previous decoding data and performing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. The method further includes returning decoded data from the multi-stage decoding operation after completion of the multi-stage decoding operation and updating the past decoding data based on results of the multi-stage decoding operation.Each stage of the multi-stage decoding operation may include performing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read level voltage from the sequence of the plurality of read level voltages corresponding to the stage. The stages of the multi-stage decoding operation may be performed sequentially until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells.Updating the previous decoding data may include incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages used to read the successfully decoded raw data. The sequence of the plurality of read level voltages may be determined based on the counter value. The past decoding data may include counter values of a plurality of respective counters corresponding to the plurality of read level voltages. Determining the sequence of the plurality of read level voltages may include arranging the plurality of read level voltages according to the counter values of the respective counters.Determining the sequence of the plurality of read level voltages may include selecting the sequence from a plurality of predetermined sequences. The sequence of the plurality of read level voltages may be determined after completion of a plurality of read requests since the last determination of the sequence. The plurality of memory cells are part of a block of a plurality of blocks on a module, and respective previous decoding data may be retained for the block, a group of blocks including the block, or the module.According to aspects of the present technology, a data storage system is provided that includes a non-volatile memory device and a controller. The controller may be configured to determine a sequence of a plurality of read level voltages based on previous decoding data and perform a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. Each stage of the multi-stage decoding operation may include performing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read level voltage from the sequence of the plurality of read level voltages corresponding to the stage. The stages of the multi-stage decoding operation may be performed sequentially until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells. The controller may be further configured to return decoded data from the multistage decoding operation after completion of the multistage decoding operation and update the past decoding data based on results of the multistage decoding operation.Updating the previous decoding data may include incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages used to read the successfully decoded raw data. The sequence of the plurality of read level voltages may be determined based on the counter value. The past decoding data may include counter values of a plurality of respective counters corresponding to the plurality of read level voltages. Determining the sequence of the plurality of read level voltages may include arranging the plurality of read level voltages according to the counter values of the respective counters.Determining the sequence of the plurality of read level voltages may include selecting the sequence from a plurality of predetermined sequences. The sequence of the plurality of read level voltages may be determined after completion of a plurality of read requests since the last determination of the sequence.The plurality of memory cells may be part of a block of a plurality of blocks on a module. Respective prior decoding data for the block, a group of blocks comprising the block, or the module may be retained.According to aspects of the present technology, a processor readable medium encoded with executable instructions that, when executed by a processor, perform a method is provided. The method includes determining a sequence of a plurality of read level voltages based on previous decoding data and performing a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. The method further includes returning decoded data from the multi-stage decoding operation after completion of the multi-stage decoding operation, and updating the past decoding data based on results of the multi-stage decoding operation by increasing a counter value corresponding to a read level voltage of the plurality of read level voltages used to read the successfully decoded raw data, wherein the sequence of the plurality of read level voltages is determined based on the counter value.Each stage of the multi-stage decoding operation may include performing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read level voltage from the sequence of the plurality of read level voltages corresponding to the stage. The stages of the multi-stage decoding operation may be performed sequentially until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells.The past decoding data may include counter values of a plurality of respective counters corresponding to the plurality of read level voltages. Determining the sequence of the plurality of read level voltages may include arranging the plurality of read level voltages according to the counter values of the respective counters. Determining the sequence of the plurality of read level voltages may include selecting the sequence from a plurality of predetermined sequences. The sequence of the plurality of read level voltages may be determined after completion of a plurality of read requests since the last determination of the sequence.The plurality of memory cells may be part of a block of a plurality of blocks on a module. Respective prior decoding data for the block, a group of blocks comprising the block, or the module may be retained.According to aspects of the present technology, there is provided a data storage system including a non-volatile memory, means for determining a sequence of a plurality of read level voltages based on previous decoding data, and means for performing a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages. The data storage system further includes means for returning decoded data from the multi-stage decoding operation after completion of the multi-stage decoding operation and means for updating the past decoding data based on results of the multi-stage decoding operation.Each stage of the multi-stage decoding operation may include performing one or more decoding operations to decode raw data read from the plurality of memory cells using a respective read level voltage from the sequence of the plurality of read level voltages corresponding to the stage. The stages of the multi-stage decoding operation may be performed sequentially until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells.Updating the previous decoding data may include incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages used to read the successfully decoded raw data. The sequence of the plurality of read level voltages may be determined based on the counter value. The past decoding data may include counter values of a plurality of respective counters corresponding to the plurality of read level voltages. Determining the sequence of the plurality of read level voltages may include arranging the plurality of read level voltages according to the counter values of the respective counters. Determining the sequence of the plurality of read level voltages may include selecting the sequence from a plurality of predetermined sequences.Many of the above-described functions and applications may be implemented as software or firmware processes specified as a set of instructions recorded on a computer readable storage medium (also referred to as a computer readable medium). When executed by one or more processing unit(s) (e.g., one or more processors, processor cores, or other processing units), these instructions cause the processing unit(s) to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, etc. The computer readable media do not include carrier waves and electronic signals transmitted by radio or via wired connections.The term "software" is intended to include, where appropriate, firmware residing in read-only memory or other forms of memory that can be read into memory for processing by a processor. Also, in some implementations, multiple software aspects of the present disclosure may be implemented as sub-portions of a larger program while maintaining the remaining individual software aspects of the present disclosure. In some implementations, multiple software aspects may also be implemented as separate programs. Finally, any combination of separate programs that together implement a software aspect described herein is within the scope of the present disclosure. In some implementations, the software programs, when installed to operate on one or more electronic systems, define one or more specific machine implementations that execute and perform the operations of the software programs.A computer program (also known as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may or may not correspond to a file in a file system. A program may be stored in a portion of a file that includes other programs or data (e.g., one or more scripts stored in a markup language document), in a single file associated with the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or code portions). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.It should be understood that illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interoperability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been generally described above in terms of functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each particular application. Various components and blocks may be arranged differently (e.g., arranged in a different order or partitioned in a different manner) without departing from the scope of the present disclosure.It should be understood that the specific order or hierarchy of steps in the disclosed processes is presented as an illustration of some example approaches. Based on design preferences and / or other considerations, it will be appreciated that the specific order or hierarchy of steps in the processes may be arranged differently. For example, in some implementations, some of the steps may be performed simultaneously. Thus, the appended method claims represent elements of the various steps in an exemplary order and are not intended to be limited to the particular order or hierarchy illustrated.The foregoing description is provided to enable one skilled in the art to practice the various aspects described herein. The foregoing description provides various examples of the present disclosure, and the present disclosure is not limited to these examples. Various modifications of these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are intended to be given the full scope consistent with the claims appended hereto, where reference to an element in the singular is not intended to mean "one and only one" element unless specifically stated, but "one or more.". Unless specifically stated otherwise, the term "some" refers to one(s) or more. Pronouns in (e.g., be) grammatical maskulin include (e.g., be and be) grammatical feminin and neutrme, and vice versa. Headers and subtitles, if present, are used for convenience only and do not limit the present disclosure.The predicate words "arranged to", "operable to", and "programmed to" do not imply a particular material or intangible modification of a subject, but rather are to be used interchangeably. For example, a processor configured to monitor an operation or component may also mean that the processor is programmed to monitor and control the operation or the processor is operable to monitor and control the operation. Also, a processor configured to execute code may be configured as a processor programmed to execute code or operable to execute code.The terms "in communication with" and "coupled" mean "in direct communication with" or "in indirect communication with" via one or more components that are designated or not designated in this document (e.g., a memory card reader).A phrase such as "an aspect" does not mean that such an aspect is essential to the present disclosure or that such an aspect applies to all configurations of the present disclosure. A disclosure related to an aspect may be applied to all configurations or one or more configurations. An aspect may provide one or more examples. An expression, such as an aspect, may refer to one or more aspects, and vice versa. A phrase such as an "implementation" does not imply that such an implementation is essential to the present disclosure or that such an implementation applies to all configurations of the present disclosure. A disclosure related to an implementation may apply to all aspects or one or more aspects. An implementation may provide one or more examples. An expression, such as an "implementation," may refer to one or more implementations, and vice versa. A term such as a "configuration" does not imply that such a configuration is essential to the present disclosure or that such a configuration applies to all configurations of the present disclosure. A disclosure related to a configuration may be applied to all configurations or one or more configurations. A configuration may provide one or more examples. An expression, such as a "configuration," may refer to one or more configurations, and vice versa.The word "exemplary" is used herein to mean "serving as an example or illustration.". Any aspect or design described herein as "exemplary" is not necessarily to be considered preferred or advantageous over other aspects or designs.

Claims

A machine-implemented method, comprising: determining (400) a sequence of a plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) based on prior decoding data, the prior decoding data including information about which levels and corresponding read level voltages succeeded in decoding raw data read from a flash memory device (118) during prior multi-level decoding operations; executing (405) a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), wherein each level of the multi-level decoding operation comprises executing one or more decoding operations to decode raw data, reading from the plurality of memory cells, wherein a respective read level voltage is used from the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) corresponding to the stage, and wherein the stages of the multistage decoding operation are sequentially performed until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells, wherein the one or more decoding operations of each stage include a hard decoding operation (305), and if the hard decoding operation is unsuccessful, up to a plurality of soft decoding operations (325), wherein raw data buffered from the previous hard decoding operation is used for the soft decoding operations; returning (315) decoded data from the multistage decoding operation after completion of the multistage decoding operation; and updating (410) the past decoding data based on the results of the multistage decoding operation.The machine-implemented method of claim 1, wherein updating (410) the prior decoding data comprises incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) used to read the successfully decoded raw data; and wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined based on the counter value.The machine-implemented method of claim 2, wherein the prior decoding data comprises counter values of a plurality of respective counters corresponding to the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), and wherein determining the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises ordering the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) according to the counter values of the respective counters.The machine-implemented method of claim 2, wherein determining (400) the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises selecting the sequence from a plurality of predetermined sequences.The machine-implemented method of claim 1, wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined after completion of a plurality of read requests since the last determination of the sequence.The machine-implemented method of claim 1, wherein the plurality of memory cells are part of a block of a plurality of blocks on a module, and wherein corresponding previous decoding data for the block, a group of blocks comprising the block, or the module is maintained.A data storage system (100) comprising: a non-volatile memory device (118); and a controller (102) configured to: determine (400) a sequence of a plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) based on prior decoding data, wherein the prior decoding data includes information about which levels and corresponding read level voltages succeeded in decoding raw data read from the memory device (118) during prior multi-level decoding operations; perform (405) a multi-level decoding operation for decoding raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), wherein each stage of the multistage decoding operation comprises performing one or more decoding operations for decoding raw data read from the plurality of memory cells, using a corresponding read level voltage from the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) corresponding to the stage, and wherein the stages of the multistage decoding operation are sequentially performed until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells, wherein the one or more decoding operations of each stage include a hard decoding operation (305), and if the hard decoding operation is unsuccessful, include up to a plurality of soft decoding operations (325), wherein raw data buffered from the previous hard decoding operation is used for the soft decoding operations; returning (315) decoded data from the multistage decoding operation after completion of the multistage decoding operation; and updating (410) the past decoding data based on results of the multistage decoding operation.The data storage system of claim 7, wherein updating (410) the prior decoding data comprises incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) used to read the successfully decoded raw data, and wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined based on the counter value.The data storage system of claim 8, wherein the prior decoding data comprises counter values of a plurality of respective counters corresponding to the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), and wherein determining the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises ordering the plurality of read level voltages according to the counter values of the respective counters.The data storage system of claim 8, wherein determining (400) the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises selecting the sequence from a plurality of predetermined sequences.The data storage system of claim 7, wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined after completion of a plurality of read requests since the last determination of the sequence.The data storage system of claim 7, wherein the plurality of memory cells are part of a block of a plurality of blocks on a module, and wherein corresponding previous decoding data for the block, a group of blocks comprising the block, or the module is maintained.A processor readable medium encoded with executable instructions that, when executed by a processor (103), perform a method comprising: determining (400) a sequence of a plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) based on prior decoding data, wherein the prior decoding data includes information about which levels and corresponding read level voltages (C, LL, RR, L, R, LLL, RRR) have succeeded in decoding raw data read from a flash memory device (118) during prior multi-level decoding operations; performing (405) a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages (C, LL, RR, l, r, lll, rrr), wherein each stage of the multistage decoding operation comprises performing one or more decoding operations for decoding raw data read from the plurality of memory cells, wherein a corresponding read level voltage from the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) corresponding to the stage is used, and wherein the stages of the multistage decoding operation are sequentially performed until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells, wherein the one or more decoding operations of each stage include a hard decoding operation (305), and when the hard decoding operation is not successful, include up to a plurality of soft decoding operations (325), wherein raw data buffered from the previous hard decoding operation is, for the soft decoding operations; returning (315) decoded data from the multistage decoding operation after completion of the multistage decoding operation; and updating (410) the past decoding data based on results of the multistage decoding operation by incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) used for reading the successfully decoded raw data, wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined based on the counter value.The processor readable medium of claim 13, wherein the prior decoding data comprises counter values of a plurality of respective counters corresponding to the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), and wherein determining the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises ordering the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) according to the counter values of the respective counters.The processor readable medium of claim 13, wherein determining (400) the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises selecting the sequence from a plurality of predetermined sequences.The processor readable medium of claim 13, wherein the sequence of the plurality of read level voltages is determined after completion of a plurality of read requests since the sequence was last determined.The processor readable medium of claim 13, wherein the plurality of memory cells are part of a block of a plurality of blocks on a module, and wherein corresponding previous decoding data for the block, a group of blocks comprising the block, or the module is maintained.A data storage system (100) comprising: a non-volatile memory (118); means for determining (400) a sequence of a plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) based on prior decoding data, the prior decoding data including information about which levels and corresponding read level voltages (C, LL, RR, L, R, LLL, RRR) have succeeded in decoding raw data read from the non-volatile memory during prior multi-level decoding operations; means for executing (410) a multi-level decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), wherein each stage of the multistage decoding operation comprises performing one or more decoding operations for decoding raw data read from the plurality of memory cells, using a corresponding read level voltage from the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) corresponding to the stage, and wherein the stages of the multistage decoding operation are sequentially performed until one of the one or more decoding operations on one of the stages successfully decodes the raw data read from the plurality of memory cells, wherein the one or more decoding operations of each stage include a hard decoding operation (305), and if the hard decoding operation is unsuccessful, include up to a plurality of soft decoding operations (325), wherein raw data buffered from the previous hard decoding operation is used for the soft decoding operations; means for returning (315) decoded data from the multi-stage decoding operation after completion of the multi-stage decoding operation; and means for updating (410) the previous decoding data based on results of the multi-stage decoding operation.The data storage system of claim 18, wherein updating the prior decoding data comprises incrementing a counter value corresponding to a read level voltage of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) used to read the successfully decoded raw data, and wherein the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) is determined based on the counter value.The data storage system of claim 19, wherein the prior decoding data comprises counter values of a plurality of respective counters corresponding to the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR), and wherein determining the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises ordering the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) according to the counter values of the respective counters.The data storage system of claim 20, wherein determining the sequence of the plurality of read level voltages (C, LL, RR, L, R, LLL, RRR) comprises selecting the sequence from a plurality of predetermined sequences.

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