Via column structures to optimize signal quality and manufacturing processes

Abstract

Via column structure (200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230), comprising: a first conductor (240) within a first interconnect layer of a semiconductor stack (100), the first conductor (240) traversing a first direction (250) and a second direction (252) within the first interconnect layer of the semiconductor stack (100); a second conductor (242) within a second interconnect layer of the semiconductor stack (100), the second conductor (242) traversing the first direction (250) and the second direction (252) within the second interconnect layer of the semiconductor stack (100); and a plurality of via structures connecting the first conductor (240) and the second conductor (242), wherein an axis of symmetry extends through the via column structure in the first direction (250) or in the second direction (252), wherein, in a plan view of the via column structure, the first conductor (240) is asymmetric and the second conductor (242) is symmetric with respect to said axis of symmetry, wherein the first conductor (240) comprises a plurality of first piecewise interconnected sections, wherein the second conductor (242) comprises a plurality of second piecewise interconnected sections, wherein a first portion of the plurality of first piecewise interconnected portions overlaps a second portion of the plurality of second piecewise interconnected portions approximately at the midpoints of the first portion and the second portion or approximately at endpoints of the second portion, and wherein at least one via structure of the plurality of via structures is arranged between the approximate midpoints or between the approximate endpoints to connect the first portion and the second portion.

Description

STATE OF THE ART

[0001] The prior art relevant to the present invention is given by US 2011 / 0 304 994 A1 and US 6 252 427 B1.

[0002] Continuous improvements in semiconductor manufacturing processes have enabled manufacturers and designers to produce smaller, more powerful electronic devices. Semiconductor manufacturing processes have progressed from a 10 µm semiconductor manufacturing process achieved around 1971 to a 22 nm semiconductor manufacturing process achieved around 2012. Semiconductor device manufacturing processes are expected to advance further to a 5 nm semiconductor manufacturing process around 2019. However, with each advancement in the semiconductor manufacturing process, new challenges in creating integrated circuits are revealed. Often, the semiconductor manufacturing process dictates one or more electronic design constraints imposed on the fabrication of the electronic devices.One such electronic design constraint concerns the spacing between conductors within conductive layers of a semiconductor stack. To ensure that this electronic design constraint is met, one of the conductive layers of the semiconductor stack is designed to include conductors in a horizontal direction, while another of the conductive layers of the semiconductor stack is designed to include conductors only in a vertical direction. By connecting the conductors in the horizontal direction and the conductors in the vertical direction, various components of the electronic devices can be interconnected to form the electronic devices.However, in some situations, these connections between the conductors in the horizontal direction and the conductors in the vertical direction can undesirably degrade signals flowing through these conductors, thereby degrading the performance of the electronic devices. For example, resistances of the conductors and their associated connections can be characterized as being inversely proportional to their physical sizes. As the semiconductor manufacturing process continues to progress, the physical size of conductors and their associated connections will become smaller, thereby increasing their resistance. Furthermore, resistances of the connections exhibit an undesirably increased degradation of the performance of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 shows a block diagram of an example of a semiconductor stack according to an embodiment of the present disclosure; Fig. 2A to Fig. 2P show top views of various examples of via column structures, each illustrated in a top view and hereinafter may also be referred to as “two-dimensional via column structures,” according to embodiments of the present disclosure; Fig. 3 shows a block diagram of an electronic design platform according to an embodiment of the present disclosure; Fig. 4 shows a block diagram of an example of a computer system for implementing the example design platform according to an embodiment of the present disclosure, and Fig. 5 shows a flow diagram of an example process for manufacturing the example via column structures according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition does not in itself prescribe any relationship between the various embodiments and / or configurations discussed. OVERVIEW

[0005] Embodiments of various via column structures include one or more conductors in a first interconnect layer of a semiconductor stack connected to one or more second conductors in a second interconnect layer of the semiconductor stack. The one or more first conductors and / or the one or more second conductors, respectively within the first interconnect layer and the second interconnect layer, may traverse multiple directions. In some situations, this allows multiple connections, such as vias, to be used to interconnect the one or more first conductors and the one or more second conductors.These multiple connections may reduce the resistance between the one or more first conductors and the one or more second conductors, thereby improving the performance of signals flowing between the one or more first conductors and the one or more second conductors. EXAMPLE OF A SEMICONDUCTOR STACK

[0006] Fig. 1 shows a block diagram of an example of a semiconductor stack according to an embodiment of the present disclosure. As in Fig. 1, an example semiconductor stack 100 comprises one or more interconnect layers 102.1 to 102.m. The one or more interconnect layers 102.1 to 102.m may comprise one or more conductive layers, such as one or more metal routing layers, for example. The one or more metal routing layers may comprise one or more conductive materials, such as tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), and / or any other known metal that is obvious to one of ordinary skill in the relevant art(s), without departing from the spirit and scope of the present disclosure. The one or more interconnect layers 102.1 to 102.m may additionally or alternatively comprise one or more non-conductive layers, such as one or more dielectric layers, for example.The one or more dielectric layers may comprise one or more dielectric materials, such as silicon oxide, spin-on glass, silicon nitride, silicon carbide, silicon carbon nitride, silicon oxynitride, silicon oxycarbide, silicon carbon nitride fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or any other known dielectric that would be apparent to one skilled in the relevant art(s), without departing from the spirit and scope of the present disclosure. Furthermore, the one or more interconnect layers 102.1 to 102.m may comprise one or more interconnects, such as one or more via structures, for example, to electrically and / or mechanically interconnect various interconnect layers of the interconnect layers 102.1 to 102.m.The one or more via structures may be implemented as one or more through-hole vias, one or more blind vias, one or more buried vias, or any other suitable via structures apparent to one skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure. Furthermore, one skilled in the relevant art(s) will appreciate that the configuration and arrangement of the example semiconductor stack 100 as shown in FIG. Fig. 1 is intended for illustrative purposes only. One skilled in the relevant art(s) will recognize that other configurations and arrangements for the one or more interconnect layers 102.1 to 102.m are possible without departing from the spirit and scope of the present disclosure.

[0007] In dem in Fig. 1, the one or more interconnect layers 102.1 to 102.m are arranged over, for example, on, a semiconductor substrate 106. The semiconductor substrate 106 may be a thin slice of semiconductor material, such as silicon crystal, but it may comprise other materials, or combinations of materials, such as sapphire or any other suitable material obvious to a person skilled in the relevant field(s), without departing from the spirit and scope of the present disclosure. In one embodiment, the example semiconductor stack 100 may comprise one or more diffusion layers and / or one or more polysilicon layers. In this embodiment, one or more semiconductor components, such asOne or more active components, for example one or more transistors, one or more passive components, for example one or more resistors, one or more capacitors and / or one or more inductors, and / or one or more other suitable components obvious to a person skilled in the relevant field(s), may be formed using the one or more diffusion layers and / or the one or more polysilicon layers. In some situations, the one or more semiconductor components may be connected to each other and / or to other semiconductor components using the one or more interconnect layers 102.1 to 102.m to form one or more integrated circuits. EXAMPLES OF TWO-DIMENSIONAL VIA-PLUMN STRUCTURES

[0008] Fig. 2A to Fig. 2P show top views of various examples of via column structures, each of which is illustrated in a top view and may also be referred to as “two-dimensional via column structures” in the following, according to embodiments of the present disclosure. As shown in Fig. 2A to Fig. 2P, two-dimensional via column structures 200 to 230 include a first conductor 240 of the one or more conductive materials formed in a first interconnect layer of a semiconductor stack, such as semiconductor stack 100, for example, and a second conductor 242 of the one or more conductive materials formed in a second interconnect layer of the semiconductor stack. Here, the terms "first interconnect layer" and "second interconnect layer" are used only to distinguish between interconnect layers of the semiconductor layer stack. The terms "first interconnect layer" and "second interconnect layer" need not be the first interconnect layer and the second interconnect layer of the semiconductor stack, respectively.Rather, one skilled in the relevant art(s) will recognize that the terms "first interconnect layer" and "second interconnect layer" may refer to any two interconnect layers of the semiconductor layer stack. In one embodiment, the first interconnect layer and the second interconnect layer represent two conductive layers, such as two metal routing layers, for example, within the semiconductor stack. For simplicity, the first conductor is referred to as "first conductor" in . Fig. 2A to Fig. 2P is shown using black shading and the second conductor is shown using white shading. Furthermore, widths of the first conductor 240 and the second conductor 242 are shown in Fig. 2A to 2P are not drawn to scale. For example, widths of the first conductor 240 in Fig. 2A to Fig. 2P has been exaggerated for illustrative purposes, as one skilled in the relevant art(s) will recognize without departing from the spirit and scope of the present disclosure. As in Fig. 2A to Fig. 2P, the first interconnect layer, which includes the first conductor 240, is disposed beneath the second interconnect layer, which includes the second conductor 242, within the semiconductor layer stack. This exaggeration of the widths of the first conductor 240 allows the first conductor 240 to be Fig. 2A to 2P. However, one skilled in the relevant art(s) will recognize that the widths of the first conductor 204 may be approximately equal to the widths of the second conductor 242 and / or the widths of the first conductor 240 may be smaller than the widths of the second conductor 242 without departing from the spirit and scope of the present disclosure.

[0009] As additionally in Fig. 2A to Fig. 2P, the first conductor 240 traverses multiple directions within the first interconnect layer, and the second conductor 242 similarly traverses multiple directions within the second interconnect layer. For example, the first conductor 240 traverses a first direction 250 and a second direction 242 within the first interconnect layer, as shown in Fig. 2A to 2P. In this example, the second conductor 242 extends equally in the first direction 250 and the second direction 242 within the second interconnect layer. In some of the Fig. 2A to 2P, in a top view of the via structures 200 to 230, the first conductor 240 may be considered asymmetrical with respect to an axis of symmetry extending through the two-dimensional via column structures 200 to 230, and the second conductor 242 may be considered asymmetrical with respect to this axis of symmetry. For example, the axis of symmetry may extend in the second direction 252 to separate the second conductor 242 into two approximately equal portions of the one or more conductive materials in the two-dimensional via column structure 204, as shown in Fig. 2C. In this Fig. 2C, the first conductor 240 may be considered asymmetrical to the axis of symmetry running vertically through the second conductor 242 in the second direction 252, and the second conductor 240 may be considered symmetrical to the axis of symmetry running vertically through the second conductor 242 in the second direction 252. As another example, the axis of symmetry may run in the first direction 250 to separate the second conductor 242 into two approximately equal portions of the one or more conductive materials in the two-dimensional via column structure 206, as shown in Fig. 2D. In this other, in Fig. 2D, the first conductor 240 may be considered asymmetrical to the axis of symmetry passing horizontally through the second conductor 242 in the first direction 250, and the second conductor 240 may be considered asymmetrical to the axis of symmetry passing horizontally through the second conductor 242 in the first direction 250.

[0010] In addition, the first conductor 240 and the second conductor 242 are connected using a plurality of connections, such as the plurality of via structures as described above in Fig. 1, to give an example, connected to each other, which is done using a square “x” in Fig. 2A to Fig. 2P to form the two-dimensional via column structures 200 to 230. The plurality of via structures represent a plurality of electrical connections, such as one or more through-hole vias, one or more blind vias, one or more buried vias, or any other suitable via structures apparent to one of ordinary skill in the relevant art(s) without departing from the spirit and scope of the present disclosure, to name a few examples, to connect the first conductor 240 and the second conductor 242.

[0011] In general, the first conductor 240 may be characterized as a first sequence of piecewise interconnected portions of the one or more conductive materials extending between the first direction 250 and the second direction 252 within the first interconnect layer, and the second conductor 242 may be characterized as a second sequence of piecewise interconnected portions of the one or more conductive materials extending between the first direction 250 and the second direction 252 within the second interconnect layer. For example, as in Fig. 2A, the first conductor 240 may be characterized as a first sequence of piecewise portions of the one or more conductive materials, including a first portion traversing the first direction 250 and a second portion traversing the second direction, within the first interconnect layer. In this example, the second conductor 242 may be characterized as a second sequence of piecewise portions of the one or more conductive materials, including a first portion traversing the first direction 250 and a second portion traversing the second direction 252, within the second interconnect layer.

[0012] In some situations, as in Fig. 2A to Fig. 2P, the plurality of via structures are arranged between overlaps between the first sequence of piecewise portions of the first conductor 240 and the second sequence of piecewise portions of the second conductor 242 to electrically and / or mechanically connect the first conductor 240 and the second conductor 242. The plurality of via structures, as shown in Fig. 2A to Fig. 2P are intended for illustrative purposes only. One skilled in the relevant art(s) will recognize that more or fewer via structures may be used without departing from the spirit and scope of the present disclosure. For example, as shown in Fig. 2A, these overlaps between the first sequence of piecewise sections of the first conductor 240 and the second sequence of piecewise sections of the second conductor 242 occur approximately at midpoints of the sections of the first sequence of piecewise sections of the first conductor 240 and the second sequence of piecewise sections of the second conductor 242. In this example, the plurality of via structures are arranged between the approximate midpoints of the sections to electrically and / or mechanically connect the first conductor 240 and the second conductor 242. As another example, as shown in Fig. 2D, these overlaps between the first sequence of piecewise sections of the first conductor 240 and the second sequence of piecewise sections of the second conductor 242 may occur approximately at endpoints of the sections of the first sequence of piecewise sections of the first conductor 240 and the second sequence of piecewise sections of the second conductor 242. In this other example, the plurality of via structures are arranged between the approximate endpoints of the sections to electrically and / or mechanically connect the first conductor 240 and the second conductor 242.

[0013] In the Fig. In the embodiments illustrated in Figures 2A to 2P, the multiple via structures may reduce the resistance between the first conductor 240 and the second conductor 242 by a factor proportional to the number of via structures within the two-dimensional via column structures 200 to 230, compared to using a single via structure to connect the first conductor 240 and the second conductor 242. In general, this reduction in resistance may be described as follows: Rnew=Raltψ where R neu represents this reduced resistance between the first conductor 240 and the second conductor 242, R altrepresents the resistance between the first conductor 240 and the second conductor 242, which have only one via structure between the first conductor 240 and the second conductor 242, and Ψ represents the number of via structures between the first conductor 240 and the second conductor 242. As an example, the two via structures of the two-dimensional via column structure 200 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of two, the three via structures of the two-dimensional via column structure 202, the two-dimensional via column structure 204, the two-dimensional via column structure 216, the two-dimensional via column structure 222, the two-dimensional via column structure 224, the two-dimensional via column structure 226,the two-dimensional via column structure 228 and the two-dimensional via column structure 230 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of three, the four via structures of the two-dimensional via column structure 212, the two-dimensional via column structure 218, and the two-dimensional via column structure 220 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of four, the five via structures of the two-dimensional via column structure 206 and the two-dimensional via column structure 214 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of five,The eight via structures of the two-dimensional via column structure 208 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of eight, and the ten via structures of the two-dimensional via column structure 210 can reduce the resistance between the first conductor 240 and the second conductor 242 by a factor of ten. This reduction in resistance between the first conductor 240 and the second conductor 242 improves the performance of signals flowing between the first conductor 240 and the second conductor 242. ELECTRONIC DESIGN PLATFORM FOR IMPLEMENTING THE EXAMPLES OF VIA-PLUM STRUCTURES

[0014] Fig. 3 shows a block diagram of an electronic design platform according to an embodiment of the present disclosure. As in Fig. 3, the electronic design platform 300 represents a design flow comprising one or more electronic design software applications that, when executed by one or more computing devices, processors, controllers, or other devices obvious to one of ordinary skill in the relevant art(s), without departing from the spirit and scope of the present disclosure, can design, simulate, analyze, and / or verify one or more high-level software descriptions of analog and / or digital circuits for an electronic device. In one embodiment, the one or more high-level software descriptions can be implemented using a high-level software language, such as a graphical design application, for example, C, System C, C++, LabVIEW, and / or MATLAB, a general system design language, such asSysML, SMDL and / or SSDL, or any other suitable high-level software or general-purpose system design language that will be obvious to one skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure, or a high-level software format such as Common Power Format (CPF), Unified Power Format (UPF), or any other suitable high-level software format that will be obvious to one skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure. In the embodiment shown in . Fig. 3, the electronic design platform 300 includes a synthesis application 302, a layout and routing application 304, a simulation application 306, and a verification application 308.

[0015] Furthermore, embodiments of the disclosure may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the disclosure may also be implemented as instructions stored on a machine-readable medium that can be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include non-transitory machine-readable media, such as read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and others. As another example, the machine-readable medium may include a volatile machine-readable medium, such as electrical, optical, acoustic, or other forms of propagation signals (e.g.,Carrier waves, infrared signals, digital signals, etc.). Further, firmware, software, routines, instructions, etc., may be described herein as performing certain operations. However, it is understood that such descriptions are for convenience only and that such operations may actually originate from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.In one embodiment, the synthesis application 302, the layout and routing application 304, the simulation application 306, and the verification application 308 represent one or more electronic design software applications that, when executed by one or more computing devices, one or more processors, one or more controllers, or other devices obvious to one of ordinary skill in the relevant art(s), without departing from the spirit and scope of the present disclosure, configure the one or more computing devices, processors, controllers, or other devices from general-purpose electronic devices to special-purpose electronic devices to perform one or more of these applications, as will be described in more detail below.

[0016] The synthesis application 302 translates one or more characteristics, one or more parameters, or one or more attributes of the electronic device into one or more logical operations, one or more arithmetic operations, one or more control operations, and / or any other suitable operation or operations that would be obvious to one of ordinary skill in the relevant art(s) without departing from the spirit and scope of the present disclosure, into the one or more high-level descriptions at the software level in terms of analog circuits and / or digital circuits of the electronic device.The synthesis application 302 may use a simulation algorithm to simulate the one or more logical operations, the one or more arithmetic operations, the one or more control operations, and / or the other suitable operation or operations to verify that the one or more logical operations, the one or more arithmetic operations, the one or more control operations, and / or the other suitable operation operate according to one or more characteristics, parameters, or attributes of the electronic device as set forth in an electronic design specification.

[0017] The layout and routing application 304 translates the one or more high-level descriptions at the software level to form an electronic architectural design for the analog circuitry and / or the digital circuitry of the electronic device. The layout and routing application 304 selectively selects from one or more standard cells within standard cell libraries to translate the one or more logical operations, the one or more arithmetic operations, the one or more control operations, and / or the other suitable operation or operations of the one or more high-level descriptions at the software level into geometric shapes and / or the connections between the geometric shapes to form the electronic architectural design for the analog circuitry and / or the digital circuitry of the electronic device.In general, the one or more standard cell variations have similar functionality to their corresponding standard cell, but are different from their corresponding standard cell with respect to the geometric shapes, the positions of the geometric shapes, and / or connections between the geometric shapes.

[0018] After selecting the one or more standard cells from the standard cell libraries, the placement and routing application 304 places the one or more selected standard cells on a footprint of the electronic device design. In one embodiment, the placement and routing application 304 places one or more conductors of the one or more conductive materials passing through interconnect layers to connect the one or more selected standard cells to form the electronic architecture design for the analog circuitry and / or the digital circuitry of the electronic device. In this embodiment, the placement and routing application 304 may thereafter create two-dimensional via column structures, such asarrange one or more of the two-dimensional via column structures 200 to 230, to name a few examples, to connect the one or more routings within different interconnect layers of the plurality of interconnect layers.

[0019] The simulation application 306 simulates the electronic architectural design for the analog circuit and / or the digital circuit of the electronic device to emulate one or more characteristics, parameters, or attributes of the electronic architectural design for the analog circuit and / or the digital circuit of the electronic device. In one embodiment, the simulation application 306 may provide static timing analysis (STA), voltage drop analysis, also referred to as IREM analysis, clock domain change (CDC) verification, formal verification, also referred to as model verification, equivalence checking, or any other suitable analysis apparent to one of ordinary skill in the relevant art(s) without departing from the spirit and scope of the present disclosure.In another embodiment, the simulation application 306 may perform an alternating current (AC) analysis, such as a linear small-signal frequency domain analysis, and / or a direct current (DC) analysis, such as a non-linear quiescent point calculation or a sequence of non-linear operating points calculated while sampling a voltage, current, and / or parameter to perform the STA, IREM analysis, or other suitable analysis.

[0020] The verification application 308 verifies whether the one or more characteristics, one or more parameters, or one or more attributes of the electronic architectural design for the analog circuit and / or the digital circuit of the electronic device, as replicated by the simulation application 306, meets the electronic design specification. The verification application 308 may also perform a physical verification, also referred to as a design rule check (DRC), to verify whether the electronic architectural design for the analog circuit and / or the digital circuit of the electronic device meets one or more recommended parameters, referred to as design rules, as defined by a semiconductor foundry and / or a semiconductor technology node for the fabrication of the electronic device. EXAMPLE COMPUTER SYSTEM FOR IMPLEMENTING THE EXAMPLE DESIGN PLATFORM

[0021] Fig. 4 shows a block diagram of an example of a computing system for implementing the example design platform according to an embodiment of the present disclosure. One computing system 400 may be used to implement the electronic design platform 100. However, in some situations, more than one computing system 400 may be used to implement the electronic design platform 100. After reading the description, it will be apparent to one of ordinary skill in the relevant art how to implement embodiments using other computing systems and / or computing architectures.

[0022] The computer system 400 includes one or more processors 404, also referred to as central processing units or CPUs, to execute the synthesis application 302, the arrangement and routing application 304, the simulation application 306 and / or the verification application 308, as described above in Fig. 3. The one or more processors 404 may be connected to a communication device or bus 406. In one embodiment, one or more of the one or more processors 404 may be implemented as a graphics processing unit (GPU). The GPU represents specialized electronic circuitry designed to quickly process mathematically intensive applications on electronic devices. The GPU may have a highly parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common to computer graphics applications, images, and videos.

[0023] The computer system 400 also includes user input / output device(s) 403, such as monitors, keyboards, pointing devices, etc., that communicate with the communication infrastructure 406 via user input / output interface(s) 402.

[0024] The computer system 400 also includes a main memory 408, such as random access memory (RAM), for example. The main memory 408 may include one or more hierarchical levels of cache. The main memory 408 has control logic (i.e., computer software) and / or data stored therein, such as the synthesis application 302, the layout and routing application 304, the simulation application 306, and / or the verification application 308, as described above in Fig. 3. The computing system 400 may also include one or more secondary storage devices or memories 410 to run the synthesis application 302, the placement and routing application 304, the simulation application 306, and / or the verification application 308, as described above in Fig. 3. The one or more secondary storage devices or memories 410 may include, for example, a hard disk drive 412 and / or a removable storage device or drive 414. The removable storage drive 414 may be a floppy disk drive, a magnetic tape drive, a CD drive, an optical storage device, a tape backup device, and / or any other storage device / drive. The removable storage drive 414 may cooperate with a removable storage unit 418. The removable storage unit 418 comprises a computer-usable or readable storage device having computer software (control logic) and / or data stored thereon. The removable storage unit 418 may be a floppy disk, a magnetic tape, a CD, a DVD, an optical disk, and / or any other computer data storage device.The removable storage drive 414 reads from and writes to the removable storage unit 418 in a manner known per se.

[0025] According to one embodiment, the one or more secondary storage devices or memories 410 may include other devices, means, or other approaches to enable the computing system 400 to access computer programs and / or other instructions and / or data. Such devices, means, or other approaches may include, for example, a removable storage unit 422 and an interface 420. Examples of the removable storage unit 422 and the interface 420 may include a program cartridge and cartridge interface (as found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and a USB port, a memory card and associated memory card slot, and / or any other removable storage unit and associated interface.

[0026] The computing system 400 may further include a communications or network interface 424. The communications or network interface 424 enables the computing system 400 to communicate with any combination of remote devices, remote networks, remote units, etc. (individually or collectively identified by reference numeral 428). For example, the communications or network interface 424 may enable the computing system 400 to communicate with the remote devices 428 via a communications path 426, which may be wired and / or wireless and which may include any combination of LANs, WANs, the Internet, etc. Control logic and / or data may be transmitted to and from the computing system 400 via a communications path 426.

[0027] In one embodiment, a tangible device or article of manufacture comprising a tangible, computer-usable or readable medium having control logic (software) stored thereon is also referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 400, main memory 408, secondary memory 410, and removable storage units 418 and 422, as well as tangible articles of manufacture executing any combination of the foregoing. Such control logic, when executed by one or more computing devices (such as computer system 400), causes such computing devices to operate as described herein.

[0028] Based on the teachings incorporated in this disclosure, it will be apparent to a person skilled in the relevant field(s) how the invention can be implemented using data processing units, computer systems and / or computer architectures different from those in Fig. 4. In particular, embodiments may operate with implementations of software, hardware, and / or an operating system that are different from those described herein. EXAMPLE OF MANUFACTURING THE EXAMPLES OF VIA PILLAR STRUCTURES

[0029] Fig. 5 shows a flow diagram of an example process for manufacturing the example via column structures according to an embodiment of the present disclosure. The disclosure is not limited to this operational description. Rather, it will be apparent to one skilled in the relevant art(s) that other operational control flows are within the scope and spirit of the present disclosure. The example operational control flow 500 represents a multi-stage sequence of photolithographic and chemical process steps for creating the example two-dimensional via column structures, such as one or more of the two-dimensional via column structures 200-230, to name a few examples.The multi-step sequence of photolithographic and chemical processing steps may include deposition, removal, and / or patterning operations, to name a few examples. The deposition operation represents one processing operation in which a material is grown, layered, or otherwise transferred. Removal represents another processing operation in which a material is removed. The patterning operation represents another processing operation in which a material is shaped or modified.

[0030] At operation 502, the operation control process 500 forms one or more first conductors, such as the first conductor 240, as described above in Fig. 2A to Fig. 2P, to name a few examples, in a first interconnect layer of a semiconductor stack. In the Fig. 5, the operation control flow 500 transfers a geometric structure corresponding to the one or more first conductors to the first interconnect layer. Thereafter, the operation control flow 500 performs a patterning process to remove some of the conductive material from the first interconnect layer according to the geometric structure to form the one or more first conductors. In one embodiment, the operation control flow 500 uses more advanced semiconductor technology nodes, such as a 12 nm semiconductor technology node, to name one example, to form the one or more first conductors. In this embodiment, the operation control flow 500 uses an NGL technology (NGL: Next Generation Lithography), such asEUV (extreme ultraviolet) technology, an X-ray lithography technology, an electron beam lithography technology, a focused ion beam lithography technology, and / or a nanoimprint lithography technology, to name a few examples, as the patterning process for forming the one or more first conductors. In this embodiment, using NGL technology allows the one or more first conductors to traverse multiple directions, such as the first direction 250 and the second direction 252, to name a few examples, within the first interconnect layer of the semiconductor stack. For example, the achievable resolutions for NGL technology are smaller than achievable resolutions of other, older lithography technologies, such as photolithography, to name one example, which only allow the one or more first conductors to traverse a single direction, such asthe first direction 250 or the second direction 252, to name a few examples, within the first interconnect layer of the semiconductor stack.

[0031] At operation 504, the operation control process 500 establishes one or more connections between the first conductor of operation 502 and a second conductor of operation 506, which is described in more detail below at operation 506. In the Fig. 5, the operation control flow 500 forms a plurality of via structures to interconnect the first conductor of process 502 and the second conductor of process 506. The plurality of via structures represent a plurality of electrical connections between the first interconnect layer and the second interconnect layer to electrically and / or mechanically interconnect the first conductor 308 and the second conductor 310. The plurality of via structures may be implemented as one or more through-hole vias, one or more blind vias, one or more buried vias, or any other suitable via structures apparent to one skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure.

[0032] At operation 506, the operation control process 500 forms one or more second conductors, such as the second conductor 242, as described above in Fig. 2A to Fig. 2P, to name a few examples, in a second interconnect layer of the semiconductor stack to form the example of the via column structure. In one embodiment, the first interconnect layer represents a lower interconnect layer of the interconnect layers of the semiconductor stack, and the second interconnect layer represents an upper interconnect layer of the interconnect layers of the semiconductor stack. In this embodiment, the lower interconnect layer is arranged over a semiconductor substrate of the semiconductor stack, and the upper interconnect layer is arranged over the lower semiconductor layer. In the embodiment shown in Fig.5, the operation control flow 500 transfers a geometric structure corresponding to the one or more second conductors to the second interconnect layer. Thereafter, the operation control flow 500 performs a patterning process to remove some of the conductive material from the second interconnect layer according to the geometric structure to form the one or more second conductors. In another embodiment, the operation control flow 500 uses the more advanced semiconductor technology nodes to form the one or more second conductors in a substantially similar manner to the one or more first conductors as described above. In this another embodiment, using NGL technology allows the one or more second conductors to have multiple directions, such asthe first direction 250 and the second direction 252, to name a few examples, within the second interconnect layer of the semiconductor stack. For example, the achievable resolutions for NGL technology are smaller than achievable resolutions of other, older lithography technologies, such as photolithography, to name a few examples, which only allow the one or more second conductors to traverse a single direction, such as the first direction 250 or the second direction 252, to name a few examples, within the second interconnect layer of the semiconductor stack. CONCLUSION

[0033] The above detailed description discloses a via column structure. The via column structure includes a first conductor within a first interconnect layer of a semiconductor stack, a second conductor within a second interconnect layer of the semiconductor stack, and a plurality of via structures electrically and / or mechanically connecting the first conductor and the second conductor. The first conductor traverses a first direction and a second direction within the first interconnect layer of the semiconductor stack, and the second conductor traverses the first direction and the second direction within the second interconnect layer of the semiconductor stack.

[0034] The above detailed description discloses another via column structure. This another via column structure includes first piecewise interconnected portions of a conductive material within a first interconnect layer of a semiconductor stack, second piecewise interconnected portions of the conductive material within a second interconnect layer of the semiconductor stack, and a plurality of via column structures electrically connecting one or more first portions of the first piecewise interconnected portions and one or more second portions of the second piecewise interconnected portions.The first piecewise interconnected sections traverse multiple directions within the first interconnect layer of the semiconductor stack and the second piecewise interconnected sections made of the conductive material traverse the multiple directions within the second interconnect layer of the semiconductor stack.

[0035] The above detailed description further discloses a method for fabricating a via column structure. The method includes forming a first conductor traversing a first direction and a second direction within a first interconnect layer of a semiconductor stack, forming a second conductor traversing the first direction and the second direction within a second interconnect layer of the semiconductor stack, and forming a plurality of via structures to connect the first conductor and the second conductor.

Claims

[1] Via column structure (200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, 228, 230) comprising: a first conductor (240) within a first interconnect layer of a semiconductor stack (100), the first conductor (240) traversing a first direction (250) and a second direction (252) within the first interconnect layer of the semiconductor stack (100); a second conductor (242) within a second interconnect layer of the semiconductor stack (100), the second conductor (242) traversing the first direction (250) and the second direction (252) within the second interconnect layer of the semiconductor stack (100); and a plurality of via structures connecting the first conductor (240) and the second conductor (242), wherein an axis of symmetry extends through the via column structure in the first direction (250) or in the second direction (252), wherein, in a plan view of the via column structure, the first conductor (240) is asymmetric and the second conductor (242) is symmetric with respect to said axis of symmetry, wherein the first conductor (240) comprises a plurality of first piecewise interconnected sections, wherein the second conductor (242) comprises a plurality of second piecewise interconnected sections, wherein a first portion of the plurality of first piecewise interconnected portions overlaps a second portion of the plurality of second piecewise interconnected portions approximately at the midpoints of the first portion and the second portion or approximately at endpoints of the second portion, and wherein at least one via structure of the plurality of via structures is arranged between the approximate midpoints or between the approximate endpoints to connect the first portion and the second portion. [2] The via column structure of claim 1, wherein the first direction (250) is perpendicular to the second direction (252). [3] The via column structure of claim 2, wherein the first direction (250) comprises: an x-axis of a Cartesian coordinate system, and wherein the second direction (252) comprises: a y-axis of the Cartesian coordinate system. [4] The via column structure of any preceding claim, wherein the axis of symmetry passes through the second conductor (242) in the first direction (250) or the second direction (252) to separate the second conductor (242) into approximately equal portions. [5] Via column structure comprising: a plurality of first piecewise interconnected sections of a conductive material within a first interconnect layer of a semiconductor stack (100), wherein the plurality of first piecewise interconnected sections traverse a plurality of directions within the first interconnect layer of the semiconductor stack (100); a plurality of second piecewise interconnected sections of the conductive material within a second interconnect layer of the semiconductor stack (100), wherein the plurality of second piecewise interconnected sections of the conductive material traverse the plurality of directions within the second interconnect layer of the semiconductor stack (100), the plurality of directions comprising a first direction (250) and a second direction (252); and a plurality of via structures connecting one or more first portions of the plurality of first piecewise interconnected portions and one or more second portions of the plurality of second piecewise interconnected portions, wherein an axis of symmetry extends through the via column structure in the first direction (250) or in the second direction (252), wherein, in a plan view of the via column structure, the first conductor (240) is asymmetric and the second conductor (242) is symmetric with respect to said axis of symmetry, wherein the first conductor (240) comprises a plurality of first piecewise interconnected sections, wherein the second conductor (242) comprises a plurality of second piecewise interconnected sections, wherein a first portion of the plurality of first piecewise interconnected portions overlaps a second portion of the plurality of second piecewise interconnected portions approximately at the midpoints of the first portion and the second portion or approximately at endpoints of the second portion, and wherein at least one via structure of the plurality of via structures is arranged between the approximate midpoints or between the approximate endpoints to connect the first portion and the second portion. [6] The via column structure of claim 5, wherein the second direction (252) is perpendicular to the first direction (250). [7] The via column structure of claim 5 or 6, wherein the resistance between the one or more first sections and the one or more second sections is reduced by a factor proportional to the number of via structures of the plurality of via structures connecting the one or more first sections and the one or more second sections. [8] The via column structure of any one of the preceding claims 5 to 7, wherein the axis of symmetry passes through the plurality of second piecewise interconnected portions in one direction of the plurality of directions to separate the second conductor (242) into approximately equal portions. [9] A method of manufacturing a via column structure, the method comprising: Forming a first conductor (240) traversing a first direction (250) and a second direction (252) within a first interconnect layer of a semiconductor stack (100), wherein forming the first conductor (240) comprises: Forming a plurality of first piecewise interconnected sections within the first interconnection layer of the semiconductor stack (100); Forming a second conductor (242) traversing the first direction (250) and the second direction (252) within a second interconnect layer of the semiconductor stack (100), wherein forming the second conductor (242) comprises: Forming a plurality of second piecewise interconnected sections within the second interconnection layer of the semiconductor stack (100), wherein a first portion of the plurality of first piecewise interconnected portions overlaps a second portion of the plurality of second piecewise interconnected portions at approximate midpoints of the first portion and the second portion or at approximate endpoints of the second portion; and Forming a plurality of via structures to connect the first conductor (240) and the second conductor (242), wherein an axis of symmetry extends through the via column structure in the first direction (250) or in the second direction (252), wherein, in a plan view of the via column structure, the first conductor (240) is asymmetric and the second conductor (242) is symmetric with respect to said axis of symmetry, wherein forming the plurality of via structures comprises: Forming at least one via structure of the plurality of via structures between the approximate midpoints or between the approximate endpoints to connect the first portion and the second portion. [10] The method of claim 9, wherein the first direction (250) is perpendicular to the second direction (252). [11] The method of claim 9 or 10, wherein the resistance between the first conductor (240) and the second conductor (242) is reduced by a factor proportional to a number of via structures of the plurality of via structures connecting the first conductor (240) and the second conductor (242).

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