INCREASING THE VOLUME OF EPITAXIC AREAS

Abstract

Procedure, comprehensive: Formation of isolation regions (22) over a bulk semiconductor substrate (20); Deepening the insulation regions, wherein upper sections of semiconductor strips (24) between the insulation regions protrude higher than the upper surfaces of the insulation regions to form a fin group, and wherein the fin group comprises: a plurality of inner fins (24'B); and a first outer fin (24'A) and a second outer fin (24'A) on opposite sides of the majority of inner fins; and Forming fin spacers (39) on side walls of the plurality of inner fins, the first outer fin and the second outer fin, the fin spacers comprising: an outer fin spacer (39A) on an outer side wall of the first outer fin, wherein the outer side wall faces away from the fin group and the outer fin spacer has a first height (H1); and an inner fin spacer (39B) on an inner side wall of the first outer fin, wherein the inner side wall faces the plurality of inner fins and the inner fin spacer has a second height (H2) that is smaller than the first height (H1); wherein the profile of the fin spacers is tuned by pulsing a preload with a plurality of cycles, the pulse frequency being in the range between 0.01 kHz and 10 kHz.

Description

BACKGROUND

[0001] Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than previous generations. As ICs have evolved, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometry sizes have decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs.

[0002] Such miniaturization has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required. For example, fin field-effect transistors (FinFETs) have been introduced to replace planar transistors. FinFET structures and FinFET manufacturing processes are being developed.

[0003] FinFETs are formed from semiconductor fins. The source and drain regions of FinFETs can be formed by etching sections of semiconductor fins on opposite sides of gates and then growing suitable materials in the spaces left over from the etched sections of semiconductor fins.

[0004] US 9 935 199 B2 discloses a semiconductor device with multiple semiconductor fins and sidewall spacers arranged on outer and inner sidewalls of the semiconductor fins. US 2016 / 0 315 172 A1 shows FinFETs with asymmetric epitaxial regions. US 2015 / 0 349 085 A1 proposes a method for fabricating a semiconductor device with sidewall spacers for intermediate epitaxial regions. Further methods for fabricating semiconductor devices with a plurality of semiconductor fins, spacers, and epitaxially grown source / drain regions are discussed in the publications US 2018 / 0 151 683 A1, US 2017 / 0 069 756 A1, US 2016 / 0 268 171 A1, and US 2018 / 0 151 439 A1. US 2017 / 0 098 648 A1 proposes an integrated circuit with asymmetric epitaxial source / drain regions for memory cells.

[0005] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. The Fig. 1 to 3, 4A, 4B-1 to 4B-5, 5A, 5B, 6 to 9, and 10A illustrate cross-sectional and perspective views of intermediate stages in the formation of a fin field effect transistor (FinFET) according to some embodiments. Fig. 10B shows a cross-sectional view of a FinFET with fused epitaxial regions according to some embodiments. Fig. 11 shows a cross-sectional view of a FinFET with unfused epitaxial regions according to some embodiments. Fig. 12 shows a cross-sectional view of a FinFET with non-recessed fins according to some embodiments. Fig. 13 shows a process flow for forming FinFETs according to some embodiments. DETAILED DESCRIPTION

[0007] For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, enforce any relationship between the various described embodiments and / or configurations.

[0008] Furthermore, spatially relative terms such as "underlying," "below," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0009] Fin field-effect transistors (FinFETs) and methods of forming the same are provided according to some embodiments. The intermediate stages for forming the FinFETs are shown according to some embodiments. Some variations of some embodiments are described. Like reference numerals are used to refer to like elements throughout different views and example embodiments. According to some embodiments, fin spacers of FinFETs are formed with different heights, with the height of the outer fin spacers being greater than the height of the inner fin spacers. As a result, the volume of the epitaxial regions between the fins is increased and the stress exerted by the epitaxial regions is increased. The risk of bridging of the epitaxial regions of adjacent FinFETs is also reduced.

[0010] The Fig. 1 to 3, 4A, 4B-1 to 4B-5, 5A, 5B, 6 to 9, and 10A show perspective and cross-sectional views of intermediate stages in the formation of a FinFET according to some embodiments of the present disclosure. The steps shown in the respective figures are also schematically reflected in the Fig. 13 shows the process flow.

[0011] Fig. 1 shows a perspective view of an initial structure. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate made of other semiconductor materials. The substrate 20 may be doped with a p-type impurity or an n-type impurity. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed extending from a top surface of the substrate 20 into the substrate 20. The portions of the substrate 20 between adjacent STI regions 22 are referred to as semiconductor stripes 24. The top surfaces of the semiconductor stripes 24 and the top surfaces of the STI regions 22 may be substantially planar with each other, according to some embodiments.

[0012] The STI regions 22 may include a dielectric liner (not shown), which may be formed of silicon oxide, silicon nitride, or the like. The dielectric liner may be deposited using, for example, atomic layer deposition (ALD), high-density chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 22 may also include a dielectric (e.g., silicon oxide) over the dielectric liner, where the dielectric may be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0013] With reference to Fig. 2, the STI regions 22 are recessed so that the upper portions of the semiconductor strips 24 protrude higher than the upper surfaces of the STI regions 22 to form protruding fins 24'. The corresponding process is described as process 202 in the Fig. 13. The portions of the semiconductor stripes 24 in the STI regions 22 are still referred to as semiconductor stripes. The etching may be performed using a dry etching process, wherein a mixture of HF and NH3 may be used as etching gases. The etching may also be performed using a mixture of NF3 and NH3 as the etching gases. Plasma may be generated during the etching process. Argon may also be used. In accordance with alternative embodiments of the present disclosure, the recessing of the STI regions 22 is performed using a wet etching process. The etching chemical may, for example, comprise an HF solution.

[0014] According to some embodiments, the fins for forming the FinFETs may be formed / patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes so that structures may be created that have, for example, center-to-center pitches smaller than those otherwise obtainable with a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.

[0015] Referring to Fig. 3, dummy gate stacks 30 are formed on the upper surfaces and side walls of the protruding fins 24'. The corresponding process is described as process 204 in the Fig. 13. It should be understood that although two dummy gate stacks 30 are shown for clarity, one or more than two dummy gate stacks may be formed that are parallel to each other, with the plurality of dummy gate stacks crossing the same one or more semiconductor fins 24'. The dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate electrodes 34 may be formed using, for example, amorphous silicon or polysilicon, and other materials may also be used. Each of the dummy gate stacks 30 may also include a hard mask layer 36 (or a plurality thereof) over the dummy gate electrode 34. The hard mask layer 36 may be made of silicon nitride, silicon carbonitride, or the like. The dummy gate stacks 30 also have longitudinal directions perpendicular to the longitudinal directions of the projecting fins 24'.

[0016] Next, sealing spacers 38A are formed on the side walls of the dummy gate stacks 30. The corresponding process is described as process 206 in the Fig. 13. According to some embodiments of the present disclosure, the sealing spacers 38A are formed from a dielectric such as silicon oxide, silicon carbon oxynitride (SiCON), silicon nitride, or the like. Forming the sealing spacers 38A may include depositing a conformal dielectric layer using a conformal deposition process such as ALD, CVD, or the like, and then performing an anisotropic etch to remove the portions on the top and sidewalls of the fins 24'.

[0017] After the formation of the sealing spacers 38A, an implantation may be performed to implant an n-type impurity or a p-type impurity to form lightly doped drain / source (LDD) regions 37 in the exposed protruding fins 24'. For example, if the particular FinFET to be formed is an n-type FinFET, an n-type impurity such as phosphorus, arsenic, or the like may be implanted. If the particular FinFET to be formed is a p-type FinFET, a p-type impurity such as boron, indium, gallium, or the like may be implanted. In subsequent drawings, the LDD regions 37 are not shown, although they may still exist.

[0018] Fig. 4A shows the formation of gate spacers 38B and fin spacers 39. The corresponding process is described as process 208 in the Fig. 13. The gate spacers 38B are formed on the sealing spacers 38A. According to some embodiments of the present disclosure, the gate spacers 38B are multilayer gate spacers, and the formation process may include blanket depositing a first dielectric layer and a second dielectric layer over the first dielectric layer and then performing anisotropic etches to remove portions of the first and second dielectric layers on the top and sidewalls of the fins 24'. The remaining portions of the dielectric layers are the gate spacers 38B. The sealing spacers 38A and the gate spacers 38B are hereinafter referred to as gate spacers 38.

[0019] Fig. 4A also shows the fin spacers 39 formed on the sidewalls of the protruding fins 24'. According to some embodiments of the present disclosure, the fin spacers 39 and the gate spacers 38B are formed simultaneously in common formation processes. For example, in the process of forming the gate spacers 38B, the one or more blanket dielectric cap layers deposited to form the gate spacers 38B may, upon etching, have some portions remaining on the sidewalls of the protruding fins 24', thereby forming the fin spacers 39.

[0020] The Fig. 4B-1 to 4B-5 show cross-sectional views of intermediate stages in the formation of the fin spacers 39 according to some embodiments. The cross-sectional views in the Fig. 4B-1 to 4B-5 are preserved in a vertical plane perpendicular to the line AA in Fig. 4A. The gate spacers 38B are formed simultaneously and are not shown because the gate spacers 38B are in different planes than in the Fig. 4B-1 to 4B-5. With reference to Fig. 4B-1, a spacer layer 140 is formed, which may be formed as a conformal layer. The spacer layer 140 is formed of a dielectric such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or the like. The spacer layer 140 includes some portions on the top surfaces and sidewalls of the protruding fins 24' and also includes some portions on the sealing spacers 38A and on the top surfaces of the gate stacks 30. The spacer layer 140 may have a thickness ranging between about 2 nm and about 10 nm. The protruding fins 24' are, as shown, arranged closely together to form a fin group. The protruding fins used to form the same FinFET may be in the same fin group, with the fin group being spaced apart from the fin group of adjacent FinFETs.The spacing S1 between the projecting fins 24' in the fin group is smaller than the spacing S2 between the immediately adjacent fin groups (or between a fin group and an adjacent, separate fin). For example, the ratio S2 / S1 may be greater than about 2.0 or greater than about 5.0. The projecting fins 24' may have a uniform center-to-center spacing P1. Throughout this specification, the two outermost fins 24' in the fin group (designated 24'A) are referred to as the outer fins of the fin group, and the fins 24'B between the outer fins 24'A are referred to as the inner fins of the fin group.

[0021] An anisotropic etch is then performed to etch the spacer layer 140. According to some embodiments of the present disclosure, the etching process is controlled such that the fin spacers 39 (including 39A and 39B) have the profiles shown in FIGS. 4B-5. The fin spacers 39A located on the outer sides of the fin group are hereinafter referred to as outer fin spacers (of the fin group), and the spacers 39B located within the fin group and between the protruding fins 24' in the fin group are hereinafter referred to as inner spacers (of the fin group). According to some embodiments, the outer spacers 39A have a height H1 that is greater than the height H2 of the inner spacers 39B. The height difference (H1-H2) may be greater than about 10 nm and may range between about 30 nm and about 80 nm.The height difference (H1 - H2) can also be greater than about 2.5 percent of the height H3 of the projecting fins 24'.

[0022] To achieve a desired height difference (H1 - H2), the etching process conditions are controlled, including the composition of the etching gases, the power used for etching, and the like. As a result, the spacer layer 140 (see Fig. 4B-1). Referring to Fig. 4B-2, a layer 142, such as a carbon-containing layer, is also formed in the etching process. The layer 142 may be a polymer layer and is therefore referred to below as polymer layer 142. The polymer layer 142 may be C x F ywhere x and y are integers. According to some embodiments of the present disclosure, the outer portions of the polymer 142 located on the outside of the fin group have a thickness T1, and the inner portions of the polymer 142 located within the fin group have a thickness T2 that is less than the thickness T1. The ratio T1 / T2 may be greater than about 1.1 and may range between about 1.1 and about 5. As a result, the etch rate of the outer portions is lower than the etch rate of the inner portions due to the protection of the polymer layer 142.

[0023] According to some embodiments of the present disclosure, the etching gas may include elements primarily used for etching and elements primarily used for forming a polymer. According to some embodiments, the etching gas comprises CH3F, CH2F2, CHF3, or combinations thereof. The fluorine in the etching gas serves for etching, and the carbon and fluorine in the etching gas serve to form the polymers. In the following description, carbon is referred to as the polymer-forming gas, although fluorine also partially functions as a polymer-forming gas. Accordingly, any of CF4, CH3F, CH2F2, CHF3 may act as both an etching gas and a polymer-forming gas, according to some embodiments. According to further embodiments, the etching gas and the polymer-forming gas may be different gases. The relative amount of the etching gas (containing, for example, fluorine) to the polymer-forming gas (containing, for example, carbon) influences the etching behavior.For example, since the internal space between the protruding fins 24' in the same fin group is smaller than the spacing between fin groups, there are (fin structure) iso-regions (the spaces between fin groups) and dense (fin structure) regions (the spaces between the fins 24' in the same fin group). During etching of the spacer layer 140, the spacer layer 140 tends to have higher etch rates in the iso-regions than in the dense regions because the etching gas can penetrate the iso-regions more easily than the dense regions. Similarly, polymers tend to have a higher accumulation rate in the iso-regions than in the dense regions because the polymer formation gases can penetrate the iso-regions more easily than the dense regions. The polymer can protect the spacer layer 140 from etching and reduce the etch rate of the spacer layer 140.Accordingly, the ratio of the etching gas to the polymer formation gas (the ratio F / C when the aforementioned gases are used) is adjusted so that more polymer is generated at the outer portions of the fin group than at the inner portions of the fin group, so that the etching rate of the outer portions of the spacer layer 140 is reduced to a value that results in the height H1 (see . Fig. 4B-5) is greater than the height H2.

[0024] For example, CH3F has an F / C ratio of 1, CH2F2 has an F / C ratio of 2, and CHF3 has an F / C ratio of 3. Accordingly, CHF3 can exhibit a higher etching rate and a lower polymer accumulation rate than CH2F2, and CH2F2 can exhibit a higher etching rate and a lower polymer accumulation rate than CH3F. Mixing CF4, CH3F, CH2F2, and CHF3 and selecting appropriate ratios of these gases can further adjust the F / C ratio. A small amount of other gases such as H2 and O2 can also be added to the etching gas. The H2 can react with the fluorine in the etching gases, thus reducing the amount of fluorine and thus decreasing the F / C ratio. The O2 can react with the carbon in the etching gases, thus reducing the amount of carbon and thus increasing the F / C ratio.It is understood that the mechanism and factors of etching are complicated, and the actual etching rate and polymer accumulation rate are affected by various factors. For example, since fluorine also acts as a polymer-forming gas, increasing fluorine affects both the etching rate and the polymer formation rate. Accordingly, increasing the F / C ratio may not always result in an increase in the thickness ratio T1 / T2 (of polymer 142). Experiments can be conducted to fine-tune the process conditions to achieve desirable etching rates and polymer accumulation rates in the iso- and dense regions and to achieve a desired thickness ratio T1 / T2 (see ). Fig. 4B-2).

[0025] Furthermore, to increase the thickness ratio T1 / T2, the main power and the bias power of the etching chamber in which the etching is performed are adjusted. For example, the etching chamber in which the wafer 10 is placed for etching the spacer layer 140 may have a main (RF) power, which may be provided by a coil and a main power source (not shown). The main power serves to generate plasma from the etching gas. A bias source may be connected to the chuck on which the wafer 10 is placed to provide bias power. The main power source and the bias source are controlled by a control unit. When the main power supply is switched on and the bias supply is also switched on, the spacer layer 140 is etched, and less of the polymer layer 142 (see Fig. 4B-2). When the main power supply is turned on and the bias supply is turned off, the etching effect is significantly reduced and can be substantially eliminated while the polymer 142 is generated and accumulated. The bias power can be turned on and off (pulsed) to obtain a plurality of cycles, and the corresponding duty cycle (the ratio of on-time / (on-time + off-time)) can be adjusted. For example, reducing the duty cycle can cause the ratio H1 / H2 (see Fig. 4B-5), and increasing the duty cycle can result in the H1 / H2 ratio being reduced. Thus, by switching the bias power on and off and adjusting the duty cycle, the etch rates and polymer accumulation rates can be controlled to achieve a desired polymer thickness difference (T1 - T2) (see Fig. 4B-2), which influences the etching process in such a way that a desired height difference (H1 - H2) (see Fig. 4B-5).

[0026] In addition to pulsing the bias voltage / bias power, the main power for generating the plasma can also be pulsed (on and off with multiple cycles). The combined effect of pulsing the bias power and the main power can further tune the profile of the resulting fin spacers 39. The duty cycles of the main power and the bias power can be synchronized, which involves turning the main power and bias voltage on and off simultaneously, or turning the main power on when the bias voltage is off, and vice versa. Alternatively, pulsing the main power and pulsing the bias power can be applied in a non-synchronized mode.

[0027] According to some embodiments, CF4, CH3F, CH2F2, CHF3, H2, CO, O2, and combinations thereof may be used as etching gas in the etching process, and Ar and / or He may also be added. For example, an etching gas may include CHF3 with a flow rate ranging between about 150 sccm and about 500 sccm and CH3F with a flow rate ranging between about 10 sccm and about 50 sccm. The chamber pressure may range between about 0.4 Pa (3 mTorr) and about 120 Pa (900 mTorr). O2 may be added at a flow rate ranging between about 5 sccm and about 50 sccm. The wafer temperature may range between about -50°C and about 200°C. The main (RF) power can range from approximately 50 watts to approximately 2,000 watts, either with continuous plasma or with plasma pulses by pulsing the main power. If pulsing is provided, the pulse frequency can range from approximately 0.01 kHz to approximately 10 kHz.The duty cycle of the main power may range between about 10 percent and about 90 percent, and may range between about 20 percent and about 60 percent. The bias power may range between about 50 watts and about 2,000 watts, and may be applied continuously or in pulsed fashion. If pulsing is provided, the pulse frequency may range between about 0.01 kHz and about 10 kHz. The duty cycle of the bias power may range between about 10 percent and about 90 percent, and may range between about 20 percent and about 60 percent.

[0028] Referring again to Fig. 4B-2, there may be a plurality of duty cycles for the main power and for the bias power, and therefore there may be a plurality of cycles for accumulating the polymer followed by etching the spacer layer 140. According to some embodiments of the present disclosure, after etching for a certain period of time, the accumulated polymer layer 142 is removed, for example, using O2 gas. The resulting structure is shown in Fig. 4B-3, in which the upper portions of the spacer layer 140 are already thinned.

[0029] The information relating to the Fig. The processes described in 4B-2 and 4B-3 can be repeated as cycles, which can range from one cycle to about 100 cycles. Fig. 4B-4 shows the accumulation of the polymer layer 142 and the continued etching of the spacer layer 140. As a result of the etching, the fin spacers 39 are formed as shown in Fig. 4B-5. The perspective view of the corresponding wafer 10 is also shown in Fig. 4A, which also shows the gate spacers 38B.

[0030] After the fin spacers 39 have been installed as shown in the Fig. 4A and 4B-5, an etching process (hereinafter also referred to as fin recessing process) is performed to recess the portions of the protruding fins 24' that are not covered by the dummy gate stacks 30 and the gate spacers 38, resulting in the Fig. 5A. The corresponding process is described as process 210 in the Fig. 13. The recessing may be anisotropic, and therefore, the portions of the fins 24' that lie directly beneath the dummy gate stacks 30 and the gate spacers 38 are protected from etching. The upper surfaces of the recessed semiconductor strips 24 may, according to some embodiments, be lower than the upper surfaces 22A of the STI regions 22. Recesses 40 are thus formed between the STI regions 22. The recesses 40 are also located on the opposite sides of the dummy gate stacks 30. The lower surfaces of the recesses 40 may be higher than the lower surfaces 22B of the STI regions 22 and lower than the upper surfaces 22A of the STI regions 22. After the recesses 40 are formed, the fin spacers 39 remain.

[0031] According to some embodiments, on the same wafer and device die as the one shown in the Fig. 4A and 4B-5, some protruding fins 24' are not etched, and source / drain regions are formed based on the unetched protruding fins 24'. For example, Fig. 12 shows the unetched fins 24' and the corresponding source / drain regions. According to some embodiments of the present disclosure, fin recessing is performed on the protruding fins for p-type FinFETs, and no fin recessing is performed on the protruding fins for n-type FinFETs.

[0032] According to some embodiments of the present disclosure, the recessing is performed by a dry etching step. The dry etching can be performed using process gases such as C2F6, CF4, SO2, a mixture of HBr, Cl2, and O2, or a mixture of HBr, Cl2, O2, and CF2, etc. According to alternative embodiments of the present disclosure, the recessing is performed by a wet etching step. The wet etching can be performed using KOH, tetramethylammonium hydroxide (TMAH), CH3COOH, NH4OH, H2O2, isopropanol (IPA), or a solution of HF, HNO3, and H2O.

[0033] Fig. Figure 5B shows a cross-sectional view of the Fig. 5A, and the cross-sectional view is obtained from the vertical plane indicating the arrows 5B-5B in Fig. 5A. According to some embodiments of the present disclosure, as shown in Fig. 5B, the recesses 40 have substantially vertical edges that are substantially flush with the inner edges of the fin spacers 39.

[0034] Fig. 6 shows the epitaxial processes for forming epitaxial regions 42. The corresponding process is shown as process 212 in the Fig. 13. Throughout the description, the epitaxial regions 42 are also referred to as source / drain regions 42. The protruding fins 24', which lie beneath the gate stack 30 and are therefore not in the plane shown, are marked with dashed lines. The formation methods for the epitaxial regions 42 may include CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like. According to some embodiments, the epitaxial regions 42 comprise silicon germanium, silicon, or silicon carbon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or n-type impurity may be doped in situ during epitaxy. For example, if the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, or the like may be grown, and the epitaxial regions 42 are p-type.In contrast, if the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown, and the epitaxial regions 42 are n-type. According to alternative embodiments of the present disclosure, the epitaxial regions 42 are formed from a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the epitaxial regions 42 completely fill the recesses 40, the epitaxial regions 42 begin to expand horizontally, and facets may form.

[0035] If the protruding fins 24' are not recessed before the epitaxial regions 42 are formed, since the outer spacers 39A are higher than the inner spacers 39B, the outer sidewall surfaces of the protruding fins 24' facing the spaces between the groups have smaller areas and heights than the inner sidewall surfaces of the protruding fins 24' facing the spaces within the groups. Therefore, the portions of the epitaxial regions 42 growing from the inner sidewall surfaces have a greater height H5 than the height H4 of the portions of the epitaxial regions 42 growing from the outer sidewall surfaces. If the protruding fins 24' are recessed, similar results occur. The heights H4 and H5 are the heights measured from the top ends of the respective fin spacers 39A and 39B perpendicular to the respective top surfaces of the epitaxial regions 42.In other words, the height H4 is measured vertically upward from the outer sidewall of the outermost protruding fin 24', and the height H5 is measured vertically upward from the inner sidewall of the outermost protruding fin 24'. Although the protruding fins 24' may not lie in the plane shown (unless the plane is the outer sidewall of the gate spacers 38B), the positions of the protruding fins 24' can be determined. For example, when taking transmission electron microscopy (TEM) images to image the pattern shown in . Fig. 6, the fins 24' are visible in the TEM images.

[0036] According to some embodiments, the height H5 is greater than the height H4. The height difference (H5 - H4) may be greater than about 2 nm and may range between about 2 nm and about 10 nm. Also, the thickness T4 of the portions of the epitaxial regions 42 grown from the outer sidewall surfaces of the protruding fins 24' is smaller than the thickness T5 of the portions of the epitaxial regions 42 grown from the inner sidewall surfaces of the protruding fins 24'. The thickness difference (T5 - T4) may be greater than about 2 nm and may range between about 2 nm and about 10 nm. When the thickness T4 is small, the probability of bridging the epitaxial region 42 to the epitaxial region 42 of the nearest neighboring FinFET is reduced.

[0037] According to some embodiments, the formation of the epitaxial regions 42 is completed when the epitaxial regions 42 grown from the various fins 24' are spaced apart from each other and form unfused source / drain epitaxial regions 42 in the final FinFET. Accordingly, the epitaxial regions 42, as shown in Fig. 6, reflects the structure in the corresponding final FinFET. According to alternative embodiments, the epitaxial regions 42 are further grown, resulting in the Fig. 7. The corresponding outer height and inner height of the epitaxial regions 42 are denoted as H4' and H5'. According to some embodiments, the height H5' is greater than the height H4'. The height difference (H5' - H4') may be greater than about 2 nm and may range between about 2 nm and about 8 nm. Air gaps 43 are formed between adjacent fin spacers 39.

[0038] Fig. 8 shows a perspective view of the Fig. Structure shown in Figure 7. Fig. Figure 9 shows a perspective view of the structure after the formation of a contact etch stop layer (CESL) 46 and an interlayer dielectric (ILD) 48. The corresponding process is described as process 214 in the Fig. 13. The CESL 46 may be formed from silicon nitride, silicon carbonitride, or the like. According to some embodiments of the present disclosure, the CESL 46 is formed using a conformal deposition process such as ALD or CVD. The ILD 48 may include a dielectric formed using, for example, flowable chemical vapor deposition (FCVD), spin-on coating, CVD, or another deposition process. The ILD 48 may also be formed from an oxygen-containing dielectric, which may be a silicon oxide-based material such as tetraethyl orthosilicate oxide (TEOS oxide), a PECVD oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like.A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may be performed to level the top surfaces of the ILD 48 and the gate spacers 38 with each other.

[0039] Fig. 9 also shows the formation of replacement gates 50. The corresponding process is shown as process 216 in the Fig. 13. The training process includes removing the remaining parts of the dummy gate stack 30 (see Fig. 8) to form trenches, and forming replacement gates 50 in the resulting trenches. The replacement gates 50 include gate dielectrics 52 and metal gate electrodes 54. According to some embodiments of the present disclosure, each of the gate dielectrics 52 includes an interface layer (IL, not shown separately) as its lower portion. The IL is formed on the exposed surfaces of the protruding fins 24'. The IL may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the protruding fins 24' (in Fig. 9) a chemical oxidation process or a deposition process. The gate dielectric layer 52 may also include a high-k dielectric layer (not shown separately) formed over the IL. The high-k dielectric layer may include a high-k dielectric such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k value) of the high-k dielectric is higher than 3.9 and may be higher than about 7.0. The high-k dielectric layer overlies and may contact the IL. The high-k dielectric layer may be formed as a conformal layer and extend onto the sidewalls of the protruding fins 24' and the sidewalls of the gate spacers 38. According to some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD or CVD.

[0040] The gate electrode 54 may include a diffusion barrier layer and one (or more) work function layers above the diffusion barrier layer. The diffusion barrier layer may be made of titanium nitride (TiN), which may (but need not be) doped with silicon. The work function layer determines the work function of the gate and includes at least one layer or a plurality of layers of different materials. For example, the work function layer material may include a TaN layer and a titanium-aluminum (TiAl) layer above the TaN layer. After deposition of the one or more work function layers, another barrier layer is formed, which may be another TiN layer. A fill metal such as tungsten or cobalt may fill the remaining trenches left behind by the removed dummy gates.A planarization process may then be performed to remove excess portions of the diffusion barrier layer, work function layer, fill metal, etc., to form the gate electrodes 54.

[0041] As in Fig. As shown in Figure 9, hard masks 56 are formed over the gate stacks 50 and between the gate spacers 38. The hard mask 56 may be formed of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or the like. Forming the hard masks 56 may include recessing the replacement gate stacks 50, filling the resulting recesses with a dielectric, and performing a planarization process to remove excess portions of the dielectric.

[0042] Referring to Fig. 10A, some portions of the ILD 48 and the CESL 46 are removed to form contact openings (which will be occupied by contact plugs 60), followed by silicide-coating the exposed portions of the source / drain regions 42 to form source / drain silicide regions 58. The corresponding process is described as process 218 in the Fig. 13. A conductive material such as tungsten is filled into the contact openings to form the source / drain contact plugs 60. The corresponding process is described as process 220 in the Fig. 13. Thus, the FinFET 62 and the associated source / drain contact plugs are formed. According to some embodiments of the present disclosure, as shown in Fig. 10, source / drain regions 42 formed on the basis of different fins are fused. According to further embodiments of the present disclosure, the source / drain regions formed on the basis of different fins remain separate from each other.

[0043] Fig. 10B shows a cross-sectional view of the Fig. 10A, wherein the structure shown in Fig. 10B is obtained from the vertical plane which is the line 10B-10B in Fig. 10A. The corresponding outer height and inner height of the epitaxial regions 42 are denoted as H4'' and H5''. According to some embodiments, the height H5'' is greater than the height H4''. The height difference (H5'' - H4'') may be greater than about 2 nm and may range between about 2 nm and about 8 nm.

[0044] Fig. 11 shows a cross-sectional view of a FinFET 62' with unfused epitaxial regions 42. The corresponding outer height and inner height of the epitaxial regions 42 are denoted as H4''' and H5''', respectively. According to some embodiments, the height H5''' is greater than the height H4'''. The height difference (H5''' - H4''') may be greater than about 2 nm and may range between about 2 nm and about 10 nm. Also, the thickness T4' of the portions of the epitaxial regions 42 grown from the outer sidewall surfaces of the protruding fins 24' is less than the thickness T5' of the portions of the epitaxial regions 42 grown from the inner sidewall surfaces of the protruding fins 24'. The thickness difference (T5' - T4') may be greater than about 2 nm and may range between about 2 nm and about 10 nm. It is understood that the Fig. 10A and Fig. 10B shown FinFET 62 with the in Fig. 11 can coexist on the same die and the same wafer.

[0045] Fig.12 shows the FinFET 62″ in which the protruding fins 24′ are not etched and the epitaxy (the source / drain regions) 42′ is formed based on the unetched protruding fins 24′. According to some embodiments of the present disclosure, the FinFET 62″ is an n-FinFET, and the corresponding epitaxial regions 42 are n-type and may be formed from SiP, SiCP, Si, or the like. Instead of substantially straight facets, the epitaxial regions 42′ may also have a rounded outer surface. The corresponding outer height (measured from a top surface of the outer fin spacer 39A) and inner height (measured from a top surface of the inner fin spacer 39B) of the epitaxial regions 42′ are denoted as H6 and H7, respectively. According to some embodiments, the height H7 is greater than the height H6. The height difference (H7 - H6) can be greater than about 2 nm and can range between about 2 nm and about 10 nm.

[0046] The embodiments of the present disclosure have several advantageous features. By controlling the etching process to form fin spacers, the portions of the epitaxial regions within a group of epitaxial regions have greater heights than the outer portions of the epitaxial regions. This results in increased volume of the epitaxial regions and increased stress generated by the epitaxial regions. The likelihood of bridging of the epitaxial regions is also reduced.

[0047] According to some embodiments of the present disclosure, a method comprises forming isolation regions over a bulk semiconductor substrate; recessing the isolation regions, wherein upper portions of semiconductor strips between the isolation regions protrude higher than the upper surfaces of the isolation regions to form a fin group, and the fin group comprises a plurality of inner fins; and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins; and forming fin spacers on sidewalls of the plurality of inner fins, the first outer fin, and the second outer fin, wherein the fin spacers comprise an outer fin spacer on an outer sidewall of the first outer fin,wherein the outer sidewall faces away from the fin group and the outer fin spacer has a first height; and an inner fin spacer on an inner sidewall of the first outer fin, the inner sidewall facing the plurality of inner fins and the inner fin spacer having a second height that is less than the first height. In one embodiment, the first height is greater than the second height by a height difference of more than about 2 nm. In one embodiment, the outer fin spacer and the inner fin spacer are formed in a common process. In one embodiment, the method further comprises forming a gate stack, the gate stack being located on sidewalls and a top surface of each of the plurality of inner fins,the first outer fin and the second outer fin. In one embodiment, the method further comprises forming a gate spacer on sidewalls of the gate stack, wherein the gate spacer and the fin spacers are formed in a common formation process. In one embodiment, the method further comprises epitaxially growing epitaxial regions based on the plurality of inner fins, the first outer fin, and the second outer fin, wherein a third height of the epitaxial regions, measured directly above the outer fin spacer, is less than a fourth height of the epitaxial regions,measured directly above the inner fin spacer. In one embodiment, the fourth height is greater than the third height by a height difference of more than about 2 nm. In one embodiment, epitaxially growing the epitaxial regions comprises pulsing a bias voltage with a plurality of cycles. In one embodiment, the pulsing has a duty cycle in a range between about 10 percent and about 90 percent.

[0048] According to some embodiments of the present disclosure, a method comprises forming a gate stack on a plurality of semiconductor fins, the plurality of semiconductor fins comprising: a plurality of inner fins; and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins; and epitaxially growing epitaxial regions based on the plurality of semiconductor fins, wherein a first height of the epitaxial regions, measured along an outer sidewall of the first outer fin, is less than a second height of the epitaxial regions, measured along an inner sidewall of the first outer fin. In one embodiment, a difference between the first height and the second height is greater than about 2 nm. In one embodiment, the epitaxial regions formed based on the plurality of semiconductor fins are fused.In one embodiment, the epitaxial regions formed based on the plurality of semiconductor fins are not fused. In one embodiment, the method further comprises forming gate spacers on sidewalls of the gate stack; and, in a same process for forming the gate spacers, forming fin spacers on sidewalls of the plurality of semiconductor fins, the fin spacers comprising: a first outer fin spacer and a second outer fin spacer, the first outer fin spacer and the second spacer having a third height; and an inner fin spacer between the first outer fin spacer and the second outer fin spacer, the inner fin spacer having a fourth height that is smaller than the third height. In one embodiment, a difference between the third height and the fourth height is greater than about 2 nm.

[0049] According to some embodiments of the present disclosure, a device comprises a plurality of semiconductor fins, the plurality of semiconductor fins comprising: a plurality of inner fins; and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins; a gate stack on a sidewall and top surfaces of the plurality of semiconductor fins; fin spacers on one side of the gate stack, the fin spacers comprising: a first outer fin spacer and a second outer fin spacer, the first outer fin spacer and the second outer fin spacer having a first height; and an inner fin spacer between the first outer fin spacer and the second outer fin spacer, the inner fin spacer having a second height that is less than the first height;and semiconductor regions extending into spaces between each pair of fin spacers. In one embodiment, a difference between the first height and the second height is greater than about 2 nm. In one embodiment, the device further comprises a gate spacer on a sidewall of the gate stack, wherein the fin spacers are continuously connected to the gate spacer. In one embodiment, a first height of the semiconductor regions, measured directly above the first outer fin spacer, is less than a second height of the semiconductor regions, measured directly above the inner fin spacer. In one embodiment, the semiconductor regions are fused into a continuous semiconductor region.;

Claims

[1] Method comprising: Forming isolation regions (22) over a bulk semiconductor substrate (20); Deepening the isolation regions, wherein upper portions of semiconductor strips (24) between the isolation regions protrude higher than upper surfaces of the isolation regions to form a fin group, and wherein the fin group comprises: a plurality of inner fins (24'B); and a first outer fin (24'A) and a second outer fin (24'A) on opposite sides of the plurality of inner fins; and Forming fin spacers (39) on sidewalls of the plurality of inner fins, the first outer fin and the second outer fin, the fin spacers comprising: an outer fin spacer (39A) on an outer sidewall of the first outer fin, the outer sidewall facing away from the fin group and the outer fin spacer having a first height (H1); and an inner fin spacer (39B) on an inner sidewall of the first outer fin, the inner sidewall facing the plurality of inner fins, the inner fin spacer having a second height (H2) less than the first height (H1); wherein the profile of the fin spacers is tuned by pulsing a bias voltage with a plurality of cycles, the pulsing frequency being in the range between 0.01 kHz and 10 kHz. [2] The method of claim 1, wherein the first height (H1) is greater than the second height (H2) by a height difference of more than about 2 nm. [3] The method according to claim 1 or 2, wherein the outer fin spacer (39A) and the inner fin spacer (39B) are formed in a common process. [4] The method of any preceding claim, further comprising forming a gate stack (30), the gate stack extending on sidewalls and a top surface of each of the plurality of inner fins (24'B), the first outer fin (24'A), and the second outer fin (24'A). [5] The method of claim 4, further comprising forming a gate spacer (38A) on sidewalls of the gate stack, wherein the gate spacer (38B) and the fin spacers (39) are formed in a common formation process. [6] The method of any preceding claim, further comprising epitaxially growing epitaxial regions based on the plurality of inner fins (24'B), the first outer fin (24'A) and the second outer fin (24'A), wherein a third height (H4) of the epitaxial regions, measured directly above the outer fin spacer (39A), is less than a fourth height (H5) of the epitaxial regions, measured directly above the inner fin spacer (39B). [7] The method of claim 6, wherein the fourth height (H5) is greater than the third height (H4) by a height difference of more than about 2 nm. [8] A method according to any one of the preceding claims, wherein the pulsing has a duty cycle in a range of 10% to 90% or 20% to 60%. [9] A method according to claim 6 or 7, wherein the epitaxial regions are not fused. [10] A method according to any one of the preceding claims, wherein forming fin spacers (39) on sidewalls of the plurality of inner fins comprises: Forming a spacer layer (140); Performing an etching process for anisotropic etching of the spacer layer (140), wherein the etching process also includes forming a polymer layer (142) on the spacer layer (140). [11] The method of claim 10, wherein the plurality of cycles comprises switching a bias power on and off, and by switching the bias power on and off and adjusting the duty cycle, the etch rates and polymer accumulation rates are controlled to result in a desired difference between the first height and the second height.

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