TIME SIGNAL MONITORING DEVICE AND INJECTION DRIVER

Abstract

Clock signal monitoring device (100.1), comprising: a signal converter (205) configured to receive a clock signal (200.3) with a duty cycle and frequency and to convert the clock signal into a monitoring signal (205.1) with a peak value (206.2) with respect to the duty cycle and frequency of the clock signal (200.3), wherein the monitoring signal (205.1) comprises a triangular waveform signal (205.1); and a detector (301) in conjunction with the signal converter (205) configured to receive the monitoring signal (205.1), wherein the detector (301) comprises an active peak detector (206) configured to detect the peak value (206.2) of the triangle waveform signal (205.1) and to provide a peak value signal that continuously provides a signal of the level of the detected peak value (206.2), wherein the detector (301) is further configured to generate an error signal (407.1) when the peak value (206.2) of the monitoring signal (205.1) lies outside a predefined area.

Description

The present disclosure relates generally to the field of automotive engine control, and more particularly to an apparatus for monitoring timing signals, a control unit for vehicles.This section provides background information related to the present disclosure, which is not necessarily prior art.In an injection drive controller, an injection drive device and / or an injection driver, a clock signal is used to control the various functions of the controller and / or the injection driver. One possible functionality may be the provision of a control signal for an injector and / or an injection needle. To this end, an actual injection driver may use an external clock signal generated by an external clock source. Generally, a microcontroller may provide the external clock signal to the injector driver. The injector driver may condition the external clock signal and generate a signal for driving the injector. The injection driver can be connected to the injector, that is to say the mechanical and / or electrical component acts in accordance with the control signals provided by the injection driver. The injection driver substantially conceals the clock signals in front of the injector, since the injection driver is located between the external clock source and the injector.Inside the injection driver, a clock signal monitoring device or an internal clock unit for processing the clock signals is provided. For safety reasons, the controller and / or the injection driver may generate an internal clock signal in the clock signal monitoring device in addition to the received external clock signal. In this way, the internal clock signal may be used for monitoring and / or verifying the external clock signal. In addition, the injection driver may use an internal clock source that generates the internal clock signal as a backup clock source when erroneous conditions are detected in one of the clock signals. In one example, the internal clock source is within the clock signal monitoring device or within the internal clock unit. In particular, the actual devices for driving an injector of an engine are equipped with such an internal clock generator that can be used for detecting an erroneous external clock signal.However, the internal clock signal generated by the internal clock source may be considered more reliable than the external clock signal. Therefore, an actual control strategy can provide that the internal clock signal is always switched over when a deviation between the external clock signal and the internal clock signal is detected. In this control strategy, the external clock signal can always be considered defective if a fault occurs. If the external clock is considered to be faulty, the injection driver switches to the internal clock to drive a corresponding vehicle component, such as the injector. However, if the injection driver can be commanded to always switch to the internal clock after detecting incorrect conditions, the controller or the injection driver can be switched to the internal clock signal and / or to the internal clock even if the internal clock signal is the source for the signal discontinuity. However, the use of the faulted internal clock signal may result in missing injections. Missing injections may result in the engine operating inefficient, using the wrong injection amount, generating a wrong pulse width, and / or stalling the engine.US 6 552 578 B1 discloses a duty cycle detector comprising a clock input; a filter for averaging the clock input over at least one clock period to generate an average clock voltage; a first comparator receiving the average clock voltage from the filter and receiving a first reference voltage and generating an upper limit signal when the average clock voltage exceeds the first reference voltage; a second comparator receiving the average clock voltage from the filter and receiving a second reference voltage and generating a lower limit signal when the average clock voltage is below the second reference voltage; and logic receiving the upper limit signal from the first comparator and the lower limit signal from the second comparator, generating a shutdown signal when the lower limit signal or the upper limit signal is activated, thereby generating the shutdown signal when the average clock voltage is above an upper limit or below a lower limit.JP 2013-150 046 A discloses a shutdown circuit configured to change an internal impedance. Further, a clock signal generation unit for generating a clock signal in accordance with the signal level of the input signal input via the termination circuit, and a control unit that adjusts the impedance of the shutdown circuit based on the clock signal are disclosed. The control unit performs processing for adjusting the impedance of the shutdown circuit to have a target impedance in synchronization with the clock signal, and changes the impedance of the termination circuit to a predetermined impedance when it is determined that the clock signal is abnormal.US 2014 / 0 035 560 A1 discloses a method and an apparatus for limiting access to an integrated circuit when abnormal conditions are detected. These may include abnormal voltage, temperature, and / or clock. Both unusually low and unusually high parameter values (e.g., unusually low or high voltage, temperature, or clock frequency) may be detected. Further, an abnormal duty ratio of a clock signal can be detected. A sampled bandgap reference can be used to provide accurate voltage and current references while consuming a minimum amount of energy. Upon detection of an abnormal parameter value, one or more tamper indicators may be provided to initiate countermeasures against tampering, such as limiting access to the integrated circuit.GAMET, A.; et al., "A simple clock-fault detection analog circuit for high-speed crystal oscillators", in: 2015 38th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPR), Opatija, Croateia: IEEE 2015, ISBN 9789532330823, pp. 1588-1591, discloses a simple architecture for detecting clock errors in high-speed applications. A possible time error is converted into a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected, while a low voltage level implies a clock error. This detection system is intended for a system-on-chip such as microcontrollers using an external clock of 4 MHz to 50 MHz.US 4 255 789 A discloses a method and apparatus for controlling the various functions of an internal combustion engine. A microprocessor receives information about an engine operating parameter. This parameter is detected and then passed to input circuits for signal conditioning and conversion to digital words usable by the microprocessor. The microprocessor-based electronic engine control system calculates a digital word indicative of a computer controlled engine control operation, and the output circuit responds to predetermined computer generated commands and to the calculated digital command words to convert them into corresponding pulse width control signals or the like to control engine operations such as fuel injection spark timing, proportional and / or on / off EGR control.DE 197 22 114 A1 discloses a clock signal provision apparatus for a processor of a control device connected to a network, having a first oscillator for generating a first clock signal which can be connected to the processor; a controllable clock signal changing device for changing the first clock signal generated by the first oscillator; and a control device connected to a network for generating a control signal for controlling the clock signal changing device in dependence on communication signals transmitted via the network.Accordingly, it is desirable to provide an efficient engine control strategy. Moreover, it is desirable to detect a defective internal clock signal. Furthermore, it is desirable to detect an erroneous internal clock signal independently of the external clock signal. It is also desirable to decide which of two clock signals the defective signal may be. Further, other desirable features and features will become apparent from the following detailed description and appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.A clock signal monitoring device and / or an internal clock unit is provided for monitoring an internal clock signal. The clock signal monitoring device comprises a signal converter configured to receive the clock signal with a duty cycle and a frequency and to convert the clock signal into a monitoring signal with a peak value with respect to the duty cycle and / or with respect to the frequency of the clock signal. In one embodiment, the duty cycle of the clock signal may be associated with the average of the monitor signal. In a further embodiment, the frequency of the clock signal can be linked to the amplitude of the monitoring signal, in particular to the ripple of the monitoring signal and / or to the peak-to-peak value of the monitoring signal. Both the mean value and the amplitude can have effects on the peak value of the monitoring signal. The clock signal monitoring device further includes a detector in communication with the signal converter configured to receive the monitoring signal. The detector comprises an active peak detector configured to detect the peak value of the triangular waveform signal and provide a peak signal continuously providing a signal of the level of the detected peak value, wherein the detector is further configured to generate an error signal when the peak value of the monitoring signal is outside a predefined range. In other words, either a duty cycle deviation from a predetermined duty cycle and / or a frequency deviation from a predetermined frequency of the clock signal may change the peak value of the monitoring signal. Thus, if an error in the clock signal is due to a change in the duty cycle and / or to a change in the frequency, such an error may become visible due to a changed peak value of the monitoring signal. According to the invention, the monitoring signal is a triangular waveform signal. The clock signal monitoring device and / or the internal clock unit may include analog components to implement the described control and / or monitoring strategy in a substantially purely analog execution.The clock signal monitoring device may include a low pass filter. In an embodiment, the low pass filter may have a cut-off frequency such that an average value of the monitor signal is proportional to the duty cycle of the clock signal and a ripple of the monitor signal is proportional to the frequency of the clock signal. In a further embodiment, the low-pass filter may have a cut-off frequency that corresponds to one tenth of the frequency of the clock signal.The detector may include a comparator configured to compare the peak value of the monitoring signal with at least one of a first threshold value of the predefined range and a second threshold value of the predefined range that is greater than the first threshold value, and output a signal outside the range for the time while the peak value is below the first threshold value or the peak value is above the second threshold value. In an embodiment, the detector may include a de-leveller configured to receive the out-of-range signal and increase an output signal of the de-leveller over time during which the comparator outputs the out-of-range signal. The detector may further include an error signal generator configured to compare the output signal of the debouncing device to a predefined threshold and generate the error signal when the output signal of the debouncing device is greater than the predefined threshold.According to another embodiment of the present disclosure, a control unit, an injection driver for a vehicle and / or an arbitration module is provided, which includes an external clock signal terminal for providing an external clock signal, an internal clock signal terminal for providing an internal clock signal, and the clock signal monitoring device or the internal clock unit. The signal converter of the clock signal monitoring device is connected to the internal clock signal terminal in order to monitor the internal clock signal.A method of monitoring a clock signal may be provided. In one embodiment, the method includes receiving a clock signal having a duty cycle and a frequency in a signal converter. The method further includes converting, with the signal converter, the clock signal into a monitoring signal having a peak value related to the duty cycle and the frequency of the clock signal. This monitoring signal is provided to a detector which is connected to the signal converter. The method further includes generating, by the detector, an error signal when the peak value of the monitoring signal is outside a predefined range.In an embodiment, the method may further include transmitting a second clock signal from a second clock source when an error signal is generated.In an embodiment, the method may further include comparing the peak value of the monitoring signal with at least one of a first threshold value of the predefined range and a second threshold value of the predefined range that is greater than the first threshold value, and outputting a signal outside the range for the time while the peak value is below the first threshold value or the peak value is above the second threshold value.In an embodiment, the method may further include increasing a deprurler output signal over a period of time that the out-of-range signal is output. In another embodiment, the method may further include generating an error signal when the output signal of the deprurler is greater than the predefined threshold.Furthermore, a non-volatile program element is provided. In one embodiment, the non-transitory program element includes software code that, when executed by a processor, executes a method for monitoring a clock signal. Further provided is a non-transitory computer readable medium including software code that, when executed by a processor, executes a method for monitoring a clock signal.The exemplary embodiments are described below in connection with the following drawing figures, wherein like numerals designate like elements. FIG. 1 shows an injection driver for a better understanding of this disclosure. FIG. 2 is a schematic block diagram of a clock arbitration module including a clock monitoring device according to an exemplary embodiment of the present disclosure; FIG. 3 is a schematic functional diagram of a clock signal monitoring apparatus according to the present disclosure;FIGS. 4A and 4B are functional block diagrams of the clock signal monitoring apparatus according to an exemplary embodiment of the present disclosure;FIGS. 5A and 5B are collections of plots illustrating output signals of various components of the clock signal monitoring device as a function of time, according to an exemplary embodiment of the present disclosure;FIGS. 6A-1, 6A-2, and 6B are collections of plots illustrating output signals from various components of the clock signal monitoring device as a function of time, where the frequency of the monitored clock signal is outside a tolerance range, according to an exemplary embodiment of the present disclosure;FIGS. 7A and 7B are collections of plots illustrating output signals from various components of the clock signal monitoring device as a function of time, where the duty cycle of the monitored clock signal is outside a tolerance range, according to an exemplary embodiment of the present disclosure; and FIG. 8 is a flow diagram for a method for monitoring a clock signal according to an exemplary embodiment of the present disclosure.FIG. 1 is an injection drive device 100, an injection driver 100, and / or an injection drive controller 100 for an injector 101 and is illustrated for a better understanding of this disclosure. A functionality of the injection driver 100 may be driving the injector 101 by a control signal 103. This driving functionality may be done to control the proper timing of the injections based on a clock signal. For safety reasons, the injection driver 100 cannot rely only on a single clock source, e.g., an external clock source, when deriving the control signal for the injector 101. Even if the external clock source, such as a microcontroller (not shown in FIG. 1 ), can provide an external clock signal 102.1 with a high accuracy, the injection driver 100 may be equipped with an internal clock source (not shown in FIG. 1 ) for redundancy reasons. The internal clock source can be used as a backup clock source or as a redundant clock source, which can be used to detect deviations in the external clock signal 102.1. The internal clock source can also be used to replace a defective external clock source by switching to the internal clock source in the event of a fault. To identify an error in the external clock signal, the controller 100 may monitor the external clock signal 102.1 as well as the internal clock signal. Errors in external clock signal 102.1 can be detected by comparing external clock signal 102.1 with the internal clock signal. The device 100 for providing the drive signal for the injector 101 receives this external clock signal 102.1, which is to be monitored via the external clock signal input 102. An output terminal or terminal 103 of the injector driver 100 is connected to an injector 101 that uses the drive signal 103.1, 103.2 derived from the clock signal to drive the injector needle 101.1.FIG. 1 also shows two schematic time diagrams 103.1 and 103.3 of a control signal for an injector 101 provided at the output 103 of the injection driver 100. The timing diagram 103.1 is based on a correct clock signal 103.2 and the timing diagram 103.3 is based on a defective clock signal 103.4. Under normal operating conditions, the injection driver 100 provides the control signal 103.1 or the drive signal 103.1 at the output terminal 103. The control signal 103.1 is based on the clock signal 103.2 that is in the range. The timing of the clock signal 103.2 is within a predefined range and therefore the output signal 103.1 may be used for driving the injector 101. However, if the injection driver 100 is provided with an erroneous clock signal 103.4, the injection driver 100 may provide an out-of-range control signal 103.3 to the injector 101. This erroneous control signal 103.3 may occur in a case where the clock signal 103.4 is outside a predefined range. The valid range of a clock signal may be defined by a predetermined duty cycle and / or by a predetermined frequency. In the example of the erroneous control signal 103.3, the clock signal 103.4 has a reduced frequency compared to the frequency of the normal clock signal 103.2. This erroneous clock signal 103.4 may occur when the external clock signal 102.1 is used, but the signal itself is in an erroneous state. This erroneous signal 103.4 may also occur when an error occurs in the internal clock signal and the injection driver 100 switches to this erroneous internal clock signal, even if the external clock signal may function correctly.In order to avoid such fault conditions, the position of a faulted clock signal must be detected as quickly as possible in order for the injection driver 100 to switch to the internal clock signal when the external clock signal is detected as faulted. Alternatively, the injection driver 100 may prevent the switching to the internal clock signal when the internal clock is identified as a source of error. If the external clock signal 102.1 is detected as faulty, for example if the external clock signal is not available or lies outside the predefined range, the internally generated backup clock signal may be used to generate a control signal for driving the injector 101. The injection timing of the fuel to be provided to an engine is associated with the drive signal. Switching to the internal clock signal may prevent the motor from being locked or stopped provided that the internal clock signal is functioning properly. For monitoring the external clock signal 102.1, the internal clock is used as a comparison signal for the external clock, and as long as no errors are detected, the external clock signal 102.1 is used as a basis for a control signal 103.1, which is provided to the injector 101 via the output terminal 103 of the injection driver 100. The internal clock or the internal clock signal is additionally used as a backup device or backup signal. However, in order to use the internal clock signal as a reference signal and / or as a backup signal, an additional functionality for distinguishing fault conditions between the external clock signal and / or for identifying the fault location may be proposed.Identifying the location of the fault source may prevent the injection driver 100 from incorrectly interpreting the external clock signal 102.1 if the internal clock has a problem or is faulty. As a result, the control algorithm can prevent switching to the internal clock in the event of an error of the internal clock signal. Thus, the engine may be protected from an incorrect injection amount, the pulse width may be correctly monitored, and / or engine stalling may be prevented.FIG. 2 is a schematic block diagram of a clock arbitration module 250 including a clock signal monitoring device 100.1 of an injection driver 100, according to an exemplary embodiment of the present disclosure. The injection driver 100 is not shown in FIG. 2. The clock arbitration module 250 has an input terminal 102 for receiving an external clock signal and may be configured to condition and / or modify the external clock signal 102.1 as needed and provide the external clock signal to the external clock signal output 203 of the clock arbitration module 250. In this way, the external clock signal is provided to an output of the injection driver 100. The clock arbitration module 250 also has an internal clock signal output terminal 204 for providing an internal clock signal. Both output terminals 203, 204 form a common output terminal 103, which can provide an actual control signal for an injector 101 (not shown in FIG. 2 ). The drive signal is derived from a corresponding clock signal. The common output terminal 103 comprises a switching device 103.6 or a switch 103.6 configured to select the correct clock signal and condition the drive signal 103.1, 103.2 according to the selected clock signal. The drive signal is provided from the injection driver 100 to the injector 101 via the connection 103. In one example, within the clock arbitration module 250, the switch 103.6 may be configured to select the clock signal to be used to generate the drive signal for the injector 101. The switch 103.6 is connected to the output terminal 103 of the injection driver 100. In one example, the switch 103.6 may be controlled by the clock signal monitoring device 100.1. The drive signal 103.1, 103.2 for the injector 101 provided via the output terminal 103 may be derived from a clock signal selected from the group of clock signals consisting of the internal clock signal generated by an internal clock 100.2 and the external clock signal 102.1. The external clock signal 102.1 can be provided via the external clock signal output 203 and the internal clock signal via the internal clock signal output 204. The clock signal monitoring device 100.1 does not receive the external clock signal 102.1 in order to be able to operate independently of the external clock signal.The internal clock, clock source or clock generator 100.2 is used to generate an internal clock signal in the injection driver 100. The internal clock 100.2 may generate the internal clock signal independently of the external clock signal received at an input terminal 102. The clock signal monitoring device 100.1 comprises a sampling connection 100.3 in connection with the internal clock 100.2 in order to provide the internal clock signal to the clock signal monitoring device 100.1. The clock signal monitoring device 100.1 is adapted to determine whether the internal clock signal, the internal clock signal provided by an internal clock source 100.2, has a correct or incorrect timing irrespective of the external clock signal. The clock signal monitoring device 100.1 is capable of distinguishing an erroneous state of the internal clock signal regardless of the external clock signal. This independence may allow for determining an error in the internal clock signal and / or internal clock 100.2.The implementation of the clock signal monitoring device 100.1 as a self-sufficient purely analog circuit can enable the detection of an abnormality of the internal clock signal independently of substantially each external input and in particular independently of the external clock signal. The purely analog circuit can be constructed from hardware components and can be essentially software-independent. This implementation may also be used to correctly identify the position of an erroneous clock signal. In particular, the internal clock 100.2 can be identified as a source of a different clock signal and a switching to the internal clock signal can be prevented. In this way, the risk of engine stall can be minimized if the internal clock 100.2 is chosen incorrectly as a clock source. Moreover, the safety of the vehicle with such a driver 100 and customer satisfaction may be improved. The clock signal monitoring device 100.1 may be used in the injection driver 100 using a backup clock or a redundant clock for monitoring an external clock signal. For example, such a clock signal monitoring device 100.1 can be retrofitted into an existing injection driver 100 using at least two redundant clock sources 100.2, 102. In an example where a plurality of clock sources are used, the switch 103.6 may be adapted to select from a plurality of clock sources.An erroneous state of the internal clock 100.2 may include a frequency deviation and / or a situation where a duty cycle of the internal clock signal is out of range. The strategy for handling at least two clock sources, 102, 100.2, within an injection driver 100 as set forth in this disclosure may include the following considerations. The internal clock signal may be substantially a square wave signal having a constant frequency and a constant duty cycle. By applying this internal clock signal to a low pass filter, a substantially triangular waveform with a constant mean value can be generated and provided at the output of the low pass filter. The average value of the triangular signal can be directly linked to the duty cycle of the clock. The amplitude of the triangular waveform or the ripple of the triangular waveform may be directly associated with the clock frequency. If the clock frequency or duty ratio is outside an acceptable range, it is possible to detect such an excess of an acceptable range by analyzing the peak value of the filtered signal. In order not to rely on the external clock, all circuits for detecting the internal clock error may be implemented as analog circuits and independent of the external clock.FIG. 3 is a schematic functional diagram of the components used for constructing the clock signal monitoring apparatus 100.1 according to an exemplary embodiment of the present disclosure. The clock signal 200.3 or the internal clock signal 200.3 generated by the internal clock signal source 100.2 is a square wave signal 200.3 having a constant frequency and a constant duty cycle. This constant frequency and duty cycle may be predefined to provide a regular signal. An example of the clock signal is shown in diagram 200.2. This timing diagram 200.2 shows the internal clock signal 200.3 as a square wave signal recorded as a voltage signal over time.The internal clock signal 200.3 is provided to the signal monitoring device 100 via the scanning line 100.3. In particular, the internal clock signal 200.3 is provided to the converter 205. The converter 205 includes a low pass filter. The low pass filter or converter 205 receives the square wave clock signal 200.3 and converts the signal into a triangular wave form 205.1. This triangular waveform 205.1 has an average value 205.2 and is shown in diagram 205.3 as a voltage curve 205.1 over time. Internal clock signal 200.3 is also shown in diagram 205.3 to illustrate how square wave clock signal 200.3 is converted to a triangular wave signal 205.1. The average 205.2 may be constant and may be an indication that the triangle wave 205.1 varies from peak to peak. Specifically, the low pass filter of the converter 205 may have a defined cut-off frequency.This cut-off frequency of the low-pass filter is configured such that the square-wave clock signal 200.3 is converted into the triangular signal 205.1 with an average value 205.2 which is directly linked to the duty cycle of the clock signal 200.3. Furthermore, the cut-off frequency is configured such that the amplitude and / or ripple of the triangular waveform 205.1 is directly associated with the clock frequency of the clock signal 200.3. This relationship between duty cycle and / or frequency and mean value or amplitude can make it possible to determine whether the duty cycle and / or the frequency are within a predefined tolerance range. If the clock frequency and / or the duty cycle is / are outside an acceptable range, it is possible to detect this error in the signal by analysing the peak value of the filtered signal. In order to generate a peak value 206.3 of the triangular signal 205.1, an active peak detector 206 is provided in the signal path of the clock signal monitoring device 100.The peak signal 206.2 generated by the peak detector 206 is depicted in the graph 206.1 as a voltage curve 206.2 over time. The peak signal 206.2 generated by the active peak detector 206 may substantially correspond to the edges 206.3 and / or peak values 206.3 of the triangular waveform 205.1. In other words, as soon as a maximum value 206.3 of curve 205.1 is detected, this value 206.3 is essentially kept as a peak value curve 206.2. A tolerance range can be defined by the lower limit value 206.4 and the upper limit value 206.5. As long as the peak value 206.3 and / or a corresponding peak value curve 206.2 lie within this tolerance range 206.4, 206.5, the corresponding clock signal is assumed to be acceptable. In other words, if the peak values 206.3 of the triangular wave 205.1 are in this tolerance range between 206.4 and 206.5, the internal clock signal 200.3 satisfies the predefined condition and the internal clock signal 100.2 is assumed to function correctly. Thus, the internal clock signal 200.3 generated by the internal clock 100.2 may be used as a reference for monitoring the external clock signal 102.1 and / or as a backup clock source in the event of a failure of the external clock signal. By converting the clock signal 200.3 into a triangular signal 205.1 and monitoring the peak values 206.2 of the triangular signal 205.1, it is therefore possible to detect the validity of the signal. The monitoring process may include comparing the peak curve 206.2 of the filtered signal with the predefined range 206.4, 206.5. Reducing the monitoring process to a comparison of the peak values 206.2 with the threshold values 206.4, 206.5 can prevent analyzing another signal and reduce the complexity of the circuit.The limits 206.4 and 206.5 of the range are monitored by an out-of-range detection comparator 207 which is adapted or configured to detect peak values 206.2 and / or peak values 206.3 which exceed at least one of the limit values 206.4, 206.5 or the threshold values 206.4, 206.5. During the time that the peak signal 206.2 and / or the peak values 206.3 are between the limits defined by the comparator 207, the comparator 207 generates substantially no output signal or an output signal that is very close to 0 V. The output signal of the comparator 207 is shown in the diagram 207.1. The high value 207.2, which is shown in the diagram 207.1 of FIG. 3, shows that the comparator 207 has detected that a limit of the upper limit 206.5 and the lower limit 206.4 has been exceeded. Referring to FIG. 3, it is noted that the peak curve 206.2 is present regardless of whether the curve 206.2 is in range or out of range, but the output of the comparator 207 reaches the value 207.2 only during the temporal peak 206.2 out of range 206.4, 206.5. In other words, the dashed line 207.2 in the diagram 207.1 only indicates the high value that could be reached during the time when the peak 206.2 is outside the range 206.4, 206.5, and is not the signal of the diagram 206.1 in which the peak curve 206.3 is within the range 206.4, 206.5. An alternative interpretation of curve 207.2 is that this curve indicates a signal that belongs to a time duration in which curve 206.2 is outside the range.The output signal 207.2 or the clock NOK signal 207.2 of the comparator 207 may be a constant high voltage or a constant low voltage (0 V), depending on the quality of the clock signal 200.3. When the internal clock signal 200.3 is within the predetermined range 206.4, 206.5, a low value signal (0 V) is provided at the output of the comparator 207. If the internal clock signal 200.3 is outside the range 206.4, 206.5 and is erroneous, a high value signal 207.2 is provided at the output 207 of the comparator. The output signal 207.2 of the comparator 207 provides the corresponding signal to the deprurizer 208. The deprurler 208 generates a signal which increases over time if, in the event of a fault, a high-value signal 207.2 is provided from the comparator 207 to the deprurler 208. The deprurizer 208 in combination with a comparator makes a varying input signal substantially a stable state to provide a stable signal indicative of a fault condition. The deprurizer 208 maintains its output at a stable error signal once an error situation exists over a tolerable period of time. The output signal 208.2 of the deprurizer 208 is shown in diagram 208.1 as a time variant signal 208.2. Using the example of diagram 208.1, it can be assumed that there is an error situation at the time of the origin of the diagram when signal 208.2 rises from the origin of diagram 208.1. The rising signal 208.2 is caused by a high value signal 207.2 during the temporal peak curve 206.2 which lies outside the range 206.4, 206.5. The deprurler signal 208.2 is compared to a threshold 209.1 set by the output comparator 209 associated with the deprurler 208. Error detection is assumed when the output signal 208.2 of the deprurler exceeds the threshold value 209.1. Setting a threshold may therefore enable providing hysteresis 208.3, minimum acquisition time 208.3, and / or delay 208.3 before an actual warning message may be generated by clock signal monitor 100.1. In other words, such a threshold 209.1 may allow a delay in the provision of an error indication, and therefore such a delay may be provided to accept a transient error condition of the internal clock signal 200.3. In other words, the threshold 209.1 may allow the sensitivity of the circuit to a fault condition to be varied. In this way, by shifting the threshold 209.1, a delay 208.3 or response time 208.3 may be arbitrarily set. The response time 208.3 is defined as the time between the first moment at which the peak value 206.3 of the triangular signal 205.1 exceeds the tolerance range 206.4, 206.5 and the moment at which the output signal 208.2 of the deprurler reaches the threshold value 209.1. This threshold value 209.1 defines a tolerance range close to time, while the limit values 206.4, 206.5 define a frequency and / or duty cycle tolerance range. During the time range 208.3, the clock signal may be judged to be incorrect or out of order (clockNOK). Reaching the threshold value 209.1 can be linked directly to a clock error signal "clock error" provided at an output of the output comparator 209. If, for example, only a short-term deviation (clockNOK) of the clock signal whose duration is below the time tolerance range 208.3 occurs, the limit value 209.1 is not exceeded and the signal deviation from the preset values is not recognized by the clock signal monitoring device 100.1. The clock signal monitoring device 100.1 includes the signal converter 205 or the low pass filter 205, the active peak detector 206 or the peak comparator 206, the comparator 207 for out-of-range detection, the deprurizer 208 and the output comparator 209.FIGS. 4A and 4B are a detailed block diagram of the clock signal monitoring apparatus 100.1 according to an exemplary embodiment of the present disclosure. In particular, Figure 4 shows an electrical circuit implementing the functionality of a clock signal monitoring device 100.1 implemented by purely analog components. For the sake of figurative reasons, the block diagram is based on a simulation program which simulates the internal clock signal as an exemplary embodiment of the present invention. Starting from such a block diagram, a corresponding analog circuit can be derived. The internal clock 100.2 or the clock source 100.2 includes two oscillating devices 300.1, 300.2. The oscillation devices 300.1, 300.2 are connected to the clock unit 300.3 in order to generate the square-wave clock signal 200.3 at the output 100.3 of the clock generation device 100.2. The clock signal 200.3 is provided to the signal converter 205 via the output interface 100.3.The signal converter 205 includes a resistor 300.4 and a capacitor 300.5. The resistor 300.4 and the capacitor 300.5 are arranged in a low pass configuration such that the signal converter 205 forms a low pass filter. Capacitor 300.5 is connected to resistor 300.4 and to a common reference potential 300.30 of circuit 100. Resistor 300.4 is also connected to clock output 100.3. In one example, resistor 300.4 has a resistance of 1 Ω and capacitor 300.5 has a capacitance of 1 μF.The clock signal monitoring apparatus 100 includes the signal converter 205 and a detector 301 in communication with the signal converter 205. The signal converter 205 is configured to receive the clock signal 200.3 provided at the output 100.3 of the clock source 100.2. The clock signal 200.3 has a duty cycle and a frequency. The signal converter 205 is further configured to convert the clock signal 200.3 into a monitoring signal 205.1 having a peak value 206.3 related to the duty cycle and the frequency of the clock signal 200.3. The clock signal 200.3 has a rectangular waveform and the monitor signal 205.1 has a triangular waveform.The detector 301 is configured to receive the monitoring signal 205.1 provided from the signal converter 205 via the connection resistor 300.7 and generate an error signal. The error signal may alternate between two output values, e.g., between two different voltages. In one example, these two output signals may be referred to as "clockNOK (clock NOK)", "clock fault (clock error)". These designations are used to distinguish the two signals within this text. Any other identification may be used for these signals. The first error signal "clockNOK" and the second error signal "clock fault" may be generated when the peak value 206.2 of the monitoring signal 205.1 is outside a predefined range 206.4, 206.5. To this end, detector 301 includes active peak detector 206, out-of-range detection comparator 207, deprurizer 208, and output comparator 209.The low pass filter 205 has a cut-off frequency configured such that the average value 205.2 of the monitor signal 205.1 is proportional to the duty cycle of the clock signal 205.1 and that a ripple of the monitor signal 205.1 or a peak-to-peak signal of the monitor signal 205.1 is proportional to the frequency of the clock signal 200.3. In one example, the cutoff frequency of the low pass filter is 1 / 10 of the frequency of the clock signal 205.1. In one example, the cutoff frequency is predefined. The monitoring signal 205.1 is derived from the internal clock signal 200.3 and has a triangular waveform.The active peak detector 206 is configured to detect a maximum value 206.2 or a peak value 206.2 of the triangular waveform 205.1 and provide a signal that substantially continuously provides a signal of the level of the detected peak value. This peak signal 206.2 of the monitoring signal is provided to a comparator 207 to monitor at least one of a first or lower limit value 206.4 and a second or upper limit value 206.5. The second limit value 206.5 is greater than the first limit value 206.4.The active peak detector 206 includes a comparator 300.6 or an operational amplifier 300.6. A non-inverting input of the comparator 300.6 is connected to the low-pass filter 205 via the connection resistor 300.7. The inverting input of the comparator 300.6 is connected via the feedback resistor 300.11 to the cathode 300.8 of the diode 300.9. The anode 300.10 of the diode 300.9 is connected to the output of the comparator 300.6. The output 300.12 of the active peak detector 206 includes a capacitor 300.13 and a resistor 300.14 in a parallel configuration forming an output low pass filter and / or a latch circuit. The comparator 300.6 of the active peak detector 206 is arranged in a voltage follower configuration with a high input resistance and a low output resistance. Capacitor 300.13 is charged via diode 300.9. Capacitor 300.13 can be charged quickly by the low output resistance of voltage follower 300.6. The diode 300.9 prevents the capacitor 300.13 from discharging. When the signal of the triangle wave signal 205.1 is in a decreasing phase, the capacitor 300.13 continues to maintain the voltage at this high level, so that the out-of-range detection comparator 207 permanently receives a peak value of the triangle wave signal 205.1. However, when the clock frequency and / or the duty cycle of the clock signal is changed, the peak value that can be stored in the capacitor 300.13 also changes.In one example, the active peak detector 206 includes a connection resistor 300.7 of 1Ω, a feedback resistor 300.11 of 1Ω, and an output resistor 300.13 of 1Ω. The gain of the comparator 300.6 or OPAMP 300.6 is 100k. The diode 300.9 has a breakdown voltage of 0.7 V and the output capacitor 300.13 has a capacitance of 100 μF. The output 300.12 of the active peak detector 206 is connected to the comparator for out-of-range detection 207 or to the area monitoring device 207.The comparator 207 for out-of-range detection includes two comparators 300.15, 300.16, both connected to the output 300.12 of the active peak detector 206. The noninverting input of the upper threshold comparator 300.15 is connected to the output 300.12 of the active peak detector 206. The inverting input of the lower threshold comparator 300.16 is connected to the noninverting input of the upper threshold comparator 300.15 and to the output 300.12. The inverting input of the upper threshold comparator 300.15 is connected to an upper reference voltage source 300.17 which determines the upper threshold 206.5. The non-inverting input of the lower threshold comparator 300.15 is connected to the lower reference voltage source 300.18, which determines the lower threshold 206.4. The output of the comparator 300.15 and the output of the comparator 300.16 are each connected to a corresponding input of the NAND gate 300.19. The output 300.20 of the NAND gate 300.19 defines the output signal of the comparator 207 for out-of-range detection. The comparator 207 for out-of-range detection generates a high value signal 207.2 when an out-of-range situation is detected, i.e. when the duty cycle and / or the frequency of the clock signal 200.3 is outside a predetermined range. The output signal 207.2 of the comparator 207 for out-of-range detection is output via the output 300.20 to the input of the deprurizer 208. In one example, out-of-range detection comparator 207 includes an upper threshold 206.5 of +3.23V and a lower threshold 206.4 of +2.98V specified by respective reference voltage sources 300.17, 300.18.The deprurizer 208 has a supply voltage 300.21 which is connected to an electronic switch 300.22, e.g. a transistor 300.22, and to a resistor 300.23 and to a capacitor 300.24. Capacitor 300.24 is connected in parallel with resistor 300.25. One end of capacitor 300.24 and resistor 300.25 form output 300.26 of deprurizer 208. The other end of the capacitor 300.24 and the resistor 300.25 are connected to the common potential 300.30. In one example, the deprurizer 208 includes a supply voltage 300.21 of 5 V, a resistor 300.23 of 1Ω, a capacitor 300.24 having a capacitance of 5 μF, and an output resistor 300.25 of 10Ω. The output 300.26 of the deprurizer 208 is connected to an input of the output comparator 209. As long as NAND 300.19 generates a signal, transistor 300.22 switches and allows capacitor 300.24 to be charged by voltage source 300.21 and to generate signal 208.2 which substantially corresponds to the charging curve of capacitor 300.24. NAND 300.19 provides switching signal 207.2 to transistor 300.22 during the time at least one of the outputs of comparators 300.15, 300.16 is active. In other words, when the peak value 206.2, 206.3 of the monitoring signal 205.1 generated by the active peak detector 206 is in a range from 206.4 to 206.5, both outputs of the comparators 300.15, 300.16 are high and the output of the NAND 300.19 is low. As a result, the transistor 300.22 does not switch and no output signal is generated. If an error situation in the internal clock generator 100.2, 300.3 generates a peak value 206.2, 206.3 outside the tolerance range 206.4, 206.5 and causes the output 300.20 of the comparator 207 to change too high for out-of-range detection and generates an output signal 207.2 with a high level, and if this error situation is continuously present over an interval of at least the minimum detection time 208.3, the detector output 300.29 indicates an error situation in the internal clock generator 100.2, 300.3 or a second error state. In one example, this second fault condition is referred to as a "clock fault" condition. The first and / or second fault state signals, e.g. "clockNOK" and / or "clock fault", are used for fault detection of the internal clock signal.Output comparator 209 includes voltage source 300.27 and comparator 300.28. The voltage source 300.27 is connected to the inverting input of the comparator 300.28, and the output of the deprurizer 208 is connected to the noninverting input of the comparator 300.28. Voltage source 300.27 determines a threshold 209.1 responsible for the time delay 208.3 between the first occurrence of an error situation that generates the second error condition and the error output signal clock fault. In other words, the threshold 209.1 may indicate a dead time, while the output 300.29 of the comparator 209 or the detector 301 ignores an erroneous internal clock signal. In one example, the voltage source 300.27 or the current source 300.27 uses a voltage of 3.5 V. Only when there is an error situation longer than the time delay 208.3 is an error indicated. When the signal 208.2 reaches the threshold determined by the voltage source 300.27, the output 300.29 of the output comparator 209 provides a high value signal for the second error signal, e.g., the "clock fault" error signal, indicating an erroneous internal clock signal. This second error signal or the error signal "clock fault" generated by the clock signal monitoring device 100.1 can be used to prevent an external clock signal from being replaced by the internal clock signal 100.2, 200.3. However, if it is determined that the external clock signal is faulty, the internal clock signal 100.2, 200.3 may be used as a substitute for a faulty external clock source.Whether the internal clock signal 100.2, 200.3 or the external clock signal provided via the input 102 is used is determined by the switch 103.6. The switch 103.6 is controlled by the first and / or second error signal.FIGS. 5A and 5B are collections of plots illustrating output signals of various components of the clock signal monitoring apparatus 100 as a function of time according to an exemplary embodiment of the present disclosure. The diagram 401 of FIG. 5 represents the square wave shape of the clock signal 200.3, the triangular waveform of the monitor signal 205.1, the peak signal 206.2, the lower threshold 206.4, and the upper threshold 206.5 of the acceptable range of the peak detector. The triangular wave signal 205.1 is a filtered clock signal 205.1. The lower threshold signal 206.4 is a constant value that determines a lower threshold, and the upper threshold signal 206.5 is a constant value that determines an upper threshold. In a particular example, the lower and upper threshold signals 206.4, 206.5 correspond to the upper reference voltage source 300.17 and the lower reference voltage source 300.18, respectively. The peak signal 206.2 is the output signal of the peak detector device 206. A detailed view of curves 206.2, 206.4, 206.5 and their relationship to each other is shown in detailed diagram 402. The abscissa 403 of the diagram 401 is in the range of 3.02 ms to 3.03 ms.The ordinate 404 is in the range of 0 V to 6.0 V. The frequency of the clock signal 200.3 is preset to 1 MHz with a duty cycle of 50% and leaves the peak signal 206.2 between the lower and upper threshold values 206.4, 206.5. A duty cycle of 50% means that the clock signal 200.3 consists of 50% of a low period or 0V and 50% of the high period or 5V, as can be seen, for example, in the first period of the signal 200.3 in the range of 3.02 ms to 3.021 ms.The diagram 405 shows the output signal 208.2 of the deprurizer 208 at 0V corresponding to a low level. This low signal indicates a correctly operating clock source 100.2, 300.3. The ordinate 406 of the diagram 405 is in the range from 0 to 2.0 V.The diagram 407 shows two signals indicative of different levels of detected clock errors, a first error signal 407.1 and a second error signal 407.2. In this particular example, illustrated in FIGS. 5, 6, 7, the clock error of the internal clock signal 200.3 is indicated by a clockNOK signal 407.1 and the clock error signal clock fault 407.2. The first clock error signal "clockNOK" 407.1, which reaches a predefined value, indicates that an error situation of the clock signal actually exists. This may be a temporary error that is eliminated over time by a type of self-healing process. The second clock fault signal "clock fault" 407.2, when a predetermined value is reached, indicates that a clock fault has been present for an unacceptably long time and initiates an alarm and / or fault handling routine. In FIG. 5, with the predetermined clock frequency and the duty cycle being provided, the two signals "clockNOK" 407.1 and "clock fault" 407.2 remain unchanged in their original state and therefore indicate that there is no problem with the internal clock signal 200.3. Accordingly, when a deviation is detected between the internal clock signal 200.3 and the external clock signal 102.1, the external clock signal 102.1 may be deemed to be erroneous and the controller may switch from the external clock signal 102.1 to the internal clock signal 200.3 to restore the clock signal.FIGS. 6A-1, 6A-2, and 6B are a collection of plots illustrating output signals of various components of the clock signal monitoring device 100 as a function of time, wherein the frequency of the clock signal 200, 3 is outside a tolerance range, according to an exemplary embodiment of the present disclosure. The frequency of the clock signal 200.3 is changed from 1 MHz to 1.5 MHz, and the duty ratio is maintained at 50%. In this case, the deprurizing signal 208.2 increases if the frequency NOK (not OK) or the frequency is erroneous. The increase in the deprurler signal 208.2 occurs because the peak detector output is out of range. The accepted frequency range is chosen to be 825 kHz - 1.2 MHz. If the frequency of the clock signal 200.3 is within this frequency range 825 kHz-1.2 MHz, the peak signal 206.2 lies between the lower and upper threshold values 206.4, 206.5, e.g. within 2.98 V and 3.23 V. However, if the frequency of the clock signal 200.3 lies outside the permissible frequency range 825 kHz-1.2 MHz, an error is detected. In this situation, the clock fault signal 407.2 is "1" or high. As shown in FIG. 6 at time 3 ms 501, the frequency of clock signal 200.3 is increased from 1 MHz to 1.5 MHz. The triangular wave signal 205.1 or the monitor signal 205.1 reduces the ripple or peak-to-peak value of the triangular wave signal 205.1. As shown in detail view 502 (FIG. 6B ), clock signal 200.3 changes the ripple of triangular wave 205.1 such that peak 206.3 and / or peak curve 206.2 of triangular wave 205.1 is outside the range defined by lower threshold 206.4 and higher threshold 206.5. As a result, the output 208.2 of the debouncing increases through the charging capacitor 300.24 at a time indicated by reference numeral 503, at 3.005 ms, or at 0.0030044 s and converges toward the output comparator threshold 209.1. The threshold 209.1 or the threshold 209.1 determines the acceptable detection time 208.3.At the time indicated by reference numeral 503, when curve 208.2 begins to develop, the first error signal "clockNOK" 407.1 changes from low to high, indicating a transient degradation of clock quality. After the tolerable out-of-range time 208.3 has been exceeded, the second error signal 407.2 or the clock error signal "clock fault" 407.2 also changes from low to high at the present time 3.0258 ms (M0), which indicates that a temporary error was present in the clock signal for too long and an unacceptable error situation is indicated in the clock signal. With respect to a clock error, there exists a first clock error signal, e.g., "clockNOK", and a second clock error signal, e.g., "clock fault". The first clock error signal clockNOKindicates whether or not the peak 206.2 is out of range. The second clock error signal clockfault means that the error has been debouncing or was present over too long a time and is thus validated. In other words, the clock error signal set to a high value indicates that the duration of an erroneous clock situation is present over a predefined period of time. Thus, clockNOK indicates temporary degradation of the internal clock signal, while clock fault means a degraded clock signal not to be recovered.Clock error signal clockNOK 407.1 having a high value or state indicates that a fuse to the internal clock source should be prevented because a frequency error has occurred. The minimum detection time 208.3 is 21 μs. This time limit 208.3 can be set by dimensioning the deprurizing filter and in particular by dimensioning the capacitance 300.24 of the deprurizing 208. The detection duration is dimensioned such that the system can tolerate the erroneous clock over this time interval without being significantly damaged. The detail view 502 of the diagram 401 in FIG. 6A-1 shows the peak detector output signal 206.2 outside of the allowable range between the range boundaries 206.4 and 206.5.In an example, the detector 301 includes a peak comparator 207 configured to compare the peak 206.2, 206.3 of the monitoring signal 205.1 to at least a first threshold 206.4 of the predefined range and a secondary threshold 206.5 of the predefined range. The secondary threshold is greater than the first threshold. The peak value comparator 207 has an output at which an out-of-range signal 207.2 is provided for the time in which the peak value lies below the first limit value 206.4 and / or the peak value lies above the second limit value 206.5. The first error signal clockNOK 407.1 is linked to the output signal 207.2 of the comparator 207 for out-of-range detection. The second error signal clockfult 407.2 is provided at the output 300.29 of the output comparator 209. This second error signal 407.2 is provided at the output 300.29 of the comparator 209. The second error signal 407.2 is an error signal that has been debouncing. In other words, the second error signal 407.2 is an error signal indicating that a first error signal 407.1 was present in a stable state over a predefined period of time.FIGS. 7A and 7B are a collection of plots illustrating output signals from various components of the clock signal monitoring device 100, wherein the duty cycle of the clock signal 200.3 is outside a tolerance range, according to an exemplary embodiment of the present disclosure. The clock frequency in Figs. 7A and 7B is selected as a preset clock frequency 1 MHz. The duty ratio is set to 60%, i.e., a value that is 10% higher than the predetermined duty ratio of 50%, and thus outside a tolerance range for the duty ratio. In this case, the deprurizing signal 208.2 rises and the frequency is erroneous or NOK, i.e. not OK, since the peak detector output is out of range. In this situation, an error is detected because the first clock error signal clock fault is "1.". The diagram 401 of FIG. 7A shows the clock signal 200.3 with the constant predetermined frequency of 1 MHz. At a time value of 3 ms (3,019 ms) indicated by the reference numerals 601, M1, the duty cycle of the clock signal 200.3 is changed. By changing the duty cycle, the peak value 206.3 of the peak value curve 206.2 of the triangular wave signal 205.1 increases by increasing the average value of the monitoring signal 205.1 to approximately 3.5 V. As shown in the detailed view 602a of FIGS. 7A and 7B after the change of the duty cycle at the time 601, the peak value 206.3 is outside the acceptable frequency range from the lower threshold value 206.4 of 825 kHz to the upper threshold value 206.5 of 1.2 MHz. As a result of this increase in the peak curve 206.2, the deprurler output signal 208.2 increases after a time indicated by the reference numeral 601 when the duty cycle changes. After the detection time 208.3 at the time 602, M0 of 3.0232 ms, the deprurler output signal 208.2 reaches the maximum permissible threshold value 209 set with the output comparator 209.1. The minimum detection time is about 21 μs and is dependent only on the deprurler filter. In particular, the time limit 208.3 can be set by dimensioning the capacitor 300.24 of the debouncing unit and / or by dimensioning the reference voltage 300.27 of the output comparator 209. The first clock error signal clockNOK 407.1, 207.2 changes from low to high at time 601, M1and indicates a temporary degradation of the internal clock signal when the peak curve 206.2 exceeds one of the threshold values 206.4, 206.5. The second clock fault signal "clock fault" 407.2 changes from low to high at time 602, M0 3.0232 ms and indicates that there is unacceptable degradation of the internal clock signal, which renders the internal clock signal unusable. As shown in detail view 602a (FIG. 7B), peak signal 206.2 is outside the allowable range between 206.4 and 206.5. In the above-described configuration of a pure analog circuit 100.1, the circuit 100.1 is configured to detect a duty cycle and / or a frequency cycle.In an example of the present disclosure, detector 301 includes a deprurizer that increases a deprurizer output signal over time while peak comparator 207 outputs out-of-range signal 207.2. The debouncing output signal is then compared to a predefined threshold to determine that a faulted situation exists. In another example, the detector 301 includes an error signal generator 209 or an output comparator 209 configured to compare the deprurler output signal 208.2 with a predefined threshold 209.1 and generate the second error signal clock fault 407.2 after the first error signal is present for longer than a predefined time period. If the second error signal 407.2, e.g. clock fault, is set to a high value, the internal clock signal is marked as faulty.An injection driver 100 for a vehicle, and in particular a clock arbitration module 250 of the injection driver 100, includes an external clock signal terminal 203 configured to provide an external clock signal 103.2, and an internal clock signal terminal 204 configured to provide an internal clock signal 200.3, and a clock signal monitoring device 100.1 according to this disclosure, wherein the signal converter 205 of the clock signal monitoring device 100.1 is connected to the internal clock signal terminal 204 via the connection 100.3.FIG. 8 is a flowchart of a method for monitoring a clock signal according to an exemplary embodiment of the present disclosure. The method begins in the idle state S 801. In state S802, a clock signal 200.3 is received in a signal converter 205, the signal 200.3 having a duty cycle and a frequency. In state S 803, the signal converter 205 converts the clock signal into a monitoring signal having a peak value related to the duty cycle and the frequency of the clock signal. In state S804, the monitoring signal is received in a detector 301 connected to the signal converter 205, and a second error signal clock fault 407.2 is generated by the detector when the peak value 206.3, 206.2 of the monitoring signal 205.1 is outside a predefined range 206.4, 206.5. The method ends in the final state S 805.By using analog circuitry and / or analog components, reliability in detecting the clock error is high. When the described method is implemented as program code and runs on a processor, a high level of recognition reliability can also be achieved by using components and / or devices, e.g. a processor, which use a dedicated clock source, i.e. a clock source which supplies essentially only the component executing the program code with a clock signal. In this way, the processor may be independent of external influences, such as an effect of an external clock source. In other words, if this method is implemented by software or as a computer program on a processor, an additional monitoring circuit may be provided to ensure that the clock signal of the processor is monitored by an additional method. The additional method may ensure that the processor operates as desired. The additional monitoring circuit may include an additional clock monitoring device. In one example, the additional monitoring circuit is also implemented as a purely analog circuit.The method may further include transmitting a second clock signal from a second clock source when an error signal is generated. The second clock signal may be an internal clock signal. Under normal conditions, the external clock is used. The internal clock source may be selected when a fault condition of the external clock is detected. However, if both clock sources are in an error state, the method prevents switching to the internal clock to avoid confusion in the status of the clock source. In this case, if both the clock sources are in error, the error signal is generated, but the clock monitoring apparatus continues to use the external clock and prevents switching to the internal clock source. A faulty internal clock source can be indicated by setting the second error signal 407.2, e.g., "clock fault", to a high value. In one example, an error in the external clock may be detected by comparing the external clock to the internal clock. Since the internal clock can be used as a reference, the internal clock is to be protected from high priority failures. For example, the internal clock can be encapsulated or sealed against external influences. Alternatively or additionally, substantially purely analog components may be used for the internal clock and for a corresponding clock signal monitoring device. Preventing incorrect states of the internal clock can make it possible to use the internal clock as a reference. In the event of damage to the internal clock and thus a fault in the signal generated by the internal clock, checking of the external clock can be difficult and an assessment of the state of the external clock must be prevented. In such a case of an erroneous internal clock, it may be substantially impossible to understand whether the external clock is also erroneous. In one example, a display device may be present to indicate that an assessment of the error state of a clock signal is not possible when such ambiguous state is detected.

Claims

A clock signal monitoring device (100.1), comprising: a signal converter (205) configured to receive a clock signal (200.3) having a duty cycle and a frequency and to convert the clock signal into a monitoring signal (205.1) having a peak value (206.2) with respect to the duty cycle and to the frequency of the clock signal (200.3), wherein the monitoring signal (205.1) comprises a triangular waveform signal (205.1); and a detector (301) in connection with the signal converter (205), which is configured to receive the monitoring signal (205.1), wherein the detector (301) comprises an active peak detector (206), which is configured to detect the peak value (206.2) of the triangular waveform signal (205.1) and to provide a peak value signal, which continuously provides a signal of the level of the detected peak value (206.2), wherein the detector (301) is further configured to generate an error signal (407.1) if the peak value (206.2) of the monitoring signal (205.1) is outside a predefined range.The clock signal monitoring apparatus (100.1) according to claim 1, wherein the signal converter (205) comprises a low pass filter (205).The clock signal monitoring apparatus (100.1) according to claim 2, wherein the low pass filter (205) has a cut-off frequency such that an average value of the monitoring signal (205.1) is proportional to the duty cycle of the clock signal (200.3) and a ripple of the monitoring signal (205.1) is proportional to the frequency of the clock signal (200.3).The clock signal monitoring device (100.1) according to claim 2, wherein the low pass filter (205) has a cut-off frequency corresponding to one tenth of the frequency of the clock signal (200.3).The clock signal monitoring device (100.1) according to claim 1, wherein the detector (301) includes a comparator (207) configured to compare the peak value (206.2) of the monitoring signal (205.1) with at least one of a first threshold value of the predefined range and a second threshold value of the predefined range that is greater than the first threshold value; and output an out-of-range signal for the time in which the peak value is below the first threshold value or the peak value is above the second threshold value.The clock signal monitoring apparatus (100.1) according to claim 5, wherein the detector (301) further comprises a deprurizer (208) configured to receive the out-of-range signal and to increase a deprurizer output signal over time by outputting the out-of-range signal by the comparator (207).The clock signal monitoring device (100.1) according to claim 6, wherein the detector (301) further comprises an error signal generator (209) configured to compare the output signal of the deprurler (208) with a predefined threshold value and to generate the error signal if the output signal of the deprurler (208) is greater than the predefined threshold value.The clock signal monitoring apparatus (100.1) according to claim 1, wherein the signal converter (205) and the detector (301) comprise analog components.An injection driver (100) comprising: a clock arbitration module (250) having a clock signal monitoring device (100.1) according to claim 1; an external clock signal terminal (203) configured to provide an external clock signal (102.1); and an internal clock signal terminal (204) configured to provide an internal clock signal (200.3); wherein the clock arbitration module (250) further comprises an input terminal (102) for receiving the external clock signal (102.1) and is configured to modify the external clock signal (102.1) and provide the external clock signal (102.1) at the external clock signal output (203); wherein the signal converter (205) of the clock signal monitoring device (100.1) is connected to the internal clock signal terminal (204) to monitor the internal clock signal, wherein the output terminals (203, 204) form a common output terminal (103) providing an actual control signal (103.1) to an injector (101), wherein the common output terminal (103) comprises a switch (103.6) configured to select the clock signal used to generate the control signal (103.1) for the injector (101), wherein the switch (103.6) is controlled by the clock signal monitoring device (100.1), to select a correct clock signal and to condition the control signal (103.1) according to the selected clock signal, and wherein the switch (103.6) is controlled by the error signal (407.1).

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