A / D converter, integrated semiconductor circuit and rotation detector

Abstract

A / D converter, including: a comparator (101) having a total input voltage range from a ground voltage to a power supply voltage; an analog-to-digital converter (ADC) control circuit (102); a correction circuit (104); and a storage device (103), wherein the comparator (101) comprises: a first comparator (201) having an NMOS differential input stage, which is suitable for performing a normal comparison operation within a range from a first input voltage higher than the ground voltage and lower than the power supply voltage to the power supply voltage; a second comparator (202) having a PMOS differential input stage, which is suitable for performing a normal comparison operation within a range from the ground voltage to a second input voltage which is higher than the first input voltage and lower than the power supply voltage; and an output selection circuit (203) configured to select an output of the first comparator (201) or an output of the second comparator (202) depending on a magnitude of an input voltage, and wherein the correction circuit (104) is designed to: pre-detecting, via the ADC control circuit (102), a first A / D converted value in a case of using the first comparator (201) and a second A / D converted value in a case of using the second comparator (202) with respect to a same input voltage in a common range belonging to a range of an input voltage of the first input voltage or more and the second input voltage or less, wherein both the first comparator (201) and the second comparator (202) are suitable for performing the normal comparison operation; Calculating a correction value based on the first A / D converted value and the second A / D converted value obtained with respect to the same input voltage; pre-storing the correction value in the storage device (103); Performing correction processing based on the correction value to prevent an offset error between the first A / D converted value and the second A / D converted value; and Outputting an A / D converted value after preventing the offset error in the entire input voltage range.

Description

Background of the invention 1. Field of the invention

[0001] The present invention relates to an analog-to-digital (A / D) converter (ADC) with a rail-to-rail input voltage range, a semiconductor integrated circuit, and a rotation detector. 2. Description of the state of the art

[0002] In an A / D converter suitable for converting a rail-to-rail input voltage ranging from a ground voltage to a power supply voltage into a digital value, it is necessary to use a comparator having a rail-to-rail input voltage range as a comparator for comparing an input voltage and a reference voltage.

[0003] As a comparator with the rail-to-rail input voltage range, a prior art device has been proposed having a circuit configuration formed by a combination of a comparator with an NMOS differential input stage and a comparator with a PMOS differential input stage (see, for example, JP 2010-517336 A).

[0004] The comparator with the NMOS differential input stage cannot perform normal comparison operation when the input voltage is approximately 1 V or less. Meanwhile, the operator with the PMOS differential input stage cannot perform normal comparison operation when the input voltage is equal to ((power supply voltage) - (approximately 1 V)) or more.

[0005] In view of this, the prior art device has a configuration for switching an output of the comparator to be used with respect to an input voltage between the comparator with the NMOS differential input stage and the comparator with the PMOS differential input stage. With such a configuration, the prior art device achieves normal comparison operation in the rail-to-rail input voltage range from the ground voltage to the power supply voltage.

[0006] By using such a state-of-the-art comparator for the A / D converter, the A / D converter can be designed with the rail-to-rail input voltage range.

[0007] Meanwhile, as a method for correcting a conversion error of the A / D converter, for example, a method is known which includes arranging a plurality of A / D converters (see, for example, JP H10-028053 A).

[0008] However, the state of the art has the following problems.

[0009] The comparator typically has an offset voltage due to manufacturing variations. Therefore, there is a deviation associated with an offset voltage relative to a reference voltage.

[0010] There is a difference in the offset voltage caused by manufacturing variations between the comparator with the NMOS differential input stage and the comparator with the PMOS differential input stage, as described above. Therefore, even if the same voltage is input, there may be a difference in the comparison result between the comparators. For example, the comparison result of the comparator with the NMOS differential input stage is high, while the comparison result of the comparator with the PMOS differential input stage is low.

[0011] If the comparison results between the comparator with the NMOS differential input stage and the comparator with the PMOS differential input stage are different, an offset error will occur in the A / D conversion result when changing the comparator being used. Hereinafter, the input voltage is represented by Vin, the offset voltage of the comparator with the NMOS differential input stage is represented by Voffset(n), and the offset voltage of the comparator with the PMOS differential input stage is represented by Voffset(p).

[0012] In this case, the A / D conversion result in the case of using the comparator with the NMOS differential input stage is a result of performing the A / D conversion at a voltage of Vin + Voffset(n). Meanwhile, the A / D conversion result in the case of using the comparator with the PMOS differential input stage is a result of performing the A / D conversion at a voltage of Vin + Voffset(p).

[0013] Therefore, this offset error may cause a problem such as the occurrence of a missing code or a loss of monotonicity.

[0014] Furthermore, as described in JP H10-028053 A, there is a known method that involves arranging a plurality of A / D converters to correct a conversion error. However, with this configuration of JP H10-028053 A, the circuit size is undesirably large.

[0015] D / A converters are also discussed in JP 2016 - 082 312 A, JP 2001 - 007 703 A and JP S59 - 191 931A. Summary of the invention

[0016] The present invention has been made to solve the problems described above, and it is an object of the present invention to provide an A / D converter, a semiconductor integrated circuit, and a rotation detector which prevent an increase in a circuit size and eliminate an offset error caused by switching between two comparators operated with a rail-to-rail input voltage range to be free from a missing code and a monotonicity loss.

[0017] This object is achieved according to the invention by the subject matter of the independent claims. The dependent claims relate to further embodiments, and this description explains how the invention can be carried out.

[0018] An A / D converter according to an embodiment of the present invention comprises: a comparator having a total input voltage range from a ground voltage to a power supply voltage; an analog-to-digital converter (ADC) control circuit; a correction circuit; and a memory device. The comparator comprises: a first comparator having an NMOS differential input stage capable of performing a normal comparison operation within a range from a first input voltage higher than the ground voltage and lower than the power supply voltage to a power supply voltage; a second comparator having a PMOS differential input stage capable of performing a normal comparison operation within a range from the ground voltage to a second input voltage higher than the first input voltage and lower than the power supply voltage;and an output selection circuit configured to select an output of the first comparator and an output of the second comparator depending on a magnitude of an input voltage. The correction circuit is configured to predetect, via the ADC control circuit, a first A / D converted value in the case of using the first comparator and a second A / D converted value in the case of using the second comparator with respect to a same input voltage in a common range belonging to an input voltage range of the first input voltage or more and the second input voltage or less, wherein both the first comparator and the second comparator are suitable for performing the normal comparison operation;Calculating a correction value based on the first A / D converted value and the second A / D converted value obtained with respect to the same input voltage; storing the correction value in advance in the storage device; performing correction processing based on the correction value to prevent an offset error between the first A / D converted value and the second A / D converted value; and outputting an A / D converted value after preventing the offset error in the entire input voltage range.

[0019] The present invention has a configuration in which, in the region where the two comparators that are selectively switched can be normally operated together, each comparator outputs with respect to the same input voltage, undergoes A / D conversion, and an offset error is corrected based on the respective A / D converted values. As a result, it is possible to obtain the A / D converter, the semiconductor integrated circuit, and the rotation detector that prevent the increase in circuit size and eliminate the offset error caused by switching between the two comparators that operate with the rail-to-rail input voltage range, so as to be free from the missing code and the monotonicity loss. Short description of the characters Fig. 1 is a configuration diagram of an A / D converter according to a first embodiment of the present invention. Fig. 2 is a diagram showing an input voltage range of a comparator. Fig. 3 is an explanatory diagram for illustrating a correction value detecting method in a correction circuit in the first embodiment of the present invention. Fig. 4 is an exemplary graph showing a correction method for an A / D converted value executed by the correction circuit in the first embodiment of the present invention. Fig. 5 is an explanatory diagram for illustrating a correction value detecting method in a correction circuit in a second embodiment of the present invention. Fig. 6 is an exemplary graph showing a correction method for an A / D conversion result performed by the correction circuit in the second embodiment of the present invention. Fig. 7 is a configuration diagram of an A / D converter according to a third embodiment of the present invention. Fig. 8 is an exemplary graph showing a correction method for A / D converted values ​​performed by a correction circuit in the third embodiment of the present invention. Fig. 9 is an exemplary graph showing a correction method for an A / D converted value executed by a correction circuit in a fourth embodiment of the present invention. Fig. 10 is a configuration diagram of an A / D converter according to a fifth embodiment of the present invention. Fig. 11 is a configuration diagram showing a semiconductor integrated circuit according to a seventh embodiment of the present invention. Fig. 12 is a configuration view showing a vehicle in an eighth embodiment of the present invention. Description of the embodiments

[0020] With reference to the accompanying figures, an A / D converter, a semiconductor integrated circuit and a rotation detector according to exemplary embodiments of the present invention will be described below. First embodiment

[0021] Fig. 1 is a configuration diagram of an A / D converter according to a first embodiment of the present invention. The A / D converter in Fig. 1 comprises: a comparator 101 having a rail-to-rail input voltage range; a storage device 103 configured to store a correction value; and a correction circuit 104 configured to perform correction processing using an A / D converted value 12 output from an ADC control circuit 102 and a correction value stored in the storage device 103.

[0022] The comparator 101 includes a comparator 201 with an NMOS differential input stage, a comparator 202 with a PMOS differential input stage, and an output selection circuit 203 for selecting an output of the comparator 201 or an output of the comparator 202.

[0023] Fig. 2 is a diagram showing an input voltage range of the comparator 101. In the comparator 101, which has the Fig. 1 and has the rail-to-rail input voltage range, there is a range in which the comparator 201 with the NMOS differential input stage and the comparator 202 with the PMOS differential input stage are normally operable together, as shown in Fig. 2 shown.

[0024] Accordingly, the A / D converter according to the first embodiment compares an operation result of the comparator 201 and an operation result of the comparator 202 with respect to the same input voltage in this range, the two comparators being normally operable together, to correct an offset error between the two comparators.

[0025] Specifically, in the A / D converter according to the first embodiment, both the comparator 201 with the NMOS differential input stage and the comparator 202 with the PMOS differential input stage perform A / D conversion at the same input voltage in the range where the two comparators are normally operable together. The A / D converter according to the first embodiment performs correction processing at the time of actually performing A / D conversion based on a difference between the two previously acquired A / D converted values, as thus described. As a result, the A / D converter capable of correcting an offset error between A / D converted values ​​of the two comparators can be achieved.

[0026] The Fig. The correction circuit 104 shown in Figure 1 performs such a correction of the offset error. A correction value detection method performed by the correction circuit 104 will be described with reference to Fig. 3 described. Fig. 3 is an explanatory diagram for illustrating the correction value detecting method in the correction circuit 104 in the first embodiment of the present invention.

[0027] The correction circuit 104 outputs a control signal 14 for controlling the output selection circuit 203 and performs switching control as to whether the output of the comparator 201 with the NMOS differential input stage or the output of the comparator 202 with the PMOS differential input stage is to be taken as an output signal 11 from the output selection circuit 203 with reference to the same input voltage.

[0028] The output selection circuit 203, which has received the control signal 14, outputs, along with the output signal 11, a control signal 13 for identifying whether the output of the comparator 201 or the output of the comparator 202 is used as the output signal 11. The ADC control circuit 102 outputs a result of performing the A / D conversion on the output signal 11 as the A / D converted value 12.

[0029] As a result, the correction circuit 104 can detect the control signal 13 from the output selection circuit 203 and the A / D converted value 12 from the ADC control circuit 102, as shown in Fig. 3, based on the control signal 14 output by the correction circuit 104 itself. That is, the correction circuit 104 can detect an A / D converted value 1 obtained by converting the same input voltage using the output of the comparator 201 with the NMOS differential input stage, and an A / D converted value 2 obtained by converting the same input voltage using the output of the comparator 202 with the PMOS differential input stage.

[0030] Further, the correction circuit 104 calculates a difference between the A / D conversion results and stores the calculated value as a correction value in the storage device 103. The correction value used when the correction processing is executed at the time of using the output of the comparator 202 with the PMOS differential input stage as the output signal 11 from the output selection circuit 203 is a value obtained by subtracting the A / D converted value 2 from the A / D converted value 1.

[0031] Meanwhile, the correction value used when the correction processing is carried out at the time of using the output of the comparator 201 with the NMOS differential input stage as the output signal 11 from the output selection circuit 203 is a value obtained by subtracting the A / D converted value 1 from the A / D converted value 2.

[0032] Fig. 4 is an exemplary graph showing a correction method for an A / D converted value executed by the correction circuit 104 in the first embodiment of the present invention. Fig. 4 is a graph for showing an example of the correction processing when a correction is performed to compensate for an offset error at the time of using the output of the comparator 201 with the NMOS differential input stage as the output signal 11 from the output selection circuit 203.

[0033] The correction circuit 104 determines whether the output of the comparator 201 with the NMOS differential input stage or the output of the comparator 202 with the PMOS differential input stage was used by the ADC control circuit 102 to perform the A / D conversion, based on the control signal 13 output from the output selection circuit 203.

[0034] When the correction circuit 104 receives as the A / D converted value 12 a result of the A / D conversion performed by using the output of the comparator 201 having the NMOS differential input stage, the correction circuit 104 adds the correction value stored in the storage device 103 to the A / D converted value 12 to perform correction so that an offset error is compensated.

[0035] As in Fig. As shown in Figure 4, when such correction processing is performed, an offset error is not generated in an A / D converted value after correction by the correction circuit 104, even if the output signal 11 from the output selection circuit 203 is switched between the output of the comparator 201 with the NMOS differential input stage and the output of the comparator 202 with the PMOS differential input stage. Consequently, an A / D converter free from missing code and monotonicity loss can be obtained.

[0036] Furthermore, the only circuits to be added to correct the A / D converted value are the correction circuit 104 and the memory device 103. Therefore, with the A / D converter according to the first embodiment, the correction processing for compensating for an offset error can be achieved at low cost by adding circuits with a small size. Second embodiment

[0037] Fig. Fig. 5 is an exemplary diagram illustrating a correction value detection method in a correction circuit 104 in a second embodiment of the present invention. A feature of the second embodiment is to execute the correction processing by a Fig. 5 illustrated correction procedure in the A / D converter from Fig. 1.

[0038] At the time of execution of the Fig. 5, in the same manner as in the first embodiment described above, the correction circuit 104 can receive the control signal 13 from the output selection circuit 203 and the A / D converted value 12 from the ADC control circuit 102, as shown in Fig. 5, based on the control signal output by the correction circuit 104 itself. That is, the correction circuit 104 can detect an A / D converted value 1 obtained by converting the same input voltage using the output of the comparator 201 with the NMOS differential input stage, and an A / D converted value 2 obtained by converting the same input voltage using the output of the comparator 202 with the PMOS differential input stage.

[0039] The correction circuit 104 in the second embodiment pre-holds an ideal A / D converted value with respect to the same input voltage. Therefore, the correction circuit 104 calculates, as a correction value 1, a difference between the ideal value and the A / D converted value 1, which is converted using the output of the comparator 201 with the NMOS differential input stage, and calculates, as a correction value 2, a difference between the ideal value and the A / D converted value 2, which is converted using the output of the comparator 202 with the PMOS differential input stage. The correction circuit 104 can cause the storage device 103 to pre-store the calculated correction values.

[0040] Fig. 6 is an exemplary graph showing a correction method for an A / D conversion result performed by the correction circuit 104 in the second embodiment of the present invention. The correction circuit 104 determines whether the A / D converted value 12 is an A / D converted value obtained by using the output of the comparator 201 with the NMOS differential input stage or an A / D converted value obtained by using the output of the comparator 202 with the PMOS differential input stage, based on the control signal 13 output from the output selection circuit 203.

[0041] When the correction circuit 104 determines that the A / D converted value 12 obtained by using the output of the comparator 201 with the NMOS differential input stage is detected, the correction circuit 104 adds the correction value 1 stored in the storage device 103 to the A / D converted value 12 to perform correction so that an offset error is compensated.

[0042] Meanwhile, when the correction circuit 104 determines that the A / D converted value 12 obtained by using the output of the comparator 202 having the PMOS differential input stage is obtained, the correction circuit 104 adds the correction value 2 stored in the storage device 103 to the A / D converted value 12 to perform correction so that an offset error is compensated.

[0043] As described above, when a correction is performed on the ideal A / D converted value with respect to the same input voltage, an offset error is not generated in an A / D converted value after the correction by the correction circuit 104, even if the output signal 11 from the output selection circuit 203 is switched between the output of the comparator 201 with the NMOS differential input stage and the output of the comparator 202 with the PMOS differential input stage, as shown in Fig. 6. Further, by the correction processing in the second embodiment, an absolute value of the A / D converted value can be corrected as shown in Fig. 6 shown. Third embodiment

[0044] Fig. Fig. 7 is a configuration diagram of an A / D converter according to a third embodiment of the present invention. The A / D converter in Fig. 7 includes: a comparator 111 with a rail-to-rail input voltage range; an ADC control circuit 112; and a correction circuit 114.

[0045] Comparator 111 includes a comparator 201 with an NMOS differential input stage and a comparator 202 with a PMOS differential input stage. Furthermore, an output 21 of comparator 201 with the NMOS differential input stage and an output 22 of comparator 202 with the PMOS differential input stage are both outputs to ADC control circuit 112.

[0046] The ADC control circuit 112 outputs to the correction circuit 114 both an A / D converted value 23 obtained based on the output 21 of the comparator 201 with the NMOS differential input stage and an A / D converted value 24 obtained based on the output 22 of the comparator 202 with the PMOS differential input stage.

[0047] The correction circuit 114 performs an averaging process by weighting the A / D converted value 23 obtained based on the output 21 of the comparator 201 with the NMOS differential input stage and the A / D converted value 24 obtained based on the output 22 of the comparator 202 with the PMOS differential input stage within a predetermined voltage range, thereby performing a correction to compensate for an offset error.

[0048] Fig. Fig. 8 is an exemplary graph showing a correction method for A / D converted values ​​performed by the correction circuit 114 in the third embodiment of the present invention. As shown in Fig. 8, the correction circuit 114 holds a switching upper limit value 31 and a switching lower limit value 32 as values ​​that determine a voltage range at which a weighted notification is executed.

[0049] When both the A / D converted value 23 and the A / D converted value 24 are within the range between the switching upper limit value 31 and the switching lower limit value 32, the correction circuit 114 performs weighted averaging processing on the A / D converted value 23 and the A / D converted value 24 and outputs the obtained value as an A / D converted value 25.

[0050] Compared to the Fig. 1 shown A / D converter requires the Fig. 7 does not include the output selection circuit 203 and the memory device 103. Accordingly, in the third embodiment, it is possible to achieve an A / D converter with a small circuit size compared to those of the first and second embodiments described above. Fourth embodiment

[0051] Fig. Fig. 9 is an exemplary graph showing a correction process for A / D converted values ​​performed by a correction circuit 114 according to a fourth embodiment of the present invention. A feature of the fourth embodiment lies in performing the correction processing by the Fig. 9 shown correction methods in the A / D converter from Fig. 7.

[0052] In the Fig. 9, the correction circuit 114 performs simple averaging on the A / D converted value 23 and the A / D converted value 24 within a prescribed voltage range, thereby performing a correction so that an offset error is compensated.

[0053] As in Fig. As shown in Figure 9, the correction circuit 114 maintains a switching upper limit value 33 and a switching lower limit value 34 as values ​​that determine a voltage range at which simple averaging is performed. When both the A / D converted value 23 and the A / D converted value 24 are within the range between the switching upper limit value 33 and the switching lower limit value 34, the correction circuit 114 performs simple averaging processing on the A / D converted value 23 and the A / D converted value 24, and the obtained value is output as the A / D converted value 25.

[0054] In the fourth embodiment, the correction processing on the A / D converted values ​​is simple compared to that in the above-described third embodiment. Thus, according to the fourth embodiment, it is possible to achieve an A / D converter with an even smaller circuit size compared to the circuit size in the above-described third embodiment. However, in the correction processing according to the fourth embodiment, the offset error is reduced but not completely eliminated. Thus, when an original offset is small, the missing code and the monotonicity loss can be improved by using the correction processing according to the fourth embodiment. Fifth embodiment

[0055] Fig. 10 is a configuration diagram of an A / D converter according to a fifth embodiment of the present invention. The A / D converter in Fig. 10 includes: a comparator 115 comprising a plurality of comparators 201 with NMOS differential input stages and a plurality of comparators 202 with PMOS differential input stages, and having a rail-to-rail input voltage range; a majority circuit 116 configured to select an output of the plurality of comparators; the output selection circuit 203; and the ADC control circuit 112.

[0056] The majority circuit 116 includes an NMOS-side majority circuit 223 and a PMOS-side majority circuit 224. Outputs 21 of the plurality of comparators 201 having the NMOS differential input stages are connected to the NMOS-side majority circuit 223, and the NMOS-side majority circuit 223 generates a majority decision result 26 from the outputs 21 of the plurality of comparators 201.

[0057] Similarly, outputs 22 of the plurality of comparators 22 having the PMOS differential input stages are connected to the PMOS-side majority circuit 224, and the PMOS-side majority circuit 224 generates a result 27 for performing a majority decision from the outputs 22 of the plurality of comparators 202.

[0058] According to the input voltage, the output selection circuit 203 outputs to the ADC control circuit 112 either the result 26 of the NMOS-side majority circuit 222 or the result 27 of the PMOS-side majority circuit 223.

[0059] The A / D converter according to the fifth embodiment can average offsets of the plurality of outputs 21 and offsets of the plurality of outputs 22 by performing a majority decision from the plurality of outputs 21 of the plurality of comparators 201 and a majority decision from the plurality of outputs 22 of the plurality of comparators 202.

[0060] That is, the A / D converter according to the fifth embodiment uses the majority circuit to perform averaging processing on an offset, instead of using the correction circuit to perform correction processing, thereby enabling a reduction in an offset caused by variations in comparator manufacturing. As a result, the A / D converter according to the fifth embodiment can also correct an offset error of an A / D converted value without a correction circuit. Sixth embodiment

[0061] A feature of a sixth embodiment of the present invention is that in each of the plurality of comparators 201 having the NMOS differential input stages and each of the plurality of comparators 202 having the PMOS differential input stages described in the fifth embodiment, transistors included in the comparators have different sizes.

[0062] An offset voltage caused by variations in comparator manufacturing also depends on the sizes of the transistors included in the comparators. Thus, when comparators with different transistor sizes are mounted, offset deviations of the comparators can be reduced. The A / D converter according to the sixth embodiment can average offsets with higher accuracy compared to the fifth embodiment described above by performing majority decision from the outputs of a plurality of comparators with reduced offset deviations. Seventh embodiment

[0063] Fig. 11 is a configuration diagram illustrating a semiconductor integrated circuit 300 according to a seventh embodiment of the present invention. Fig. The semiconductor integrated circuit 300 shown in Figure 11 comprises: an amplifier circuit 301 configured to amplify a sensor signal to be input from a sensor 310; an A / D converter 302 configured to convert an output of the amplifier circuit 301 into a digital signal; and a digital circuit 303 configured to perform signal processing on an output of the A / D converter 302.

[0064] A sensor signal is typically a weak signal. Therefore, it is necessary to amplify the amplitude of the sensor signal by the amplifier circuit 301. The A / D converter according to the present invention can be used as an A / D converter for converting the output of the amplifier circuit 301 into the digital signal. By adopting the A / D converter according to the present invention, the A / D conversion can be performed even when the sensor signal is amplified to a power supply voltage by the amplifier circuit 301. It is therefore possible to use an amplifier circuit with a higher gain. Accordingly, the semiconductor integrated circuit 300 according to the seventh embodiment can process the sensor signal with higher accuracy.

[0065] In this way, it is possible to apply one of the A / D converters according to the above-described first to sixth embodiments as an A / D converter included in a known semiconductor integrated circuit. Eighth embodiment

[0066] In an eighth embodiment of the present invention, a description will be given of a case where the semiconductor integrated circuit 300 according to the above-described seventh embodiment is applied as a semiconductor integrated circuit included in a known rotation detector.

[0067] Fig. 12 is a configuration view showing a vehicle 401 in the eighth embodiment of the present invention. Fig.The vehicle 401 shown in Figure 12 includes wheels 402 and a rotation detector 403, which includes the integrated semiconductor circuit 300. The rotation detector 403 is configured to detect a rotation axis of a rotating machine mounted in the vehicle 401, for example, a rotation axis of the wheels 402.

[0068] A plurality of vehicle detectors, such as the rotation detector 403, are required to operate with high accuracy and low power consumption based on a demand for low fuel consumption. Such a requirement is met by using the semiconductor integrated circuit 300, which is described in the seventh embodiment described above as the semiconductor integrated circuit included in the plurality of detectors.

[0069] In this way, it is possible to apply the semiconductor integrated circuit 300 including one of the A / D converters according to the above-described first to sixth embodiments as a semiconductor integrated circuit included in a known rotation detector.

[0070] As described above, the eighth embodiment is configured to apply the semiconductor integrated circuit comprising any one of the A / D converters according to the above-described first to sixth embodiments as the semiconductor integrated circuit included in the known rotation detector. Therefore, it is possible to achieve a rotation detector including an A / D converter, free from the occurrence of missing code and monotonicity loss, with the rail-to-rail input voltage range.

[0071] The first to eighth embodiments have been described as examples of the present invention, however, the present invention is not limited to the configurations of the first to eighth embodiments. Within the scope of the invention, the configurations of the first to eighth embodiments can be appropriately combined, or can be partially modified or partially omitted without departing from the spirit of the invention.

Claims

[1] A / D converter, including: a comparator (101) with a total input voltage range from an earth voltage to a power supply voltage; an analog-to-digital converter (ADC) control circuit (102); a correction circuit (104); and a storage device (103), where the comparator (101) comprises: a first comparator (201) with an NMOS differential input stage, which is suitable for performing normal comparator operation within a range from a first input voltage which is higher than the ground voltage and lower than the power supply voltage, up to the power supply voltage; a second comparator (202) with a PMOS differential input stage, which is suitable for performing normal comparator operation within a range from the ground voltage to a second input voltage which is higher than the first input voltage and lower than the power supply voltage; and an output selection circuit (203) configured to select an output of the first comparator (201) or an output of the second comparator (202) depending on the magnitude of an input voltage, and wherein the correction circuit (104) is configured to: Preliminary acquisition, via the ADC control circuit (102), of a first A / D converted value in the case of using the first comparator (201) and a second A / D converted value in the case of using the second comparator (202) with reference to the same input voltage in a common range, which belongs to a range of an input voltage of the first input voltage or more and the second input voltage or less, wherein both the first comparator (201) and the second comparator (202) are suitable for performing normal comparison operation; Calculating a correction value based on the first A / D converted value and the second A / D converted value, which are obtained with reference to the same input voltage; Pre-storage of the correction value in the storage device (103); Performing a correction process based on the correction value to prevent an offset error between the first A / D converted value and the second A / D converted value; and Outputting an A / D converted value after preventing offset error across the entire input voltage range. [2] A / D converter according to claim 1, wherein the correction circuit (104) is configured to: Calculate the difference between the first A / D converted value and the second A / D converted value as the correction value; and Performing a correction process, either an addition or a subtraction of the correction value, thereby preventing the offset error between the first A / D converted value and the second A / D converted value. [3] A / D converter according to claim 1, wherein the correction circuit (104) is configured to: Hold in advance as an ideal value, an ideal A / D converted value with reference to the same input voltage; Preliminary calculation of a difference between the first A / D converted value and the ideal value as a first correction value; Preliminarily calculate a difference between the second A / D converted value and the ideal value as a second correction value; and Perform a correction process to add the first correction value to the first A / D converted value and a correction process to add the second correction value to the second A / D converted value to prevent the offset error between the first A / D converted value and the second A / D converted value. [4] A / D converter, including: a comparator (111) with an entire input voltage range from an earth voltage to a power supply voltage; an ADC control circuit (112); and a correction circuit (114), where the comparator (111) comprises: at least a first comparator (201) with an NMOS differential input stage, which is suitable for performing normal comparator operation within a range from a first input voltage which is higher than the ground voltage and lower than the power supply voltage, up to the power supply voltage; and at least a second comparator (202) with a PMOS differential input stage suitable for performing normal comparator operation within a range from the ground voltage to a second input voltage which is higher than the first input voltage and lower than the power supply voltage, wherein the ADC control circuit (112) is configured to generate a first A / D converted value based on an output of the at least one first comparator (201) and a second A / D converted value based on an output of the at least one second comparator (202), and wherein the correction circuit (114) is configured to: Performing an averaging correction process by using the first A / D converted value and the second A / D converted value in a common range belonging to a range of an input voltage, the first input voltage or more and the second input voltage or less, wherein both the at least one first comparator (201) and the at least one second comparator (202) are suitable for performing normal comparison operation in order to prevent an offset error between the first A / D converted value and the second A / D converted value; and Outputting an A / D converted value after preventing offset error across the entire input voltage range. [5] A / D converter according to claim 4, wherein the correction circuit (114) has an upper limit and a lower limit of an A / D converted value for determining a range, wherein the averaging correction processing is performed, wherein the upper limit and the lower limit are preset, and wherein the correction circuit (114) is configured to perform weighted averaging on the first A / D converted value and the second A / D converted value as the averaging correction processing with reference to an input voltage for which both the first A / D converted value and the second A / D converted value are within a range of the lower limit or more and the upper limit or less, in order to prevent the offset error between the first A / D converted value and the second A / D converted value. [6] A / D converter according to claim 4, wherein the correction circuit (114) has an upper limit and a lower limit of an A / D converted value for determining a range, wherein the averaging correction processing is performed, wherein the upper limit and the lower limit are preset, and wherein the correction circuit (114) is configured to perform a simple averaging process on the first A / D converted value and the second A / D converted value, as the averaging correction process with reference to an input voltage for which both the first A / D converted value and the second A / D converted value are within a range of the lower limit or more and the upper limit or less, in order to prevent the offset error between the first A / D converted value and the second A / D converted value. [7] A / D converter, including: a plurality of comparators (115), each of which has an entire input voltage range from an earth voltage to a power supply voltage; a majority circuit (116) configured to select one output from the outputs of the plurality of converters; an output selection circuit (203); and an ADC control circuit (112), the multitude of comparators includes (115): a plurality of first comparators (201) with NMOS differential input stages, which are suitable for performing normal comparator operation within a range from a first input voltage which is higher than the ground voltage and lower than the power supply voltage, up to the power supply voltage; and a plurality of second comparators (202) with PMOS differential input stages suitable for performing normal comparator operation within a range from the ground voltage to a second input voltage which is higher than the first input voltage and lower than the power supply voltage, the majority circuit (116) comprises: a first majority circuit (223) configured to output a majority result formed from corresponding outputs of the plurality of first comparators (201); and a second majority circuit (224) which is configured to output a majority result formed from corresponding outputs of the plurality of second comparators (202), wherein the output selection circuit (203) is configured to select and output an output of the first majority circuit or an output of the second majority circuit, wherein the ADC control circuit (112) is configured to output an A / D converted value with reference to the output selected in the output selection circuit, and This prevents an offset error of the A / D converted value caused by using any of the many comparators. [8] A / D converter according to claim 7, wherein the plurality of first comparators (201) includes comparators with different transistor sizes, and wherein the plurality of second comparators (202) includes comparators with different transistor sizes. [9] Integrated semiconductor circuit (300) comprising the A / D converter according to any one of claims 1 to 8. [10] Rotation detector (403) comprising the integrated semiconductor circuit according to claim 9.

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