DOWN-UP SWITCHING CONVERTER

Abstract

Step-down / step-up switching converter (200, 300, 400, 900) with one input for receiving an input voltage and one output for providing an output voltage, which has the following features: a first set of switches comprising a first circuit breaker (205) and a first ground switch (210); a second set of switches comprising a second circuit breaker (206) and a second ground switch (211); a control device configured to send control signals to the first set of switches and the second set of switches, and configured such that: in a downward mode, the first set of switches operates to provide downward control, while the second circuit breaker (206) is held in a closed state; In an upward mode, the second set of switches operates to provide upward control, while the first circuit breaker (205) is held in a closed state; and the control device is configured to operate the step-down / step-up converter (200, 300, 400, 900) selectively in the step-down mode or in the step-up mode based on the length of a time period during which both the first circuit breaker (205) and the second circuit breaker (206) are in a closed state; wherein In operation in the step-down mode, the control device is configured to switch the step-down / step-up converter (200, 300, 400, 900) to the step-up mode when the time period during which both the first circuit breaker (205) and the second circuit breaker (206) are in a closed state exceeds a first threshold; and In operation in the upward mode, the control device is designed to switch the buck-boost switching converter (200, 300, 400, 900) into the downward mode when the time period during which both the first circuit breaker (205) and the second circuit breaker (206) are in a closed state exceeds a second threshold.

Description

Technical area

[0001] The present disclosure relates to an apparatus and method for regulating an output of a four-switch non-inverting buck-boost switching converter. background

[0002] Four-switch non-inverting buck-boost switching converters can switch between different operating modes depending on the relationship between an input voltage and an output voltage of the switching converter. Fig. Figure 1 is a schematic diagram of a non-inverting buck-boost switching converter 10 with four switches. An input voltage VIN is received at an input terminal, and an output voltage VOUT is provided at an output terminal. An inductor 12 has a first terminal coupled to a first set of switches 14 at a first node LXU and a second terminal coupled to a second set of switches 16 at a second node LXO. An error amplifier 18 is used to generate a control signal based on the output voltage VOUT and a reference voltage VREF. The control signal is provided to a controller 19, and the controller 19 provides the control signal for regulating the power switches 14, 16.The first set of power switches includes a high-side switch that couples the inductor 12 to the input voltage VIN when in a closed state, and the second set of power switches includes a high-side switch that couples the inductor 12 to the output voltage VOUT when in a closed state.

[0003] When the input voltage VIN is significantly greater than the output voltage VOUT, the switching converter can operate in a buck mode by operating only the first set of switches 14, which can be referred to as the buck-mode power switches. In the buck mode, the high-side switch of the second set of switches 16 is in the closed state and couples the inductor 12 to the output voltage VOUT. When the input voltage VIN is significantly less than the output voltage VOUT, the switching converter can operate in a boost mode by operating only the second set of switches 16, which can be referred to as the boost-mode power switches. In the boost mode, the high-side switch of the first set of power switches 14 is in the closed state and couples the inductor 12 to the input voltage VIN.When the input voltage VIN is approximately equal to the output voltage VOUT, the switching converter operates in a buck-boost mode, which can be referred to as a buck-boost window, in which all power switches 14, 16 are used to regulate the output voltage VOUT.

[0004] There are several existing methods for controlling the four-switch non-inverting buck-boost switching converter and selecting the appropriate operation mode. Fig. Figure 2 is a schematic diagram of a first implementation of a four-switch non-inverting buck-boost switching converter 20. The output voltage VOUT and the reference voltage VREF are received at an error amplifier, and an error amplifier voltage VEA is provided to a first comparator 22 and a second comparator 24. The first comparator 22 receives a first voltage ramp, and the second comparator 24 receives a second voltage ramp. An output of the first comparator 22 is provided to a reset terminal of a first SR latch 26. An output of the second comparator 24 is provided to a reset terminal of a second SR latch 28. The first SR latch 26 receives a first clock signal, and the second SR latch 28 receives a second clock signal.The first SR latch 26 provides the control signal MagBOOST for operation of the second set of switches 16 and the second SR latch 28 provides the control signal MagBUCK for operation of the first set of switches 14.

[0005] The method for controlling the four-switch, non-inverting buck-boost converter 20 is typically referred to as "voltage mode." This involves comparing voltages, i.e., the voltage ramps, with the error amplifier voltage VEA.

[0006] Fig. Figure 3 is a diagram illustrating the operation of switching converter 20, with the input voltage VIN decreasing from left to right. The decreasing input voltage VIN results in an increasing error amplifier voltage VEA. Fig. 3 shows a second clock signal 30, a first clock signal 31, a first voltage ramp 32, a second voltage ramp 33, an error amplifier voltage VEA 34, a control signal MagBUCK 35, a control signal MagBOOST 36, and a current 37 through the inductor 12.

[0007] For a small output voltage VOUT compared to the input voltage VIN, the error amplifier voltage VEA is small, so that the error amplifier voltage VEA intersects the second voltage ramp 33 such that the control signal MagBUCK 35 provides a suitable signal for controlling the first set of switches, whereby the switching converter 20 is operated as a buck converter.

[0008] For a large output voltage VOUT compared to the input voltage VIN, the error amplifier voltage VEA is large, so that the error amplifier voltage VEA intersects the first voltage ramp 32 such that the control signal MagBOOST 36 provides a suitable signal to control the second set of switches, thereby operating the switching converter 20 as a boost converter.

[0009] For an output voltage VOUT approximately equal to the input voltage VIN, the error amplifier voltage VEA intersects the first voltage ramp 32 and the second voltage ramp 33, so that the control signal MagBUCK 35 and the control signal MagBOOST 36 provide appropriate signals for controlling the first set of power switches and the second set of switches, thereby operating the switching converter 20 as a buck-boost converter.

[0010] A schematic representation of a second implementation of a non-inverting buck-boost switching converter with four switches is shown in Fig. 4. The non-inverting buck-boost switching converter with four switches from Fig. 4 is a current-mode buck-boost converter 40. The operation of the current-mode buck-boost converter 40 has three phases: a first phase related to boost-mode operation and a charging current; a second phase related to buck-mode operation and a discharging current; and a bypass phase in which a first high-side switch 42 and a second high-side switch 44 are closed. The buck-boost converter 40 has a current sensing function.

[0011] The current-mode buck-boost converter 40 includes a current-sensing resistor 46 having a resistance of 10 mΩ. The current-sensing resistor 46 converts a current flowing through an inductor 48 into a sensed voltage. The sensed voltage is received by a first comparator 41 and a second comparator 43. The sensed voltage is compared by the first comparator 41 with a first constraint -k.VEA, and the sensed voltage is compared by the second comparator 43 with a second constraint +k.VEA. An output of the first comparator 41 is used to generate the control signal MagBUCK, and an output of the second comparator 43 is used to generate the control signal MagBOOST. The method for controlling the current-mode buck-boost switching converter 40 is typically referred to as "current mode."

[0012] The Fig. 1, Fig. 2 and Fig. The switching converters shown in Figure 4 require a constant clock. In addition, the Fig. 1, Fig. 2 and Fig. The switching converters shown in Figure 4 rely on process- and time-dependent comparators and voltage ramps, which can lead to voltage fluctuations where the error amplifier voltage VEA overlaps with the voltage ramps 32 and 33. This can change the values ​​of the input voltage VIN and the output voltage VOUT over which the switching converters operate in the buck-boost mode. Trimming steps or additional correction loops are required to resolve this issue.

[0013] The switching converters of the Fig. 1, Fig. 2 and Fig. 4 also require the design of additional analog circuit blocks, including oscillators, current sensors, comparators, and compensation. Therefore, it is desirable to reduce the complexity of the above switching converters.

[0014] DE 10 2015 223 768 A1 describes the operation of a buck-boost converter. The buck-boost converter comprises an inductor, a buck converter with a first switch and a second switch coupled to an input terminal of the inductor, and a boost converter with a third switch and a fourth switch coupled to an output terminal of the inductor. The buck converter controls the first switch and the second switch according to a buck duty cycle, while the boost converter controls the third switch and the fourth switch according to a boost duty cycle. The converter further comprises a voltage feedback loop for regulating an output voltage of the converter. In the voltage feedback loop, an error voltage determination unit determines an error voltage indicating a difference between the output voltage and a target voltage.

[0015] US 2016 / 0 164 411 A1 describes switched boost / buck regulators and a control of such switched boost / buck regulators using a current mode control scheme.

[0016] US 2016 / 0 087 531 A1 describes the measurement of an inductor current in a buck / boost power converter with four switches.

[0017] US 2011 / 0 227 550 A1 describes a buck / boost converter. The buck / boost converter generates an output voltage in response to an input voltage and at least one switching control signal in a buck operating mode, a boost operating mode, and a buck / boost operating mode.

[0018] US 2010 / 0 231 189 A1 describes a buck / boost converter, a control circuit and a method for reducing switching losses and for smoothly transitioning between the operating modes of the buck / boost converter. Summary

[0019] It is an object of the present disclosure to reduce the complexity of four-switch non-inverting buck-boost switching converters.

[0020] According to a first aspect of the disclosure, a buck-boost switching converter is provided having an input for receiving an input voltage and an output for providing an output voltage, comprising a first set of switches comprising a first power switch and a first ground switch, a second set of switches comprising a second power switch and a second ground switch, a control device configured to send control signals to the first set of switches and the second set of switches, and configured such that in a buck mode, the first set of switches operates to provide buck regulation during which the second power switch is maintained in a closed state, in a boost mode, the second set of switches operates to provide boost regulation during which the first power switch is maintained in a closed state,and the control device is configured to selectively operate the buck-boost switching converter in the buck mode or in the boost mode based on a length of a time period during which both the first power switch and the second power switch are in a same state.,

[0021] Optionally, when operating in the buck mode, the control device is configured to switch the buck-boost switching converter into the boost mode when the time period during which both the first power switch and the second power switch are in a same state exceeds a first threshold, and, when operating in the boost mode, the control device is configured to switch the buck-boost switching converter into the buck mode when the time period during which both the first power switch and the second power switch are in a same state exceeds a second threshold.

[0022] Optionally, the first and second thresholds are the same.

[0023] Optionally, the buck-boost switching converter comprises an energy storage element, wherein the output is coupled to the energy storage element when the second power switch is in a closed state, and the input is coupled to the energy storage element when the first power switch is in a closed state.

[0024] Optionally, the same state is a closed state.

[0025] Optionally, the energy storage element is an inductor.

[0026] Optionally, the buck-boost switching converter has an input of a first integration circuit coupled to a first terminal of the inductor, wherein the first integration circuit is configured to receive a first voltage signal from the first terminal of the inductor and to provide an integrated first voltage signal at an output of the first integration circuit, an input of a second integration circuit coupled to a second terminal of the inductor, wherein the second integration circuit is configured to receive a second voltage signal from the second terminal of the inductor and to provide an integrated second voltage signal at an output of the second integration circuit, and a comparator having a first input coupled to the output of the first integration circuit and a second input coupled to the output of the second integration circuit,wherein the comparator is configured to output the control signals at an output of the comparator and to provide the control signals to the control device.,

[0027] Optionally, the buck-boost switching converter is a hysteresis buck-boost switching converter, with the comparator exhibiting hysteresis.

[0028] Optionally, the buck-boost switching converter has a feedback voltage coupled to the first input of the comparator and a reference voltage coupled to the second input of the comparator.

[0029] Optionally, the control device comprises a demultiplexer configured to receive the control signals from the output of the comparator and to provide the control signals to the first set of switches in the step-down mode and to provide the control signals to the second set of switches in the step-up mode.

[0030] Optionally, the demultiplexer provides the control signals to the first set of switches when operating in a first demultiplexer state and provides the control signals to the second set of switches when operating in a second demultiplexer state, wherein the demultiplexer is configured to selectively operate in the first demultiplexer state or the second demultiplexer state based on the length of the time period during which both the first power switch and the second power switch are in the same state.

[0031] Optionally, the first integration circuit comprises a first resistor and a first capacitor and the second integration circuit comprises a second resistor and a second capacitor.

[0032] Optionally, the output of the first integration circuit is coupled to the first input of the comparator via a first transmission element and the output of the second integration circuit is coupled to the second input of the comparator via a second transmission element.

[0033] Optionally, the first and second transmission elements are capacitors.

[0034] Optionally, the control device comprises a decision circuit, wherein, when operating in the buck mode, the decision circuit is configured to provide a first mode signal to switch the buck-boost switching converter into the boost mode when the time period during which both the first power switch and the second power switch are in a same state exceeds the first threshold, and, when operating in the boost mode, the decision circuit is configured to provide a second mode signal to switch the buck-boost switching converter into the buck mode when the time period during which both the first power switch and the second power switch are in a same state exceeds the second threshold.

[0035] Optionally, the decision circuit comprises an AND gate having a first input coupled to the first power switch and a second input coupled to the second power switch, a timing circuit having an input coupled to an output of the AND gate, and a mode circuit having an input coupled to an output of the timing circuit;wherein the AND gate outputs a "high" signal when the first power switch and the second power switch are in the same state, wherein, when operating in the buck mode, when a "high" signal is received at the input of the timing circuit for the first threshold, the timing circuit outputs a signal to the mode circuit, and in response, the mode circuit provides the first mode signal to switch the operating mode of the switching converter from the buck mode to the boost mode, and, when operating in the boost mode, when a "high" signal is received at the input of the timing circuit for the second threshold, the timing circuit outputs a signal to the mode circuit, and in response, the mode circuit provides the second mode signal to switch the operating mode of the switching converter from the boost mode to the buck mode;

[0036] According to a second aspect of the disclosure, a method is provided for controlling the operation of a buck-boost switching converter of the type having a first set of switches comprising a first power switch and a first ground switch, and a second set of switches comprising a second power switch and a second ground switch, the method comprising sending control signals to the first set of switches and the second set of switches, in a buck mode, operating the first set of switches to provide buck regulation while maintaining the second power switch in a closed state, in a boost mode, operating the second set of switches to provide boost regulation while maintaining the first power switch in a closed state,and selectively operating the switching converter in the buck mode or the boost mode based on a length of a time period during which both the first power switch and the second power switch are in a same state.,

[0037] Optionally, the method comprises, when operating in the buck mode, switching the buck-boost switching converter to the boost mode when the time period during which both the first power switch and the second power switch are in a same state exceeds a first threshold, and, when operating in the boost mode, switching the buck-boost switching converter to the buck mode when the time period during which both the first power switch and the second power switch are in a same state exceeds a second threshold.

[0038] Optionally, the first and second thresholds are the same.

[0039] Optionally, the buck-boost switching converter comprises an energy storage element, wherein an output of the buck-boost switching converter is coupled to the energy storage element when the second power switch is in a closed state, and an input is coupled to the energy storage element when the first power switch is in a closed state.

[0040] Optionally, the same state is a closed state.

[0041] Optionally, the energy storage element is an inductor.

[0042] Optionally, the method comprises integrating a first voltage signal from a first terminal of the inductor and providing an integrated first voltage signal to a first input of a comparator, integrating a second voltage signal from a second terminal of the inductor and providing an integrated second voltage to a second input of the comparator, and outputting the control signals from an output of the comparator.

[0043] Optionally, the comparator shows a hysteresis.

[0044] Optionally, the method comprises providing a feedback voltage to the first input of the comparator and providing a reference voltage to the second input of the comparator.

[0045] According to a third aspect of the disclosure, a buck-boost switching converter is provided having an input for receiving an input voltage and an output for providing an output voltage, comprising a first set of switches comprising a first power switch and a first ground switch, a second set of switches comprising a second power switch and a second ground switch, a comparator, an energy storage element, wherein the output is coupled to the energy storage element when the second power switch is in a closed state, and the input is coupled to the energy storage element when the first power switch is in a closed state, an input of a first integration circuit is coupled to a first terminal of the energy storage element,wherein the first integration circuit is configured to receive a first voltage signal from the first terminal of the energy storage element and to provide an integrated first voltage signal to an output of the first integration circuit, and an input of a second integration circuit is coupled to a second terminal of the energy storage element, wherein the second integration circuit is configured to receive a second voltage signal from the second terminal of the energy storage element and to provide an integrated second voltage signal to an output of the second integration circuit, wherein the comparator has a first input coupled to the output of the first integration circuit, a second input coupled to the output of the second integration circuit,the comparator is configured to output the control signals at an output of the comparator and to provide control signals to the first set of switches and the second set of switches and is configured such that, in a step-down mode, the first set of switches operates to provide step-down control while the second power switch is maintained in a closed state, and, in a step-up mode, the second set of switches operates to provide step-up control while the first power switch is maintained in a closed state.

[0046] Optionally, the energy storage element is an inductor.

[0047] According to a fourth aspect of the disclosure, a method is provided for controlling the operation of a buck-boost switching converter of the type having a first set of switches comprising a first power switch and a first ground switch, and a second set of switches comprising a second power switch and a second ground switch, the method comprising integrating a first voltage signal from a first terminal of an energy storage element, the input being coupled to the energy storage element when the first power switch is in a closed state, providing an integrated first voltage signal to a first input of a comparator, integrating a second voltage signal from a second terminal of the energy storage element, the output being coupled to the energy storage element when the second power switch is in a closed state,Providing an integrated second voltage signal to a second input of the comparator, and receiving control signals at the first set of switches and the second set of switches from an output of the comparator, wherein, in a buck mode, the first set of switches operates to provide buck regulation while the second power switch is maintained in a closed state, and, in a boost mode, the second set of switches operates to provide boost regulation while the first power switch is maintained in a closed state.

[0048] Optionally, the energy storage element is an inductor. Short description of the drawings

[0049] The invention will now be described in more detail by way of example and with reference to the accompanying drawings, in which: Fig. 1 is a schematic diagram of a prior art four-switch non-inverting buck-boost converter; Fig. 2 is a schematic diagram of a first prior art implementation of a four-switch non-inverting buck-boost switching converter; Fig. 3 is a diagram showing the operation of the four-switch non-inverting buck-boost switching converter as shown in Fig. 2, and according to the prior art; Fig. 4 is a schematic diagram of a second prior art implementation of a four-switch non-inverting buck-boost converter; Fig. 5 is a schematic diagram of a prior art peak current buck regulator; Fig. Figure 6 is a diagram showing the operation of two examples using the peak current buck regulator of Fig. 5 implement according to the state of the art; Fig. 7 is a schematic diagram of another prior art peak current buck regulator; Fig. 8 is a schematic diagram of a buck regulator using a sensorless method according to the prior art; Fig. 9 is a schematic diagram of a prior art hysteresis buck converter; Fig. 10 is a schematic diagram of a buck-boost switching converter according to a first embodiment of this disclosure; Fig. 11 is a schematic diagram of a buck-boost switching converter according to a second embodiment of this disclosure; Fig. 12 is a schematic diagram of a buck-boost switching converter according to a third embodiment of this disclosure; Fig. 13 is a diagram illustrating the operation of the buck-boost switching converter of Fig. 11 shows; Fig. 14 is a first diagram of simulation results relating to an operation of the buck-boost switching converter of Fig. 11 refer; Fig. 15 is a second diagram of simulation results relating to the operation of the buck-boost switching converter of Fig. 11 refer; Fig. 16A and Fig. 16B shows a third diagram of simulation results relating to the operation of the buck-boost switching converter of Fig. 11; and Fig. 17 is a schematic diagram of a buck-boost switching converter according to a fourth embodiment of this disclosure. Description

[0050] To reduce complexity of four-switch non-inverting buck-boost switching converters, it is desirable to implement aspects of a current-mode switching converter, such as the current-mode switching converter 40 of Fig. 4, but to avoid implementing a current detection function.

[0051] Fig. Figure 5 shows a schematic diagram of a prior art peak current buck regulator 50. An error amplifier 52 outputs an error voltage Verr to a comparator 54. The error voltage Verr is used to adjust a peak value of an inductor current IL, where the inductor current IL is the current through an inductor 56. The inductor current IL is sensed using a current sensor 58 and provided to the comparator 54 as a current sense voltage VCUR. The comparator 54 outputs a stop signal to an SR latch 59, which also receives a clock signal clk. The SR latch 59 outputs a control signal mag to regulate the set of switches 51.

[0052] Fig. Figure 6 is a diagram showing the operation of a first example and a second example, both examples implementing the same circuit, ie, the peak current buck regulator 50 of Fig. 5.

[0053] The second example includes a discrepancy in sensing the current sense voltage VCUR compared to the first example. There may be a discrepancy between examples if, for example, each example is implemented on a different die.

[0054] In Fig. 6, a clock signal 60 is shown, a voltage at a switching node LX at a first terminal of the inductor 56 for the first example 62, a voltage at the switching node LX at a first terminal of the inductor 56 for the second example 64, an error voltage Verr(S1) of the first example and an error voltage Verr(S2) of the second example, a current sense voltage VCUR(S1) of the first example and a current sense voltage VCUR(S2) of the second example.

[0055] Initially, the discrepancy in sensing the current sense voltage VCUR results in a shorter duty cycle, as shown by the voltage at switching node LX for the second example 64. However, the control loop eventually adjusts and increases the error voltage Verr(S2) until the duty cycle matches for both examples. Therefore, a DC content of the current in the inductor 56 is not required for the peak current buck regulator 50.

[0056] Fig. Figure 7 shows a peak current step-down regulator 70 corresponding to the peak current step-down regulator 50 of Fig. 5, but further including a high-pass filter 72 to remove the DC content of the sensed current from the inductor 56.

[0057] The current sense voltage VCUR of the peak current buck regulator 50, as shown in Fig. 5 can be represented by the following equation: VC​UR=RIV⋅∫0tV(LX)−V(OUT)L+DCconstant where RIV is a conversion ratio between the inductor current IL and the current sense voltage VCUR, t is time, V(LX) is the voltage at the switching node LX, V(OUT) is the output voltage VOUT, L is the inductance of the inductor 56, and DC_constant is the DC content of the sensed current in the inductor 56, represented as a voltage.

[0058] The AC (alternating current) characteristic of the inductor is the integrated voltage across the inductor 56. As in Fig. As shown in Figure 6, it is possible to remove the DC component and thus DC_constant from the above equation. Therefore, instead of using a current sensing method, it is possible to implement the AC content of the above equation directly, as shown by the scheme in Fig. 8 shown. Fig. Figure 8 shows a step-down regulator 80 corresponding to the switching converter of Fig. 7, but using a sensorless method. The buck regulator 80 includes an integration circuit 82 that allows the integrated voltage across the inductor to be used to regulate the output voltage VOUT of the buck regulator 80.

[0059] The sensorless method can be implemented in a buck converter, a boost converter, a hysteresis buck converter, or a hysteresis boost converter.

[0060] Fig. 9 shows a diagram of a hysteresis buck converter 100 using a sensorless method for regulating an output voltage Vout according to the prior art. The buck converter 100 includes a first set of switches including a first power switch 105, which may be referred to as a high-side power switch, and a first ground switch 110, which may be referred to as a low-side power switch, connected to a first terminal of an inductor 115 via a switch node LX1. A gate driver 130 has a first output coupled to the first power switch 105 and a second output coupled to the first ground switch 110. The first power switch 105 receives an input voltage Vin, and the first ground switch 110 is coupled to ground.A second terminal of inductor 115 is coupled to a first terminal of an output capacitor 120, which has a second terminal coupled to ground. The first terminal of output capacitor 120 is at the output voltage Vout.

[0061] The second terminal of inductor 115 is coupled to a first terminal of a first potential divider resistor RH. A second terminal of the first potential divider resistor RH is coupled to a first terminal of a second potential divider resistor RL at a feedback node Nfb, which is at a feedback voltage Vfb. A second terminal of the second potential divider resistor RL is coupled to ground.

[0062] It is known that conventional hysteretic buck converters can be unstable due to the small size of the output capacitor 120 and / or due to high loads. The output capacitor 120 has an equivalent series resistance (ESR) that adds a zero in the left half-plane by stacking a first ESR voltage at the output, where the first ESR voltage is equal to a current through the inductor 115 multiplied by the ESR. A standard technique for compensating the ESR of the capacitor 120 and maintaining stability is to mimic the ESR by adding, at the feedback node Nfb, a second ESR voltage that has the same information as the ESR and the current through the inductor 115.

[0063] An integration circuit 125 includes a first resistor R1 having a first terminal coupled to the switching node LX1 and a second terminal coupled to a first terminal of a first capacitor C1 having a second terminal coupled to ground. A first terminal of a first transfer capacitor CT1 is coupled to a node between the first resistor R1 and the first capacitor C1.

[0064] The feedback node Nfb and a second terminal of the first transfer capacitor CT1 are coupled to a first input of a comparator 135. A second input of the comparator 135 receives a reference voltage Vref. An output of the comparator 135 is coupled to an input of the gate driver 130.

[0065] In operation, the gate driver 130 drives the switching of the first power switch 105 and the first ground switch 110 based on control signals generated by the comparator 135. The output of the comparator 135 depends on the comparison of the feedback voltage Vfb and the reference voltage Vref.

[0066] In operation, integration circuit 125 integrates a voltage signal at switching node LX1, which corresponds to the AC characteristics of the inductor. The feedback voltage Vfb includes contributions from the output voltage Vout and the integrated voltage signal from switching node LX1.

[0067] The integrated voltage signal from switching node LX1 is stacked onto the feedback voltage Vfb using the transfer capacitor CT1. This allows a ripple to be stacked onto the feedback voltage Vfb as if an ESR were present on the output capacitor 120. This ensures that the hysteresis buck converter 100 is stable.

[0068] "Stacked" means that two voltages are added together. In the example above, the integrated voltage signal from switching node LX1 is stacked onto the feedback voltage Vfb. This means that the integrated voltage signal from switching node LX1 is added to the feedback voltage Vfb that would be present if there were no coupling between the first transfer capacitor CT1 and the feedback node Nfb.

[0069] Fig. Figure 10 is a schematic diagram of a first embodiment of a buck-boost switching converter 200 according to the disclosure. The buck-boost switching converter 200 receives an input voltage Vin and uses a sensorless method to provide a regulated output voltage Vout. The buck-boost switching converter 200 is configured to operate in a buck mode or a boost mode.

[0070] The buck-boost switching converter 200 includes an inductor 215, which is a type of energy storage element having a first terminal coupled to a first set of switches and a second terminal coupled to a second set of switches.

[0071] In the present embodiment, the buck mode corresponds to operation of the buck-boost switching converter 200 as a buck converter, and the boost mode corresponds to operation of the buck-boost switching converter 200 as a boost converter. The buck-boost switching converter 200 operates in the buck mode, corresponding to operation as a buck converter, when the output voltage Vout is significantly lower than the input voltage Vin; operates in the boost mode, corresponding to operation as a boost converter, when the output voltage Vout is significantly greater than the input voltage Vin; and switches between operation as a buck converter and operation as a boost converter when the output voltage Vout and the input voltage Vin are approximately equal.

[0072] In the present example, the first set of switches includes a first power switch 205, which may be referred to as a first high-side power switch, and a first ground switch 210, which may be referred to as a first low-side power switch, coupled to a first terminal of the inductor 215 via a first switching node LX1. The first switching node LX1 is at a first switching node voltage VLX1. A first gate driver 230 has a first output coupled to the first power switch 205 and a second output coupled to the first ground switch 210. The first power switch 205 receives the input voltage Vin, and the first ground switch 210 is coupled to ground. The first power switch 205 is coupled to a first terminal of an input capacitor 221, the second terminal of which is coupled to ground.

[0073] The buck-boost switching converter 200 further includes a second set of switches including a second power switch 206, which may be referred to as a second high-side power switch, and a second ground switch 211, which may be referred to as a second low-side switch, coupled to a second terminal of the inductor 215 via a second switching node LX2. The second switching node LX2 is at the second switching node voltage VLX2. A second gate driver 231 has a first output coupled to the second power switch 206 and a second output coupled to the second ground switch 211. The second power switch 206 has an output at the output voltage Vout, and the second ground switch 211 is coupled to ground. The second power switch 206 is coupled to a first terminal of an output capacitor 220, the second terminal of which is coupled to ground.

[0074] The output is coupled to the inductor 215 when the second power switch 206 is in a closed state, and the input is coupled to the inductor 215 when the first power switch 205 is in a closed state.

[0075] In the buck mode, the first set of switches operates to provide buck regulation while the second power switch 206 is maintained in the closed state. In the boost mode, the second set of switches operates to provide boost regulation while the first power switch 205 is maintained in the closed state.

[0076] The first switching node LX1 is coupled to an input of a first integration circuit 225. The input of the first integration circuit 225 receives the first switching node voltage VLX1, which may be referred to as a first voltage signal. The first integration circuit 225 outputs an integrated first switching node voltage ∫VLX1, which may be referred to as an integrated first voltage signal, at an output. The output of the first integration circuit 225 is coupled to a first input of a comparator 235 via a first transfer element 227.

[0077] The first integration circuit 225 includes a first resistor R1 having a first terminal coupled to the first switching node LX1 and a second terminal coupled to a first terminal of a first capacitor C1 having a second terminal coupled to ground. The first transfer element 227 includes a first transfer capacitor CT1 having a capacitance less than C1. The capacitance of the first transfer capacitor CT1 may, for example, be 10% of the capacitance of the first capacitor C1. A first terminal of the first transfer capacitor CT1 is coupled to a node between the first resistor R1 and the first capacitor C1. A second terminal of the first transfer capacitor CT1 is coupled to the first input of the comparator 235.

[0078] The second switching node LX2 is coupled to an input of a second integration circuit 226. The input of the second integration circuit 226 receives the second switching node voltage VLX2, which may be referred to as a second voltage signal. The second integration circuit 226 outputs an integrated second switching node voltage ∫VLX2, which may be referred to as an integrated second voltage signal, at an output. The output of the second integration circuit 226 is coupled to a second input of the comparator 235 via a second transfer element 228.

[0079] The second integration circuit 226 includes a second resistor R2 having a first terminal coupled to the second switching node LX2 and a second terminal coupled to a first terminal of a second capacitor C2 having a second terminal coupled to ground. The second transfer element 228 includes a second transfer capacitor CT2 having a capacitance less than C2. The capacitance of the second transfer capacitor CT2 may, for example, be 10% of the capacitance of the second capacitor C1. A first terminal of the second transfer capacitor CT2 is coupled to a node between the second resistor R2 and the second capacitor C2. A second terminal of the second transfer capacitor CT2 is coupled to the second input of the comparator 235.

[0080] In operation, comparator 235 outputs control signals at an output to control the first set of switches in the buck mode and the second set of switches in the boost mode. Comparator 235 may exhibit hysteresis, which would result in buck-boost switching converter 200 being a hysteresis buck-boost switching converter.

[0081] The first terminal of the output capacitor 220 is coupled to an input of a feedback voltage circuit 229 having an output at a feedback voltage Vfb. The feedback voltage circuit 229 may be implemented as a potential divider comprising a first potential divider resistor RH1 having a first terminal coupled to the first terminal of the output capacitor 220 and a second terminal coupled to a first terminal of a second potential divider resistor RL1 having a second terminal coupled to ground. The first potential divider resistor RH1 and the second potential divider resistor RL1 are coupled to a feedback node Nfb at the feedback voltage Vfb. The feedback node Nfb is coupled to the first input of a comparator 235.

[0082] An input of an impedance matching circuit 236 receives an initial reference voltage Vref0. An output of the impedance matching circuit 236 is at a reference voltage Vref.

[0083] The impedance matching circuit 236 includes a first matching resistor RH2 coupled in parallel to a second matching resistor RL2, forming a matching resistor pair. A first resistance value corresponding to a parallel combination of the first matching resistor RH2 and the second matching resistor RL2 is equal to a second resistance value corresponding to a parallel combination of the first potential divider resistor RH1 and the second potential divider resistor RL1. For example, this may correspond to the first matching resistor RH2 and the first potential divider resistor RH1 being equal; and the second matching resistor RL2 and the second potential divider resistor RL1 being equal. A first terminal of the matching resistor pair receives an initial reference voltage Vref0. A second terminal of the matching resistor pair is at Vref and is coupled to the second input of the comparator 235.The impedance matching circuit 236 ensures that the impedance seen by CT1 is the same as the impedance seen by CT2.

[0084] The output of voltage feedback circuit 229 and the second terminal of the first transfer capacitor CT1 are coupled to the first input of a comparator 235. The output of impedance matching circuit 236 and the second terminal of the second transfer capacitor CT2 are coupled to the second input of comparator 235. The feedback voltage Vfb includes contributions from the output voltage Vout and the integrated first switching node voltage ∫VLX1. The reference voltage Vref includes contributions from the initial reference voltage Vref0 and the integrated second switching node voltage ∫VLX2.

[0085] The buck-boost switching converter 200 includes a controller configured to send control signals to the first set of switches and the second set of switches. The controller receives the control signals from the comparator 235. The controller is configured to selectively operate the buck-boost switching converter 200 in the buck mode or the boost mode based on the length of a time period during which both the first power switch 205 and the second power switch 206 are in a same state. In the present example, the same state exists when the power switches 205, 206 are in the closed state.

[0086] When operating in the buck mode, the control device is configured to switch the buck-boost switching converter 200 to the boost mode when the time period during which both switches 205, 206 are in the same state exceeds a first threshold. When operating in the boost mode, the control device is configured to switch the buck-boost switching converter 200 to the buck mode when the time period during which both switches 205, 206 are in the same state exceeds a second threshold. The first and second thresholds may be the same, for example, a time of 300 ns.

[0087] The control device includes a demultiplexer 240. An output of the comparator 235 is coupled to a first input of the demultiplexer 240 such that the first input of the demultiplexer 240 receives the control signals. The demultiplexer 240 has a first demultiplexer state 241, in which the first input of the demultiplexer is coupled to a first output, and a second demultiplexer state 242, in which the first input of the demultiplexer 240 is coupled to a second output. The first output of the demultiplexer 240 is coupled to an input of the first gate driver 230, and the second output of the switching circuit is coupled to an input of the second gate driver 231.

[0088] In the present example, buck mode corresponds to operation of the buck-boost converter 200 as a buck converter. In buck mode, the demultiplexer 240 is in the first demultiplexer state 241, and the output of the comparator 235 is coupled to the first gate driver 230 such that the control signals are provided to the first set of switches. The first gate driver 230 drives the switching operation of the first power switch 205 and the first ground switch 210 based on a signal generated by the comparator 235. During buck mode, the second power switch 206 is closed and the second ground switch 211 is open.

[0089] In the present example, boost mode corresponds to operation of buck-boost converter 200 as a boost converter. In boost mode, demultiplexer 240 is in second demultiplexer state 242, and the output of comparator 235 is coupled to second gate driver 231 such that control signals are provided to the second set of switches. Second gate driver 231 drives the switching of second power switch 206 and second ground switch 211 based on a signal generated by comparator 235. During boost mode, first power switch 205 is closed and first ground switch 210 is open.

[0090] The demultiplexer 240 is configured to operate in the first demultiplexer state 241 or the second demultiplexer state 242 based on the length of the time period during which both the first power switch 205 and the second power switch 206 are in the same state, for example, the closed state.

[0091] The output of comparator 235 depends on the comparison of the feedback voltage Vfb and the reference voltage Vref.

[0092] In operation, the first integration circuit 225 integrates the first switching node voltage VLX1 at the first switching node LX1 to provide the integrated first switching node voltage ∫VLX1. The integrated first switching node voltage ∫VLX1 corresponds to the AC characteristics of the inductor 215 when operating in the buck mode. The first transfer element 227 is used to stack the integrated first switching node voltage ∫VLX1 onto the feedback voltage Vfb. Therefore, the feedback voltage Vfb includes a contribution from the output voltage Vout, as set by the feedback voltage circuit 229, and the integrated first switching node voltage ∫VLX1.

[0093] In operation, the second integration circuit 226 integrates the second switching node voltage VLX2 at the second switching node LX2 to provide the integrated second switching node voltage ∫VLX2. The integrated second switching node voltage ∫VLX2 corresponds to the AC characteristics of the inductor 215 when operating in the boost mode. The second transfer element 228 is used to stack the integrated second switching node voltage ∫VLX2 onto the reference voltage Vref. Therefore, the reference voltage Vref includes a contribution from the initial reference voltage Vref0, as set by the impedance matching circuit 236, and the integrated second switching node voltage fVLX2. Since the integrated first switching node voltage ∫VLX1 is a component of the feedback voltage Vfb and the integrated second switching node voltage ∫VLX2 is a component of the reference voltage Vref, a decreasing Vref is equivalent to an increasing Vfb in the operation of the comparator 235.。

[0094] It is not possible to operate the switching converter 200 by stacking the integrated second switching node voltage ∫VLX2 onto the feedback voltage Vfb, because a negative ripple would be stacked onto the feedback voltage Vfb. This would cause energy to build up in the inductor 215 as the inductor current IL increases. The energy is not transferred to the output, resulting in a decreasing output voltage Vout. In response, the comparator 235 would attempt to increase the output voltage Vout, but since the energy would not be transferred to the output, the switching converter 200 would not be able to adjust the output voltage Vout.

[0095] Fig. 11 is a schematic diagram of a second embodiment of a buck-boost switching converter 300 according to the disclosure. The buck-boost switching converter 300 receives an input voltage Vin and uses a sensorless method to provide a regulated output voltage Vout. The buck-boost switching converter 300 is configured to operate in a buck mode or a boost mode. Common features between the buck-boost switching converter 300 and the buck-boost switching converter 200 of Fig. 10 have common reference numerals. The process relating to common features between the first and second embodiments will not be repeated, as reference may be made to the description of the first embodiment to understand the operation of other embodiments.

[0096] In addition to the common features between the buck-boost switching converter 300 and the buck-boost switching converter 200, the controller of the buck-boost switching converter 300 further includes a decision circuit 245.

[0097] When operating in the buck mode, the decision circuit 245 is configured to provide a first mode signal that switches the buck-boost switching converter 300 to the boost mode when the time period during which both the first power switch 205 and the second power switch 206 are in the same state exceeds the first threshold.

[0098] When operating in the boost mode, the decision circuit 245 is configured to provide a second mode signal to switch the buck-boost switching converter 300 to the buck mode when the time period during which both the first power switch 205 and the second power switch 206 are in the same state exceeds the second threshold.

[0099] In this embodiment, the same state is a closed state and the first and second thresholds are equal.

[0100] The decision circuit 245 has a first input coupled to the first switching node LX1 and receives the first switching node voltage VLX1. The decision circuit 245 has a second input coupled to the second switching node LX2 and receives the second switching node voltage VLX2. An output of the decision circuit 245 is coupled to a second input of the demultiplexer 240. In operation, the output of the decision circuit 245 provides a mode signal to control the state of the demultiplexer 240. When the demultiplexer 240 receives the first mode signal from the decision circuit 245, the demultiplexer 240 switches from the first demultiplexer state 241, corresponding to operation of the switching converter 300 in the buck mode, to the second demultiplexer state 242, corresponding to operation of the switching converter 300 in the boost mode.When the demultiplexer 240 receives the second mode signal from the decision circuit 245, the demultiplexer 240 switches from the second demultiplexer state 242, which corresponds to operation of the switching converter 300 in the up-mode, to the first demultiplexer state 241, which corresponds to operation of the switching converter 300 in the down-mode.

[0101] The decision circuit 245 includes an AND gate 305, a timing circuit 310, and a mode circuit 315. The AND gate 305 has a first input coupled to the first switching node LX1 to receive the first switching node voltage VLX1. The AND gate 305 has a second input coupled to the second switching node LX2 to receive the second switching node voltage VLX2. An output of the AND gate 305 is coupled to an input of the timing circuit 310. An output of the timing circuit 310 is coupled to an input of the mode circuit 315. An output of the mode circuit 315 is coupled to the second input of the demultiplexer 240.

[0102] Each of the switching nodes LX1, LX2 can be coupled to the AND gate via a high-state detector, for example a Schmitt trigger.

[0103] In operation, the AND gate 305 outputs a "high" signal to the timing circuit 310 when both inputs of the AND gate 305 receive a "high" signal from the first and second switching node voltages VLX1, VLX2. A "high" signal at a first input of the AND gate 305 may correspond to a logic 1 for a first state in which the first switching node voltage VLX1 exceeds a threshold. This occurs when the first power switch 205 is closed and the first ground switch 210 is open. A "low" signal may correspond to a logic 0 for a second state in which the first switching node voltage VLX1 is below a threshold. This occurs when the first power switch 205 is open and the first ground switch 210 is closed. A "high" signal at a second input of the AND gate 305 may correspond to a logic 1 for a first state in which the second switching node voltage VLX2 exceeds a threshold.This occurs when the second power switch 206 is closed and the second ground switch 211 is open. A "low" signal may correspond to a logic 0 for a second state in which the second switching node voltage VLX2 is below a threshold. This occurs when the second power switch 206 is open and the second ground switch 211 is closed. Consequently, a "high" signal may be received at both inputs of the AND gate 305 when the first power switch 205 and the second power switch 206 are closed and the first ground switch 210 and the second ground switch 211 are open.

[0104] When a "high" signal is received at both inputs of AND gate 305, a "high" signal, for example, a logic 1, is output to timing circuit 310. Timing circuit 310 has a timing function, wherein, when a "high" signal is received at the input and the "high" signal remains unchanged for a period of time, for example, 300 ns, timing circuit 310 outputs a signal to mode circuit 315. In response to the signal, mode circuit 315 switches the operation of buck-boost switching converter 300 from buck mode to boost mode or from boost mode to buck mode. The time period required to switch from the down mode to the up mode may be different from the time period required to switch from the up mode to the down mode. This corresponds to the first threshold and the second threshold, as previously defined.Alternatively, the time period may be the same in both cases. Timing circuit 310 may be implemented using a resistor-capacitor delay circuit.

[0105] Since the duration of the time period in which both switches are closed is the criterion for switching modes, switching between modes is independent of the switching frequency of the control signals used to operate the first set of switches and the second set of switches. It is obvious that the time period can be any time other than 300 ns. Adjusting the time period can be used to adjust the values ​​of the input voltage VIN and the output voltage VOUT over which the switching converter 300 operates in the buck-boost mode.

[0106] In the present embodiment, the mode circuit 315 switches operation of the buck-boost switching converter 300 by outputting a "high" signal or a "low" signal to the demultiplexer 240 in response to the signal received from the timing circuit 310. The "high" signal corresponds to the first mode signal, as described above, and the "low" signal corresponds to the second mode signal, as described above.

[0107] The mode circuit 315 may be a memory element that receives the signal from the timing circuit 310 and, in response to receiving the signal from the timing circuit 310, switches the operating mode of the buck-boost switching converter 300.

[0108] When demultiplexer 240 receives a "high" signal from mode circuit 315, the state of the demultiplexer is switched to the second demultiplexer state 242, which corresponds to operation of the buck-boost converter in the boost mode, as a boost converter. When demultiplexer 240 receives a "low" signal from mode circuit 315, the state of demultiplexer 240 is switched to the first demultiplexer state 241, which corresponds to operation of the buck-boost converter in the buck mode, as a buck converter.

[0109] The signal is used to change the state of the demultiplexer 240 as follows: when the demultiplexer 240 is in the first demultiplexer state 241, it switches to the second demultiplexer state 242, and when the demultiplexer 240 is in the second demultiplexer state 242, it switches to the first demultiplexer state 241. For example, if the first power switch 205 and the second power switch 206 are closed for a time period of 300 ns, the timing circuit 310 sends a signal to the mode circuit 315, which sends a signal to the demultiplexer 240, and the demultiplexer 240 changes its state. Buck-boost mode operation corresponds to the case where switching between the two states occurs after each time period cycle.

[0110] Fig. 12 shows a diagram of a third embodiment of the buck-boost switching converter 400 that uses a sensorless method for regulating an output voltage Vout.

[0111] The buck-boost switching converter 400 is as in Fig. 11, however, in this case, the voltage feedback circuit 229 and the impedance matching circuit 236 are implemented as follows. The voltage feedback circuit 229 includes a feedforward capacitor Cff1 coupled in parallel with the first potential divider resistor RH1. The impedance matching circuit 236 includes a matching capacitor Cff2 coupled to the second terminal of the matching resistor pair, where Cff1 = Cff2. The inclusion of Cff1 and Cff2 improves the transient response of the buck-boost switching converter 400.

[0112] Fig. 13 shows a timing diagram of the buck-boost switching converter 300 as shown in Fig. 11, during operation for various input voltages Vin 400 relative to the output voltage Vout 405. The following profiles are also shown: a state of the first switching node LX1 410, a state of the second switching node LX2 415, and the AC component of the inductor current 420. The state of the first switching node LX1 410 is a "high" signal, for example, a logic 1, when the first power switch 205 is closed and the first ground switch 210 is open. The state of the first switching node LX1 410 is a "low" signal, for example, a logic 0, when the first power switch 205 is open and the first ground switch 210 is closed. The state of the second switching node LX2 415 is a "high" signal when the second power switch 206 is closed and the second ground switch 211 is open.The state of the second switching node LX2 415 is a “low” signal when the second power switch 206 is open and the second ground switch 211 is closed.

[0113] In a section S1, the input voltage Vin 400 is significantly greater than the output voltage Vout 405. The first power switch 205 and the first ground switch 210 undergo a switching operation 410. The second power switch 206 is closed, as shown by the state of the second switching node LX2 415. Under these circumstances, the buck-boost switching converter operates as a buck converter. The AC component of the inductor current 420 is characteristic of a voltage ripple provided by the integrated first switching node voltage ∫VLX1 to the feedback voltage Vfb during buck converter operation. Since the slope of the integrated first switching node voltage ∫VLX1 is sufficiently steep after stacking to the feedback voltage Vfb, it interrupts the reference voltage Vref within a sufficiently short period of time to continue operating as a buck converter.

[0114] The slope of the inductor current 420 is given by the following equation: dIdt=Vin−VoutL where dl is a change in inductor current over a time period dt, Vin is the input voltage Vin, Vout is the output voltage Vout, and L is the inductance of the inductor 215.

[0115] In a section S3, the input voltage Vin 400 is significantly lower than the output voltage Vout 405. The second power switch 206 and the second ground switch 211 undergo a switching operation 415. The first power switch 205 is closed 410. Under these circumstances, the buck-boost switching converter operates as a boost converter. The AC component of the inductor current 420 is characteristic of a voltage ripple provided by the integrated second switching node voltage ∫VLX2 for the reference voltage Vref during boost converter operation. Since the slope of the integrated second switching node voltage ∫VLX2 is sufficiently steep, it interrupts the feedback voltage Vfb within a sufficiently short period of time to remain in boost converter operation.

[0116] In section S2, the input voltage Vin 400 is approximately equal to the output voltage Vout 405. In section S2a, the converter initially operates as a buck converter. The AC component of the inductor current 420 is characteristic of a voltage ripple provided by the integrated first switching node voltage ∫VLX1 for the feedback voltage Vfb during buck converter operation. Because the slope of the integrated first switching node voltage ∫VLX1 is not sufficiently steep, it does not interrupt the reference voltage Vref within a sufficiently short time period to remain in buck converter operation. The first power switch 205 and the second power switch 206 are both closed for the time period t, as defined in the discussion of the decision circuit 245.Since the time period t has been exceeded while both power switches 205, 206 are high 410, 415, the decision circuit 245 outputs a signal to the demultiplexer 240 in which the demultiplexer 240 is changed from the first demultiplexer state 241, corresponding to the buck converter operation, to the second demultiplexer state 242, corresponding to the boost converter operation.

[0117] In section S2b, the converter initially operates as a boost converter. The AC component of the inductor current 420 is characteristic of a voltage ripple provided by the integrated second switching node voltage ∫VLX2 for the reference voltage Vref during boost converter operation. Because the slope of the integrated second switching node voltage ∫VLX2 is not sufficiently steep, it does not interrupt the feedback voltage Vfb within a sufficiently short time period to remain in boost converter operation. The first power switch 205 and the second power switch 206 are both closed for the time period t, as defined in the discussion of the decision circuit 245.Since the time period t has been exceeded while both power switches 205, 206 are high 410, 415, the decision circuit 245 outputs a signal to the demultiplexer 240, changing the switching circuit 240 from the second demultiplexer state 242, corresponding to the upconverter operation, to the first demultiplexer state 241, corresponding to the downconverter operation.

[0118] In section S2, the condition required for the decision circuit 245 to change the state of the demultiplexer 240 is always met and therefore the switching converter repeatedly switches between the buck converter operation and the boost converter operation after each cycle of the time period t, thereby operating as a buck-boost converter.

[0119] Fig. 14 is a first diagram of simulation results of the Fig. 11, where the output voltage Vout and the input voltage Vin are approximately equal. Therefore, under these conditions, the buck-boost converter 400 alternates between buck and boost operation. The following features are shown: state of the first switching node LX1 605, state of the second switching node LX2 610, state of a magnetization 615, state of boost mode 620, feedback voltage Vfb 625, reference voltage Vref 630, hysteresis voltage VOUT_COMP 635, and inductor current 640.

[0120] The hysteresis voltage VOUT_COMP 635 is an internal state of comparator 235 that indicates what comparator 235 sees at its first input due to hysteresis. For example, when the magnetization state 615 is high, comparator 235 sees an input at the first input that is less than the feedback voltage Vfb; and when the magnetization state 615 is low, comparator 235 sees the feedback voltage Vfb at the first input.

[0121] The hysteresis voltage VOUT_COMP 635 is effectively a replica of the feedback voltage Vfb 625, but with a hysteresis effect. Consequently, during operation, the comparator 235 compares the hysteresis voltage VOUT_COMP 635 and the reference voltage Vref 630.

[0122] The state of the first switching node LX1 605 is high when the first power switch 205 is closed and the first ground switch 210 is open. The state of the first switching node LX1 605 is low when the first power switch 205 is open and the first ground switch 210 is closed. The state of the second switching node LX2 610 is high when the second power switch 206 is closed and the second ground switch 211 is open. The state of the second switching node LX2 610 is low when the second power switch 206 is open and the second ground switch 211 is closed.

[0123] When the boost mode 620 is high, the buck-boost switching converter operates as a boost converter, and when the boost mode 620 is low, the buck-boost switching converter operates as a buck converter.

[0124] Magnetization 615 is the output of comparator 235 and therefore corresponds to the control signals as previously defined. Magnetization signal 615 is applied to first gate driver 230 when boost mode signal 620 is low, and magnetization signal 615 is applied to second gate driver 231 when boost mode signal 620 is high. The switching action demonstrated by magnetization signal 615 is controlled by feedback voltage Vfb 625 and reference voltage Vref 630, with switching occurring when Vfb 625 and Vref 630 overlap.

[0125] A high magnetization signal 615 applied to the first gate driver 230, corresponding to operation of the buck-boost switching converter as a buck converter, corresponds to a closed first power switch 205 and an open first ground switch 210. The state of the first switching node LX1 605 is high. A low magnetization signal 615 applied to the first gate driver 230 corresponds to the open first power switch 205 and the closed first ground switch 210. The state of the first switching node LX1 605 is low. During operation as a buck converter, the second power switch 206 remains closed and the second ground switch 211 remains open.

[0126] A high magnetization signal 615 applied to the second gate driver 231, corresponding to operation of the buck-boost switching converter as a boost converter, corresponds to the open second power switch 206 and the closed second ground switch 211. The state of the second switching node LX2 610 is low. A low magnetization signal 615 applied to the second gate driver 231 corresponds to the closed second power switch 206 and the open second ground switch 211. The state of the second switching node LX2 610 is high. During operation as a boost converter, the first power switch 205 remains closed and the first ground switch 210 remains open.

[0127] Immediately before time t1, the boost mode signal 620 is high and the buck-boost switching converter operates as a boost converter. The magnetization signal 615 is applied to the second gate driver 231. Since the input voltage Vin and the output voltage Vout are approximately equal, the state of the switching nodes LX1 605 and LX2 610 remains high for the time period of 300 ns, so that the state of the boost mode 620 is switched at time t1, according to the Fig. 11 shown circuit.

[0128] Before switching the boost mode signal, the discharging inductor current 640 has a smooth slope, identified by its small gradient, and the comparator inputs, i.e., the hysteresis voltage VOUT_COMP 635 and the reference voltage Vref 630, do not cross.

[0129] Between time t1 and time t2, the buck-boost switching converter operates as a buck converter, and the magnetization signal 615 is applied to the first gate driver 230. At time t1, the low magnetization signal 615 causes the state of the first switching node LX1 605 to change to low and the inductor 640 to discharge at a steeper slope than the smooth slope immediately before time t1. Consequently, the hysteresis voltage VOUT_COMP 635 and the reference voltage Vref 630 cross, and the magnetization signal 615 is switched, causing LX1 605 to return to a high state. The inductor 640 discharges again with a smooth slope, and the reference voltage Vref 630 and the feedback voltage Vfb 625 do not cross within the time period of 300 ns.

[0130] At time t2, the boost mode 620 switches to a high state, and the buck-boost switching converter operates as a boost converter. The magnetization signal 615 is applied to the second gate driver 231, and the "high" signal causes the second switching node LX2 610 to switch low. The inductor current 640 increases, and the reference voltage Vref 630 and the hysteresis voltage VOUT_COMP 635 cross, resulting in the switching of the magnetization signal 615. The low magnetization signal 615 causes LX2 610 to return to a high state.

[0131] The one for Fig. The cycle described in Figure 14 is repeated and corresponds to operation of the buck-boost switching converter as a buck-boost converter for the case where the output voltage Vout and the input voltage Vin are approximately equal.

[0132] Fig. 15 is a second diagram of simulation results of the Fig. 11, in which the input voltage Vin suddenly transitions from a value below the output voltage Vout to a value greater than the output voltage Vout. The following features are shown: the input voltage Vin 705, the boost mode state 710, the magnetization state 715, the state of the first switching node LX1 720, the state of the second switching node LX2 725, the inductor current 730, the load current 735, and the output voltage Vout 740.

[0133] Before time t3, the input voltage Vin is 2.5 V, which is significantly lower than the output voltage of the buck-boost switching converter. Consequently, the buck-boost switching converter operates as a boost converter. This is also illustrated by the high state of the boost mode signal 710 and the switching of the state of the second switching node LX2 725, while the state of the first switching node LX1 720 remains fixed. From time t3 to time t4, which is 1 µs, the input voltage Vin rises to 5.5 V. During this transition period, the state of the boost mode 710 switches to a low state, and the buck-boost converter operates as a buck converter. This is illustrated by the switching of the state of the first switching node LX1 720, while the state of the second switching node LX2 725 remains fixed.

[0134] The Fig. 16A and Fig. 16B show a third diagram of simulation results of the Fig. 11, in which the input voltage Vin gradually increases from a value below the output voltage Vout to a value greater than the output voltage Vout. The following features are shown: boost mode state 805, first switching node LX1 state 810, second switching node LX2 state 815, inductor current 820, output voltage 825, and input voltage 830.

[0135] At a time period t5, the input voltage Vin is significantly lower than the output voltage Vout, and the buck-boost converter operates in boost mode. The boost mode state 805 is high, the first switching node LX1 810 is high, and the second switching node LX2 815 indicates the switching process associated with the converter operating as a boost converter.

[0136] At a time period t6, the input voltage Vin 830 has risen to a range of values ​​such that the state of boost mode 810 transitions between high and low. At time t6, the buck-boost converter transitions between buck converter operation and boost converter operation, as shown by the state of the first switching node LX1 810 and the state of the second switching node LX2 815.

[0137] At a time period t7, the input voltage Vin is significantly greater than the output voltage Vout, and the buck-boost converter operates in buck mode. The boost mode 805 state is low, the second switching node LX2 815 state is high, and the first switching node LX1 810 state indicates the switching process associated with the converter operating as a buck converter.

[0138] Fig. Figure 17 shows a diagram of a fourth embodiment of the buck-boost switching converter 900 that uses a sensorless method for regulating an output voltage Vout. The buck-boost switching converter 900 is as shown in Fig.11, however, the inputs of comparator 235 differ from those previously described. The first input is coupled to a first terminal of a matching capacitor Cff3, a first terminal of a third matching resistor RH3, and a first terminal of a fourth matching resistor RL3. A second terminal of the matching capacitor Cff3 is coupled to ground. A second terminal of the third matching resistor RH3 is coupled to a second terminal of the fourth matching resistor RL3. The second terminals of the third matching resistor RH3 and the fourth matching resistor RL3 are coupled to a fixed voltage source at a first reference voltage Vref1. The matching capacitor Cff3, the third matching resistor RH3, and the fourth matching resistor RL3 are used to provide an impedance matching function for the first reference voltage Vref1.The matching capacitor Cff2 is matched to the matching capacitor Cff3, as achieved when Cff2 = Cff3. The feedforward capacitor Cff1 is optional and can be omitted. Additionally, the matching capacitor Cff2 and the matching capacitor Cff3 are optional, and one or both can be omitted.

[0139] The input of the impedance matching circuit 236 is coupled to an output of a front-end error amplifier 905. A first input of the front-end error amplifier 905 is coupled to the feedback node Nfb, and a second input of the front-end error amplifier 905 receives a second reference voltage Vref2.

[0140] The above embodiments show implementations of a buck-boost switching converter with analog blocks, a comparator, simple RC networks, and a 300 ns timer that achieves the same performance as more complex buck-boost switching converters. In particular, a complex system does not require the management of transitions between different operating modes.

Claims

[1] Buck-boost switching converter (200, 300, 400, 900) having an input for receiving an input voltage and an output for providing an output voltage, comprising: a first set of switches comprising a first power switch (205) and a first ground switch (210); a second set of switches comprising a second power switch (206) and a second ground switch (211); a control device configured to send control signals to the first set of switches and the second set of switches, and configured such that: in a buck mode, the first set of switches operates to provide buck regulation while the second power switch (206) is maintained in a closed state; in a boost mode, the second set of switches operates to provide boost regulation while the first power switch (205) is maintained in a closed state; and the control device is configured to selectively operate the buck-boost switching converter (200, 300, 400, 900) in the buck mode or in the boost mode based on a length of a time period during which both the first power switch (205) and the second power switch (206) are in a closed state; wherein when operating in the buck mode, the control device is designed to switch the buck-boost switching converter (200, 300, 400, 900) to the boost mode when the time period during which both the first power switch (205) and the second power switch (206) are in a closed state exceeds a first threshold; and when operating in the boost mode, the control device is designed to switch the buck-boost switching converter (200, 300, 400, 900) into the buck mode when the time period during which both the first power switch (205) and the second power switch (206) are in a closed state exceeds a second threshold. [2] The buck-boost switching converter (200, 300, 400, 900) of claim 1, wherein the first and second thresholds are equal. [3] The buck-boost switching converter (200, 300, 400, 900) according to any one of the preceding claims, wherein the buck-boost switching converter (200, 300, 400, 900) comprises an energy storage element, the output being coupled to the energy storage element when the second power switch (206) is in a closed state, and the input being coupled to the energy storage element when the first power switch (205) is in a closed state. [4] The buck-boost switching converter (200, 300, 400, 900) according to any one of the preceding claims, wherein the energy storage element is an inductor (215). [5] The buck-boost switching converter (200, 300, 400, 900) according to claim 4, comprising: an input of a first integration circuit (225) coupled to a first terminal of the inductor (215), the first integration circuit (225) being configured to receive a first voltage signal from the first terminal of the inductor (215) and to provide an integrated first voltage signal at an output of the first integration circuit (225); an input of a second integration circuit (226) coupled to a second terminal of the inductor (215), wherein the second integration circuit (226) is configured to receive a second voltage signal from the second terminal of the inductor (215) and to provide an integrated second voltage signal at an output of the second integration circuit (226); and a comparator (235) having a first input coupled to the output of the first integration circuit (225) and a second input coupled to the output of the second integration circuit (226), wherein the comparator (235) is configured to output the control signals at an output of the comparator (235) and to provide the control signals to the control device. [6] The buck-boost switching converter (200, 300, 400, 900) according to claim 5, which is a hysteresis buck-boost switching converter, wherein the comparator (235) exhibits hysteresis. [7] The buck-boost switching converter (200, 300, 400, 900) of claim 5 or claim 6, comprising a feedback voltage coupled to the first input of the comparator (235) and a reference voltage coupled to the second input of the comparator (235). [8] The buck-boost switching converter (200, 300, 400, 900) according to one of claims 5 to 7, wherein the control device comprises a demultiplexer (240) configured to receive the control signals from the output of the comparator (235) and provide the control signals to the first set of switches in the buck mode and provide the control signals to the second set of switches in the boost mode. [9] The buck-boost switching converter (200, 300, 400, 900) of claim 8, wherein the demultiplexer (240) provides the control signals to the first set of switches when operating in a first demultiplexer state and provides the control signals to the second set of switches when operating in a second demultiplexer state, the demultiplexer (240) being configured to selectively operate in the first demultiplexer state or the second demultiplexer state based on the length of the time period during which both the first power switch (205) and the second power switch (206) are in the closed state. [10] The buck-boost switching converter (200, 300, 400, 900) according to any one of claims 5 to 9, wherein the first integration circuit (225) comprises a first resistor and a first capacitor and the second integration circuit (226) comprises a second resistor and a second capacitor. [11] The buck-boost switching converter (200, 300, 400, 900) according to one of claims 5 to 10, wherein the output of the first integration circuit (225) is coupled to the first input of the comparator (235) via a first transfer element and the output of the second integration circuit (226) is coupled to the second input of the comparator (235) via a second transfer element. [12] The buck-boost switching converter (200, 300, 400, 900) according to claim 11, wherein the first and second transfer elements are capacitors. [13] The buck-boost switching converter (200, 300, 400, 900) according to claim 1 or claim 2, wherein the control device comprises a decision circuit (245), wherein: when operating in the buck mode, the decision circuit (245) is configured to provide a first mode signal to switch the buck-boost switching converter (200, 300, 400, 900) to the boost mode when the time period during which both the first power switch (205) and the second power switch (206) are in the closed state exceeds the first threshold; and when operating in the boost mode, the decision circuit (245) is configured to provide a second mode signal to switch the buck-boost switching converter (200, 300, 400, 900) to the buck mode when the time period during which both the first power switch (205) and the second power switch (206) are in the closed state exceeds the second threshold. [14] The buck-boost switching converter (200, 300, 400, 900) according to claim 13, wherein the decision circuit (245) comprises: an AND gate (305) having a first input coupled to the first power switch (205) and a second input coupled to the second power switch (206); a timing circuit (310) having an input coupled to an output of the AND gate (305); and a mode circuit (315) having an input coupled to an output of the timing circuit (310); wherein the AND gate (305) outputs a “high” signal when the first power switch (205) and the second power switch (206) are in the closed state; wherein when operating in the buck mode, if a "high" signal is received at the input of the timing circuit (310) for the first threshold, the timing circuit (310) outputs a signal to the mode circuit (315), and in response, the mode circuit (315) provides the first mode signal to switch the operating mode of the switching converter from the buck mode to the boost mode; and when operating in the boost mode, if a "high" signal is received at the input of the timing circuit for the second threshold, the timing circuit outputs a signal to the mode circuit, and in response, the mode circuit provides the second mode signal to switch the operating mode of the switching converter from the boost mode to the buck mode. [15] A method of controlling the operation of a buck-boost switching converter (200, 300, 400, 900) of the type having a first set of switches comprising a first power switch (205) and a first ground switch (210), and a second set of switches comprising a second power switch (206) and a second ground switch (211), the method comprising: Sending control signals to the first set of switches and the second set of switches; in a buck mode, operating the first set of switches to provide buck regulation while maintaining the second power switch (206) in a closed state; in a boost mode, operating the second set of switches to provide boost regulation while maintaining the first power switch (205) in a closed state; and selectively operating the switching converter in the buck mode or the boost mode based on a length of a time period during which both the first power switch (205) and the second power switch (206) are in the closed state; when operating in the buck mode, switching the buck-boost switching converter (200, 300, 400, 900) to the boost mode when the time period during which both the first power switch (205) and the second power switch (206) are in the closed state exceeds a first threshold; and when operating in the boost mode, switching the buck-boost switching converter (200, 300, 400, 900) to the buck mode when the time period during which both the first power switch (205) and the second power switch (206) are in the closed state exceeds a second threshold. [16] The method of claim 15, wherein the first and second thresholds are equal. [17] The method according to any one of claims 15 to 16, wherein the buck-boost switching converter (200, 300, 400, 900) comprises an energy storage element, wherein an output of the buck-boost switching converter (200, 300, 400, 900) is coupled to the energy storage element when the second power switch (206) is in a closed state, and an input is coupled to the energy storage element when the first power switch (205) is in a closed state. [18] The method of claim 17, wherein the energy storage element is an inductor (215). [19] The method according to claim 18, comprising: Integrating a first voltage signal from a first terminal of the inductor (215) and providing an integrated first voltage signal to a first input of a comparator; Integrating a second voltage signal from a second terminal of the inductor (215) and providing an integrated second voltage to a second input of the comparator (235); and Outputting the control signals from an output of the comparator (235). [20] The method of claim 19, wherein the comparator (235) exhibits hysteresis. [21] The method of claim 19 or claim 20, comprising providing a feedback voltage to the first input of the comparator (235) and providing a reference voltage to the second input of the comparator (235).

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