Active matrix substrate and method for producing an active matrix substrate

Abstract

Active matrix substrate (100, 200, 400) with a display area comprising a plurality of pixel areas (P) and a non-display area, excluding the display area, wherein the active matrix substrate (100, 200, 400) comprises: a substrate (1); a plurality of source bus lines (SL) extending along a first direction and a plurality of gate bus lines (GL) extending along a second direction intersecting the first direction, wherein the source bus lines (SL) and the gate bus lines (GL) are supported on the substrate (1); and a thin-film transistor (10, 20) arranged in each of the plurality of pixel areas (P), each thin-film transistor (10, 20) having a gate electrode (GE), an oxide semiconductor layer (7c) arranged on the gate electrode (GE) by means of a gate insulating layer (5), and a source electrode (SE) and a drain electrode (DE),which are arranged on the oxide semiconductor layer (7c) and are electrically connected to the oxide semiconductor layer (7c); the plurality of gate bus lines (GL) and the gate electrode (GE) are made from a first electrically conductive film; at least a portion of each of the plurality of source bus lines (SL), the source electrode (SE), and the drain electrode (DE) has a multilayer structure comprising a lower layer (8) made from a second electrically conductive film and an upper layer (9) made from a first transparent electrically conductive film; wherein the active matrix substrate (100, 200, 400) further comprises a pixel electrode (PE) arranged in each of the plurality of pixel regions (P) and a common electrode (CE) arranged on the pixel electrode (PE) by means of an intermediate insulating layer (11),wherein the pixel electrode (PE) is made from the first transparent electrically conductive film and the common electrode (CE) is made from a second transparent electrically conductive film; or further comprising in each of the plurality of pixel regions (P) a pixel electrode (PE) arranged on the thin-film transistor (10, 20) by means of an intermediate insulating layer (11), wherein the pixel electrode (PE) is made from a second transparent electrically conductive film; and a plurality of first oxide strips (7a) arranged between the plurality of source bus lines (SL) and the gate insulating layer (5), wherein the plurality of first oxide strips (7a) are made from the same oxide semiconductor film as the oxide semiconductor layer (7c) and extend along the first direction,wherein each of the plurality of source bus lines (SL) is located on an upper surface of a corresponding first oxide strip (7a) of the plurality of first oxide strips (7a) and the width of each of the plurality of source bus lines (SL) along the second direction is less than the width of the one corresponding first oxide strip (7a) along the second direction, wherein the active matrix substrate (100, 200, 400) further comprises a plurality of source-gate interconnect sections (Csg) arranged in the non-display area, wherein each of the plurality of source-gate interconnect sections (Csg) comprises a gate interconnect section (GC) made from the first electrically conductive film, a source interconnect section (SC) having the multilayer structure, a second oxide strip (7b) arranged between the source interconnect section (SC) and the gate insulating layer (5) and made from the oxide semiconductor film,and comprises an upper interconnection section (TC) made of the second transparent electrically conductive film, which connects the gate interconnection section (GC) and the source interconnection section (SC); the upper interconnection section (TC) is in direct contact with the gate interconnection section (GC), the second oxide strip (7b), and the source interconnection section (SC) within an opening (Hc) formed in the intermediate insulating layer (11) and the gate insulating layer (5); and viewed in a direction perpendicular to the substrate (1), within the opening (Hc) an edge of the second oxide strip (7b) is located inwards from an edge of the source interconnection section (SC), and within the opening (Hc) a side face of the second oxide strip (7b) and a side face of the gate insulating layer (5) are aligned.

Description

BACKGROUND1. Technical Field:The present invention relates to an active matrix substrate and a method for producing an active matrix substrate.2. Description of the Prior Art:An active matrix type liquid crystal display device generally includes: a substrate having a thin film transistor (hereinafter also referred to as "TFT") formed as a switching element for each pixel thereof (hereinafter referred to as "active matrix substrate"); a counter substrate on which a counter electrode, color filters and the like are formed; a liquid crystal layer provided between the active matrix substrate and the counter substrate; and a pair of electrodes for applying a voltage to the liquid crystal layer.Depending on their applications, various modes of operation have been proposed and used for active matrix type liquid crystal display devices. Examples of the operation modes include a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane Switching) mode, an FFS (Fringe Field Switching) mode, etc.Of these, the TN mode and the VA mode are modes of the vertical field method in which an electric field is applied to liquid crystal molecules through a pair of electrodes between which the liquid crystal layer is disposed. The IPS mode and the FFS mode are lateral field method modes in which a pair of electrodes are provided on one of the substrates and an electric field is applied to the liquid crystal molecules from a direction parallel to the substrate plane (lateral direction). Using the lateral field method, the liquid crystal molecules do not protrude from the substrate, which provides the advantage of realizing a wider viewing angle than is possible with the vertical field method.In recent years, use of an oxide semiconductor instead of a silicon semiconductor has been proposed for forming the active layer of a TFT. Such a TFT is referred to as an "oxide semiconductor TFT". An oxide semiconductor provides higher mobility than amorphous silicon. Therefore, an oxide semiconductor TFT can operate faster than an amorphous silicon TFT.For example, WO 2013 / 073 635 A1 discloses a method in which oxide semiconductor TFTs are used as switching elements in providing an active matrix substrate for use in a liquid crystal display device of the FFS mode. In this production method, eight photolithography steps are carried out (i.e., eight photomasks are used) (cf. WO 2013 / 073 635 A1, FIG. 6 ). A method of thus requiring eight photomasks may be referred to as "8 mask method".US 2013 / 234 331 A1 discloses an active matrix substrate for use in a liquid crystal display device of the FFS mode, in which an improved connection structure is used. More specifically, the document teaches a connection conversion part including a first transparent conductive film covering an end surface of a first conductive film and formed in a predetermined pattern to suppress floating of an insulating film on the first transparent conductive film and to increase the electric conductivity between the first transparent conductive film and the first conductive film.US 2012 / 0 241 750 A1 describes an article in which the middle connector covers the end surfaces of the two insulating films at the main opening and thereby does not cover the end surface of the protective film at the other opening, so that the conical shape of the contact hole of the terminal portion can be controlled with high accuracy, whereby the reliability of the semiconductor device can be improved.US 2013 / 271 690 A1 describes an active matrix substrate, wherein a structure for connecting a source bus line and a gate connection line using a conductive layer made of a pixel electrode material is provided. At this time, in a connection portion, the conductive layer is formed by patterning the same transparent conductive film as the pixel electrode. In this structure, the connection portion is desirably configured such that the end of the source bus line is located above the upper surface of the oxide semiconductor layer when viewed along a normal line to the substrate. As a result, the contact hole is given a tapered shape, so that a required process margin can be ensured and a connection failure due to peeling of the conductive layer can be avoided.SUMMARYIn order to improve the machability of an active matrix substrate using oxide semiconductor TFTs, it is desired to further reduce the number of photomasks required for manufacturing an active matrix substrate, thereby reducing the manufacturing cost. Further, a method that produces an active matrix substrate using oxide semiconductor TFTs with a good production yield is also desired.An embodiment of the present invention has an object of providing an active matrix substrate having good mullability. Another object thereof is to provide a method for producing an active matrix substrate, which can reduce the production cost and / or improve the production yield.The above and other objects of the invention are achieved with an active matrix substrate and a method for producing an active matrix substrate as set forth in the independent claims. Preferred embodiments are set out in the dependent claims.According to one embodiment of the present invention, an active matrix substrate having good mullability is provided. In addition, a method for producing an active matrix substrate is provided that can reduce the production cost and / or improve the production yield.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 : A diagram schematically showing an example of a planar structure of an active matrix substrate 100 according to Embodiment 1. FIG. 2A is a plan view showing an example of each pixel region P of the active matrix substrate 100 of Embodiment 1. FIG. 2B is a cross-sectional view of the pixel region P taken along the line I-I' in FIG. 2A. FIG. 2C is a cross-sectional view of a source bus line SL taken along line II-II' in FIG. 2A. FIG. 3A is a diagram showing an exemplary source-gate connection portion Csg according to Embodiment 1, including the portions: (a) a plan view; and (b) a cross-sectional view taken along the line III-III' in (a). FIG. 3B is a diagram showing another source-gate connection portion Csg according to Embodiment 1, including the portions: (a) a plan view; and (b) a cross-sectional view taken along the line III-III' in (a). FIG. 4A is a plan view showing another source-gate connection portion Csg according to Embodiment 1. FIG. 4B is a cross-sectional view showing the source-gate connection portion Csg in FIG. 4A. FIG. 5A is a plan view showing a terminal portion T according to Embodiment 1. FIG. 5B is a cross-sectional view showing the terminal portion T in FIG. 5A. FIG. 6A is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 100. FIG. 6B is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 100. FIG. 6C is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 100. FIG. 6D is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 100. FIG. 6E is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 100. FIG. 7 is a diagram showing the procedure of a method for manufacturing the active matrix substrate 100. FIG. 8A is a step-by-step cross-sectional view for describing a method of manufacturing an active matrix substrate 200 according to Variation 1. FIG. 8B is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 200 according to Variation 1. FIG. 8C is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 200 according to Variation 1. FIG. 8D is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 200 according to Variation 1. FIG. 8E is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 200 according to Variation 1. FIG. 9A is a plan view showing a source bus line SL according to Variation 2. FIG. 9B is a cross-sectional view of the source bus line SL according to Variation 2 taken along line IX-IX' in FIG. 9A. FIG. 9C is a cross-sectional view of the source bus line SL according to Variation 2 taken along line X-X' in FIG. 9A. FIG. 10A is a step-by-step cross-sectional view for describing a method of manufacturing an active matrix substrate 300 according to Variation 3. FIG. 10B is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 300 according to Variation 3. FIG. 10C is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 300 according to Variation 3. FIG. 10D is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 300 according to Variation 3. FIG. 10E is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 300 according to Variation 3. FIG. 11A is a cross-sectional view showing an exemplary active matrix substrate 400 according to Embodiment 2. FIG. 11B is a cross-sectional view showing another source-gate connection portion according to Embodiment 2. FIG. 11C is a cross-sectional view showing another drain extension according to Embodiment 2. FIG. 12A is a step-by-step cross-sectional view for describing a method of manufacturing an active matrix substrate 400. FIG. 12B is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 400. FIG. 12C is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 400. FIG. 12D is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 400. FIG. 12E is a step-by-step cross-sectional view for describing a method of manufacturing the active matrix substrate 400. Fig. 13 is a diagram showing the procedure of a method for producing an active matrix substrate 400.DETAILED DESCRIPTIONHereinafter, with reference to the drawings, active matrix substrates and methods for manufacturing the same according to the embodiments of the present invention will be described.Embodiment 1An active matrix substrate according to Embodiment 1 is an active matrix substrate for use in, for example, a liquid crystal display device of the FFS mode. It should be noted that an active matrix substrate according to the present embodiment may include at least TFTs and two transparent conductive layers on one substrate, and broadly includes active matrix substrates for use in liquid crystal display devices having other operation modes, various display devices other than liquid crystal display devices, electronic devices, and the like.FIG. 1 is a diagram schematically showing an exemplary planar structure of an active matrix substrate 100 according to the present embodiment. The active matrix substrate 100 includes a display area DR contributing to display and an edge area (frame area) FR located outside the display area DR.In the display region DR, a plurality of source bus lines (data lines) SL extend along a first direction, and a plurality of gate bus lines (gate lines) GL extend along a second direction intersecting the first direction (e.g., orthogonal in this example). Each area surrounded by these bus lines defines a "pixel area P". The pixel regions P are regions corresponding to pixels of a display device, and thus may be referred to as "pixels". The plurality of pixel regions P are arranged in a matrix form. In each pixel region P, a pixel electrode PE and a thin film transistor (TFT) 10 are formed. A gate electrode of each TFT 10 is electrically connected to a corresponding gate bus line GL, while a source electrode of each TFT 10 is electrically connected to a corresponding source bus line SL. Moreover, a drain electrode of each TFT 10 is electrically connected to the pixel electrode PE. In the present embodiment, a common electrode (not shown) opposite to the pixel electrode PE is connected via a dielectric layer (insulating layer) above the pixel electrode PE.In the peripheral area FR, a plurality of gate terminal portions Tg, a plurality of source terminal portions Ts, a plurality of source gate connection portions Csg, and the like are arranged. Each gate bus line GL is connected to a gate driver (not shown) by a corresponding gate terminal portion Tg. Each source bus line SL is connected to a source driver (not shown) via a corresponding source terminal portion Ts. The gate driver or drivers and source drivers may be monolithically formed on the active matrix substrate 100 or may be mounted on the active matrix substrate 100.Each source-gate connection portion Csg is a connection between a source bus line SL (or any wiring line made of the same electrically conductive film as a source bus line SL); and a wiring line made of the same electrically conductive film as a gate bus line GL. As shown in the figure, a source-gate connection portion Csg may be disposed between each source bus line SL and each source terminal portion Ts, for example, so that the source bus line SL may be connected to a connection line (gate connection line) made of the same electrically conductive film as the gate bus line GL. The gate connection line is connected to the source driver via the source terminal portion Ts. In this case, the source terminal portion Ts may have a similar structure as the gate terminal portion Tg.Next, each region of the active matrix substrate 100 according to the present embodiment will be described more specifically.Pixel Area PFIG. 2A is a plan view showing an example of each pixel region P of the active matrix substrate 100. FIG. 2B is a cross-sectional view of the pixel region P taken along the line I-I' above the TFT 10 in FIG. 2A. FIG. 2C is a cross-sectional view of a source bus line SL taken along line II-II' in FIG. 2A.The pixel region P is, for example, a region surrounded by source bus lines SL extending along the first direction and gate bus lines GL extending along a second direction intersecting the first direction. The pixel region P includes a substrate 1, a TFT 10 supported on the substrate 1, a pixel electrode PE, and a common electrode CE. The common electrode CE is disposed on the pixel electrode PE via an interlayer insulating layer 11.The TFT 10 is a channel etching type bottom gate pattern TFT. The TFT 10 includes a gate electrode GE disposed on the substrate 1, a gate insulating film 5 covering the gate electrode GE, an oxide semiconductor film 7 cdisposed on the gate electrode GE via the gate insulating film 5, and a source electrode SE and a drain electrode DE electrically connected to the oxide semiconductor film 7 c. The gate electrode GE is electrically connected to a corresponding gate bus line GL, while the source electrode SE is electrically connected to a corresponding source bus line SL. The drain electrode DE is electrically connected to the pixel electrode PE.The source electrode SE and the drain electrode DE are each disposed to be in contact with a part of an upper surface of the oxide semiconductor layer 7 c. Within the oxide semiconductor layer 7 c, a part in contact with the source electrode SE is referred to as a source contact region, and a part in contact with the drain electrode DE is referred to as a drain contact region. When viewed in the direction perpendicular to the substrate 1, a region that is located between the source contact region and the drain contact region and that overlaps the gate electrode GE defines a "channel region".The gate electrode GE and the gate bus line GL are made of a first electrically conductive film. The source bus line SL and the source electrode SE and the drain electrode DE each have a multilayer structure including a lower layer 8 formed of a second electrically conductive film and an upper layer 9 made of the same transparent electrically conductive film as the pixel electrode PE (first transparent electrically conductive film). The upper layer 9 is in direct contact with an upper surface of the lower layer 8, and the source electrode SE and the drain electrode DE may be located inside the oxide semiconductor layer 7 cwhen viewed in the direction perpendicular to the substrate 1.On the substrate 1 side of the plurality of source bus lines SL (i.e., between the plurality of source bus lines SL and the gate insulating film 5), a plurality of first oxide stripes 7 aare disposed, the first oxide stripe 7 abeing made of the same oxide semiconductor film as the oxide semiconductor layer 7 cand extending along the first direction. Each source bus line SL is located on an upper surface of a corresponding first oxide strip 7a and is in direct contact with an upper surface of this first oxide strip 7a. When viewed in the direction perpendicular to the substrate 1, the source bus line SL does not protrude from the first oxide strip 7 a. Each source bus line SL has a width ws along the second direction (hereinafter referred to as the "line width" or simply as the "width") that is less than the width (along the second direction) wo 1 of the corresponding first oxide strip 7 a. In other words, when viewed in the direction perpendicular to the substrate 1, the lower layer 8 and the upper layer 9 of the source bus line SL are located inside the upper surface of the first oxide strip 7 a(i.e., between the two edges of the first oxide strip 7 aextending along the first direction).The resistance of a part of the first oxide strip 7 athat is in direct contact with the lower layer 8 (e.g., formed of a metal film) may be reduced due to the lower layer 8. In this case, the first oxide strip 7 aincludes a low resistance region (or a conductor region) having a lower electric resistance than that of the oxide semiconductor layer 7 cthat constitutes the active layer of the TFT 10.The TFT 10 and the pixel electrode PE are covered by the interlayer insulating layer 11. The interlayer insulating film 11 is, for example, an inorganic insulating film (passivation film). The interlayer insulating film 11 is in direct contact with the channel region of the TFT 10.On the interlayer insulating film 11, the common electrode CE is formed. The common electrode CE is made of a second transparent electrically conductive film. The common electrode CE has one or more slit(s) (opening(s)) 15 sor recess(s) formed therein, each(s) of which corresponds to a pixel region P. Moreover, an opening 15 pmay be formed in a region where the TFT 10 (TFT forming region) is formed.The pixel electrode PE and the common electrode CE are arranged to partially overlap each other via the interlayer insulating layer 11. Separate pixel electrodes PE are provided for the respective pixels. The common electrode CE cannot be separated for each pixel. For example, the common electrode CE may be formed over the entire pixel region P except for the TFT formation regions.In the present specification, a layer M 1 formed using the first electrically conductive film (also referred to as "gate electrically conductive film") is referred to as a "gate metal layer"; a layer M 2 formed using the second electrically conductive film (also referred to as "source electrically conductive film") is referred to as a "source metal layer"; a layer T 1 formed using the first transparent electrically conductive film is referred to as a "first transparent conductive layer"; and a layer T 2 formed using the second transparent electrically conductive film is referred to as a "second transparent conductive layer". In addition, a layer OS formed using an oxide semiconductor film is referred to as a "metal oxide layer". The metal oxide layer OS also includes any part of the oxide semiconductor that has become electrically conductive by reduction.From the substrate 1 side, the active matrix substrate 100 includes, in this order, the gate metal layer M 1, the gate insulating layer 5, the metal oxide layer OS, the source metal layer M 2, the first transparent conductive layer T 1, the interlayer insulating layer 11, and the second transparent conductive layer T 2. Figs. 2A to 2C show which constituent element is formed in which layer.In the example shown, the gate electrode GE and the gate bus line GL may be integrally formed within the gate metal layer M 1 (by using the first electrically conductive film). The gate electrode GE may be a part inside the gate bus line GL or may be a protrusion from the gate bus line GL.The lower layer 8 of the source electrode SE and the lower layer 8 of the source bus line SL may be integrally formed within the source metal layer M 2 (by using the second electrically conductive film). The upper layer 9 of the source electrode SE and the upper layer 9 of the source bus line SL may be integrally formed within the first transparent conductive layer T 1 (by using the first transparent electrically conductive film). The source electrode SE may be a source bus line SL or a protrusion from the source bus line SL.The first oxide stripes 7 aand the oxide semiconductor layer 7 care integrally formed within the metal oxide layer OS (by using an oxide semiconductor film). It should be noted that each source electrode SE may be a part of the source bus line SL, while the source contact region of each oxide semiconductor layer 7 cmay be a part of the first oxide stripe 7 a.The lower layer 8 of the drain electrode DE can be island-shaped, for example. The upper layer 9 of the drain electrode DE and the pixel electrode PE are integrally formed within the first transparent conductive layer T 1 (using the first transparent electrically conductive film). The upper layer 9 of the drain electrode DE may act as part of the pixel electrode PE.Source-Gate Connection Portion CsgIn FIG. 3A, the portions (a) and (b) are a plan view and a cross-sectional view taken along the line III-III' in (a) showing an exemplary source-gate connection portion Csg.The source gate connection portion Csg includes a gate connection portion GC formed in the gate metal layer M 1, a source connection portion SC formed in the source metal layer M 2 and the first transparent conductive layer T 1, and an upper connection portion TC formed in the second transparent conductive layer T 2. The gate connection portion GC and the source connection portion SC are electrically connected to each other by the upper connection portion TC. The source connection portion SC has a similar multilayer structure as the source bus line SL (i.e., a structure in which the lower layer 8 and the upper layer 9 are stacked in this order from the substrate 1 side). Moreover, on the substrate 1 side of the source connection portion SC (i.e., between the source connection portion SC and the gate insulating film 5), a second oxide strip 7 bmade of an oxide semiconductor film is disposed.The source connection portion SC may be an end portion of the source bus line SL. The gate connection portion GC may be a connection line (gate connection line) that connects the source bus line SL and the source terminal portion Ts.In the gate insulating film 5 and the interlayer insulating film 11, the source-gate connection portion Csg has a single opening (referred to as "SG contact hole") Hc through which at least a part of the gate connection portion GC, at least a part of the second oxide stripe 7 b, and at least a part of the source connection portion SC are exposed. Inside the SG contact hole Hc, the side surfaces (end surfaces) at the ends of the gate insulating film 5 and the second oxide stripe 7 bare substantially aligned. When viewed in the direction perpendicular to the substrate 1, inside the SG contact hole Hc, the edge of the second oxide stripe 7 bis located inward from the edge of the source connection portion SC (i.e., protrudes into the SG contact hole Hc). Such a structure can be formed by a method described later.The upper connection portion TC is disposed on the interlayer insulating film 11 and inside the SG contact hole Hc, and is in direct contact with the gate connection portion GC, the second oxide strip 7b, and the source connection portion SC inside the SG contact hole Hc.In the present embodiment, within the SG contact hole Hc, the edge of the interlayer insulating film 11, the edge of the source connection portion SC, and the edges of the second oxide stripe 7 band the gate insulating film 5 are sequentially present inward in this order. In other words, the side surface of the SG contact hole Hc, which is on the source connection portion SC side, is in a staircase shape. As a result, the upper connecting portion TC is prevented from being interrupted.As shown in the portions (a) and (b) of FIG. 3B, a first opening h 1 through which the gate connection portion GC is exposed and a second opening h 2 through which the source connection portion SC is exposed may be spaced apart from each other. On the other hand, in the example shown in the portions (a) and (b) of FIG. 3A, the first opening through which the gate connection portion GC is exposed (formed in the gate insulating film 5 and the interlayer insulating film 11) and the second opening through which the source connection portion SC is exposed (formed in the interlayer insulating film 11) partially overlap, thereby forming a single SG contact hole Hc. This reduces the geometric area required for the source-gate connection portion Csg, whereby the geometric area of the peripheral area FR can be reduced (i.e., a narrow frame). As an example, the geometric area required for the source gate connection portion Csg may be reduced to less than 1 / 2 (e.g., 300 μm 2) of the case where two openings h 1 and h 2 are formed in the source gate connection portion Csg (e.g., 700 μm 2).FIGS. 4A and 4B are a plan view and a cross-sectional view, respectively, showing another source gate connection portion Csg according to the present embodiment.As shown in the figure, an island-shaped upper connection portion TC may be formed only within the SG contact hole Hc without being in contact with the upper surface of the interlayer insulating film 11 (i.e., without being present on the interlayer insulating film 11). As a result, level differences in the non-display region FR (particularly, a region where an encapsulating material with which the liquid crystal layer is to be encapsulated is formed (hereinafter, an "encapsulating region")) can be reduced. Consequently, the invasion of moisture from outside the sealing material can be reduced, whereby spot-like display defects which might otherwise occur near the peripheral edge of the display area can be reduced. Moreover, in the peripheral edge of the display area, variations in the liquid crystal cell gap (increase and decrease non-uniformities) due to level differences in the encapsulation area can be restricted. Further, when an alignment film is rubbed, occurrence of rubbing streaks (i.e., unevenness occurring in a line shape in the alignment film) due to differences in level (slopes and wastes) in the sealing area transferred to the alignment film within the display area by the rubbing cloth can be reduced. This enables the reduction of display irregularities associated with friction stripes.Terminal Portion TFIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, showing an exemplary source terminal portion Ts and / or a gate terminal portion Tg (hereinafter collectively referred to as "terminal portions T").The terminal portion T includes a lower conductive portion GR formed in the gate metal layer M 1 and an island-shaped upper conductive portion TR formed in the second transparent conductive layer T 2. Within a terminal portion contact hole Hr formed in the gate insulating film 5 and the interlayer insulating film 11 so as to expose at least a part of the lower conductive portion GR, the upper conductive portion TR is in direct contact with the lower conductive portion GR. In the gate terminal portion Tg, the lower conductive portion GR may be an end portion of the gate bus line GL. In the source terminal portion Ts, the lower conductive portion GR may be, for example, an end portion of the above gate connection line. The gate connection line may be connected to the source bus line SL via the source gate connection portion Csg.Method for Producing Active Matrix Substrate 100Next, with reference to FIGS. 6A to 6E and FIG. 7, an exemplary method of manufacturing the active matrix substrate 100 according to the present embodiment will be described.FIGS. 6A to 6E are step-by-step cross-sectional views for describing the exemplary method of manufacturing the active matrix substrate 100, schematically showing: a region (gate bus line forming region) 101 in which a gate bus line GL is formed, a region (source bus line forming region) 102 in which a source bus line SL is formed; a pixel opening region 103 to become the opening (light transmitting portion) of each pixel; a TFT forming region 104 in which a TFT 10 is formed; and a source gate connection portion forming region 105 in which a source gate connection portion Csg is formed. FIG. 7 shows the concept of a manufacturing method of the active matrix substrate 100.STEP 1: Formation of Gate Metal Layer M 1 (FIG. 6A )On the substrate 1, a first electroconductive film (electroconductive film for gate) (thickness: e.g., not less than 50 nm and not more than 500 nm) is formed by, for example, a sputtering technique. Next, by a first photolithography step using a first photomask and a wet etching or dry etching step, the first electroconductive film is patterned. As a result, as shown in FIG. 6A, a gate metal layer M 1 is formed, which includes a gate bus line GL, a gate electrode GE of a TFT, a gate connection portion GC, and a lower conductive portion (not shown).As the substrate 1, a transparent and electrically insulating substrate such as a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate), or the like can be used.As for the material of the first electroconductive film, there is no particular limitation, and a film containing any metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof, or a metal nitride thereof may be suitably used. Moreover, a multilayer film obtained by stacking a plurality of such films may be used. Here, as the first electroconductive film, a multilayer film including a Ti layer (thickness: 30 nm), an Al film (thickness: 200 nm), and a TiN film (thickness: 100 nm) in this order from the substrate 1 side is used.STEP 2: Formation of a gate insulating film 5 and a metal oxide film OS, first patterning the source metal film M2 (FIG. 6B)Next, a gate insulating film 5 is formed on the substrate 1 so as to cover the gate metal film M 1.The gate insulating film 5 is formed by, for example, a CVC technique. As the gate insulating film 5, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNxOy; x>y) film, or the like can be used as appropriate. The gate insulating film 5 may be a single layer or may have a multilayer structure. For example, in order to prevent diffusion of impurity or the like from the substrate 1, a silicon nitride (SiNx) layer, a silicon nitride oxide layer, or the like may be formed on the substrate (lower layer) side, and in a layer above (upper layer), a silicon oxide (SiO 2)- layer, a silicon oxynitride layer, or the like may be formed for providing electrical insulation. Here, the gate insulating film 5 is formed to have a multilayer structure in which an SiNxlayer having a thickness of, for example, 300 nm defines a lower layer and an SiO 2- film having a thickness of, for example, 50 nm defines an upper layer.In the case where an oxide semiconductor layer is used as the active layer of the TFT, it is preferable that the uppermost layer (i.e., a layer in contact with the oxide semiconductor layer) of the gate insulating layer 5 is an oxygen-containing layer (e.g., an oxide layer such as SiO 2). As a result, when oxygen vacancies occur in the oxide semiconductor layer, the oxygen vacancies can be eliminated with the oxygen contained in the oxide layer, whereby oxygen vacancies in the oxide semiconductor layer can be effectively reduced.Thereafter, an oxide semiconductor film and a second electrically conductive film are formed in this order on the gate insulating film 5.The oxide semiconductor film can be formed by a sputtering technique, for example. The thickness of the oxide semiconductor film may be, for example, not less than 30 nm and not more than 200 nm. Here, as the oxide semiconductor film, an In-Ga-Zn-O-based semiconductor film (thickness: 50 nm) containing In, Ga, and Zn is formed.The second electroconductive film may be formed by, for example, a sputtering technique. As for the material of the second electroconductive film, there is no particular limitation, and a film containing any metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), or titanium (Ti), or an alloy thereof, or a metal nitride thereof may be suitably used. Here, as the electrode film for sources, a Ti layer (thickness: 50 nm), an Al layer (thickness: 150 nm), and a Ti layer (thickness: 50 nm) are formed in this order, thereby providing a multilayer film.Next, the oxide semiconductor film and the second electrically conductive film are patterned. Here, first, the second electroconductive film is patterned by a second photolithography step using a second photomask and dry etching. Then, the oxide semiconductor film is patterned by wet etching with oxalic acid.Consequently, as shown in FIG. 6B, in the TFT forming region 104, an electrode layer 84 that becomes the source / drain of the TFT is formed of the second electrically conductive film, and an oxide semiconductor layer 7 cthat becomes the active layer of the TFT is formed of the oxide semiconductor film. Patterning of the oxide semiconductor film and the second electrically conductive film is performed using the same resist mask, and therefore side surfaces of the electrode layer 84 and the oxide semiconductor layer 7 care aligned. The electrode layer 84 is not divided into a source and a drain, and has the same planar shape as that of the oxide semiconductor layer 7 c.In the source bus line forming region 102, a temporary source bus line 82, which becomes the lower layer of the source bus line SL, is formed of the second electrically conductive film, and a first oxide strip 7 ais formed of the oxide semiconductor film. Side surfaces of the first oxide strip 7 aand the preliminary source bus line 82 are aligned. The width wo 1 of the preliminary source bus line 82 and the first oxide strip 7 ais larger than the desired width of the source bus line SL. For example, when the desired width of the source bus line SL is 4 μm, the width wo 1 may be made to be 7 μm.In the source gate connection portion forming region 105, a preliminary source connection portion 85 is formed of the second electrically conductive film, and a second oxide strip 7 bis formed of the oxide semiconductor film. Side surfaces of the temporary source connection portion 85 and the second oxide strip 7 bare aligned, and the width of the temporary source connection portion 85 and the second oxide strip 7 bis larger than the desired width of the source connection portion.In the other regions (e.g., the pixel opening region 103), the oxide semiconductor film and the second electrically conductive film are removed, so that the gate insulating film 5 is exposed.By this step, a metal oxide layer OS including the oxide semiconductor layer 7 c, the first oxide stripe 7 a, and the second oxide stripe 7 bis obtained. Moreover, a source metal layer in a preliminary shape including the preliminary source bus line 82, the electrode layer 84, and the like is obtained.STEP 3: Second Patterning of Source Metal Layer M2 and Formation of First Transparent Conductive Layer T1 (FIG. 6C)Next, a first transparent electrically conductive film is formed so as to cover the source metal layer in the preliminary shape (i.e., the preliminary source bus line 82 and the electrode layer 84, etc.). As the first transparent electroconductive film, for example, an ITO (indium tin oxide) film (thickness: 50 nm to 150 nm), an IZO film (indium zinc oxide), a ZnO film (zinc oxide film), or the like can be used. Here, as the transparent electroconductive film, an ITO film (thickness: 65 nm) is formed by a sputtering technique.Next, patterning of the first transparent electroconductive film and the second electroconductive film is performed. At first, by a third photolithography step using a third photomask and wet etching, the first transparent electroconductive film is patterned. For example, oxalic acid may be used as the etchant. Then, the second electroconductive film is patterned by dry etching.Consequently, as shown in FIG. 6C, a pixel electrode PE is obtained from the first transparent electrically conductive film, and a source electrode SE and a drain electrode DE are formed from the first transparent electrically conductive film and the second electrically conductive film (source-drain separation), thereby obtaining the TFT 10. Moreover, from the first transparent electrically conductive film and the second electrically conductive film, a source bus line SL and a source connection portion SC are obtained.The source bus line SL, the source electrode SE, the drain electrode DE, and the source connection portion SC each have a multilayer structure including a lower layer 8 and an upper layer 9. Since the patterning of the first transparent electroconductive film and the second electroconductive film is performed using the same resist mask, side surfaces of the lower layer 8 and the upper layer 9 can be aligned in the multilayer structure.Specifically, in the TFT forming region 104, the upper layer 9 of the source electrode SE and the drain electrode DE are formed of the first transparent electrically conductive film, and the lower layer 8 of the source electrode SE and the drain electrode DE is formed of the electrode layer 84. In the pixel opening region 103, the pixel electrode PE is obtained from the first transparent electroconductive film.In the source bus line forming portion 102, the upper layer 9 of the source bus line SL is formed of the first transparent electrically conductive film, and the lower layer 8 of the source bus line SL is formed of the preliminary source bus line 82. The width of the upper layer 9 of the source bus line SL and the lower layer 8 is smaller than the width of the first oxide strip 7 a.In the source gate connection portion forming region 105, the upper layer 9 of the source connection portion SC is formed of the first transparent electrically conductive film, and the lower layer 8 of the source connection portion SC is formed of the temporary source connection portion 85. The lower layer 8 and the upper layer 9 of the source connection portion SC are disposed so as not to protrude from the upper surface of the second oxide strip 7 b. The width wsc of the lower layer 8 and the upper layer 9 of the source connection portion SC is smaller than the width wo 2 of the second oxide strip 7 b. In other words, when viewed in the direction perpendicular to the substrate 1, the lower layer 8 and the upper layer 9 of the source connection portion SC are located inward of (the upper surface) the second oxide strip 7 b.By this step, a source metal layer M2 including the lower layer 8 of the source bus line SL, etc., and a first transparent conductive layer T1 including the upper layer 9 of the source bus line SL, etc., and the pixel electrode PE are obtained.STEP 4: Formation of Interlayer Insulating Layer 11 (FIG. 6D)On the entire substrate 1, an interlayer insulating film 11 is formed so as to cover the TFT 10 and the source bus line SL. As the interlayer insulating film 11, for example, an inorganic insulating film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNxOy; x>y) film, or the like can be formed. The inorganic insulating layer may be formed by a CVD technique, for example. Although there is no particular limitation on the thickness of the interlayer insulating film 11, it may be, for example, not less than 300 nm and not more than 1000 nm. The interlayer insulating layer 11 does not need to include any planarization film such as an organic insulating layer.In this example, as the interlayer insulating film 11, a multilayer film in which a silicon oxide (SiO 2)- layer 11A constitutes a lower layer and a silicon nitride (SiNx) layer 11B constitutes an upper layer is formed by a CVD technique. Within the interlayer insulating film 11, since an oxide film such as the SiO 2- film 11A is used as the lower layer that directly contacts the channel region of the oxide semiconductor film 7 c, oxygen vacancies in the oxide semiconductor film 7 cmay be reduced, thereby enabling stability of the characteristics of the TFT 10. Moreover, the use of the SiNxlayer 11B as the upper layer enables the suppression of pinholes, and enables the interlayer insulating layer 11 to become a thick film, thereby reducing leakage between the pixel electrode PE and a common electrode CE (described later) with more certainty.Next, by a fourth photolithography step using a fourth photomask and dry etching, the interlayer insulating film 11 and the gate insulating film 5 are patterned.Consequently, as shown in FIG. 6D, a single opening (SG contact hole Hc) may be formed in the interlayer insulating film 11 and the gate insulating film 5 through which at least a part of the gate connection portion GC, at least a part of the second oxide stripe 7 band at least a part of the source connection portion SC are exposed. In this case, the second oxide strip 7 b, which is an SG oxide semiconductor film, functions as an etching barrier. Therefore, the side surface of the gate insulating film 5 and the side surface of the second oxide stripe 7 bare aligned with the side surface of the SG contact hole Hc.Although not shown, an opening (terminal portion contact hole) Hr through which a part of the gate bus line GL or the gate connection line is exposed is also formed in the terminal portion forming region (see FIGS. 5A and 5B ).In this patterning step, preferably, the side surfaces of the contact holes Hc and Hr are tapered forward, and the etching conditions such as the etching time are adjusted so that overetch of the electrodes and wiring lines to be exposed is reduced (i.e., so that the surface layer of the electrodes and wiring lines by the etching does not become a thin film (i.e., have a reduced film thickness)).STEP 5: Formation of Second Transparent Conductive Layer T 2 (FIG. 6E)Next, a second transparent electrically conductive film is formed on the interlayer insulating film 11 and within the SG contact hole Hc. The material and thickness of the second transparent electroconductive film may be similar to those of the first transparent electroconductive film. At this time, an ITO film (thickness: 65 nm) is formed by a sputtering technique.Thereafter, the second transparent electroconductive film is patterned. Consequently, as shown in FIG. 6E, a common electrode CE covering substantially the entire display region (except for the TFT formation region 104) is formed, and also an upper connection portion TC is formed in the source gate connection portion formation region 105. In the TFT forming region 104, the common electrode CE has one or more slit(s). Within the SG contact hole Hc, the upper connection portion TC is in direct contact with the source connection portion SC, the second oxide stripe 7b, and the gate connection portion GC. Although not shown, also in the terminal portion forming region, an upper conductive portion TR which is in direct contact with the lower conductive portion GR is formed inside the terminal portion contact hole Hr.In this step, a second transparent conductive layer T2 including the common electrode CE and the upper connection portion TC is obtained. In this manner, the active matrix substrate 100 is formed.It should be noted that, in STEP 4, instead of forming a single SG contact hole Hc in the source gate connection portion forming region 105, a first opening h 1 through which a part of the gate electrode GE is to be exposed may be formed in the gate insulating layer 5 and in the interlayer insulating layer 11 and a second opening h 2 through which a part of the pixel electrode PE is exposed may be formed in the interlayer insulating layer 11 (see FIG. 3B ). In this case, in STEP 5, an upper connection portion TC that is in direct contact with the gate connection portion GC within the first opening h 1 and that is in direct contact with the source connection portion SC within the second opening h 2 is formed.With the method for manufacturing the active matrix substrate 100 according to the present embodiment, the number of photomasks used can be made much smaller than conventionally, and also the manufacturing cost and the number of manufacturing steps can be reduced. For example, eight photomasks have conventionally been required for manufacturing an active matrix substrate including oxide semiconductor TFTs (see Patent Document 1); on the other hand, the above-described method enables manufacturing with five photomasks. Consequently, improved mullability can be obtained.Moreover, in the above-described method, the source bus line SL has a multilayer structure including the lower layer 8 in the source metal layer M 2 and the upper layer 9 in the first transparent conductive layer T 1 (redundant structure). As a result, during the manufacturing process, even if a broken portion occurs in the lower layer 8 of the source bus line SL due to the patterning, failure of the source metal layer M 2 accompanied with dust or foreign materials such as a broken portion in the lower layer 8 can be cured by the upper layer 9; consequently, interruptions in the source bus line SL can be reduced. According to an investigation by the inventors, by employing a redundant structure for the source bus line SL, the defect percentage associated with interruptions in the source bus line SL can be reduced to 1 / 3 or less of the case where a redundant structure is not employed.Further, in the above-described method, the patterning of the source metal layer M 2 is performed in two steps. Specifically, in the second photolithography step, the oxide semiconductor film is patterned while first patterning the second electrically conductive film is performed; and in the third photolithography step, second patterning of the second electrically conductive film is performed while the first transparent electrically conductive film is patterned. By performing such two stages of patterning, the first oxide strip 7 ais formed under the source bus line SL to have a line width larger than that of the source bus line SL. This provides improved coverage of the interlayer insulating film 11 with respect to the source bus line SL. Moreover, with respect to the source-gate connection portion Csg, the edge of the second oxide stripe 7b is located inward from the edge of the source connection portion SC within the SG contact hole Hc, whereby the coverage of the upper connection portion TC can be improved and interruption of the upper connection portion TC can be suppressed. Consequently, the manufacturing yield can be improved.In the case where an amorphous silicon semiconductor layer is used as the active layer of the TFT, during a patterning step of the interlayer insulating layer 11 (STEP 4), when the interlayer insulating layer 11 is dry-etched, there is a possibility that the amorphous silicon semiconductor layer is also etched ("side etching"), so that the side surface of the amorphous silicon semiconductor layer may shrink from the side surface of the source connection portion SC (thus resulting in an inverted tapered shape). When the side surface of the opening is reversely tapered, the coverage of the upper connecting portion TC is greatly reduced. On the other hand, the second oxide strip 7 bis highly resistant to dry etching, and thus the second oxide strip 7 bis unlikely to be etched during the etching step of the interlayer insulating film 11. Therefore, according to the present embodiment, without increasing the number of photomasks, the side surface of the SG contact hole Hc can be made to have a staircase shape tapering forward, whereby the coverage of the upper connection portion TC can be improved.Further, in the case where an amorphous silicon semiconductor layer is used, the presence of the amorphous silicon semiconductor layer under the source bus line may allow photoexcitation of the amorphous silicon semiconductor caused by light from backlight (PWM dimming), so that the amorphous silicon semiconductor may become electrically conductive. This will change the capacitance between the source metal layer M 2 and the second transparent conductive layer T 2, thereby causing a problem in that the field driving frequency may interfere with the PWM frequency, which may result in sounds (hitting sound) on the screen within a specific frequency band. In the present embodiment, the oxide semiconductor layer 7 cthat is less sensitive to light than an amorphous silicon semiconductor is used, and even when a silicon oxide layer having a low insulating constant is used for the interlayer insulating layer 11, variations in capacitance can be suppressed and occurrence of striking sound can be suppressed.Variant 1An active matrix substrate according to Variation 1 is different from the active matrix substrate 100 in that, in the display region, the source bus line SL is a transparent wiring line including only the upper layer 9 (i.e., not including the lower layer 8).Figs. 8A to 8E are step-by-step cross-sectional views for describing a method of manufacturing an active matrix substrate 200 according to Variation 1. Differences in the steps shown with reference to Figs. 6A to 6E will be mainly described below.First, as shown in FIG. 8A, a gate metal layer M 1 is formed.Next, as shown in FIG. 8B, an oxide semiconductor film and a second electrically conductive film are formed and patterned. In Variation 1, there is a difference from the step shown in FIG. 6B in that in the source bus line forming region 102 within the display region, the oxide semiconductor film and the second electrically conductive film are removed.Next, as shown in FIG. 8C, a first transparent electroconductive film is formed, and the first transparent electroconductive film and the second electroconductive film are patterned. As a result, the lower layer 8 of the source electrode SE, the lower layer 8 of the drain electrode DE and the lower layer 8 of the source connection portion SC are formed of the second electrically conductive film, whereas the source bus line SL, the pixel electrode PE, the upper layer 9 of the source electrode SE, the upper layer 9 of the drain electrode DE and the upper layer 9 of the source connection portion SC are formed of the first transparent electrically conductive film. In the display area, the source bus line SL is a transparent wiring line including only the first transparent electrically conductive film. Since the first oxide strip 7 ais not disposed on the transparent wiring line substrate 1 side, the transparent wiring line is in contact with the upper surface of the gate insulating film 5.Thereafter, as shown in FIGS. 8D and 8E, the interlayer insulating film 11 and the second transparent conductive film T 2 are formed. In this manner, the active matrix substrate 200 is formed.According to Variation 1, the pixel opening ratio can be increased because the transparent source bus line SL is formed in the display region. Moreover, since an oxide semiconductor is not disposed below the source bus line SL, the above-mentioned striking sound can be more effectively reduced.As shown in FIGS. 8A to 8E, in the non-display region (e.g., the source-gate connection portion forming region), the source bus line SL may have a multilayer structure including a lower layer 8 made of the second electrically conductive film and an upper layer 9 made of the first transparent electrically conductive film. As a result, the pixel aperture ratio can be increased while reducing the circuit resistance. Alternatively, the entire source bus line SL (including any portion located in the non-display region) may have a single-layer structure made of only the first transparent electrically conductive film.Variant 2Variation 2 is different from the active matrix substrate 100 in that, in the display region, one portion of the source bus line SL has a single-layer structure, while the other portion of the source bus line SL has a multi-layer structure.FIG. 9A is a plan view of the source bus line SL according to Variation 2, and FIGS. 9B and 9C are cross-sectional views of the source bus line SL taken along the line XI-XI' and the line X-X', respectively.The source bus line SL includes: a first source portion L 1_SMR having a multilayer structure including a lower layer 8 and an upper layer 9; and a second source portion L 2_SMR including an upper layer 9 but not including a lower layer 8. The second source portion L 2_MR has a single-layer structure including only an upper layer 9, for example, and is transparent.The first source portion L 1_MR is located above the first oxide stripe 7 a. On the other hand, the first oxide strip 7 ais not disposed on the substrate 1 side of the second source portion L 2_MR. The second source portion L 2_MR is in contact with an upper surface of the gate insulating film 5, for example.In this example, the second source portion L 2_VL is to be disposed in each intersecting region where the source bus line SL and the gate bus line GL intersect when viewed in the direction perpendicular to the substrate 1, whereas the first source portion L 1_VL is to be disposed in any region of the display region (i.e., a region located between two adjacent gate bus lines GL) other than the intersecting region. Any portion of the source bus line SL located in the non-display region may be the first source portion L 1_SL having a multilayer structure.In this variant, it is sufficient as long as the source bus line SL includes the first source portion L 1_LN and the second source portion L 2_LN, and the arrangement thereof is not limited to the example shown. Disposing the second source portion L 2_SLD in the intersecting region between the source bus line SL and the gate bus line GL has an advantage that level differences occurring in the intersecting region can be reduced.The active matrix substrate of Variant 2 is formed by steps described with reference to Figs. 6A to 6E. In STEP 2, in a portion of the source bus line forming region 102 where the second source portion L 2_MR is to be formed, the oxide semiconductor film and the second electrically conductive film are removed (see FIG. 8B showing Variation 1); and in the portion where the first source portion L 1_MR is to be formed, the first oxide stripe 7 aand the lower layer 8 are formed of the oxide semiconductor film and the second electrically conductive film. Thus, the resultant source bus line SL partially has a single-layer structure.Variation 3An active matrix substrate of Variation 3 is different from the active matrix substrate 100 in that an upper layer 9 of the source bus line SL is disposed so as to cover the upper surface and the side surface of a lower layer 8.Figs. 10A to 10E are step-by-step cross-sectional views for describing a method of manufacturing an active matrix substrate 300 according to Variation 3. Differences in the steps shown with reference to Figs. 6A to 6E will be mainly described below.As shown in FIG. 10A, a gate metal layer M 1 is formed.Next, as shown in FIG. 10B, an oxide semiconductor film and a second electrically conductive film are formed and patterned.According to Variation 3, in the source bus line forming region 102, the first oxide stripe 7 aand the lower layer 8 of the source bus line SL are formed. A difference with respect to the step shown in FIG. 6B is that the width wa of the first oxide stripe 7 aand the lower layer 8 is smaller than the width of the finally obtained source bus line.Accordingly, in the source gate connection portion forming region 105, the second oxide stripe 7 band a lower layer 8 of the source connection portion SC are formed. The width of the second oxide stripe 7 band the source connection portion SC is smaller than the width of the finally obtained source connection portion SC.Next, as shown in FIG. 10C, a first transparent electroconductive film is formed, and the first transparent electroconductive film and the second electroconductive film are patterned.In the source bus line forming region 102, the upper layer 9 of the source bus line SL is formed of the first transparent electrically conductive film. A difference with respect to the step shown in FIG. 6B is that the upper layer 9 is formed so as to cover the upper surface and the side surface of the lower layer 8 of the source bus line SL and the side surface of the first oxide strip 7 a. The width wb of the upper layer 9 will be larger than the width wa of the lower layer 8 and the first oxide strip 7a. In this way, the source bus line SL including the upper layer 9 and the lower layer 8 is obtained.Accordingly, in the source-gate connection portion forming region 105, an upper layer 9 of the source connection portion SC is formed of the first transparent electrically conductive film. The upper layer 9 is formed so as to cover the upper surface and the side surface of the lower layer 8 of the source connection portion SC and the side surface of the second oxide strip 7 b. The width of the upper layer 9 is greater than the width of the lower layer 8 and the second oxide strip 7 b. In this way, the source connection portion SC including the upper layer 9 and the lower layer 8 is obtained.Thereafter, as shown in FIGS. 10D and 10E, the interlayer insulating film 11 and the second transparent conductive film T 2 are formed.In variant 3, too, the source bus line SL is formed with a redundant structure. Based on the structure of the variant 3, the width wa of the lower layer 8 can be made smaller than conventional while reducing the increase in the electric resistance of the source bus line SL. As a result, the pixel aperture ratio can be further increased.Embodiment 2An active matrix substrate according to Embodiment 2 is an active matrix substrate to be used in a liquid crystal display device based on the vertical field driving method, e.g., VA mode. In a liquid crystal display device based on the vertical field driving method, usually, the pixel electrodes PE are formed on the active matrix substrate while the common electrode CE is formed on the counter substrate side.A liquid crystal display device of the VA mode is disclosed in, for example, Japanese Patent Laid-Open No. 2004-078157. The entire disclosure of Japanese Patent Laid-Open No. 2004-078157 is incorporated herein by reference.FIG. 11A is a cross-sectional view showing examples of respective regions of an active matrix substrate 400 according to the present embodiment. In FIG. 11A, a source bus line forming region 102, a pixel opening region 103, a TFT forming region 104, and a source gate connection portion forming region 105 are respectively shown in a cross-sectional structure. Differences from Embodiment 1 will be mainly described below, while description of similar constituent elements will be omitted as appropriate.A pixel region P includes a substrate 1, a TFT 20 supported on the substrate 1, a storage capacitor lower electrode C 1, and a pixel electrode PE. The lower storage capacitor electrode C1 is formed in a gate metal layer M1. The position, shape, size, etc. of the storage capacitor lower electrode C 1 may be selected in an appropriate manner.The TFT 20 is a channel etching type TFT whose structure is similar to that of the TFT 10. A source electrode SE and a drain electrode DE of the TFT 20 have a multilayer structure including a lower layer 8 formed in a source metal layer M 2 and an upper layer 9 formed in a first transparent conductive layer T 1.The TFT 20 is covered by an interlayer insulating film 11. The interlayer insulating layer 11 includes, for example, an inorganic insulating layer (passivation film) 12 and an organic insulating layer 13 disposed on the inorganic insulating layer 12.The pixel electrode PE is disposed within an opening (referred to as a "pixel opening" or a "pixel contact hole") CH formed in the interlayer insulating film 11 and the interlayer insulating film 11 and is in contact with the drain electrode DE within the pixel contact hole CH. Separate pixel electrodes PE are provided for the respective pixel regions P. In the pixel electrode PE, one or more slit(s) 15 qfor pixel division may be provided for each pixel region P.In the pixel opening region 103, an extension (drain extension) DL of the drain electrode DE may be provided. The drain extension DL has a multilayer structure similar to that of the drain electrode DE. On the side of the substrate 1 of the drain extension DL, a third oxide strip 7 dis arranged, which has a greater width than the drain extension DL. The third oxide strip 7 dmay be connected (i.e., integrally formed) to the oxide semiconductor layer 7 c. The drain extension DL is provided to allow a storage capacitor electrode (not shown) formed in the source metal layer M 2 to be connected to the drain electrode DE.As shown in FIG. 11C, the drain extension DL may include: a first drain portion L 1_DL having a multilayer structure including a lower layer 8 and an upper layer 9; and a transparent second drain portion L 2_DL including only an upper layer 9. In this case, the third oxide strip 7 dis disposed between the first drain portion L 1_DL and the gate insulating film 5, but is not disposed on the substrate 1 side of the second drain portion L 2_DL. Accordingly, the drain electrode DE may include a first drain portion L 1_DE and a second drain portion L 2_DE such that the first drain portion L 1_DE is located closer to the channel region of the TFT 20 than the second drain portion L 2_DE. For example, the pixel electrode PE may be in contact with a transparent second drain portion L 2_DE (i.e., only a transparent upper layer 9) within the contact hole CH. By providing the transparent second drain portion or portions L 2_DL and / or L 2_DE in a part of the drain extension DL and / or the drain electrode DE, the pixel opening ratio can be improved.The gate bus line GL (not shown), the source bus line SL, and the source-gate connection portion Csg have a similar structure to those of the active matrix substrate 100, and description thereof is omitted. Also in the present embodiment, at the source-gate connection portion Csg, as shown in FIG. 11B, the upper connection portion TC may be disposed only within the SG contact hole Hc without being present on the interlayer insulating film 11.The structure of the present embodiment is not limited to the structure shown in Figs. 11A to 11C. For example, as in Variations 1 and 2 of Embodiment 1, the source bus line SL may include a first source portion having a multilayer structure and a second source portion having a single layer structure formed of only the first transparent electrically conductive film. Moreover, as in Variation 3, the upper layer 9 of the source bus line SL may cover the side surface of the first oxide strip 7 aand the upper surface and the side surface of the lower layer 8.Method for Producing Active Matrix Substrate 400Next, with reference to FIGS. 12A to 12E and FIG. 13, an exemplary method of manufacturing an active matrix substrate 400 according to the present embodiment will be described. Hereinafter, any description concerning aspects similar to those of Embodiment 1 (material, thickness, forming method, processing method, etc., of each layer) is omitted as appropriate.Figs. 12A to 12E are step-by-step cross-sectional views for describing the exemplary method of manufacturing the active matrix substrate 400, and show a source bus line forming region 102, a pixel opening region 103, a TFT forming region 104, and a source gate connection portion forming region 105. Fig. 13 shows a concept of the manufacturing method of the active matrix substrate 400.STEP 1: Formation of a gate metal layer M1 (FIG. 12A)By a method similar to that of Embodiment 1 (Fig. 6A), a first electroconductive film is formed on a substrate 1, and the first electroconductive film is patterned by a first photolithography step using a first photomask. As a result, a gate metal layer M 1 is formed, which includes a gate electrode GE made of a TFT, a gate connection portion GC, a storage capacitor lower electrode C 1, a terminal portion lower conductive portion (not shown), and a gate bus line GL.STEP 2: Formation of the gate insulating film 5 and the metal oxide film OS, first patterning the source metal film M 2 (FIG. 12B )Next, a gate insulating film 5 is formed so as to cover the gate metal film M 1. Thereafter, an oxide semiconductor film and a second electrically conductive film are formed in this order on the gate insulating film 5. Then, similarly to Embodiment 1 (FIG. 6B ), by a second photolithography step using a second photomask, a source metal layer in a preliminary shape (including a preliminary source bus line 82, a preliminary drain extension 83, an electrode layer 84, and the like) and a metal oxide layer OS (including an oxide semiconductor layer 7 c, a first oxide strip 7 a, a second oxide strip 7 b, and a third oxide strip 7 d) are obtained.STEP 3: Second Patterning of Source Metal Layer M2 and Formation of First Transparent Conductive Layer T1 (FIG. 12C)Next, a first transparent electrically conductive film is formed so as to cover the source metal layer in a preliminary shape (i.e., the preliminary source bus line 82, the electrode layer 84, etc.). Then, by a third photolithography step using a third photomask, the first transparent electroconductive film and the second electroconductive film are patterned. Consequently, as shown in FIG. 12C, the source electrode SE and the drain electrode DE are formed (source-drain separation), thereby providing a TFT 20. Moreover, a source bus line SL, a drain extension DL, and a source connection portion SC are formed. Differences from STEP 3 of Embodiment 1 are that the pixel electrode is not formed in the first transparent conductive layer T 1 and that the drain extension DL is formed.The source bus line SL, the source electrode SE, the drain electrode DE, the drain extension DL, and the source connection portion SC have a multilayer structure including a lower layer 8 and an upper layer 9.Through this step, a source metal layer M 2 including a lower layer 8 (e.g., the source bus lines SL) and a first transparent conductive layer T 1 including an upper layer 9 (e.g., the source bus lines SL) are obtained.STEP 4: Step of forming the interlayer insulating film 11 (FIG. 12D)An interlayer insulating film 11 is formed on the entire substrate 1 so as to cover the TFT 10 and the source bus line SL. Here, the interlayer insulating layer 11 has a multilayer structure including an inorganic insulating layer 12 and an organic insulating layer 13 disposed on the inorganic insulating layer 12. As the inorganic insulating layer 12, for example, an inorganic insulating layer such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x>y) film, a silicon nitride oxide (SiNxOy; x>y) film, or the like may be formed. The inorganic insulating layer 12 is formed by, for example, a CVD technique. The organic insulating layer 13 may be, for example, a positive type photosensitive resin film having a thickness of 2000 nm. The organic insulating layer 13 may be formed by deposition, for example.Next, after patterning the organic insulating film 13 by a fourth photolithography step using a fourth photomask, the inorganic insulating film 12 and the gate insulating film 5 are etched using the organic insulating film 13 as an etching mask. Consequently, as shown in FIG. 12D, in the TFT forming region 104, a pixel contact hole CH through which a part of the drain electrode DE is exposed is formed in the interlayer insulating film 11, and at SG contact hole Hc through which a part of the gate connection portion GC and a part of the source connection portion SC are exposed is formed in the source gate connection portion forming region 105. In this case, the second oxide stripe 7 b, which is an oxide semiconductor film, functions as an etching barrier; therefore, the side surface of the gate insulating film 5 and the side surface of the second oxide stripe 7 bare aligned with the side surface of the SG contact hole Hc.STEP 5: Formation of Second Transparent Conductive Layer T 2 (FIG. 12E)Next, a second transparent electrically conductive film is formed on the interlayer insulating film 11 and inside the pixel contact hole CH and the SG contact hole Hc. Thereafter, by a fifth photolithography step using a fifth photomask and wet etching, the second transparent electroconductive film is patterned. As a result, a pixel electrode PE is formed in each pixel region P, and an upper connection portion TC is formed in the source-gate connection portion forming region 105. (A) slot(s) 15q for one pixel division may be provided for each pixel electrode PE. Thus, the active matrix substrate 400 is prepared.Without being limited to the above-mentioned FFS mode or VA mode, an active matrix substrate according to the present invention is applicable to display devices having different display modes. For example, it is also applicable to a TBA (Transverse Bend Alignment) mode. The TBA mode is a display method in which, using a positive type liquid crystal as a liquid crystal material, the liquid crystal is driven with a lateral field using a pair of electrodes provided on an active matrix substrate, thereby determining the alignment direction of the liquid crystal molecules. When no applied voltage is present, the liquid crystal assumes a vertical orientation; when a voltage is applied, the liquid crystal assumes a "bent" liquid crystal orientation rather than an in-plane rotation. An active matrix substrate similar to that of Embodiment 1 can be used in TBA mode applications. However, vertical alignment films are used as the alignment films. The TBA mode is disclosed in, for example, International Publication No. 2011 / 040080 and the like. Moreover, for example, Japanese Patent Laid-Open No. 2015-148638 discloses a type of TBA mode in which an electrode is also formed on the counter substrate so that both a vertical field and a lateral field are used. The entire disclosure of Japanese Patent Laid-Open No. 2015-148638 and International Publication No. 2011 / 040080 is incorporated herein by reference.Further, although liquid crystal display devices have been shown as examples in the above description, active matrix substrates according to the embodiments may also be used in other display devices, such as organic electroluminescence (EL) display devices, inorganic electroluminescence display devices, MEMS display devices, etc. The display device may include an active matrix substrate, a counter substrate facing the active matrix substrate, and a display medium layer provided between the active matrix substrate and the counter substrate. The display medium layer may be a liquid crystal layer, an organic EL layer, or the like.Regarding the oxide semiconductorThe oxide semiconductor included in the oxide semiconductor layer 7 cmay be an amorphous oxide semiconductor film or a crystalline oxide semiconductor having (a) crystalline portion(s). Examples of crystalline oxide semiconductors may include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axis is oriented substantially perpendicular to the layer plane.The oxide semiconductor layer 7 cmay have a multilayer structure including two or more layers. When the oxide semiconductor layer 7 chas a multilayer structure, the oxide semiconductor layer 7 cmay include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included. In the case where the oxide semiconductor layer 7 cis of a two-layer structure including an upper layer and a lower layer, it is preferable that the oxide semiconductor included in the upper layer has an energy gap larger than the energy gap of the oxide semiconductor included in the lower layer. However, when the difference between the energy gaps of these layers is relatively small, the energy gap of the lower layer oxide semiconductor may be larger than the energy gap of the upper layer oxide semiconductor.Materials, structures, film forming methods, and the like of amorphous oxide semiconductors and the above-mentioned crystalline oxide semiconductors, the structure of an oxide semiconductor layer having a multilayer structure, and the like are described in, for example, Japanese Patent Laid-Open No. 2014-007399. The entire disclosure of Japanese Patent Laid-Open No. 2014-007399 is incorporated herein by reference.The oxide semiconductor layer 7 cmay include, for example, at least one metal element of In, Ga, and Zn. In the present embodiment, the oxide semiconductor layer 7 cincludes, for example, an In-Ga-Zn-O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc). The ratio between In, Ga, and Zn (composition ratio) is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, and the like. Such an oxide semiconductor layer 7 cmay be made of an oxide semiconductor film including an In-Ga-Zn-O-based semiconductor.The In-Ga-Zn-O-based semiconductor may be amorphous or crystalline. As the In-Ga-Zn-O-based crystalline semiconductor, an In-Ga-Zn-O-based crystalline semiconductor whose c-axis is oriented generally perpendicular to the layer plane is preferable.It should be noted that the crystal structure of an In-Ga-Zn-O-based crystalline semiconductor is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2014-007399, Japanese Patent Laid-Open Publication No. 2012-134475, Japanese Patent Laid-Open Publication No. 2014-209727, etc. above. The entire disclosure of Japanese Patent Laid-Open No. 2012-134475 and Japanese Patent Laid-Open No. 2014-209727 is incorporated herein by reference. A TFT having an In-Ga-Zn-O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than 1 / 100 that of an a-Si TFT), and is suitably used as a driving TFT (e.g., a TFT included in a driving circuit provided around a display area including a plurality of pixels and provided on the same substrate as the display area) or a pixel TFT (a TFT provided in one pixel).The oxide semiconductor layer 7 cmay include other oxide semiconductors instead of an In-Ga-Zn-O-based semiconductor. For example, it may include an In-Sn-Zn-O-based semiconductor (e.g., In 2 O 3- SnO 2- ZnO; InSnSnO). An In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 7 cmay include an In-Al-Zn-O-based semiconductor, an In-Al-Sn-Zn-O-based semiconductor, a Zn-O-based semiconductor, an In-Zn-O-based semiconductor, a Zn-Ti-O-based semiconductor, a Cd-Ge-O-based semiconductor, a Cd-Pb-O-based semiconductor, CdO (cadmium oxide), an Mg-Zn-O-based semiconductor, an In-Ga-Sn-O-based semiconductor, an In-Ga-O-based semiconductor, a Zr-In-Zn-O-based semiconductor, an Hf-In-Zn-O-based semiconductor, an Al-Ga-Zn-O-based semiconductor, a Ga-Zn-O-based semiconductor, an In-Ga-Zn-Sn-O-based semiconductor, or the like.The active matrix substrates according to embodiments of the present invention are widely applicable to display devices such as liquid crystal display devices, organic electroluminescence (EL) display devices, and inorganic electroluminescence display devices; imaging devices such as image sensor devices; image input devices; fingerprint reading devices; or other electronic devices.

Claims

An active matrix substrate (100, 200, 400) having a display area comprising a plurality of pixel areas (P) and a non-display area excluding the display area, wherein the active matrix substrate (100, 200, 400) comprises: a substrate (1); a plurality of source bus lines (SL) extending along a first direction and a plurality of gate bus lines (GL) extending along a second direction intersecting the first direction, wherein the source bus lines (SL) and the gate bus lines (GL) are supported on the substrate (1); and a thin film transistor (10, 20) disposed in each of the plurality of pixel regions (P), each thin film transistor (10, 20) including a gate electrode (GE), an oxide semiconductor layer (7c) disposed on the gate electrode (GE) via a gate insulating film (5), and a source electrode (SE) and a drain electrode (DE) disposed on the oxide semiconductor layer (7c) and electrically connected to the oxide semiconductor layer (7c); the plurality of gate bus lines (GL) and the gate electrode (GE) are made of a first electrically conductive film; at least a part of each of the plurality of source bus lines (SL), the source electrode (SE), and the drain electrode (DE) has a multilayer structure including a lower layer (8) made of a second electrically conductive film and an upper layer (9) made of a first transparent electrically conductive film; wherein the active matrix substrate (100, 200, 400) further includes a pixel electrode (PE) disposed in each of the plurality of pixel regions (P) and a common electrode (CE) disposed on the pixel electrode (PE) via an interlayer insulating layer (11), wherein the pixel electrode (PE) is made of the first transparent electrically conductive film and the common electrode (CE) is made of a second transparent electrically conductive film; or further comprising, in each of the plurality of pixel regions (P), a pixel electrode (PE) disposed on the thin film transistor (10, 20) via an interlayer insulating film (11), the pixel electrode (PE) being made of a second transparent electrically conductive film; and a plurality of first oxide stripes (7a) being disposed between the plurality of source bus lines (SL) and the gate insulating film (5), the plurality of first oxide stripes (7a) being made of the same oxide semiconductor film as the oxide semiconductor layer (7c) and extending along the first direction, wherein each of the plurality of source bus lines (SL) is located on an upper surface of a corresponding first oxide stripe (7a) among the plurality of first oxide stripes (7a), and the width of each of the plurality of source bus lines (SL) along the second direction is smaller than the width of the corresponding first oxide stripe (7a) along the second direction, the active matrix substrate (100, 200, 400) further comprising a plurality of source gate connection portions (Csg) arranged in the non-display area, each of the plurality of source gate connection portions (Csg) comprising a gate connection portion (GC) made of the first electrically conductive film and a source connection portion (SC) having the multilayer structure, a second oxide strip (7b) disposed between the source connection portion (SC) and the gate insulating film (5) and made of the oxide semiconductor film, and an upper connection portion (TC) made of the second transparent electrically conductive film and making connection between the gate connection portion (GC) and the source connection portion (SC); the upper connection portion (TC) is in direct contact with the gate connection portion (GC), the second oxide strip (7b), and the source connection portion (SC) within an opening (Hc) formed in the intermediate insulating film (11) and the gate insulating film (5); and viewed in a direction perpendicular to the substrate (1), inside the opening (Hc), an edge of the second oxide strip (7b) is present inward from an edge of the source connection portion (SC), and inside the opening (Hc), a side surface of the second oxide strip (7b) and a side surface of the gate insulating film (5) are aligned.An active matrix substrate (100, 200, 400) having a display area comprising a plurality of pixel areas (P) and a non-display area excluding the display area, wherein the active matrix substrate (100, 200, 400) comprises: a substrate (1); a plurality of source bus lines (SL) extending along a first direction and a plurality of gate bus lines (GL) extending along a second direction intersecting the first direction, wherein the source bus lines (SL) and the gate bus lines (GL) are supported on the substrate (1); and a thin film transistor (10, 20) disposed in each of the plurality of pixel regions (P), each thin film transistor (10, 20) including a gate electrode (GE), an oxide semiconductor layer (7c) disposed on the gate electrode (GE) via a gate insulating film (5), and a source electrode (SE) and a drain electrode (DE) disposed on the oxide semiconductor layer (7c) and electrically connected to the oxide semiconductor layer (7c); the plurality of gate bus lines (GL) and the gate electrode (GE) are made of a first electrically conductive film; at least a part of each of the plurality of source bus lines (SL), the source electrode (SE), and the drain electrode (DE) has a multilayer structure including a lower layer (8) made of a second electrically conductive film and an upper layer (9) made of a first transparent electrically conductive film; wherein the active matrix substrate (100, 200, 400) further includes a pixel electrode (PE) disposed in each of the plurality of pixel regions (P) and a common electrode (CE) disposed on the pixel electrode (PE) via an interlayer insulating layer (11), wherein the pixel electrode (PE) is made of the first transparent electrically conductive film and the common electrode (CE) is made of a second transparent electrically conductive film; or further comprising, in each of the plurality of pixel regions (P), a pixel electrode (PE) disposed on the thin film transistor (10, 20) via an interlayer insulating film (11), the pixel electrode (PE) being made of a second transparent electrically conductive film; and a plurality of first oxide stripes (7a) being disposed between the plurality of source bus lines (SL) and the gate insulating film (5), the plurality of first oxide stripes (7a) being made of the same oxide semiconductor film as the oxide semiconductor layer (7c) and extending along the first direction, and in each of the plurality of source bus lines (SL), the lower layer (8) is located on an upper surface of a corresponding first oxide stripe (7a) of the plurality of first oxide stripes (7a), and the upper layer (9) covers an upper surface and a side surface of the lower layer (8) and a side surface of the one corresponding first oxide strip (7a) and is in contact with the gate insulating film (5), the active matrix substrate (100, 200, 400) further comprising a plurality of source-gate connection portions (Csg) disposed in the non-display region, each of the plurality of source-gate connection portions (Csg) including a gate connection portion (GC) made of the first electrically conductive film, a source connection portion (SC) having the multilayer structure, a second oxide strip (7b) disposed between the source connection portion (SC) and the gate insulating film (5) and made of the oxide semiconductor film, and an upper connecting portion (TC) made of the second transparent electroconductive film and connecting between the gate connecting portion (GC) and the source connecting portion (SC); the upper connecting portion (TC) is in direct contact with the gate connecting portion (GC), the second oxide strip (7b) and the source connecting portion (SC) within an opening (Hc) formed in the interlayer insulating film (11) and the gate insulating film (5); and viewed in a direction perpendicular to the substrate (1), inside the opening (Hc), an edge of the second oxide strip (7b) is present inward from an edge of the source connection portion (SC), and inside the opening (Hc), a side surface of the second oxide strip (7b) and a side surface of the gate insulating film (5) are aligned.The active matrix substrate (100, 200, 400) according to claim 1 or 2, wherein the upper connection portion (TC) is disposed only inside the opening (Hc) and is not in contact with an upper surface of the interlayer insulating layer (11).The active matrix substrate (100, 200, 400) according to any one of claims 1 to 3, wherein at least one of the plurality of source bus lines (SL) includes a first source portion (L1_SL) having the multilayer structure and a second source portion (L2_SL) including the upper layer (9) but not the lower layer (8).The active matrix substrate (100, 200, 400) of claim 4, wherein the first source portion (L1_SL) is in the non-display region and the second source portion (L2_SL) is in the display region.The active matrix substrate (100, 200, 400) according to claim 4, wherein in each of the plurality of source bus lines (SL) viewed in a direction perpendicular to the substrate (1), the first source portion (L1_SL) is disposed in a region existing between adjacent gate bus lines (GL) of the plurality of gate bus lines (GL), and the second source portion (L2_SL) is disposed in a region intersecting the plurality of gate bus lines (GL).The active matrix substrate (100, 200, 400) according to any one of claims 1 to 6, wherein the interlayer insulating layer (11) is a multilayer film including a silicon oxide layer in contact with a channel region of the oxide semiconductor layer (7c) and a silicon nitride layer disposed on the silicon oxide layer.The active matrix substrate (100, 200, 400) according to any one of claims 1 to 7, wherein the oxide semiconductor film comprises an In-Ga-Zn-O-based semiconductor.The active matrix substrate (100, 200, 400) of claim 8, wherein the In-Ga-Zn-O-based semiconductor comprises a crystalline portion.A method for manufacturing an active matrix substrate according to claim 1 or 2, wherein patterning of the first electroconductive film is performed by a first photolithography step using a first photomask; first patterning of the second electroconductive film and patterning of the oxide semiconductor film are performed by a second photolithography step using a second photomask; patterning of the first transparent electroconductive film and second patterning of the second electroconductive film are performed by a third photolithography step using a third photomask; patterning of the interlayer insulating film (11) and the gate insulating film (5) is performed by a fourth photolithography step using a fourth photomask by using the second oxide stripes (7b) as etching barriers; and patterning of the second transparent electroconductive film is performed by a fifth photolithography step using a fifth photomask.A method for manufacturing an active matrix substrate (100, 200, 400) having a display area including a plurality of pixel areas (P) and a non-display area excluding the display area, wherein the active matrix substrate (100, 200, 400) includes: a plurality of source bus lines (SL) and a plurality of gate bus lines (GL); a thin film transistor (10, 20); and a pixel electrode (PE) disposed in each of the plurality of pixel areas (P); A common electrode (CE), the method comprising: (a) a step of forming, on the substrate (1), a first electrically conductive film, and thereafter patterning the first electrically conductive film to form a gate metal layer comprising the plurality of gate bus lines (GL) and a gate electrode (GE) of each thin film transistor (10, 20), and forming a gate insulating film (5) covering the gate metal layer; (b) a step of forming an oxide semiconductor film and a second electrically conductive film in this order on the gate insulating film (5), and thereafter patterning the second electrically conductive film and the oxide semiconductor film, wherein in a transistor forming region (104) in which each thin film transistor (10, 20) is to be formed, an electrode layer (84) to be an(s) source / drain of the thin film transistor (10, 20) is formed of the second electrically conductive film, and an oxide semiconductor layer (7c) to be an active layer of the thin film transistor (10, 20) is formed of the oxide semiconductor film, and in a source bus line forming region (102) in which the plurality of source bus lines (SL) are to be formed, a plurality of temporary source bus lines (82) having a first width is formed of the second electrically conductive film, and a plurality of first oxide stripes (7a) having the first width is formed of the oxide semiconductor film; (c) a step of forming a first transparent electrically conductive film, which covers the plurality of temporary source bus lines (82) and the electrode layer (84), and thereafter, patterning the first transparent electrically conductive film, the plurality of temporary source bus lines (82), and the electrode layer (84), and forming a source electrode (SE) and a drain electrode (DE) of each thin film transistor (10, 20) to obtain the thin film transistor (10, 20), and obtaining the pixel electrode (PE) and the plurality of source bus lines (SL), wherein at least a part of each of the plurality of source bus lines (SL), the source electrode (SE), and the drain electrode (DE) has a multilayer structure including a lower layer (8) and an upper layer (9), wherein the pixel electrode (PE) is formed of the first transparent electrically conductive film, wherein in the transistor formation region (104), the upper layer of the source electrode (SE) and the upper layer of the drain electrode (DE) are formed of the first transparent electrically conductive film, and the lower layer of the source electrode (SE) and the lower layer of the drain electrode (DE) are formed of the electrode layer (84), wherein in the source bus line formation region (102), the upper layer of the plurality of source bus lines (SL) is formed of the first transparent electrically conductive film, the lower layer of the plurality of source bus lines (SL) is formed of the plurality of temporary source bus lines (82), the lower layer of each of the plurality of source bus lines (SL) has a second width less than the first width; (d) a step of forming an interlayer insulating film (11) covering the thin film transistor (10, 20) and the plurality of source bus lines (SL); and (e) a step of forming a second transparent electrically conductive film on the interlayer insulating film (11) and patterning the second transparent electrically conductive film to form the common electrode (CE), wherein the active matrix substrate (100, 200, 400) further comprises source-gate connection portions (Csg) disposed in the non-display region; in the step (a), the gate metal layer includes a gate connection portion (GC) disposed in a source gate connection portion forming region (105) in which each source gate connection portion (Csg) is to be formed; the step (b) includes a step of forming a preliminary source connection portion from the second electrically conductive film; and forming a second oxide strip (7b) from the oxide semiconductor film, the second oxide strip (7b) being on the substrate side of the preliminary source connection portion, in each source gate connection portion forming region (105); the step (c) includes a step of forming a source connection portion (SC) having the multilayer structure in each source gate connection portion forming region (105), wherein the lower layer of the source connection portion (SC) is formed of the temporary source connection portion, the upper layer of the source connection portion (SC) is formed of the first transparent electrically conductive film, and the lower layer of the source connection portion (SC) and the upper layer are located inward of the second oxide strip (7b) as viewed from a direction perpendicular to the substrate (1); the step (d) includes a step of patterning the interlayer insulating film (11) and the gate insulating film (5) by using the second oxide stripe (7b) as an etching barrier, thereby forming an opening through which at least a part of the gate connection portion (GC), at least a part of the second oxide stripe (7b), and at least a part of the source connection portion (SC) are exposed, in each source gate connection portion forming region (105); and the step (e) includes a step of forming an upper connection portion (TC) in direct contact with the source connection portion (SC) and the gate connection portion (GC) within the opening in each source gate connection portion forming region (105) by patterning the second transparent electrically conductive film.A method of manufacturing an active matrix substrate (100, 200, 400) having a display area comprising a plurality of pixel areas (P) and a non-display area excluding the display area, wherein the active matrix substrate (100, 200, 400) comprises: a plurality of source bus lines (SL) and a plurality of gate bus lines (GL); and a thin film transistor (10, 20) and a pixel electrode (PE) disposed in each of the plurality of pixel regions (P), the method comprising: (a) a step of forming, on the substrate (1), a first electrically conductive film, and thereafter patterning the first electrically conductive film to form a gate metal layer comprising the plurality of gate bus lines (GL) and a gate electrode (GE) of each thin film transistor (10, 20), and forming a gate insulating film (5) covering the gate metal layer; (b) a step of forming an oxide semiconductor film and a second electrically conductive film in this order on the gate insulating film (5), and thereafter patterning the second electrically conductive film and the oxide semiconductor film, wherein, in a transistor formation region (104) in which each thin film transistor (10, 20) is to be formed, an electrode layer (84) to be one(s) source / drain of the thin film transistor (10, 20) is formed from the second electrically conductive film and an oxide semiconductor layer (7c) to be an active layer of the thin film transistor (10, 20) is formed from the oxide semiconductor film, and in a source bus line formation region (102) in which the plurality of source bus lines (SL) are to be formed, a plurality of preliminary source bus lines (82) having a first width is formed from the second electrically conductive film, and a plurality of first oxide stripes (7a) having the first width is formed from the oxide semiconductor film; (c) a step of forming a first transparent electrically conductive film covering the plurality of temporary source bus lines (82) and the electrode layer (84), and thereafter patterning the first transparent electrically conductive film, the plurality of temporary source bus lines (82), and the electrode layer (84), and forming a source electrode (SE) and a drain electrode (DE) of each thin film transistor (10, 20) to obtain each thin film transistor (10, 20) and to obtain the plurality of source bus lines (SL), wherein at least a part of each of the plurality of source bus lines (SL), at least a part of the drain electrode (DE) and the source electrode (SE) having a multilayer structure include a lower layer (8) and an upper layer (9), wherein in the transistor formation region (104), the upper layer of the source electrode (SE) and the upper layer of the drain electrode (DE) are formed of the first transparent electrically conductive film, and the lower layer of the source electrode (SE) and the lower layer of the drain electrode (DE) are formed of the electrode layer (84), and wherein in the source bus line formation region (102), the upper layer of the plurality of source bus lines (SL) is formed of the first transparent electrically conductive film, the lower layer of the plurality of source bus lines (SL) is formed of the plurality of temporary source bus lines (82), the lower layer of each of the plurality of source bus lines (SL) having a second width less than the first width; (d) a step of forming an interlayer insulating film (11) covering the thin film transistor (10, 20) and the plurality of source bus lines (SL), and forming a pixel opening (103) in the interlayer insulating film (11) through which a portion of the drain electrode (DE) is exposed; (e) a step of forming a second transparent electrically conductive film on the interlayer insulating film (11) and inside the pixel opening (103), and patterning the second transparent electrically conductive film to form the pixel electrode (PE) so as to be in contact with the portion of the drain electrode (DE) inside the pixel opening (103), wherein the active matrix substrate (100, 200, 400) further comprises source-gate connection portions (Csg) disposed in the non-display region; in the step (a), the gate metal layer comprises a gate connection portion (GC) disposed in a source-gate connection portion formation region (105) in which each source-gate connection portion (Csg) is to be formed; the step (b) includes a step of forming a preliminary source connection portion from the second electrically conductive film; and forming a second oxide stripe (7b) from the oxide semiconductor film, the second oxide stripe (7b) being on the substrate side of the preliminary source connection portion, in each source gate connection portion forming region (105); the step (c) includes a step of forming a source connection portion (SC) having the multilayer structure in each source gate connection portion forming region (105), wherein the lower layer of the source connection portion (SC) is formed of the temporary source connection portion, the upper layer of the source connection portion (SC) is formed of the first transparent electrically conductive film, and the lower layer of the source connection portion (SC) and the upper layer are located inward of the second oxide strip (7b) as viewed from a direction perpendicular to the substrate (1); the step (d) includes a step of patterning the interlayer insulating film (11) and the gate insulating film (5) by using the second oxide stripe (7b) as an etching barrier, thereby forming an opening through which at least a part of the gate connection portion (GC), at least a part of the second oxide stripe (7b), and at least a part of the source connection portion (SC) are exposed, in each source gate connection portion forming region (105); and the step (e) includes a step of forming an upper connection portion (TC) in direct contact with the source connection portion (SC) and the gate connection portion (GC) within the opening in each source gate connection portion forming region (105) by patterning the second transparent electrically conductive film.The method for manufacturing an active matrix substrate (100, 200, 400) according to claim 11 or 12, wherein in the step (b), after patterning the second electrically conductive film by dry etching, the oxide semiconductor film is patterned by wet etching using oxalic acid.The method for manufacturing an active matrix substrate (100, 200, 400) according to any one of claims 11 to 13, wherein in the step (c), after patterning the first transparent electrically conductive film by wet etching using oxalic acid, the plurality of preliminary source bus lines (SL) and the electrode layer (84) are patterned by dry etching.The method for manufacturing an active matrix substrate (100, 200, 400) according to any one of claims 11 to 14, wherein at least one of the plurality of source bus lines (SL) includes a first source portion having the multilayer structure and a second source portion including the upper layer but not the lower layer; and the plurality of preliminary source bus lines (SL) and the first oxide strip (7a) are not formed in any region where the second source portion is disposed.The method for manufacturing an active matrix substrate (100, 200, 400) according to any one of claims 11 to 15, wherein the oxide semiconductor film comprises an In-Ga-Zn-O-based semiconductor.The method for producing an active matrix substrate (100, 200, 400) according to claim 16, wherein the In-Ga-Zn-O-based semiconductor comprises a crystalline portion.

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