INTEGRATED CIRCUIT STRUCTURE

Abstract

Integrated circuit structure comprising the following: a first magnetic layer (56'); a first conducting line (68) and a second conducting line (68) above the first magnetic layer (56') and parallel to each other; and a dielectric layer (70) comprising the following: first sections directly above the first leading line (68); a second section between the first leading line (68) and the second leading line (68); and third sections on opposite sides of a combined area, the combined area comprising the first conducting line (68), the second conducting line (68), and the second section of the dielectric layer (70), wherein side walls (70') of the third sections are inclined with bevel angles less than about 40 degrees and a stacked layer (82') over and in contact with the dielectric layer (70), wherein the stacked layer (82') comprises an adhesive layer (82A'), a dielectric layer (82B'), an etch stop layer and a magnetic layer (82C').

Description

GENERAL STATE OF THE ART

[0001] Inductors are important components in integrated circuits. However, inductors do not scale well, and downscaling inductors in integrated circuits is often associated with the disadvantage of degraded performance.

[0002] US 6,134,080 A discloses a strip of baked photoresist to define the zero-neck height (ZTH) of a read head section of an assembled head. The zero-neck height is the point at which the first and second pole pieces of the read head first begin to separate after an air bearing area (ABS) of the read head has formed between them to reduce flux loss. A read head section of the assembled head includes a read sensor with a recessed edge. The recessed edge defines a strip height of the read head. The strip height, i.e., the distance between the ABS and the recessed edge, determines the magnetic properties of the read head. The present invention positions the ZTH more accurately and with improved predictability relative to the strip height because the shrinkage of the photoresist strip during a baking step is minimal.Furthermore, the photoresist strip has a desirable tip angle at its leading ZTH-determining edge to minimize flux loss between the pole pieces. Further prior art is known from KR 10 2004 0 004 879 A, ​​US 2005 / 0 254 289 A1, US 2014 / 0 191 362 A1, US 2018 / 0 034 369 A1, US 5 548 265 A, US 2013 / 0 106 552 A1, US 2016 / 0 149 122 A1, JP H06-96 423 A and US 8 102 236 B1.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood through the following detailed description, with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements may not be drawn to scale. The dimensions of the various features may be arbitrarily enlarged or reduced for the clarity of the discussion. The Fig. Figures 1 to 7, 8A, 8B and 9 to 14 illustrate cross-sectional views of intermediate stages in the formation of an inductor in accordance with some embodiments. Fig. Figure 15 illustrates another cross-sectional view of an inductor in accordance with some embodiments. Fig. Figure 16 illustrates a cross-sectional view of a package component showing a metal bump in accordance with some embodiments. Fig. Figure 17 illustrates a top view of an inductor in accordance with some embodiments. The Fig. 18 and Fig. Figure 19 illustrates the absorption of light-sensitive materials as a function of wavelengths in accordance with some embodiments. Fig. Figure 20 illustrates a process flow for forming an inductor in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The formation of a first feature over or on a second feature in the following description may, for example, include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or reference letters in the various examples. This repetition is intended for the sake of simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatial reference terms, such as "below," "under," "lower," "above," "above," and the like, can be used here to facilitate description and to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. The purpose of these spatial reference terms is to encompass different orientations of the component during use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial reference descriptors used here are interpreted accordingly.

[0007] An inductor and the method for forming it in a die / wafer are provided in accordance with some embodiments. The intermediate steps in forming the inductor are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numerals are used throughout to denote the same elements. In accordance with some embodiments of the present disclosure, the inductor comprises a dielectric material that separates a magnetic material from conductive tracks within the inductor. The dielectric material comprises a negative photosensitive material that is structured using a double exposure process followed by a single development process, and the sidewalls of the dielectric material have a tapered profile.

[0008] The Fig. Figures 1 to 7, 8A, 8B, and 9 to 14 illustrate cross-sectional views of intermediate stages in the formation of an inductor in a component wafer (and die) in accordance with some embodiments of the present disclosure. The corresponding processes are also schematically shown in process flow 200, as in Fig. 20 shown, reproduced.

[0009] Fig. Figure 1 illustrates a cross-sectional view of a package component 20. The package component 20 comprises a plurality of package components 22. According to some embodiments of the present disclosure, the package component 20 is a component wafer comprising integrated circuit components 26, which may include active components and possibly passive components. According to alternative embodiments of the present disclosure, the package component 20 is an interposer wafer that does not include active components and may or may not include passive components. According to still alternative embodiments of the present disclosure, the package component 20 is a package substrate tape comprising a plurality of package substrates. The package component 20 may also be a reconstructed wafer containing a plurality of packages.In the following discussion, a component wafer is discussed as an exemplary package component 20, while the embodiments of the present disclosure can also be applied to interposer wafers, package substrates, packages, reconstructed wafers, etc.

[0010] In accordance with some embodiments of the present disclosure, the package component 20 has a semiconductor substrate 24 and features formed on an upper surface of the semiconductor substrate 24. The semiconductor substrate 24 can be formed from crystalline silicon, crystalline germanium, silicon-germanium, or a III-V compound semiconductor such as GaN, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 24 can also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) can be formed in the semiconductor substrate 24 to isolate the active regions in the semiconductor substrate 24. Although it is in Fig. Not shown in Figure 1, vias (occasionally called silicon vias or semiconductor vias) can be formed to extend into the semiconductor substrate 24, the vias being used to electrically interconnect the features on opposite sides of the package component 20.

[0011] In accordance with some embodiments of the present disclosure, the package component 20 includes integrated circuit components 26, which may have sections formed on the upper surface of the semiconductor substrate 24. The integrated circuit components 26 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like, in accordance with some embodiments. The details of the integrated circuit components 26 are not illustrated herein. In accordance with alternative embodiments, the package component 20 is used to form interposers, and the substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0012] The interlayer dielectric (ILD) 28 is formed over the semiconductor substrate 24 and fills the space between the gate stacks of transistors (not shown) in integrated circuit devices 26. In accordance with some embodiments, the ILD 28 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethyl orthosilicate (TEOS) oxide, or the like.In accordance with some embodiments of the present disclosure, the ILD 28 is formed using a deposition process such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), spin-on coating, flowable chemical vapor deposition (FCVD), or the like.

[0013] Contact plugs (not shown) are formed in the ILD 28 and used to electrically connect integrated circuit components 26 to overlying metal traces and vias. In accordance with some embodiments of the present disclosure, the contact plugs are formed from a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the contact plugs may include forming contact openings in the ILD 28, filling the contact openings with conductive material(s), and performing a planarization process (such as chemical mechanical polishing - CMP) or a mechanical grinding process to match the top surfaces of the contact plugs to the top surface of the ILD 28.

[0014] The ILD 28 and the contact plugs can be part of an interconnection structure 32. The interconnection structure 32 further comprises metal conductors 34 and vias 36 formed in dielectric layers 38 (also called inter-metal dielectric layers – IMDs). The metal conductors at the same level are collectively referred to below as a metal layer. In accordance with some embodiments of the present disclosure, the interconnection structure 32 comprises a plurality of metal layers, including metal conductors 34 interconnected by vias 36. The metal conductors 34 and vias 36 can be formed of copper or copper alloys, and they can also be formed of other metals. In accordance with some embodiments of the present disclosure, dielectric layers 38 are formed of low-θ dielectric materials.The dielectric constants (θ values) of the dielectric low-θ materials can, for example, be lower than 3.0. The dielectric layers 38 can also comprise dielectric carbon-containing low-θ material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. In accordance with some embodiments of the present disclosure, the formation of the dielectric layers 38 involves the deposition of a pore-forming dielectric material and then performing a curing process to drive off the pore-forming agent, such that the remaining dielectric layer 38 is porous.

[0015] The formation of the metal conductors 34 and vias 36 can involve single-damascene and / or dual-damascene processes. In a single-damascene process, a trench is first formed in one of the dielectric layers 38, followed by filling the trench with a conductive material. Planarization, such as a CMP process, is then performed to remove excess portions of the conductive material that are higher than the top surface of the corresponding dielectric layer 38, leaving a metal conductor in the trench. In a dual-damascene process, both a trench and a via opening are formed in one of the dielectric layers 38, with the via opening located below and connected to the trench. The conductive material is then filled into the trench and the via opening to form a metal conductor and a via, respectively.The conductive material may include a diffusion barrier layer and a copper-containing metallic material above the diffusion barrier layer. The diffusion barrier layer may consist of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0016] The interconnection structure 32 features upper conductive (metal) features, such as metal conductors, metal pads, or vias, in an upper dielectric layer of the dielectric layers 38. In some embodiments, the upper dielectric layer is formed from a low-θ dielectric material similar to the material of the lower dielectric layers 38. In other embodiments, the upper dielectric layer consists of a non-low-θ dielectric material, which may be silicon nitride, undoped silicate glass (USG), silicon oxide, or the like. The upper dielectric layer may also have a multilayer structure, for example, comprising two USG layers with a silicon nitride layer in between. The upper dielectric layer is sometimes referred to as a passivation layer.

[0017] The passivation layer 44 is formed over the interconnection structure 32. The passivation layer 44 can be a single layer or a composite layer and can be formed from a non-porous material. In accordance with some embodiments of the present disclosure, the passivation layer 44 is a composite layer comprising a silicon oxide layer and a silicon nitride layer over the silicon oxide layer.

[0018] Fig. Figure 1 also illustrates the formation of the dielectric layer 48. In accordance with some embodiments of the present disclosure, the dielectric layer 48 is formed from a polymer, such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. The dielectric layer 48 is therefore occasionally called a first polymer layer (or polymer-1), while it can also be formed from other materials. In accordance with other embodiments, the dielectric layer 48 is formed from an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. The dielectric layer 48 can be formed from a photosensitive material (such as a photoresist), which can be a negative photoresist or a positive photoresist. The formation and structuring of the dielectric layer 48 can include an exposure process and a development process.

[0019] Fig. Figure 1 further illustrates the formation of stacked layers 50, 52, 54 and 56 over the dielectric layer 48. The respective process is designated as process 202 in the process sequence as shown in Fig. Figure 20 illustrates this. An adhesive layer 50 is formed over the dielectric layer 48. In some embodiments, the adhesive layer is formed from titanium, which exhibits good adhesion to the dielectric layer 48. The adhesive layer 50 can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. The dielectric layer 52 is formed over the adhesive layer 50. In some embodiments, the dielectric layer 52 is formed from silicon nitride, silicon oxynitride, or the like. The dielectric layer 52 can be formed using atomic layer deposition (ALD), CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like.

[0020] An etch stop layer 54 is formed over the dielectric layer 52. In some embodiments, the etch stop layer 54 is formed by depositing a metal layer, such as a cobalt layer, and then performing an oxidation process, such as a plasma oxidation process, a heat oxidation process, or the like, on the metal layer, so that the metal layer is converted into a metal oxide layer, such as a cobalt oxide layer. The etch stop layer 54 can also be formed from a tantalum oxide layer or a titanium oxide layer, which are formed by depositing the corresponding metal layer and then oxidizing the metal layer.

[0021] Magnetic layers 56 are formed over the etch stop layer 54. In some embodiments, the magnetic layers 56 comprise a magnetic foil layer 56A, a magnetic foil layer 56B over magnetic foil 56A, and a magnetic foil layer 56C over magnetic foil 56B, wherein the materials of the magnetic foils 56A, 56B, and 56C are formed from different materials. The magnetic foil layers 56 may also comprise other layers and materials, such as a boron layer. In some embodiments of the present disclosure, there is a single composite layer comprising a layer 56A, a layer 56B, and a layer 56C. In other embodiments of the present disclosure, there is a plurality of composite layers, each comprising a layer 56A, a layer 56B, and a layer 56C.Layers 56A, 56B, and 56C are therefore formed alternately. The total thickness T1 of the magnetic layers 56 can be in the range between 2 µm and 10 micrometers, according to some embodiments. The adhesive layer 50, the dielectric layer 52, the etch stop layer 54, and the magnetic layers 56 can be deposited as full-surface layers extending through the package component 20.

[0022] With reference to Fig. 2. An etching mask 58 is formed. The etching mask 58 can be a photoresist layer. The top view of the etching mask 58 can have an elongated rectangular shape. The stacked layers, which include an adhesive layer 50, the dielectric layer 52, the etch stop layer 54, and the magnetic layers 56, are then etched with the etch stop on the dielectric layer 48. The respective process is designated as process 204 in the process sequence, as described in Fig. 20 shows, illustrating. Etching the magnetic layers 56 results in magnetic layers 56', as shown in Fig. Figure 3 shows that, in accordance with some embodiments of the present disclosure, the magnetic layers 56 are etched using reactive ion beam etching (IBE). The etching can be carried out using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), or the like. The sidewalls of the magnetic layers 56' can be chamfered, which is achieved by adjusting the parameter settings of the etching process. During the etching of the magnetic layers 56, the etch stop layer 54 is used to stop the etching process.

[0023] After etching the magnetic layers 56, the etch stop layer 54 is etched to form the etch stop layer 54', followed by etching the dielectric layer 52 and the adhesive layer 50 to form a dielectric layer 52' ​​and an adhesive layer 50', respectively. In accordance with some embodiments, the tilt angle α1 of the stacked layers, including the magnetic layer 56' and possibly the adhesive layer 50', the dielectric layer 52', and the etch stop layer 54', is in the range between about 40 degrees and about 60 degrees. After etching, the etch mask 58 ( Fig. 2) removed. In the description, the adhesive layer 50', the dielectric layer 52', the etch stop layer 54' and the magnetic layers 56' are consistently referred to as stacked layers 57 in combination.

[0024] Following, with reference to Fig. 4, a dielectric layer 60 is formed. The respective process is designated as process 206 in the process sequence, as in Fig. Figure 20 illustrates this. In accordance with some embodiments of the present disclosure, the formation of the dielectric layer 60 comprises a full-surface deposition process followed by a structuring process. The remaining sections of the dielectric layer 60 have two sections, which may be elongated bands parallel to each other. The cross-sectional shape of the dielectric layer 60 is obtained from a plane orthogonal to the longitudinal direction of the bands. The dielectric layer 60 is formed from a dielectric material, which may comprise silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0025] The Fig. Figures 5 to 7 illustrate the formation of conductive pathways. The respective process is designated as process 208 in the process flow, as shown in Fig. 20 shown, illustrated. Fig. Figure 5 illustrates the formation of a conductive nucleus layer 62, which is located on the structure that is in Fig. Figure 4 shows how the conductive seed layer 62 is deposited. The conductive seed layer 62 can be a metal seed layer. In some embodiments, the conductive seed layer 62 is a composite layer comprising a plurality of layers. For example, the conductive seed layer 62 can have a bottom layer and an top layer, wherein the bottom layer can be a titanium layer and the materials of the top layer can be copper or a copper alloy. In alternative embodiments, the conductive seed layer 62 is a single layer, which can be, for example, a copper layer. The conductive seed layer 62 can be formed using physical vapor deposition (PVD), while other methods can also be used.

[0026] Fig. Figure 5 further illustrates the formation of an electroplating mask 64. In accordance with some embodiments, the electroplating mask 64 consists of a photoresist. The electroplating mask 64 is structured to form openings 66 through which some sections of the conductive seed layer 62 are exposed. The remaining sections of the dielectric layer 60 may also have some sections directly below the openings 66, and some other sections extending laterally over the edges of the respective openings 66 above them. A plating process is then carried out to form conductive tracks 68, as shown in Figure 5. Fig. 6 shown, to form. The conductive tracks 68 can be formed from a metal or a metal alloy, such as copper or a copper alloy or the like.

[0027] After the electroplating process, the electroplating mask 64 is removed by a stripping process. If the electroplating mask 64 is formed from a photoresist, for example, it can be ashed using oxygen. The sections of conductive nucleation 62 covered by the electroplating mask 64 are then removed. Subsequently, the exposed sections of conductive nucleation 62 previously covered by the electroplating mask 64 are removed by etching, while the sections of conductive nucleation 62 covered by conductive traces 68 are not removed. The resulting structure is in Fig. Figure 7 is shown. In the course of the description, the remaining sections of the conducting nucleus layer 62 are considered as parts of the conducting pathways 68.

[0028] The Fig. Figures 8A (or 8B) and 9 illustrate the coating and a double exposure process of the photosensitive coating 70, which is formed from a photosensitive material. With reference to Fig. In step 8A, a photosensitive coating 70 is applied, for example, by spin-on coating. The respective process is designated as process 210 in the process flow, as shown in Fig. Figure 20 illustrates this. In accordance with some embodiments of the present disclosure, the photosensitive coating 70 is a negative photoresist. The photosensitive coating 70 can, for example, be a negative polyimide. Other negative photoresists, such as photosensitive benzocyclobutene (BCB) or photosensitive polybenzoxazole (PBO), which exhibit a low shrinkage rate during subsequent curing processes, can also be used. The photosensitive coating 70 is occasionally referred to as a second polymer layer (or polymer-2). The upper surface of the photosensitive coating 70 is higher than the upper surfaces of the conductive tracks 68. For example, the thickness T2 of the section of the photosensitive coating 70 directly above the conductive tracks 68 can, in accordance with some embodiments, be in the range between about 4 µm and about 8 µm.The strength T2 is selected such that the strength T3 in the final structure, which is in . Fig. Figure 14 shows that the dimensions can fall within the range of approximately 3 µm to approximately 6 micrometers, as discussed in the following paragraphs.

[0029] With further reference to Fig. In embodiment 8A, a lithography mask 72 is placed over the package component 20. The lithography mask 72 has opaque sections 72A for blocking light and transparent sections 72B that allow light to pass through. In accordance with some embodiments, two of the transparent sections 72B have edges that are flush (or substantially flush) with the respective edges of conductive traces 68, the offset (if any) of the corresponding edges being less than about 1 µm. The offset, if any, may be less than about 20 percent of the width W1 of the conductive traces 68. One of the opaque sections 72A is vertically aligned with the section of photosensitive coating 70 between conductive traces 68. Exposure is performed using a light beam 74 such that the sections of photosensitive coating 70 are exposed directly beneath the transparent sections 72B.The respective process is designated as process 212 in the process flow, as shown in . Fig. Figure 20 shows and illustrates this. As a result, the sections of light-sensitive coating 70 are cross-linked.

[0030] Fig. Figure 8B illustrates the exposure of the photosensitive coating 70 in accordance with some other embodiments. A lithography mask 72' is placed over the package component 20. The lithography mask 72' has opaque sections 72A' for blocking light and transparent sections 72B' that allow light to pass through. In accordance with some embodiments, the transparent section 72B' covers conductive traces 68 and the sections of photosensitive coating 70 between conductive traces 68. The opposite edges of the transparent section 72B' are also flush with the respective edges of the conductive traces 68 (or substantially flush, such that the offset is less than about 1 nm). The offset, if any, is also less than about 20 percent of the width W1 of the conductive traces 68.An exposure is carried out using the light beam 74 such that the sections of the photosensitive coating 70 that lie directly above the conductive tracks 68 and the section of photosensitive coating 70 between conductive tracks 68 are exposed. As a result, the sections of photosensitive coating 70 are cross-linked.

[0031] The exposure process, as in Fig. 8A or Fig. Shown in 8B, this is called the first exposure process of a double exposure process. Fig. Figure 9 illustrates a second exposure process of the double exposure process. The respective process is designated as process 214 in the process flow, as shown in Fig. Figure 20 illustrates this. It is understood that the order of the first and second exposure processes can be reversed. In the second exposure process, a lithography mask 76 is placed over the package component 20. The lithography mask 76 has opaque sections 76A and a transparent section 76B. In accordance with some embodiments, the transparent section 76B covers conductive tracks 68 and the sections of photosensitive coating between conductive tracks 68. Opaque sections 76A further extend laterally over the respective outer edges of the conductive tracks 68 by a lateral distance D1. In accordance with some embodiments of the present disclosure, the lateral distance D1 is greater than about 10 µm and can be in the range between about 10 µm and about 30 µm.The lateral distance D1 is equal to or greater than the height difference ΔH between the upper surfaces of the conductive tracks 68 and the upper surface of the magnetic layer 56'. Exposure is carried out using a light beam 78 such that the sections of photosensitive coating 70 directly beneath the transparent section 76B are exposed. As a result, the sections of photosensitive coating 70 are cross-linked.

[0032] It is understood that the structures of the lithography masks 72 ( Fig. 8A), Fig. 72' ( Fig. 8B) and Fig. 76 ( Fig. 9) are designed for exposing the negative photosensitive layer 70. In accordance with other embodiments, a positive photosensitive coating can be used, and in order to expose the positive photosensitive coating, the structures of the opaque and transparent sections of the corresponding lithography masks can be reversed compared to the respective lithography masks 72, 72' and 76.

[0033] By using the double exposure process, a continuous section of the photosensitive coating 70 is cross-linked. The cross-linked section is in Fig. 10 shown, and the unconnected section and subconnected sections are in Fig. 10 not shown. The design of the profile of the networked section is briefly described as follows with reference to the Fig. 18 and Fig. 19 discussed.

[0034] Fig. Figure 18 illustrates the normalized absorption rate of light energy in the photosensitive coating 70 as a function of the wavelengths of the light beams used for exposure. The most likely wavelengths for broadband UV lithography lie in a range between 300 nm and 450 nanometers, which includes the characteristic wavelengths of high-pressure mercury lamps at 436 nm (g-line), 405 nm (h-line), and 365 nm (i-line). As shown in Fig. As shown in Figure 8, the i-line has the highest absorption rate, and the absorption rate generally decreases with increasing wavelength. According to Beer-Lambert's law, the strength of an electromagnetic wave within a material decreases exponentially from the surface into the material.

[0035] Fig. Figure 19 illustrates the total absorbed energy as a function of wavelengths, indicating the efficiency of light energy absorption when light beams of different wavelengths are used. The amount of absorbed energy also indicates the amount of cross-linking generated in the exposed photosensitive coating; the more energy is absorbed, the more cross-linking is generated, and vice versa. Fig. Equation 19 also states that the penetrating power of a light beam increases with increasing wavelength and decreases with decreasing wavelength. Consequently, to ensure that the sections of photosensitive coating 70 directly over conductive tracks 68 are well cross-linked (so that these sections are not removed in a subsequent development process), the first exposure process ( Fig. 8A or Fig. 8B) the light beam 74, which has a wavelength between about 350 nm and about 450 nm, and the light can have any one, two of or all three of the i-line, g-line and h-line wavelengths ( Fig. 18) If the wavelength is longer than 450 nm, the cross-linked section of the photosensitive coating 70 directly above the conductive tracks 68 is too thin. If the wavelength is shorter than 350 nm, the cross-linked section of the photosensitive coating 70 directly above the conductive tracks 68 is too thick. The first exposure serves primarily to define the thickness of the cross-linked section of the photosensitive coating 70.

[0036] The second exposure (of Fig. 9) mainly serves to define the profile of the cross-linked section of the photosensitive coating 70, so that the beveled edges, as in Fig. 10 shown, can be generated. The second exposure process uses light beam 78 ( Fig. 9), which has a wavelength between approximately 390 nm and approximately 450 nm, and the light may have a spectrum that mainly contains g-line and h-line wavelengths, but not the i-line. If the wavelength is longer than 450 nm, the beveled edges would be too steeply beveled. If the wavelength is shorter than 390 nm, the beveled edges would be too vertical.

[0037] Each of the first light beam 74 and the second light beam 78 can be a laser beam with a single wavelength falling within the aforementioned range. Each of the first light beam 74 and the second light beam 78 can also have wavelengths spanning a range within the aforementioned range. Therefore, the corresponding light beam 74 or 78 can exhibit multiple wavelengths within the aforementioned range.

[0038] After the first and second exposure processes, as in Fig. As shown in Figures 8A (or 8B) and 9, the light-exposed photosensitive coating 70 is developed. The respective process is designated as process 216 in the process flow, as shown in Fig. Figure 20 illustrates this. The uncrosslinked and undercrosslinked sections are removed, and the suitably crosslinked sections remain. The resulting photosensitive coating 70 is in Fig. 10 illustrated. Fig. Figure 10 shows that the outer sections of the photosensitive coating 70 on the outer sides of conductive tracks 68 have beveled sidewalls 70'. The tilt angle α2 of the beveled sidewalls 70' is less than about 45 degrees and can be in the range between about 20 degrees and about 50 degrees. The upper surface of the photosensitive coating 70 has two substantially planar sections directly above conductive tracks 68 and a recessed section between the two substantially planar sections.

[0039] Fig. Figure 11 illustrates the light-sensitive coating 70 after a curing process has been carried out. The respective process is designated as process 218 in the process flow, as shown in Fig. Figure 20 illustrates this. In accordance with some embodiments, the curing process is a heat curing process carried out at a temperature in the range of about 180 °C to about 350 °C. The curing time can be in the range of about 20 minutes to about 240 minutes. As a result of the curing process, the photosensitive coating 70 is completely solidified and shrinks. Furthermore, sections of the photosensitive coating 70 directly over conductive tracks 68 shrink less due to better cross-linking, and the outer sections of the photosensitive coating further away from the conductive tracks 68 shrink more due to poorer cross-linking. As a result, the tilt angle α3 of the beveled sidewalls 70' is reduced to be smaller than an angle α2 ( Fig. 10) In accordance with some embodiments of the present disclosure, the tilt angle α3 is less than about 40 degrees and can be in the range between about 10 degrees and about 40 degrees.

[0040] With a tilt angle α3 of less than approximately 40 degrees, the subsequently deposited magnetic layer formed on the beveled side walls 70' has better coverage than on the otherwise vertical side walls. Conversely, if the tilt angle α3 is greater than 40 degrees, the subsequently formed magnetic layer may not have acceptable coverage. A small tilt angle α3 results in less stress being exerted on the cured photosensitive coating 70. On the other hand, the tilt angle α3 cannot be too small, for example, less than approximately 35 degrees. Otherwise, the side walls 70' may subsequently extend towards the side walls of (instead of over) the conductive tracks 68. In accordance with some embodiments, to ensure that the tilt angle α3 falls within the desired range, the light spectrum of the light rays 74 and 78 ( Fig. 8A, Fig. 8B and Fig. 9), the exposure energy and the structures of the lithography masks 72, 72' and 76 are set.

[0041] Fig. Figure 12 illustrates the separation of the stacked layers 82. The respective process is designated as process 220 in the process flow described in Fig. Figure 20 illustrates this. In accordance with some embodiments of the present disclosure, the stacked layers 82 comprise the adhesive layer 82A, the dielectric layer 82B, an etch stop layer (not shown) over the dielectric layer 82B, and magnetic layers 82C over the etch stop layer. The candidate materials and forming methods for forming the adhesive layer 82A, the dielectric layer 82B, the etch stop layer, and the magnetic layers 82C may be substantially the same as those, respectively, of the adhesive layer 50, the dielectric layer 52, the etch stop layer 54, and the magnetic layers 56. Fig. 1) The details are therefore not repeated here. The coverage and conformity of the stacked layers 82 are improved due to the well-controlled chamfered edges of the photosensitive coating 70.

[0042] Fig. Figure 13 illustrates the structuring of the stacked layer 82, which is achieved by etching, consequently the formation of stacked layers 82' comprising an adhesive layer 82A', the dielectric layer 82B' and etch stop layer, as well as magnetic layers 82C'. The respective process is designated as process 222 in the process sequence, as shown in Fig. Figure 20 illustrates this. The magnetic layers 82C' are magnetically coupled to the magnetic layers 56' by the dielectric layer 82B', and the magnetic layers 82C' and the magnetic layers 56' together form a shell that can improve the inductance of the resulting inductor.

[0043] Then, as in Fig. As shown in Figure 14, the dielectric layer 84 is formed. The respective process is referred to as process 224 in the process sequence, as shown in Fig. Figure 20 illustrates this. In accordance with some embodiments of the present disclosure, the dielectric layer 84 is formed from a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. The dielectric layer 84 is therefore sometimes called a third polymer layer (or polymer-3). The conductive tracks 68 and the magnetic shell formed from the magnetic layers 56' and 82' in combination constitute the inductor 86. The inductance of the inductor 86 is enhanced due to the interaction of the conductive tracks 68 and the magnetic shell 56' / 82'. In subsequent processes, electrical conductors (such as solder regions 94 and under-bump metallurgies 92) can be formed in Fig. 16) are formed, and the package components 20 can be separated into individual dies 22.

[0044] With renewed reference to Fig. 14. The sections of the photosensitive coating 70 directly above the conductive tracks 68 have a thickness T3. The thickness T3 cannot be too large. Otherwise, the resulting inductance of the inductor 86 will be too small. The thickness T3 cannot be too small. Otherwise, the resulting inductance of the inductor 86 will be too large, and the reliability of the inductor 86 will be impaired. In accordance with some embodiments of the present disclosure, the thickness T3 is in the range between about 3 µm and about 6 µm.

[0045] Fig. Figure 15 illustrates a cross-section of the reference plane 15-15, as shown in Fig. 14 shown. Fig. Figure 15 illustrates the longitudinal direction of the conductive pathways. Figure 68. Fig. 14 and Fig. 15 in combination show the shape of the shell formed from the magnetic layers 56' and 82'.

[0046] Fig. Figure 16 illustrates an area of ​​the package component 22 in which no inductor is formed. The combination of the Fig. 14 and Fig. 16 therefore shows where the inductor 86 is located in the package component 22 with respect to other features, such as solder areas, metal pads and dielectric layers. Fig. Figure 16 illustrates the metal pad 88, which can be an aluminum pad, formed in the passivation layer 44 and beneath the dielectric layer 48 (polymer-1). The conductive track 90, also called a post-passivation interconnect (PPI), extends into the dielectric layer 48. A section of the conductive track 90 is formed above the dielectric layer 48. The dielectric layer 84 is formed above the dielectric layer 48. The inductor 86 is inserted between the dielectric layers 48 and 84 in another region, which is shown in Fig. Figure 14 shows that the UBM 92 is formed to extend into the dielectric layer 84. The electrical connector 96 is formed on the UBM 92. The electrical connector 96 can be a solder area, a metal column, a metal column with an additional solder layer overlying it, or the like.

[0047] Fig. Figure 17 illustrates a top view of the inductor 86, wherein Fig. 14 a cross-section of the reference plane 14-14 in Fig. 17 illustrates, and Fig. 15 a cross-section of the reference plane 15-15 in Fig. Figure 17 illustrates this. In accordance with some embodiments, the current I1 can flow into a first conductive path 86, be guided into underlying layers, and flow into a second conductive path 86 as current I1'. The inductance of the inductor 86 can be improved by the magnetic shell 82' / 56'.

[0048] The embodiments of the present disclosure exhibit several advantageous features. Co-Zr-Ta foils have demonstrated lower resistive losses and lower permeability while maintaining higher saturation magnetization. The present disclosure discloses a method and the corresponding inductor comprising a magnetic shell that may be formed from Co-Zr-Ta foils. The profile of the dielectric layer in the inductor is structured by a double exposure process followed by a single development process, such that the tilt angle of the dielectric layer's sidewalls is within a desirable range. This improves the coverage and alignment of the magnetic layers over the dielectric layer. The beveled sidewalls of the dielectric layer also reduce stress in the resulting structure.Experimental results have shown that if a dual-sublayer dielectric layer is applied using two coatings, two exposure processes, and two development processes, the profile of the resulting dual-sublayer dielectric layer is incapable of achieving the small tilt angle α3. The stress on the component die containing the dual-sublayer dielectric layer is also greater, and the respective wafer exhibits more pronounced distortion, which can be around 600 µm. By using the embodiments of the present disclosure, the wafer distortion is reduced to approximately 400 µm.

Claims

[1] Integrated circuit structure comprising: a first magnetic layer (56'); a first conductive line (68) and a second conductive line (68) over the first magnetic layer (56') and parallel to each other; and a dielectric layer (70) comprising: first sections directly above the first conductive line (68); a second section between the first conductive line (68) and the second conductive line (68); and third sections on opposite sides of a combined region, the combined region comprising the first conductive line (68), the second conductive line (68), and the second section of the dielectric layer (70), wherein sidewalls (70') of the third sections are sloped at bevel angles less than about 40 degrees, and a stacked layer (82') over and in contact with the dielectric layer (70), the stacked layer (82') comprising an adhesion layer (82A'), a dielectric layer (82B'), an etch stop layer, and a magnetic layer (82C'). [2] The integrated circuit structure of claim 1, wherein the dielectric layer (70) is formed of a negative photoresist. [3] The integrated circuit structure of claim 1 or 2, wherein the first portions of the dielectric layer (70) have a thickness in a range between about 3 µm and about 6 µm. [4] Integrated circuit structure according to one of the preceding claims, wherein the first magnetic layer (56') is formed from cobalt, zirconium and tantalum. [5] The integrated circuit structure of any preceding claim, wherein the dielectric layer (70) is formed of a homogeneous material with no distinguishable interface within the dielectric layer (70). [6] The integrated circuit structure of any preceding claim, wherein the dielectric layer is a photosensitive coating (70). [7] The integrated circuit structure of claim 6, wherein the first conductive line (68) and the second conductive line (68) are parallel to each other, and wherein the second conductive line (68) is coated with the photosensitive coating (70). [8] Integrated circuit structure according to one of the preceding claims, wherein the first magnetic layer (56'), the first conductive line (68) and the second magnetic layer (82C') form parts of an inductor. [9] Integrated circuit structure according to one of the preceding claims, wherein the first magnetic layer (56') comprises: a first magnetic film (56A), a second magnetic film (56B) over the first magnetic film (56A) and a third magnetic film (56C) over the second magnetic film (56B), wherein the first magnetic film (56A), the second magnetic film (56B) and the third magnetic film (56C) are formed of different materials. [10] Integrated circuit structure comprising: a magnetic layer (56') having a first inclined sidewall; a first conductive line (68) and a second conductive line (68) over the magnetic layer (56'); a photoresist layer (70), wherein the first conductive line (68) and the second conductive line (68) lie in the photoresist layer (70), the photoresist layer (70) having second inclined sidewalls (70') on opposite sides of a combined region comprising the first conductive line (68) and the second conductive line (68), the second inclined sidewalls having inclination angles (α3) that are less than about 40°; and a stacked layer (82) over and in contact with the photoresist layer (70), the stacked layer (82') comprising an adhesion layer (82A'), a dielectric layer (82B'), an etch stop layer, and a magnetic layer (82C'). [11] The integrated circuit structure of claim 10, wherein the stacked layer (82) forms a shell over the photoresist layer. [12] Integrated circuit structure according to claim 10 or 11, wherein the magnetic layer (56') forms part of a further stacked layer (57). [13] The integrated circuit structure of claim 12, wherein the further stacked layer (57) comprises an adhesion layer (50'), a dielectric layer (52'), an etch stop layer (54') and the magnetic layer (56'). [14] The integrated circuit structure of claim 11 or 12, wherein the further stacked layer (57) has inclined sidewalls.

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