METHOD FOR OVERLAPKING MEMORY ACCESSES

Abstract

Improved methods and systems for accessing memory in a computer are disclosed. In one embodiment, the actual and complementary parts of a differential write clock signal are used as two asymmetrical clock signals for independently controlling different memory chips in a memory system. In a memory system with two memory chips, for example, one memory chip is configured to use the actual write clock signal, and the other memory chip is configured to use the complementary write clock signal. Using the differential write clock signal as two asymmetrical clock signals allows write and read operations to overlap across multiple memory chips, which reduces the time required to access the memory.Accordingly, the disclosed methods and systems provide a more efficient storage system that can be used to improve the operation of a computer.

Description

TECHNICAL AREA

[0001] This application is generally directed towards storage systems, and in particular towards increasing the performance of storage systems by reducing the access time when switching between different memory chips of a storage system. BACKGROUND

[0002] Storage systems often include multiple memory chips connected to and controlled by a single memory controller. Some storage systems are called memory packages, which contain memory chips with multiple memory banks, where each memory bank of a memory chip shares a common input / output bus. A single memory controller can be used to manage the memory operations of the multiple memory chips within a memory package.

[0003] Improvements in the processing power and energy efficiency of storage systems are driven by the development of various computer applications. Storage systems are key to new data-intensive applications such as virtual reality (VR) and augmented reality (AR), cloud computing, and artificial intelligence. These and other applications demand improvements in memory access, including higher bandwidth, faster speeds, and, of course, lower power consumption. US Patent 6,198,688 B1 discloses a method for clocking synchronous memory elements. SUMMARY

[0004] In one aspect, the invention provides a method for operating a memory with multiple memory chips according to claim 1. In one embodiment, the method includes: (1) using a differential write clock signal as two asymmetric clock signals, which are a first write clock signal and a second write clock signal, (2) controlling read and write operations of a first memory chip of the memory using the first write clock signal, and (3) controlling, independently of the control of the first memory chip, read and write operations of a second memory chip of the memory using the second write clock signal.

[0005] In a further aspect, an integrated circuit according to claim 18 is disclosed. In one embodiment, the integrated circuit comprises: (1) a dynamic random access memory with double data rate (DDR) comprising a first memory bank and a second memory bank that share a bus for instructions and other buses for transferring data, and (2) a memory control device configured to independently control read and write operations of the first memory bank and the second memory bank using a proper signal and a complementary signal of a differential write clock signal as asymmetrical clock signals. SHORT DESCRIPTION

[0006] The following description, in conjunction with the accompanying drawings, refers to the following: Fig. 1 A block diagram of an example of a storage system is illustrated, which is configured to operate in accordance with the principles of the invention; Fig. Two timing diagrams illustrate the buses of the storage system of Fig. 1 corresponds to switching between accessing the different memory chips of the storage system; Fig. 3 illustrates a flowchart of an exemplary method 300 for operating a storage system, carried out in accordance with the principles of the invention; and Fig. 4 A block diagram of an example of an integrated circuit (IC) as disclosed herein is illustrated, which may also be configured to use a differential write clock (WCK) as asymmetric write clock signals. DETAILED DESCRIPTION

[0007] In addition to improvements in bandwidth, speed, and power consumption, memory systems with a smaller footprint are also desirable. One way to achieve a smaller footprint is to reduce the number of buses or traces required and minimize the number of pins. However, sharing buses and pins can decrease the access speed between different memory chips when switching between them. This can occur because each memory chip has a separate clock input that must be synchronized before reading from or writing to the chip.

[0008] For example, dynamic random access memory (DRAM) is a type of memory used in the various memory systems of the applications mentioned above. DRAM memory systems can include memory banks and can be one of the various generations of double data rate (DDR) DRAMs, including low-power DDR (LPDDR) DRAMs. A memory bank is a set of DRAM chips connected to and controlled by the same memory controller, and they share data pins.

[0009] An interface protocol is typically used for the memory banks to manage the switching between read and write operations on the various DRAM chips. A synchronization operation is an example of an interface protocol that involves sending a write clock postamble to a first DRAM bank at the end of its write clock signal and then sending a write clock preamble to a second DRAM bank to activate the write clock signal.

[0010] An alternative to sending the preamble after the postamble has finished is to perform a synchronization operation on both DRAM banks simultaneously. However, this requires each DRAM bank to keep its receiver and internal clock active for the duration of the write clock signal during an idle state, resulting in increased power consumption for that memory bank. Conversely, if the preamble and postamble of the write clock do not overlap for each DRAM bank, the bank turnover time increases, reducing system performance or increasing system power consumption.

[0011] Accordingly, the invention provides a method for accessing memory chips of a memory system, such as DRAM banks of a memory package, which reduces the access switching time required when switching between the different memory chips. The access switching time is the number of cycles between a read or write data burst for a first memory chip and a read or write data burst for a second memory chip. For memory banks, the access switching time is the bank turnaround time or rank turnaround time, also known in the industry as bank-to-bank turnaround time or rank-to-rank turnaround time. In addition to reducing the access switching time, the disclosed method and system also consume less energy than would be the case if the receiver and the clocking for the write clock signal were continuously active.Instead, the write clock signal for a memory chip can be activated only when a read or write operation is about to be performed on the memory chip. This reduces the power and / or current consumption required by the storage system.

[0012] The disclosed method advantageously utilizes the actual signal, or useful signal, and its complementary signal, or complement, of a differential write clock signal as asymmetrical clock signals, each used independently by different memory chips. Considering a memory bank with two DRAM banks, one DRAM bank is configured to use the useful write clock signal, and the other DRAM bank is configured to use the complementary write clock signal of a differential signal in an asymmetrical, or single-ended, operation. Using the differential write clock signal as asymmetrical clock signals allows for the overlap of write clock signal operations across multiple banks. For example, a synchronization instruction, or sync instruction, of a synchronization operation can be sent to one DRAM bank while a memory operation, i.e.,a read or write operation is performed on a different DRAM bank.

[0013] The invention provides an improvement in memory access, optimizing chip-to-chip switching (e.g., bank-to-bank switching). The disclosed configurations and operating procedures of a memory system provide improvements through more efficient use of memory buses. Further improvements also result from an increase in performance (memory accesses) per watt of power consumed.

[0014] Now, referring to the characters, it illustrates Fig. Figure 1 shows a block diagram of an example of an integrated circuit (IC) 100 constructed in accordance with the principles of the invention. The IC 100 can be used in various devices, such as mobile computing devices. The IC 100 includes a memory controller 110 and a memory system 150 with a first memory chip 160 and a second memory chip 170. The memory controller 110 is configured to retrieve data from the memory system 150 for processing and to send data to the memory system 150 for storage. The memory controller 110 includes a processor 111, a clock generator 112, a write clock controller 114, and a data controller 116.

[0015] The memory control device 110 can be a system-on-a-chip (SoC), such as a Tegra® processor from NVIDIA Corporation in Santa Clara, California. The memory control device 110 can also be another type of electronic component or integrated circuit, such as other components or circuits that lack a central processing unit (CPU) but have memory interfaces. Some examples include integrated circuits such as an application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA).

[0016] The processor 111 controls the operation of the memory control unit 110 and processes the data stored in the memory system 150. The memory control unit 110 can contain multiple processors, such as a CPU and a graphics processing unit (GPU). The clock generator 112 provides an operating clock signal (CK) at a CK pin 120 for operating the memory system 150 and for controlling the first and second memory chips 160 and 170. The operating clock signal is used for all address, instruction, and control input signals for the memory system 150. For example, instruction and address (CA) signals for the memory system 150 are referenced to the operating clock signal. The operating clock signal can be a differential clock signal.

[0017] The write clock control unit 114 controls the write clock signal for reading from and writing to the various memory chips, the first memory chip 160 and the second memory chip 170. A true signal (WCKT) and a complement (WCKC) of the write clock signal are provided at WCKT pin 130 and WCKC pin 135, respectively. The write clock signal can be a higher-frequency clock than the operating clock signal and is used to drive data.

[0018] The data control unit 116 sends data to and receives data from the first memory chip 160 and the second memory chip 170 via data buses connected to 0 to n data pins, represented by data pins 140 and 145 in Fig. 1. The number of data pins can vary, for example, depending on the architecture of the memory controller 110 or another type of memory controller. In some examples, n is eight. A data mask inversion (DMI) signal can also be transmitted with the data. A DMI pin can be used with the data pins.

[0019] The memory controller 110 can include additional pins typically used for communication with a memory system, such as chip select pins, which are used to inform each memory chip when to accept input from a signal line, and a command interface (CA) pin for transmitting an address, acquire commands, write commands, etc. The memory controller 110 can also include additional components typically found in a system-on-a-chip (SoC). These additional components may include a power supply, communication buses, memory, etc.

[0020] As mentioned above, the memory system 150 comprises the first memory chip 160 and the second memory chip 170. In some examples, the first memory chip 160 and the second memory chip 170 may be located in different memory packages. Additionally, the memory control unit 110 may be communicatively coupled to multiple memory packages. The memory system 150 may be a single memory package, such as a DRAM memory package, where the first and second memory chips 160 and 170 may be DRAM banks. In various embodiments, the memory system 150 may be DDR or LPDDR, such as fifth-generation LPDDR.

[0021] The first memory chip 160 and the second memory chip 170 each contain data pins that are connected to the same data buses from the memory controller 110. Data pin 162 and data pin 172 are shown to represent the data pins for each of the memory chips 160 and 170. The first memory chip 160 and the second memory chip 170 also have pins that receive a write clock signal and the operating clock signal. The first memory chip 160 has a WCKT pin 164 that receives the write clock signal (WCKT) from the memory controller 110, and the second memory chip 170 has a WCKC pin 174 that receives the write clock complement signal (WCKC) from the memory controller 110. In another embodiment, the memory chips 160, 170 can also operate in such a way that they receive the write clock signal as a differential clock signal.Thus, depending on the configuration, the 160 and 170 memory chips can be operated using a write clock signal as a differential signal or as two asymmetric signals. The 160 and 170 memory chips may include logic circuits that determine how the write clock signals are to be used when received as a differential pair. Fig. Figure 4 provides an example of such an embodiment. The first memory chip 160 and the second memory chip 170 include CK pins 166 and 176 for receiving the operating clock signal from the memory control unit 110.

[0022] By using the differential write clock signal as asymmetric signals, the access switching time is reduced when switching between memory operations on the two different memory chips 160 and 170. For example, using asymmetric write clock signals prevents bubble cycles resulting from synchronization operations. A bubble cycle is a DQ bus (data bus) cycle in which no data is transferred to or from memory. Instead, the access time can be limited to a delay corresponding to the process edge fluctuations. With asymmetric signals, write clock operations across the different memory chips 160 and 170 can overlap for a shorter access time.

[0023] Furthermore, using the write clock signal as an asymmetric signal can reduce the need for leveling. For example, if memory chips 160 and 170 need to be trimmed separately due to distortion problems in the write clock signal, the same trim setting will not work for both memory chips 160 and 170, and the internal trim setting would have to be changed before sending the write clock signal to memory chips 160 and 170 to ensure the timing requirements are met. However, because the write clock signal is used as an asymmetric signal, the trim can be individually tailored to each of the memory chips 160 and 170, and leveling between them is not required.

[0024] Fig. Figure 2 illustrates timing diagrams 200, corresponding to the buses between the storage control unit 110 and the storage system 100 when the storage system 150 is operated with asymmetrical write clock signals. The waveforms of Fig. Figure 2 illustrates the advantage of using the write clock signal as an asymmetric signal when switching from accessing memory chip 160 to accessing memory chip 170. Some instruction signals, including Chip Select (CS) instructions and address instructions, such as ColumnAddressStrobe (CAS) instructions, are shown in Fig. 2. Not represented by waveforms, but are used when switching, and are mentioned below.

[0025] Before accessing a memory chip, an activation step is performed, which involves sending a signal containing the row address over the instruction bus. A CAS instruction is then sent to the instruction bus, initiating the preamble alignment for the write clock signal and containing a column address with either a read or a write instruction. After alignment, the data is then transferred to the memory chip via the data bus. The same sequence is followed for accessing the next chip. The various instructions can be sent serially over the instruction bus, and since this bus can be shared by at least two memory chips, the instructions are separated to avoid conflicts on the instruction bus.

[0026] Overlapping data from different memory chips on the data bus must also be prevented. This can be achieved through a synchronization operation. As mentioned above, the CAS instruction includes the synchronization operation for the write clock signal. During the synchronization operation, a write clock preamble and a write clock postamble are sent. The memory chip has an internal write clock divider to align an internal write clock with the high-frequency write clock signal. The preamble tells the memory chip's internal divider which clock to use for performing the read or write operation. The preamble can interact with the divider to align phases.

[0027] The preamble can be a multi-cycle pattern that, in an active system, typically does not overlap with either a write clock signal or a write clock postamble. Because of this pattern, the synchronization operation for the write clock signal cannot overlap with a data burst on the data bus, as this involves a full-rate or full-speed switchover. This can be prevented in several ways. One possibility is to enable the write clock receiver / clocking for both memory chips, such as memory chips 160 and 170. However, this increases the power consumption of memory system 150, as the two memory chips 160 and 170 consume additional power for their receiver and add internal clocking to their write clock distribution and dividers.

[0028] Another possibility is to send the complete postamble to a first memory chip, followed by sending the complete preamble to a second memory chip. However, this results in many clock cycles of idle bubbles on the data bus. The waveforms of Fig. Figure 2 illustrates the use of the write clock signal as an asymmetric signal, allowing an overlap of the preamble and postamble for different memory chips in the synchronization clock signal synchronization operation.

[0029] Fig. Figure 2 contains four waveforms: 210 for the operating clock signal CK, 220 for the write clock signal (WCKT), 230 for the data lines zero to n (0-n), and 240 for the write clock complement signal (WCKC). The waveforms represent the example of switching a memory operation from memory chip 160 to memory chip 170. The waveform 210 in Fig. The operating clock signal CK, represented in Figure 2, is provided to both memory chip 160 and memory chip 170, as shown in Figure 2. Fig. 1 is shown.

[0030] To begin accessing memory chip 170, CS is set and a command is sent containing the column and row address as well as either read or write (in Fig. (2 not shown). A faster clock, the write clock signal, is also desired for the memory chip 170 in order to operate the data buses (or lines) at a higher clock frequency than the operating clock signal CK. However, the timing relationship between the write clock signal and the operating clock signal CK must be maintained. Therefore, the synchronization of the write clock signal with the operating clock for the memory chip 170 begins with the sending of the preamble to the memory chip 170, as shown in waveform 240.

[0031] A memory operation with memory chip 160 takes place as shown in waveform 230 by a data burst over data lines 0-n. During the memory operation, the write clock signal WCKT is applied to memory chip 160 via the postamble, as indicated by waveform 220.

[0032] To switch access from memory chip 160 to memory chip 170, a preamble for a synchronization operation is sent to memory chip 170, as shown in waveform 240. Advantageously, the preamble can be sent to memory chip 170 during the data burst with memory chip 160, while the postamble is sent to memory chip 160, as shown in waveform 220. Thus, the preamble can be sent before or in parallel with the preamble being sent to memory chip 170.

[0033] After the preamble of memory chip 170 (on waveform 240) is completed, the data burst switches to memory chip 170 on the data bus. In this example, there is no connection between the postamble to memory chip 160 and the start of the data transfer to memory chip 170. Thus, the data operation on memory chip 170 is completely independent of waveform 220, and the postamble on memory chip 160 is independent of the activity on memory chip 170. The access time required between switches on the data bus is indicated by the hatching in waveform 230. Typically, the data bursts between the two memory chips 160 and 170 are not aligned to account for process fluctuations, such as those of the memory chips themselves.Data output from a DRAM during a read operation exhibits a specific range of possible response times due to fluctuations in the internal clock, depending on the process corner. Similarly, during write operations, data output from a SOC is delayed to match clock fluctuations to the DRAM's internal capture flops (also specified as an expected range). A delay between switching data bursts can be controlled by the memory control unit 110 to account for these or other manufacturing variations. Since the preamble for the memory chip 170 has already completed, the access time can be equal to the delay to account for fluctuations. In some examples, the gap or access time between bursts can be two write clock cycles.

[0034] The waveforms of Fig. Figure 2 illustrates the advantageous overlap of the synchronization operation, which reduces access time. Furthermore, since an asymmetrical signal is used, the leveling requirement is reduced because memory chip 160 can be leveled with the write clock signal WCKT, and memory chip 170 can be leveled with the write clock complement signal WCKC. Thus, when memory operations are changed between memory chips 160 and 170, the timing of the write clock signal does not need to be changed. In addition, the power load is reduced because the higher-frequency write clock signal can be made available to each memory chip as needed, instead of being supplied continuously.

[0035] Fig. Figure 3 illustrates a flowchart of an exemplary method 300 for operating a storage system, carried out in accordance with the principles of the invention. The method 300 can be used with a storage system such as, for example, the storage system 150. Fig. 1. A SOC or other device can be used to access the storage system. Procedure 300 begins in step 305.

[0036] In step 310, a differential write clock signal is used as two asymmetrical clock signals for accessing a memory system. The two asymmetrical clock signals are a first write clock signal and a second write clock signal.

[0037] In step 320, the first write clock signal is assigned to a first memory chip and the second write clock signal to a second memory chip of the memory system. The memory system can be a DDR or LPDDR system, and the first and second memory chips can be DRAM banks.

[0038] In step 330, the first write clock signal is used to level the first memory chip, and the second write clock signal is used to independently level the second memory chip. Since asymmetrical signals are used, the leveling requirements are reduced.

[0039] Method 300 continues in step 340 by controlling read and write operations of the first memory chip using the first write clock signal and, independently of the control of the first memory chip, controlling read and write operations of the second memory chip using the second write clock signal.

[0040] In step 350, a read or write operation on the first memory chip is switched to a read or write operation on the second memory chip. Switching between memory chip accesses may involve synchronizing the second write clock signal by sending a preamble signal while the read or write operation on the first memory chip is in progress. The preamble signal may be a multi-cycle pattern that is incompatible with the first or second write clock signal on a bus. The switch may also involve sending a postamble signal along with the first write clock signal while sending the preamble signal. In one example, the switch is completed after the preamble and postamble signals have finished. Additionally, a delay time may be included to cover process edge fluctuations and other variables.The delay time can be two cycles of the first or second write clock signal. Therefore, the access time can advantageously be equal to the delay time. Procedure 300 proceeds to step 360 and terminates.

[0041] The invention provides examples of using asymmetrical write clock signals for two memory chips. It will be understood by those skilled in the art that the principle can be applied to more than two memory chips. For example, if there are more than two memory chips, some of the memory chips can be configured for a write clock signal, and the remaining memory chips can be configured to use the write clock complement signal. Switching between the "actual" memory chips and the "complementary" memory chips can then be performed as described herein by sending the preamble and postamble in parallel. Additionally, two of the memory chips can be operated as described herein, and the remaining memory chips can be operated in a conventional manner.The two memory chips, or groups of "actual" and "complementary" chips, can be selected and connected for operation according to various criteria, such as load or priority.

[0042] Fig. Figure 4 illustrates a block diagram of an example of an IC 400 as disclosed herein, which can also be configured to use a differential write clock (WCK) as the asymmetric write clock signal. The IC 400 includes a memory controller 410 and a memory system 450 with a first memory chip 460 and a second memory chip 470. The memory controller 410 is configured to retrieve data from the memory system 450 for processing and to send data to the memory system 450 for storage. The memory controller 410 can be configured like the memory controller 110 according to Fig. 1 or function similarly. Accordingly, the Memory Control Unit 410 can include a clock generator, a processor, a write clock control unit, and a data control unit. As with the Memory Control Unit 110, the Memory Control Unit 410 can be a SoC, such as a Tegra® processor, which includes a CPU. The Memory Control Unit 410 can also be another type of electronic component or integrated circuit that has memory interfaces but does not have a CPU. Some examples include an integrated circuit such as an ASIC and an FPGA.

[0043] As mentioned above, the 450 memory system includes the first memory chip 460 and the second memory chip 470. The first memory chip 460 and the second memory chip 470 can be located in different memory packages. Additionally, the memory control unit 410 can be communicatively coupled to multiple memory packages. The 450 memory system can be a single memory package, such as a DRAM memory package, where the first and second memory chips 460 and 470 can be DRAM banks. As with the 150 memory system... Fig. 1 The storage system 450 can be a DDR or an LPDDR in various embodiments, such as a fifth generation LPDDR.

[0044] The first memory chip 460 and the second memory chip 470 contain data pins that are coupled to data buses from the memory controller 410. The first memory chip 460 and the second memory chip 470 also have pins that receive a write clock signal and the operating clock signal. Unlike the memory system 150, the first memory chip 460 and the second memory chip 470 of the memory system 450 receive both the write clock (WCKT) signal and the write clock complement (WCKC) signal from the memory controller 410. The first and second memory chips 460 and 470 contain logic circuitry that can be configured to use the received WCKT and WCKC signals as a differential clock signal or as unbalanced signals, as used, for example, in the first and second memory chips 160 and 170.Thus, depending on the configuration, the 460 and 470 memory chips can receive both write clock signals and operate using one write clock signal as a differential signal or as two asymmetric signals.

[0045] The devices, systems, or methods described above, or at least a part thereof, may be embodied in or executed by various processors, such as digital data processors or computers, wherein the processors are programmed or store executable programs or sequences of software instructions to perform one or more of the steps of the methods or functions of the devices or systems. The software instructions of such programs may represent algorithms and be stored in machine-executable form on non-volatile digital data storage media, e.g.,magnetic or optical disks, random access memory (RAM), magnetic hard disks, flash memory and / or read-only memory (ROM), may be encoded to enable different types of digital data processors or computers to perform one, several or all steps of one or more of the procedures or functions of the system described above.

[0046] Certain embodiments disclosed herein may further relate to computer storage products comprising a non-volatile, computer-readable medium containing program code for performing various computer-implemented operations that embody at least part of the devices or systems, or that perform or direct at least some of the steps of the methods described herein. A non-volatile medium used herein refers to all computer-readable media except volatile, propagating signals. Examples of non-volatile, computer-readable media include, but are not limited to: magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs; magneto-optical media such as floppy disks; and hardware devices specifically configured for storing and executing program code, such as ROM and RAM devices.Examples of program code include both machine code, such as that generated by a compiler, and files with higher-level code that can be executed by the computer using an interpreter.

[0047] It is understood by the person skilled in the art in the field to which this application relates that other and further additions, omissions, substitutions and modifications can be made to the described embodiments.

Claims

[1] Method for operating a memory with multiple memory chips, comprising: Using a differential write clock signal as two asymmetrical clock signals, one being a first write clock signal and the other a second write clock signal; Controlling read and write operations of a first memory chip of the memory using the first write clock signal; and Control, independently of the control of the first memory chip, of read and write operations of a second memory chip of the memory using the second write clock signal. [2] Method according to claim 1, further comprising switching a read or write operation from the first memory chip to the second memory chip. [3] Method according to claim 2, wherein the switching includes synchronizing the second write clock signal by sending a preamble signal while a read or write operation is in progress on the first memory chip. [4] Method according to claim 2 or 3, wherein the switching includes leveling the first memory chip and the second memory chip. [5] Method according to claim 3, wherein the preamble signal is a multiple cycle pattern and is incompatible on a bus with the first or second write clock signal. [6] Method according to any one of claims 3 to 5, wherein the switching further includes sending a postamble signal with the first write clock signal during the sending of the preamble signal. [7] Method according to any one of claims 3 to 6, wherein the switching begins after the preamble has finished. [8] Method according to claim 7, wherein the switching is completed after termination of the preamble signal, a postamble signal and a delay time. [9] Method according to any one of claims 2 to 8, wherein the switching is completed after an access time and the access time is equal to a delay time that takes into account manufacturing variations. [10] Method according to any of the preceding claims, further comprising leveling the first asymmetric clock signal for the first memory chip independently of leveling the second asymmetric clock signal for the second memory chip. [11] Method according to any of the preceding claims, wherein the memory comprises a memory package with the first memory chip and the second memory chip. [12] Method according to claim 11, wherein the first and second memory chips are each a dynamic direct access memory bank (DRAM bank). [13] Method according to claim 11, wherein the memory package is a double data rate (DDR) DRAM. [14] Method according to claim 11, wherein the memory package is a fifth generation low-energy DDR (LPDDR) DRAM. [15] Method according to any one of claims 11 to 14, wherein the memory package has a common instruction bus for transmitting instructions and common data buses to both the first and the second memory chip. [16] Method according to one of the preceding claims, wherein the first and second memory chips further receive an operating clock signal which is at a lower frequency than the first and second write clock signal. [17] Method according to any of the preceding claims, further comprising assigning the first asymmetric clock signal to the first memory chip and the second asymmetric clock signal to the second memory chip. [18] Method according to any of the preceding claims, wherein the first asymmetric clock signal and the second asymmetric clock signal are actual and complementary signals of the differential write clock signal. [19] Integrated circuit comprising: a dynamic direct access memory (DRAM) with double data rate (DDR) comprising a first memory bank and a second memory bank that share a bus for instructions and other buses for data transmission; and a memory control device configured to independently control read and write operations of the first memory bank and the second memory bank using a proper signal and a complementary signal of a differential write clock signal as asymmetrical clock signals. [20] Integrated circuit according to claim 19, wherein the DDR is a low-energy DDR (LPDDR) DRAM. [21] Integrated circuit according to claim 19 or 20, further configured to perform a method according to any one of claims 1 to 18.

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