Integrated chips with bottom electrode structures in memory devices and methods for manufacturing them

Abstract

Integrated chip, including: one or more lower interconnect layers (108) disposed in a dielectric structure (106) over a substrate (102); a lower electrode (114) disposed over one of the one or more lower interconnect layers (108), wherein a lower surface (114b) of the lower electrode (114) comprises a material having a first electronegativity; a data storage layer (116) separating the lower electrode (114) from an upper electrode (118); and a reactivity reducing layer (112) contacting the lower surface (114b) of the lower electrode (114) and having a second electronegativity greater than or equal to the first electronegativity.

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when powered on, while non-volatile memory can store data when power is interrupted. Resistive random-access memory (RRAM) devices are a promising candidate for a next-generation non-volatile memory technology. This is because RRAM devices offer many advantages, including fast write time, long endurance, low power consumption, and low susceptibility to radiation damage.

[0002] German patent application DE 10 2014 107 416 A1 discloses a resistive RAM / RRAM cell with a bottom electrode that ensures low leakage currents in the RRAM cell without the use of insulating sidewall spacers. US patent application US 2016 / 0 276 586 A1 discloses a resistive random access memory cell (RRAM) with a composite cap layer over a bottom electrode layer, wherein a diffusion barrier layer is arranged between the bottom electrode layer and a bottom interconnect structure. German patent application DE 10 2016 100 272 A1 discloses an integrated circuit with a memory cell, wherein an interconnect structure is arranged over a semiconductor substrate.The interconnect structure includes a lower and an upper metal layer, with a lower electrode disposed above and in electrical contact with the lower metal layer, and a data storage layer disposed above an upper surface of the lower electrode. An upper electrode is disposed above an upper surface of the data storage layer and is in direct electrical contact with an underside of the upper metal layer. The object is to improve corresponding RRAM devices. This object is achieved by the integrated chips according to claims 1 and 11, as well as by the method according to claim 18. Further embodiments emerge from the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip with a resistive random access memory (RRAM) device having a bottom electrode over a reactivity reduction layer. The Fig. 2A-2C show cross-sectional views of some additional embodiments of an RRAM device including a bottom electrode over a reactivity reduction layer. The Fig. 3-7 show cross-sectional views of some additional embodiments of an integrated chip with an RRAM device over a reactivity reduction layer. The Fig. 8A-8B show some additional embodiments of an integrated chip with an RRAM device over a reactivity reduction layer. The Fig. 9A-9B show cross-sectional views of some additional embodiments of an integrated chip with an RRAM device over a reactivity reduction layer. Fig. 10 shows a cross-sectional view of some additional embodiments of an integrated chip with an RRAM device over a reactivity reduction layer. Fig. 11 is a diagram illustrating some embodiments of a data cycle of a disclosed RRAM device over a reactivity reduction layer. The Fig. 12-21 show cross-sectional views of some embodiments of a method for forming an integrated chip with an RRAM device over a reactivity reduction layer. Fig. 22 shows a flow diagram of some embodiments of a method for forming an integrated chip with an RRAM device over a reactivity reduction layer. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0006] Resistive random access memory (RRAM) devices generally include a data storage layer (e.g., a layer of high-k dielectric) disposed between conductive bottom and conductive top electrodes arranged in a back-end-of-line (BEOL) interconnect stack. RRAM devices are configured to operate based on a process of reversibly switching between resistive states. This reversible switching is enabled by selectively forming a conductive filament through the data storage layer. For example, the data storage layer, which is normally insulating, can be made conductive by applying a voltage to the conductive electrodes to form a conductive filament extending through the data storage layer. An RRAM device having a first (e.g.,high) resistance state corresponds to a first data value (e.g., a logic “0”), and an RRAM device with a second (e.g., low) resistance state corresponds to a second data value (e.g., a logic “1”).

[0007] RRAM devices are good candidates to replace existing non-volatile memory (NVM) devices (e.g., Flash) due to their high density, high speed, good endurance, and compatibility with CMOS processes. Designing RRAM devices to have good reliability (e.g., sufficient cycles and stable data retention) is a challenge for integrated circuit manufacturers. It has been recognized that the reliability of RRAM devices (e.g., cycles and data retention) is correlated with the reactivity of the bottom electrode to oxygen in the data storage layer. For example, a bottom electrode with low reactivity to oxygen offers relatively good reliability, while a bottom electrode with high reactivity to oxygen offers relatively poor reliability.It was also recognized that the reactivity of the bottom electrode towards oxygen can be influenced by both a bottom electrode material and a material directly beneath the bottom electrode.

[0008] The present disclosure, in some embodiments, relates to an integrated chip comprising an RRAM device having a bottom electrode over a reactivity reduction layer configured to reduce a reactivity of the bottom electrode to oxygen. The integrated chip comprises an RRAM device having a bottom electrode disposed over one or more bottom interconnect layers. A bottom surface of the bottom electrode comprises a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reduction layer contacts the bottom surface of the bottom electrode and has a second electronegativity greater than or equal to the first electronegativity.The electronegativity of the reactivity reduction layer reduces reactivity of the bottom electrode to oxygen in the data storage layer and thereby improves the reliability (e.g., data cycling and / or data retention) of the RRAM device.

[0009] Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip 100 including a resistive random access memory (RRAM) device over a reactivity reduction layer.

[0010] The integrated chip 100 includes an RRAM device 111 disposed in a dielectric structure 106 over a substrate 102. The RRAM device 111 is separated from the substrate 102 by one or more lower interconnect layers 108 disposed in the dielectric structure 106. In some embodiments, the one or more lower interconnect layers 108 may include a conductive contact 107 connected to overlying and alternating layers of interconnect vias 109 and bond wires 110. The one or more lower interconnect layers 108 are configured to connect the RRAM device 111 to an access device 104 disposed in the substrate 102. In some embodiments, the access device may include a transistor device (e.g., a MOSFET, a bipolar transistor (BJT), a high electron mobility transistor (HEMT), or the like).

[0011] The RRAM device 111 includes a data storage layer 116 disposed between a bottom electrode 114 and a top electrode 118. The bottom electrode 114 is connected to the one or more bottom interconnect layers 108, and the top electrode 118 is connected to an top interconnect structure 120 comprising a bond wire or via. The data storage layer 116 is configured to store data states by undergoing reversible changes between a high resistance state corresponding to a first data state (e.g., a "0") and a low resistance state corresponding to a second data state (e.g., a "1"). For example, to achieve a low resistance state in the data storage layer 116 during operation, a first set of bias states may be applied to the bottom electrode 114 and the top electrode 118.The first set of bias states drives oxygen from the data storage layer 116 to the top electrode 118, forming a conductive filament 117 of oxygen vacancies through the data storage layer 116. Conversely, to create a low resistance state in the data storage layer 116, a second set of bias states can be applied to the bottom electrode 114 and the top electrode 118. The second set of bias states disrupts the conductive filament 117 by driving oxygen from the top electrode 118 to the data storage layer 116.

[0012] The bottom electrode 114 includes a bottom surface 114b and a top surface 114t. The bottom surface 114b includes a material having a first electronegativity. In some embodiments, the material extends continuously between the bottom surface 114b and the top surface 114t. A reactivity reduction layer 112 contacts the bottom surface 114b of the bottom electrode 114. The reactivity reduction layer 112 has a second electronegativity that is greater than or equal to the first electronegativity. For example, in some embodiments, the material of the bottom electrode 114 may have a first electronegativity of 1.5, and the reactivity reduction layer 112 may have a second electronegativity that is greater than or equal to 1.5. The electronegativity of the reactivity reduction layer 112 reduces the reactivity of the lower electrode 114 towards oxygen in the data storage layer 116.By reducing a reactivity of the bottom electrode 114 to oxygen, a reliability of the RRAM device 111 is improved, thereby increasing a data retention time and a number of error-free read / write cycles.

[0013] The Fig. 2A-2C show cross-sectional views of some additional embodiments of an RRAM device over a reactivity reduction layer.

[0014] As shown in cross-sectional view 200 of Fig. As shown in Figure 2A, the RRAM device 111 includes a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. In some embodiments, a cap layer 202 is disposed between the data storage layer 116 and the top electrode 118. The cap layer 202 is configured to store oxygen, which may facilitate resistance changes in the data storage layer 116.

[0015] In some embodiments, the top electrode 118 may comprise a metal, a metal nitride, or doped polysilicon. For example, in various embodiments, the top electrode 118 may comprise aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, titanium nitride, tantalum nitride, n-doped polysilicon, p-doped polysilicon, or the like. In some embodiments, the top electrode 118 may have a thickness t TE in a range between approximately 0 nm (nanometers) and approximately 500 nm. In some additional embodiments, the top electrode 118 may have a thickness t TE in a range between approximately 5.0 nm and approximately 20.0 nm.

[0016] In some embodiments, the cap layer 202 may comprise a metal or a metal oxide. For example, in some embodiments, the cap layer 202 may comprise hafnium, titanium, tantalum, aluminum, zirconium, or the like. In further embodiments, the cap layer 202 may comprise hafnium oxide, titanium oxide, zirconium oxide, cesium oxide, germanium oxide, or the like. In some embodiments, the cap layer 202 may have a thickness T C in a range between approximately 0 nm and approximately 500 nm. In some embodiments, the cap layer 202 may have a thickness T C in a range between approximately 7.0 nm and approximately 20.0 nm.

[0017] In some embodiments, the data storage layer 116 may comprise a metal, a metal oxynitride, or a compound metal oxide. In various embodiments, the data storage layer 116 may comprise, for example, titanium dioxide (TiO2), hafnium dioxide (HfO2), hafnium alumina (Hf x Al 1-x O2), tantalum pentoxide (Ta2O5), hafnium tantalum dioxide (Hf x Ta 1-x O2), tungsten dioxide (WO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), strontium oxide (StO), silicon dioxide (SiO2), or the like. In some embodiments, the data storage layer 116 may have a thickness t DS in a range between approximately 1 nm and approximately 100 nm. In some additional embodiments, the data storage layer 116 may have a thickness in a range between approximately 3.0 nm and approximately 10.0 nm.

[0018] In some embodiments, a lower surface (e.g., a bottom surface) of the lower electrode 114 may comprise a material including a metal, a metal nitride, a metal oxide, doped polysilicon, or the like. For example, in some embodiments, the material may comprise aluminum, titanium, tantalum, tungsten, nickel, titanium nitride, tantalum nitride, iridium oxide, n-doped polysilicon, p-doped polysilicon, or the like. In some embodiments, the material may comprise a noble metal (i.e., an inert metal), such as rhenium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, or gold. In some embodiments, the entirety of the lower electrode 114 may be made of this material. In some embodiments, the lower electrode 114 may have a thickness T BE in a range between approximately 1 nm and approximately 200 nm.

[0019] A reactivity reduction layer 112 contacts the lower surface (e.g., a bottom surface) of the lower electrode 114. In some embodiments, the reactivity reduction layer 112 is made of a metal, a metal nitride, a metal oxide, doped polysilicon, or the like. For example, in various embodiments, the reactivity reduction layer 112 may comprise aluminum, titanium, tantalum, gold, platinum, tungsten, nickel-iridium, titanium nitride, tantalum nitride, iridium oxide, n-doped polysilicon, p-doped polysilicon, or the like. In some embodiments, the lower electrode 114 and the reactivity reduction layer 112 are made of different materials. In some embodiments, the reactivity reduction layer 112 and the one or more lower interconnect layers 108 are made of different materials. In some embodiments, the reactivity reduction layer 112 is not made of copper.The reactivity reducing layer 112 may have a thickness T. RR in a range between approximately 1 nm and approximately 200 nm. In some additional embodiments, the reactivity reduction layer 112 may have a thickness T RR in a range between approximately 5 nm and approximately 20 nm.

[0020] In some embodiments, the reactivity reduction layer 112 has a first electronegativity, and the material along the bottom surface of the bottom electrode 114 has a second electronegativity that is less than or equal to the first electronegativity. A material of the reactivity reduction layer 112 having the first electronegativity contacts the material of the bottom electrode 114 having a second electronegativity along an interface. The electronegativity of the reactivity reduction layer 112 reduces the reactivity of the bottom electrode 114 toward oxygen in the data storage layer 116. For example, if the reactivity reduction layer 112 has a greater electronegativity than the material along the bottom surface of the bottom electrode 114, bonding electrons of the bottom electrode 114 and the reactivity reduction layer 112 may be drawn toward the reactivity reduction layer 112.Attracting the bonding electrons to the reactivity reduction layer 112 may reduce the ability of the bottom electrode 114 to react with oxygen in the data storage layer 116, thereby increasing the reliability of the RRAM device 111.

[0021] In some embodiments, the first electronegativity of the reactivity reduction layer 112 is greater than or equal to about 1.5. In some additional embodiments, the first electronegativity may be greater than about 1.9 to reduce a reactivity of the bottom electrode 114. In some additional embodiments, the first electronegativity may be greater than about 2.2 to reduce a reactivity of the bottom electrode 114. In some embodiments, the second electronegativity may be approximately equal to 1.5. In further embodiments, the second electronegativity may be greater than 1.5. For example, in some embodiments, the second electronegativity may be greater than about 2.0. In some embodiments, a difference between the first electronegativity and the second electronegativity is greater than about 0.1.In further embodiments, a difference between the first electronegativity and the second electronegativity is greater than about 0.2.

[0022] As shown in cross-sectional views 204 and 208 of the Fig. 2B-2C, in some embodiments, one or more additional materials 206 may be disposed beneath the reactivity reduction layer 112. In some embodiments, the one or more additional materials 206 may be disposed between the reactivity reduction layer 112 and one of the nearest underlying (e.g., immediately underlying) bond wires 110 (e.g., an immediately underlying copper bond wire). In some embodiments, the one or more additional materials 206 may include a bottom electrode diffusion barrier, a liner, a conductive layer, and / or the like. In some embodiments, the one or more additional materials 206 may include a different material than the reactivity reduction layer 112.In some embodiments, the one or more additional materials 206 may have electronegativities less than those of the reactivity-reducing layer 112. For example, in some embodiments, the reactivity-reducing layer 112 may have an electronegativity of approximately 2.5 and may contact one of the one or more additional materials 206 having an electronegativity of less than 2.5. In further embodiments, the one or more additional materials 206 may have electronegativities greater than those of the reactivity-reducing layer 112.

[0023] In some embodiments, shown in cross-sectional view 204 of Fig. 2B, the one or more additional materials 206 may include a first additional material 206a contacting the bottom surface of the reactivity reduction layer 112. In some of these embodiments, the first additional material 206a may include a metal, a metal nitride, a metal oxide, doped polysilicon, or the like. For example, the first additional material 206a may include aluminum, titanium, tantalum, tungsten, gold, platinum, nickel, iridium, titanium nitride, tantalum nitride, iridium oxide, n-doped polysilicon, or p-doped polysilicon.

[0024] In some additional embodiments shown in cross-sectional view 208 of Fig. 2C, the one or more additional materials 206 may comprise a plurality of additional materials. For example, the one or more additional materials 206 may comprise a first additional material 206a contacting a bottom surface of the reactivity reduction layer 112, a second additional material 206b contacting a bottom surface of the first additional material 206a, and a third additional material 206c contacting a bottom surface of the second additional material 206b. In some embodiments, the first additional material 206a, the second additional material 206b, and / or the third additional material 206c may comprise a metal (e.g., aluminum, titanium, tantalum, tungsten, gold, platinum, nickel, iridium), a metal nitride (e.g., titanium nitride, tantalum nitride), a metal oxide (e.g., iridium oxide), doped polysilicon (e.g., n-doped polysilicon or p-doped polysilicon), or the like.In some embodiments, the first additional material 206a, the second additional material 206b, and / or the third additional material 206c may comprise different materials. For example, the first additional material 206a may comprise titanium, while the second additional material 206b may comprise an oxide (e.g., tantalum oxide), and the third additional material 206c may comprise cobalt. In some additional embodiments (not shown), the one or more additional materials 206 may comprise further materials (e.g., a fifth additional material, a sixth additional material, etc.).

[0025] Fig. 3 shows an additional embodiment of a cross-sectional view of an integrated chip 300 with an RRAM device over a reactivity reduction layer.

[0026] The integrated chip 300 includes an RRAM device 111 arranged in a dielectric structure 106 disposed over a substrate 102. In some embodiments, the dielectric structure 106 includes a plurality of stacked interlayer dielectric (ILD) layers 302a-302d. The plurality of stacked ILD layers 302a-302d include one or more lower ILD layers 302a-302c laterally surrounding one or more lower interconnect layers 108 including conductive contacts 107, interconnect vias 109, and interconnect wires 110. In some embodiments, the plurality of stacked ILD layers 302a-302d may comprise one or more of silicon dioxide, SiCOH, a fluorosilicate glass, a phosphate glass (e.g., boron-phosphosilicate glass), or the like.The one or more lower interconnect layers 108 are configured to connect the RRAM device 111 to an access device 104 disposed in the substrate 102. In some embodiments, the access device 104 may comprise a MOSFET device having a gate electrode 104d laterally disposed between a source region 104a and a drain region 104b and vertically separated from the substrate 102 by a gate dielectric 104c.

[0027] The RRAM device 111 includes a data storage layer 116 disposed between a bottom electrode 114 and a top electrode 118. The bottom electrode 114 is disposed over the one or more bottom interconnect layers 108. In some embodiments, a bottom insulating layer 304 may be disposed over the one or more bottom ILD layers 302a-302c. The bottom insulating layer 304 includes sidewalls defining an opening located between the bottom electrode 114 and the one or more bottom interconnect layers 108. In various embodiments, the bottom insulating layer 304 may comprise silicon nitride, silicon dioxide, silicon carbide, or the like. In some embodiments, a bottom electrode diffusion barrier 306 is disposed between sidewalls of the bottom insulating layer 304.The bottom electrode diffusion barrier 306 may have a substantially flat top surface overlying the bottom insulating layer 304. In some embodiments, the bottom electrode diffusion barrier 306 may comprise titanium nitride, tantalum nitride, or the like.

[0028] A reactivity reduction layer 112 is disposed over the bottom electrode diffusion barrier 306. In some embodiments, the bottom electrode diffusion barrier 306 is disposed between the reactivity reduction layer 112 and the one or more bottom interconnect layers 108. The reactivity reduction layer 112 extends continuously from a top surface of the bottom electrode diffusion barrier 306 to contact a bottom surface of the bottom electrode 114. In some embodiments, the reactivity reduction layer 112 has a bottom surface that lies entirely over a top surface of the bottom insulating layer 304. In some embodiments, the reactivity reduction layer 112 has sidewalls aligned along a line with sidewalls of the bottom electrode 114 and the bottom electrode diffusion barrier 306.

[0029] In some embodiments, the data storage layer 116 may have a bottom surface with a first width and a top surface with a second width less than the first width. In such embodiments, the data storage layer 116 may have a bottom sidewall connected to a top sidewall by a horizontally extending surface overlying the data storage layer 116. In some embodiments, the bottom sidewall may be aligned along a first line with a sidewall of the bottom electrode 114, and the top sidewall may be aligned along a second line with a sidewall of the top electrode 118.

[0030] In some embodiments, sidewalls of the reactivity reduction layer 112 may be oriented at a first angle α with respect to a top surface of the lower insulating layer 304. The first angle α may be greater than 90°. In some embodiments, the sidewalls of the reactivity reduction layer 112 may be aligned along a line with sidewalls of the bottom electrode 114 and the data storage layer 116. In some embodiments, the sidewalls of the cap layer 202 may be oriented at a second angle β with respect to a horizontal plane extending along a top surface of the data storage layer 116. The second angle β may also be greater than 90°. In some embodiments, the first angle α differs from (e.g., is greater than) the second angle β.

[0031] In some embodiments, sidewall spacers 308 may be disposed along sidewalls of the cap layer 202 and the top electrode 118. In some embodiments, the sidewall spacers 308 may also be disposed along a sidewall of the data storage layer 116. In some embodiments, the sidewall spacers 308 may be disposed on a horizontally extending surface of the top electrode 118 and / or the data storage layer 116. In some embodiments, the sidewall spacers 308 may comprise a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), a carbide (e.g., silicon carbide), or the like. An upper ILD layer 302d is located over the RRAM device 111. In some embodiments, the upper ILD layer 302d may comprise one or more of silicon dioxide, SiCOH, a fluorosilicate glass, a phosphate glass (e.g., boron-phosphosilicate glass), or the like.

[0032] Fig. 4 shows a cross-sectional view of some additional embodiments of an integrated chip 400 with an RRAM device over a reactivity reduction layer.

[0033] The integrated chip 400 includes one or more lower interconnect layers 108 disposed in one or more lower ILD layers 302a-302c over a substrate 102. A lower insulating layer 304 is disposed over the one or more lower ILD layers 302a-302c and includes sidewalls defining an opening extending through the lower insulating layer 304.

[0034] A bottom electrode diffusion barrier 306 is disposed along the sidewalls of the bottom insulating layer 304 and above the one or more bottom interconnect layers 108. The bottom electrode diffusion barrier 306 may extend continuously from a first sidewall of the bottom insulating layer 304 to a second sidewall of the bottom insulating layer 304. In some embodiments, the bottom electrode diffusion barrier 306 has a substantially uniform thickness across the outermost sidewalls of the bottom electrode diffusion barrier 306. In some embodiments, the bottom electrode diffusion barrier 306 may comprise a refractory metal or a refractory metal nitride, such as tantalum, tantalum nitride, titanium, titanium nitride, or the like.

[0035] A reactivity reduction layer 112 is disposed over the bottom electrode diffusion barrier 306 and has a second electronegativity. The reactivity reduction layer 112 extends from directly between the sidewalls of the bottom insulating layer 304 to above the bottom insulating layer 304. In some embodiments, the reactivity reduction layer 112 may completely cover the bottom electrode diffusion barrier 306. In some embodiments, the reactivity reduction layer 112 may have a greater thickness in a center of the reactivity reduction layer 112 than along the outermost edges. In some embodiments, the reactivity reduction layer 112 may have a substantially planar top surface facing away from the substrate 102.

[0036] An RRAM device 111 is disposed on the reactivity reduction layer 112. The RRAM device 111 includes a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. The bottom electrode 114 is disposed on the reactivity reduction layer 112. The bottom electrode 114 has a bottom surface comprising a material with a first electronegativity less than or equal to a second electronegativity of the reactivity reduction layer 112. The material in the bottom surface of the bottom electrode 114 contacts the reactivity reduction layer 112 along an interface.

[0037] Fig. 5 shows a cross-sectional view of some additional embodiments of an integrated chip 500 with an RRAM device over a reactivity reduction layer.

[0038] The integrated chip 500 includes one or more lower interconnect layers 108 disposed in one or more lower ILD layers 302a-302b above a substrate 102. A lower ILD layer 302c is disposed above the one or more lower ILD layers 302a-302b. A reactivity reduction layer 112 is laterally surrounded by the lower ILD layer 302c. The reactivity reduction layer 112 has a second electronegativity. A lower insulating layer 304 overlies the lower ILD layer 302c and the reactivity reduction layer 112 such that the lower ILD layer 302c and the reactivity reduction layer 112 have upper surfaces that are below a bottom surface of the lower insulating layer 304. The lower insulating layer 304 includes sidewalls that define an opening extending through the lower insulating layer 304.The opening in the lower insulating layer 304 is located directly above the reactivity reduction layer 112.

[0039] An RRAM device 111 is disposed over the lower insulating layer 304. The RRAM device 111 includes a lower electrode 114 separated from a top electrode 118 by a data storage layer 116. The lower electrode 114 extends from directly between sidewalls of the lower insulating layer 304 to above the lower insulating layer 304. The lower electrode 114 has a bottom surface contacting the reactivity reduction layer 112. The bottom surface of the lower electrode 114 comprises a material having a first electronegativity less than or equal to the second electronegativity.

[0040] Fig. 6 shows a cross-sectional view of some additional embodiments of an integrated chip 600 with an RRAM device over a reactivity reduction layer.

[0041] The integrated chip 600 includes one or more lower interconnect layers 108 disposed in one or more lower ILD layers 302a-302c over a substrate 102. A lower insulating layer 304 is disposed over the one or more lower ILD layers 302a-302c and includes sidewalls defining an opening extending through the lower insulating layer 304.

[0042] A reactivity reduction layer 112 is disposed on the one or more lower interconnect layers 108. The reactivity reduction layer 112 has a second electronegativity. The reactivity reduction layer 112 extends from directly between the sidewalls of the lower insulating layer 304 to above the lower insulating layer 304. In some embodiments, the reactivity reduction layer 112 comprises a material (e.g., titanium, titanium nitride, or the like) configured to act as a diffusion barrier. The reactivity reduction layer 112 may have sidewalls and a bottom surface directly contacting the lower insulating layer 304. In some embodiments, the reactivity reduction layer 112 may have a substantially planar top surface facing away from the substrate 102.

[0043] An RRAM device 111 is disposed over the reactivity reduction layer 112. The RRAM device 111 includes a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. The bottom electrode 114 has a bottom surface comprising a material with a first electronegativity less than or equal to the second electronegativity. The bottom surface of the bottom electrode 114 may contact the reactivity reduction layer 112.

[0044] Fig. 7 shows a cross-sectional view of some additional embodiments of an integrated chip 700 with an RRAM device over a reactivity reduction layer.

[0045] The integrated chip 700 includes a lower insulating layer 304 over one or more lower ILD layers 302a-302c surrounding one or more lower interconnect layers 108. The lower insulating layer 304 includes sidewalls that define an opening extending through the lower insulating layer 304.

[0046] A bottom electrode diffusion barrier 306 is disposed in the opening. The bottom electrode diffusion barrier 306 lines sidewalls of the bottom insulating layer 304. A reactivity reduction layer 112 is disposed directly on the bottom electrode diffusion barrier 306. The reactivity reduction layer 112 has a top surface that is substantially coplanar with a top surface of the electrode diffusion barrier 306. The reactivity reduction layer 112 has a second electronegativity.

[0047] An RRAM device 111 is disposed over the reactivity reduction layer 112. The RRAM device 111 includes a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. The bottom electrode 114 has a bottom surface comprising a material with a first electronegativity less than or equal to the second electronegativity. The bottom surface of the bottom electrode 114 may contact the reactivity reduction layer 112 and the bottom electrode diffusion barrier 306.

[0048] The Fig. 8A-8B show some additional embodiments of an integrated chip with an RRAM device over a reactivity reduction layer.

[0049] As shown in cross-sectional view 800 of Fig. 8A, the integrated chip includes one or more lower interconnect layers 108 disposed within one or more lower ILD layers 302a-302c above a substrate 102. A lower insulating layer 304 is located above the one or more lower ILD layers 302a-302c and includes sidewalls defining an opening extending through the lower insulating layer 304 directly above the one or more lower interconnect layers 108.

[0050] A bottom electrode diffusion barrier 306 is disposed along the sidewalls of the bottom insulating layer 304 and above the one or more bottom interconnect layers 108. A reactivity reduction layer 112 is disposed above the bottom electrode diffusion barrier 306 and has a second electronegativity. An RRAM device 111 is disposed above the reactivity reduction layer 112. The RRAM device 111 includes a data storage layer 116 disposed between a bottom electrode 114 and a top electrode 118. The bottom electrode 114 has a bottom surface comprising a material having a first electronegativity that is less than or equal to a second electronegativity of the reactivity reduction layer 112.

[0051] The lower electrode diffusion barrier 306, the reactivity reduction layer 112, the lower electrode 114, the data storage layer 116, the cap layer 202, and the upper electrode 118 each have an inner region 802 that is laterally surrounded by an outer region 804. Layers in the inner region 802 each have a depressed upper surface that is laterally disposed between and vertically below upper surfaces of a corresponding layer in the outer region 804. For example, the reactivity reduction layer 112 has an upper surface in the inner region 802 that is laterally disposed between and vertically below upper surfaces of the reactivity reduction layer 112 in the outer region 804. As shown in the top view 806 of Fig. 8B, the outer region 804 of the bottom electrode diffusion barrier 306 extends along an outermost perimeter of the bottom electrode diffusion barrier 306. In some embodiments, the outer region 804 may extend continuously in an uninterrupted ring around the inner region 802.

[0052] In some embodiments, the bottom electrode diffusion barrier 306, the reactivity reduction layer 112, the bottom electrode 114, the data storage layer 116, the cap layer 202, and the top electrode 118 may each have a substantially equal thickness between outermost sidewalls. In some alternative embodiments, the inner region 802 of the data storage layer 116 may have a first thickness, and the outer region 804 of the data storage layer 116 may have a second thickness that is less than the first thickness.

[0053] Fig. 9A shows a cross-sectional view of some additional embodiments of an integrated chip 900 with an RRAM device over a reactivity reduction layer.

[0054] The integrated chip 900 includes a substrate 102 with a logic region 902 and an embedded memory region 904. A dielectric structure 106 is disposed over the substrate 102. The dielectric structure 106 includes a plurality of stacked ILD layers 302a-302d separated by etch stop layers 906. In some embodiments, the etch stop layers 906 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0055] The logic region 902 includes a transistor device 908 arranged in the substrate 102. The transistor device 908 includes a source region 908a, a drain region 908b separated from the source region 908a by a channel region, and a gate structure 908g over the channel region. In some embodiments, the transistor device 908 may include a high-k metal gate (HKMG) transistor. In such embodiments, the gate structure 908g may include a metal gate electrode (e.g., comprising aluminum, ruthenium, palladium, or the like) and a gate dielectric comprising a high-k dielectric (e.g., comprising aluminum oxide, hafnium oxide, or the like). In further embodiments, the gate structure 908g may include a polysilicon gate electrode and a gate dielectric comprising an oxide (e.g., silicon dioxide).

[0056] The source region 908a and / or the drain region 908b are connected to a plurality of interconnect layers surrounded by the dielectric structure 106. The plurality of interconnect layers include conductive contacts 910, bond wires 912, and interconnect vias 914. In some embodiments, the plurality of interconnect layers may include copper, tungsten, aluminum, and / or the like.

[0057] The embedded memory region 904 includes an access device 104 (e.g., an access transistor) disposed in the substrate 102. The access device 104 is connected to an RRAM device 111 having a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. The bottom electrode 114 contacts a reactivity reduction layer 112. The reactivity reduction layer 112 is disposed along a horizontal plane that intersects sidewalls of one of the interconnect vias 914 in the logic region 902. In some embodiments, one or more isolation structures 905 may be disposed on opposite sides of the access device 104 in the substrate 102. The isolation structures 905 may include one or more dielectrics disposed in trenches defined by interior surfaces of the substrate 102.In some embodiments, the isolation structures 905 may comprise shallow trench isolation (STI) structures. In some of these embodiments, the isolation structures 905 may comprise a single isolation structure that extends continuously in a closed loop around a perimeter of the access device 104.

[0058] Fig. 9B shows a cross-sectional view of some alternative embodiments of an integrated chip 916 with an RRAM device over a reactivity reduction layer.

[0059] The integrated chip 916 includes a substrate 102 with a logic region 902 and an embedded memory region 904. The embedded memory region 904 includes an access device 104 (e.g., an access transistor) disposed in the substrate 102. The access device 104 is connected to an RRAM device 111 having a bottom electrode 114 separated from a top electrode 118 by a data storage layer 116. The bottom electrode 114 contacts a reactivity reduction layer 112. The reactivity reduction layer 112 is disposed along a horizontal plane that intersects sidewalls of one of the bond wires 912 in the logic region 902.

[0060] Fig. 10 shows a cross-sectional view of some additional embodiments of an integrated chip 1000 with an RRAM device over a reactivity reduction layer.

[0061] The integrated chip 1000 includes a 1T1R RRAM cell architecture with an access device 104 connected to an RRAM device 111. The access device 104 is disposed in a substrate 102. In some embodiments, the access device 104 may include a MOSFET device with a gate electrode 104d disposed between a source region 104a and a drain region 104b and separated from the substrate 102 by a gate dielectric 104c. In further embodiments, the access device 104 may include a HEMT, a BJT, or the like.

[0062] A dielectric structure 106 is arranged above the substrate 102. One or more lower interconnect layers 108, comprising conductive contacts 107, interconnect vias 109, and interconnect wires 110, are surrounded by the dielectric structure 106. The interconnect wires 110 comprise a source line SL having a first interconnect wire electrically connected to the source region 104a. In some embodiments, the source line SL may be arranged in a second interconnect wire layer connected to the source region 104a by a conductive contact, a first interconnect wire, and a first interconnect via. The interconnect wires 110 further comprise a word line WL having a second interconnect wire electrically connected to the gate electrode 104d.In some embodiments, the word line WL may be arranged in the first bond wire layer and is connected to the gate electrode 104d via a conductive contact.

[0063] An RRAM device 111 is disposed in the dielectric structure 106 above a reactivity reduction layer 112. The RRAM device includes a bottom electrode 114 separated from an upper electrode 118 by a data storage layer 116. The bottom electrode 114 is directly connected to the drain region 104b through the reactivity reduction layer 112 and the one or more lower interconnect layers 108. The upper electrode 118 is further connected to a bit line BL via an upper interconnect structure 120.

[0064] In some embodiments, sidewall spacers 308 are disposed along opposite sides of the top electrode 118. In some embodiments, the sidewall spacers 308 may include a horizontally extending segment 308a protruding outwardly from a sidewall of the sidewall spacers 308. In some embodiments, horizontally extending segments 308a may protrude outwardly from opposite sides of the sidewall spacers 308. In further embodiments (not shown), a horizontally extending segment 308a may protrude outwardly from one side of the sidewall spacers 308, rather than from an opposite side of the sidewall spacers 308.

[0065] Although integrated chip 1000 depicts word line WL, source line SL, bit line BL, and RRAM device 111 as being located at specific levels within a back-end-of-line (BEOL) stack, it should be appreciated that the location of these elements is not limited to these illustrated positions. Rather, the elements may be located at other locations within a BEOL stack. For example, in some alternative embodiments, RRAM device 111 may be located between a second and a third metal bond wire.

[0066] Fig. Figure 11 shows a diagram 1100 illustrating some embodiments of a data cycle of a disclosed RRAM device over a reactivity reduction layer. The diagram 1100 shows a read current along a y-axis and a cycle count (i.e., a number of read / write cycles) along an x-axis.

[0067] As shown in diagram 1100, a read current includes a first current range 1102 for stored data states with a first value (e.g., for data states with a "1") and a second current range 1104 for stored data states with a second value (e.g., for data states with a "0"). A read window 1106 is a difference in signals (e.g., current) from an RRAM device between a "1" and a "0." During operation of an RRAM device (e.g., the RRAM device 111 of Fig. 1) a sufficiently large read window must be maintained, since a larger read window 1106 makes it easier to distinguish different data states during a read operation.

[0068] An RRAM device without a reactivity reduction layer (e.g., the reactivity reduction layer 112 of Fig. 1) has a read window that becomes too small to be reliable after a certain number of read and / or write operations (denoted by line 1108). The reactivity reduction layer (e.g., the reactivity reduction layer 112 of Fig. 1) However, it provides for an RRAM device that can maintain a sufficient read window for a relatively large number of read and / or write operations (e.g., a number of read and / or write operations that is three or more times greater than a number of read and / or write operations that can be performed by an RRAM device that does not have a reactivity reduction layer).

[0069] The Fig. 12-21 show cross-sectional views 1200-2100 of some embodiments of a method for forming an integrated chip with an RRAM device over a reactivity reduction layer. Although the Fig. 12 - 21 in relation to a specific procedure, it can be seen that the Fig. 12 - 21 are not limited to such a process, but instead can stand alone as structures that are independent of the process.

[0070] As shown in the cross-sectional view 1200 of Fig. 12, an access device 104 is formed in a substrate 102. In various embodiments, the substrate 102 may be comprised of any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers connected thereto. In some embodiments, the access device 104 may comprise a transistor device formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric 104c and a gate electrode 104d. The substrate 102 may then be implanted to form a source region 104a and a drain region 104b in the substrate 102 on opposite sides of the gate electrode 104d.

[0071] In some embodiments, one or more isolation structures 905 may be formed in the substrate 102 on opposite sides of the access device 104. In some embodiments, the one or more isolation structures 905 may be formed by selectively etching the substrate 102 to form one or more shallow trenches 1202 and then forming one or more dielectrics in the one or more shallow trenches 1202. In some embodiments, the etching process may comprise a dry etching process. For example, the etching process may comprise a coupled plasma etching process, such as an inductively coupled plasma (ICP) process or a capacitively coupled plasma (CCP) process. In further embodiments, the etching process may comprise a wet etching process.

[0072] As shown in cross-sectional view 1300 of Fig. As shown in Figure 13, one or more lower interconnect layers 108 are formed in one or more lower interlayer dielectric (ILD) layers 302a-302c above the substrate 102. The one or more lower interconnect layers 108 may include conductive contacts 107, interconnect vias 109, and bond wires 110. The one or more lower interconnect layers 108 may be formed by forming one of the one or more ILD layers 302a-302c over the substrate 102, selectively etching the ILD layer (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric) to define a via and / or a trench in the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) in the via and / or a trench to fill the opening, and performing a planarization process (e.g., a chemical mechanical planarization process).

[0073] As shown in the cross-sectional view 1400 of Fig. 14, a lower insulating layer 304 is formed on the one or more lower interconnect layers 108 and the one or more lower ILD layers 302a-302c. In some embodiments, the lower insulating layer 304 may comprise silicon nitride, silicon carbide, or the like. In some embodiments, the lower insulating layer 304 may be formed by a deposition technique (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in a range between approximately 20.0 nm and approximately 30.0 nm. After deposition, the lower insulating layer 304 is selectively patterned to define an opening 1404 extending through the lower insulating layer 304 to the one or more lower interconnect layers 108. In some embodiments, the lower insulating layer 304 may be removed by an etchant 1402 (e.g.,a dry etchant or wet etchant) can be selectively structured.

[0074] As shown in the cross-sectional view 1500 of Fig. 15, in some embodiments, a bottom electrode diffusion barrier layer 1502 is formed over the bottom insulating layer 304 and the one or more bottom interconnect layers 108. The bottom electrode diffusion barrier layer 1502 extends from within the opening 1404 to a position overlying the bottom insulating layer 304. In some embodiments, the bottom electrode diffusion barrier layer 1502 may comprise tantalum nitride, titanium nitride, or the like. A planarization process (e.g., a chemical mechanical planarization process) may subsequently be performed. In some embodiments, the planarization process results in the bottom electrode diffusion barrier layer 1502 having a thickness in a range between approximately 10.0 nm and approximately 30.0 nm over the bottom insulating layer 304.In some embodiments, the bottom electrode diffusion barrier layer 1502 may be formed by a deposition process (e.g., CVD, PVD, ALD, PE-CVD, or the like).

[0075] A reactivity reduction coating 1504 is formed over the bottom electrode diffusion barrier layer 1502. The reactivity reduction coating 1504 has a second electronegativity. In some embodiments, the second electronegativity may be greater than or equal to 1.5. In further embodiments, the second electronegativity may be greater than or equal to 2.0. In some embodiments, the reactivity reduction coating 1504 may be formed by a deposition process (e.g., CVD, PVD, ALD, PE-CVD, or the like). In some embodiments, the reactivity reduction coating 1504 may be formed with a thickness ranging between approximately 1 nm and approximately 200 nm.

[0076] As shown in the cross-sectional view 1600 of Fig. 16, a bottom electrode layer 1602 is formed on the reactivity reduction coating 1504. In some embodiments, the bottom electrode layer 1602 has a bottom surface comprising a material having a first electronegativity less than or equal to the second electronegativity of the reactivity reduction coating 1504. In some embodiments, the entirety of the bottom electrode layer 1602 may be comprised of the material. In some embodiments, the first electronegativity may be approximately 1.5. In further embodiments, the first electronegativity may be greater than 1.5. In some embodiments, the bottom electrode layer 1602 may comprise a metal, a metal nitride, a metal oxide, or doped polysilicon formed via a deposition process (e.g., PVD, CVD, or the like).

[0077] In some embodiments, the bottom electrode layer 1602 may be formed in situ (e.g., without breaking a vacuum of a processing chamber in which the depositions are performed) together with the reactivity reduction coating 1504. In such embodiments, a material of the reactivity reduction coating 1504 having the second electronegativity directly contacts the material of the bottom electrode layer 1602 having the first electronegativity along an interface. In some embodiments, the bottom electrode layer 1602 may be formed to a thickness T BEin a range between approximately 1 nm and approximately 200 nm. In further embodiments, the bottom electrode layer 1602 may be formed ex situ with the reactivity reduction coating 1504. In some of these embodiments, an additional etching process may be performed to remove any native oxide from a top surface of the reactivity reduction coating 1504 prior to forming the bottom electrode layer 1602, such that a material of the reactivity reduction coating 1504 having the second electronegativity directly contacts the material of the bottom electrode layer 1602 having the first electronegativity along an interface.

[0078] As shown in the cross-sectional view 1700 of Fig. 17, a data storage element 1702 is formed on the reactivity reduction coating 1504. In some embodiments, the data storage element 1702 may comprise a high-k dielectric with a variable resistance. In some embodiments, the data storage element 1702 may comprise, for example, hafnium oxide (HfO X ), zirconium oxide (ZrO X ), aluminum oxide (AlO X ), nickel oxide (NiO X ), tantalum oxide (TaO X ) Titanium oxide (TiO X ) or the like. In some embodiments, the data storage element 1702 may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, sputtering, ALD, etc.) to a thickness in a range between about 2.5 nm and about 7.5 nm.

[0079] In some embodiments, a capping film 1704 may be formed over the data storage element 1702. In various embodiments, the capping film 1704 may comprise a metal or a metal oxide. In some embodiments, the capping film 1704 may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, sputtering, ALD, etc.).

[0080] A top electrode layer 1706 is formed over the data storage element 1702. The top electrode layer 1706 may comprise a metal such as titanium, tantalum, or the like. In some embodiments, the top electrode layer 1706 may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, sputtering, ALD, or the like). In some embodiments, the top electrode layer 1706 may have a thickness in a range between approximately 10.0 nm and approximately 40.0 nm.

[0081] As shown in the cross-sectional view 1800 of Fig. 18, a first structuring process is performed on the upper electrode layer (1706 of Fig. 17). In some embodiments, the first patterning process includes forming a masking layer 1804 over the top electrode layer (1706 of Fig. 17) and subsequent exposure of the upper electrode layer (1706 of Fig. 17) a first etchant 1802 configured to define a top electrode 118 by removing unmasked portions of the top electrode layer (1706 of Fig. 17). In some embodiments, the first etchant 1802 may also remove unmasked portions of the cover film 1704 to define a cover layer 202.

[0082] In various embodiments, the first etchant 1802 may comprise a dry etchant having an etch chemistry comprising a fluorine species (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant comprising hydrofluoric acid (HF). In some embodiments, the first patterning process may reduce a thickness of the masking layer 1804. For example, in some embodiments, the first patterning process may reduce a thickness of the masking layer 1804 by between about 70% and about 85% (e.g., by about 55.0 nm to about 10.0 nm).

[0083] In some embodiments, overetching the top electrode layer (1706 of Fig. 17) cause a portion of the data storage element 1702 to be etched. For example, in some embodiments, a portion of the data storage element 1702 may be etched away such that the data storage element 1702 has a sidewall that is laterally offset from an outermost sidewall of the data storage element 1702.

[0084] As shown in the cross-sectional view from 1900 by Fig. 19, sidewall spacers 308 may be formed on opposite sides of the top electrode 118. In some embodiments, the sidewall spacers 308 may be formed by depositing a spacer layer over the substrate 102 using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). The spacer layer is then etched to remove the spacer layer from horizontal surfaces, leaving the spacer layer along opposite sides of the top electrode 118 as sidewall spacers 308. In various embodiments, the spacer layer may comprise silicon nitride, a silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), or the like. In various embodiments, the spacer layer may be formed with a thickness in a range between approximately 40.0 nm and approximately 60.0 nm.

[0085] After forming the sidewall spacers 308, a second patterning process is performed to define a data storage layer 116, a bottom electrode 114, a reactivity reduction layer 112, and a bottom electrode diffusion barrier 306. In some embodiments, the second patterning process sets the data storage element (1702 of Fig. 18), the lower electrode layer (1602 of Fig. 18), the reactivity reduction coating (1504 of Fig. 18) and the lower electrode diffusion barrier layer (1502 of Fig. 18) a second etchant 1902 according to a mask comprising the masking layer 1804 and the sidewall spacers 308. The second etchant 1902 is configured to etchant unmasked portions of the data storage element (1702 of Fig. 18), the lower electrode layer (1602 of Fig. 18), the reactivity reduction coating (1504 of Fig. 18) and the lower electrode diffusion barrier (1502 of Fig. 18). In various embodiments, the second etchant 1902 may comprise a dry etchant or a wet etchant.

[0086] In some embodiments, the second patterning process may reduce a thickness of unmasked regions of the lower insulating layer 304. For example, in some embodiments, the second patterning process may reduce a thickness of the unmasked regions of the lower insulating layer 304 by approximately 20% to approximately 35% (e.g., by approximately 27.0 nm to approximately 22.0 nm). Reducing the thickness of the unmasked regions of the lower insulating layer 304 causes the lower insulating layer 304 to have a greater thickness directly beneath the reactivity reduction layer 112 than outside the reactivity reduction layer 112.

[0087] As shown in the cross-sectional view 2000 of Fig. As shown in Figure 20, an upper dielectric layer 2002 is formed over the substrate 102. Subsequently, an upper interlayer dielectric (ILD) layer 302d is formed over the upper dielectric layer 2002. The upper dielectric layer 2002 has a first side adjacent to the lower insulating layer 304 and a second side adjacent to the upper ILD layer 302d.

[0088] As shown in the cross-sectional view 2100 of Fig. 21, an upper interconnect structure 120 is formed at a location adjacent to the upper electrode 118. In various embodiments, the upper interconnect structure 120 may include an interconnect via or a bond wire. In some embodiments, the upper interconnect structure 120 may be formed by etching the upper ILD layer 302d to form an opening 2102 extending through the upper ILD layer 302d, the upper dielectric layer 2002, and the masking layer 1804 to the upper electrode 118. The opening 2102 is then filled with a conductive material (e.g., copper and / or aluminum) to form the upper interconnect structure 120.

[0089] Fig. 22 shows a flow diagram of some embodiments of a method 2200 for forming an integrated chip with an RRAM device over a reactivity reduction layer.

[0090] While method 2200 is shown and described below as a sequence of acts or events, it should be understood that the shown order of such acts or events should not be interpreted in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. Additionally, not all acts shown may be required to implement one or more aspects or embodiments of the present description. Further, one or more of the acts shown herein may be performed in one or more separate steps and / or phases.

[0091] At 2202, an access device is formed in a substrate. Fig. 12 shows a cross-sectional view 1200 of some embodiments associated with operation 2202.

[0092] At 2204, one or more lower interconnect layers are formed in one or more lower ILD layers above the substrate. Fig. 13 shows a cross-sectional view 1300 of some embodiments associated with operation 2204.

[0093] At 2206, a lower insulating layer is formed over the one or more lower ILD layers. Fig. 14 shows a cross-sectional view 1400 of some embodiments associated with operation 2206.

[0094] At 2208, in some embodiments, a bottom electrode diffusion barrier layer may be formed over the bottom insulating layer and the one or more bottom interconnect layers. Fig. 15 shows a cross-sectional view 1500 of some embodiments associated with operation 2208.

[0095] At 2210, a reactivity reduction coating having a second electronegativity is formed over the bottom electrode diffusion barrier layer. Fig. 15 shows a cross-sectional view 1500 of some embodiments associated with operation 2210.

[0096] At 2212, a bottom electrode layer having a first electronegativity is formed on the reactivity-reducing coating. The second electronegativity is greater than or equal to the first electronegativity. Fig. 16 shows a cross-sectional view 1600 of some embodiments associated with operation 2212.

[0097] At 2214, a data storage element is formed over the bottom electrode layer. Fig. 17 shows a cross-sectional view 1700 of some embodiments associated with operation 2214.

[0098] At 2216, a cover film is formed over the data storage element. Fig. 17 shows a cross-sectional view 1700 of some embodiments associated with operation 2216.

[0099] At 2218, an upper electrode layer is formed over the data storage element. Fig. 17 shows a cross-sectional view 1700 of some embodiments associated with operation 2218.

[0100] At 2220, the top electrode layer is selectively patterned to define a top electrode. Fig. 18 shows a cross-sectional view 1800 of some embodiments associated with process 2220.

[0101] In 2222, sidewall spacers are formed on opposite sides of the top electrode. Fig. 19 shows a cross-sectional view 1900 of some embodiments associated with process 2222.

[0102] At 2224, the data storage element, the bottom electrode layer, the reactivity reduction coating, and the bottom electrode diffusion barrier layer are selectively patterned to define a data storage layer, a bottom electrode, a reactivity reduction layer, and a bottom electrode diffusion barrier, respectively. Fig. 19 shows a cross-sectional view 1900 of some embodiments associated with process 2224.

[0103] At 2226, an upper ILD layer is formed over the upper electrode. Fig. 20 shows a cross-sectional view 2000 of some embodiments associated with operation 2226.

[0104] At 2228, an upper interconnect structure is formed on the upper electrode. Fig. 21 shows a cross-sectional view 2100 of some embodiments associated with operation 2228.

[0105] Although the disclosed figures and description are described with respect to resistive random access memory (RRAM) devices, it should be understood that the disclosed reactivity reduction layer is not limited to such memory devices. Rather, in some alternative embodiments, the disclosed reactivity reduction layer may also be applied to other types of memory devices, such as, but not limited to, phase-change random access memory (PCRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), programmable metallization memory, carbon nanotube memory, or the like.

[0106] Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising an RRAM device having a bottom electrode over a reactivity reduction layer configured to reduce reactivity of the bottom electrode to oxygen. By reducing the reactivity of the bottom electrode to oxygen, the reactivity reduction layer improves the reliability (e.g., a number of read and / or write cycles that can be reliably performed) of the RRAM device.

[0107] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises one or more bottom interconnect layers disposed in a dielectric structure over a substrate; a bottom electrode disposed over one of the one or more bottom interconnect layers, wherein a bottom surface of the bottom electrode comprises a material having a first electronegativity; a data storage layer separating the bottom electrode from a top electrode; and a reactivity reduction layer contacting the bottom surface of the bottom electrode and having a second electronegativity greater than or equal to the first electronegativity. In some embodiments, the integrated chip further comprises a bottom electrode diffusion barrier disposed between the reactivity reduction layer and the one or more bottom interconnect layers.In some embodiments, the integrated chip further comprises a bottom insulating layer disposed on the dielectric structure and having sidewalls defining an opening directly below the bottom electrode, the bottom insulating layer surrounding the reactivity reduction layer. In some embodiments, the integrated chip further comprises one or more additional materials disposed between the reactivity reduction layer and a directly underlying bond wire. In some embodiments, the second electronegativity is greater than about 2.2. In some embodiments, the bottom surface of the bottom electrode comprises a noble metal. In some embodiments, the first electronegativity is less than the second electronegativity. In some embodiments, the reactivity reduction layer has sidewalls aligned along a line with sidewalls of the bottom electrode.In some embodiments, the reactivity reduction layer comprises a metal, a metal nitride, a metal oxide, or doped polysilicon. In some embodiments, the reactivity reduction layer comprises aluminum, titanium, tantalum, tungsten, gold, platinum, nickel, iridium, titanium nitride, tantalum nitride, iridium oxide, n-doped polysilicon, or p-doped polysilicon.

[0108] In further embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom insulating layer disposed over one or more interlayer dielectric (ILD) layers, the bottom insulating layer having sidewalls defining an opening directly above one or more interconnect layers surrounded by the one or more ILD layers; a bottom electrode diffusion barrier disposed in the opening; a bottom electrode over the bottom electrode diffusion barrier and having a first electronegativity; a data storage layer separating the bottom electrode from an upper electrode; and a reactivity reduction layer disposed directly between the bottom electrode diffusion barrier and the bottom electrode, the reactivity reduction layer having a second electronegativity greater than the first electronegativity.In some embodiments, the reactivity reduction layer comprises a metal nitride or a metal oxide. In some embodiments, the reactivity reduction layer covers an entire lower surface of the lower electrode. In some embodiments, the reactivity reduction layer is located entirely above the lower insulating layer. In some embodiments, the lower electrode comprises a noble metal that extends continuously from the reactivity reduction layer to the data storage layer. In some embodiments, the reactivity reduction layer is not made of copper. In some embodiments, the lower electrode is made of a noble metal.

[0109] In still further embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a reactivity reduction coating over one or more lower interconnect layers disposed over a substrate; forming a lower electrode layer on and in contact with the reactivity reduction coating, the lower electrode layer having a first electronegativity less than or equal to a second electronegativity of the reactivity reduction coating; forming a data storage element over the lower electrode layer; forming an upper electrode layer over the data storage element; and patterning the upper electrode layer, the data storage element, the reactivity reduction coating, and the lower electrode layer to define a memory device.In some embodiments, the method further comprises forming a bottom electrode diffusion barrier layer over the one or more bottom interconnect layers; and forming the reactivity reduction coating on the bottom electrode diffusion barrier layer. In some embodiments, the method further comprises forming a bottom insulating layer over a dielectric structure surrounding the one or more bottom interconnect layers; and patterning the bottom insulating layer to form sidewalls of the bottom insulating layer defining an opening directly beneath the bottom electrode layer, wherein the reactivity reduction coating has a bottommost surface overlying a bottommost surface of the bottom insulating layer.

Claims

[1] Integrated chip comprising: one or more lower interconnect layers (108) disposed in a dielectric structure (106) over a substrate (102); a lower electrode (114) disposed over one of the one or more lower interconnect layers (108), wherein a lower surface (114b) of the lower electrode (114) comprises a material having a first electronegativity; a data storage layer (116) separating the lower electrode (114) from an upper electrode (118); and a reactivity reducing layer (112) contacting the lower surface (114b) of the lower electrode (114) and having a second electronegativity greater than or equal to the first electronegativity. [2] The integrated chip of claim 1, further comprising: a lower electrode diffusion barrier (306) disposed between the reactivity reduction layer (112) and the one or more lower interconnect layers (108). [3] The integrated chip of claim 1 or 2, further comprising: a lower insulating layer (304) disposed on the dielectric structure (106) and comprising sidewalls defining an opening directly below the lower electrode (114), the lower insulating layer (304) surrounding the reactivity reduction layer (112). [4] Integrated chip according to one of the preceding claims, further comprising: one or more additional materials (206) arranged between the reactivity reduction layer (112) and a connecting wire (110) immediately below it. [5] Integrated chip according to claim 4, wherein the one or more additional materials (206) comprise one or more materials other than the reactivity reduction layer (112); and wherein the one or more additional materials (206) comprise a metal, a metal nitride, a metal oxide, or doped polysilicon. [6] An integrated chip according to any preceding claim, wherein the second electronegativity is greater than about 2.

2. [7] An integrated chip according to any preceding claim, wherein the lower surface of the lower electrode (114b) comprises a noble metal. [8] An integrated chip according to any preceding claim, wherein the first electronegativity is less than the second electronegativity. [9] An integrated chip according to any preceding claim, wherein the reactivity reduction layer (112) comprises a metal, a metal nitride, a metal oxide, or doped polysilicon. [10] An integrated chip according to any one of the preceding claims, wherein the reactivity reduction layer (112) comprises aluminum, titanium, tantalum, tungsten, gold, platinum, nickel, iridium, titanium nitride, tantalum nitride, iridium oxide, n-doped polysilicon or p-doped polysilicon. [11] Integrated chip comprising: a lower insulating layer (304) disposed over one or more interlayer dielectric layers, ILD layers, (302a, 302b, 302c), the lower insulating layer (304) having sidewalls defining an opening directly above one or more interconnect layers (108) surrounded by the one or more ILD layers (302a, 302b, 302c); a lower electrode diffusion barrier (306) disposed in the opening; a lower electrode (114) above the lower electrode diffusion barrier (306) and having a first electronegativity; a data storage layer (116) separating the lower electrode (114) from an upper electrode (118); and a reactivity reduction layer (112) disposed directly between the lower electrode diffusion barrier (306) and the lower electrode (114), the reactivity reduction layer (112) having a second electronegativity greater than the first electronegativity. [12] The integrated chip of claim 11, wherein the reactivity reducing layer (112) comprises a metal nitride or a metal oxide. [13] The integrated chip according to claim 11 or 12, wherein the reactivity reducing layer (112) covers an entirety of a lower surface of the lower electrode (114). [14] The integrated chip of any one of claims 11 to 13, wherein the reactivity reduction layer (112) is located entirely above the lower insulating layer (304). [15] The integrated chip of any one of claims 11 to 14, wherein the lower electrode (114) comprises a noble metal extending continuously from the reactivity reduction layer (112) to the data storage layer (116). [16] The integrated chip of any one of claims 11 to 15, wherein the reactivity reducing layer (112) is not made of copper. [17] Integrated chip according to one of claims 11 to 16, further comprising: one or more additional materials (206) disposed between a lower surface of the reactivity reduction layer (112) and an upper surface of a nearest underlying connecting wire (110). [18] A method of forming an integrated chip, comprising: Forming a reactivity reduction coating (1504) over one or more lower interconnect layers (108) disposed over a substrate (102); Forming a lower electrode layer (1602) on and in contact with the reactivity reduction coating (1504), the lower electrode layer (1602) having a first electronegativity that is less than or equal to a second electronegativity of the reactivity reduction coating (1504); Forming a data storage element (1702) over the lower electrode layer (1602); Forming a top electrode layer (1706) over the data storage element (1702); and Patterning the top electrode layer (1706), the data storage element (1702), the reactivity reduction coating (1504), and the bottom electrode layer (1602) to define a memory device (111). [19] The method of claim 18, further comprising: Forming a lower electrode diffusion barrier layer (1502) over the one or more lower interconnect layers (108); and Forming the reactivity reducing coating (1504) on the lower electrode diffusion barrier layer (1502). [20] The method of claim 18 or 19, further comprising: Forming a lower insulating layer (304) over a dielectric structure (106) surrounding the one or more lower interconnect layers (108); and Patterning the lower insulating layer (304) to form sidewalls of the lower insulating layer (304) defining an opening (1404) directly beneath the lower electrode layer (1602), wherein the reactivity reduction coating (1502) has a lowermost surface overlying a lowermost surface of the lower insulating layer (304).

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