PFM power management system with autonomous mode switching

Abstract

Method comprising: Determining a desired operating mode of a pulse frequency modulation (PFM) voltage converter (100) as a function, at least in part, of a voltage difference between an input voltage to the PFM voltage converter (100) and an output voltage generated by the PFM voltage converter (100); Generating a display of the desired operating mode; autonomously switching to the desired operating mode of the PFM voltage converter (100) in response to a current operating mode that is different from the desired operating mode; wherein the current operating mode is one of a buck mode and a low drop-out (LDO) mode and the desired operating mode is one of the buck mode and the LDO mode; Using a switched LDO converter (105) in LDO mode; and Maintain a coulomb count for buck mode and LDO mode.

Description

STATE OF THE ARTField of the invention

[0001] This application relates to voltage converters and, in particular, to switching between different modes used by voltage converters. Description of the state of the art

[0002] Voltage converters convert a voltage from a voltage source, such as a battery, into a voltage used by electronic circuits. For example, a cell phone uses a voltage converter to convert the voltage supplied by the battery into a voltage used by the cell phone's circuits. The conversion process of converting from one voltage to another consumes energy, and higher voltage conversion efficiency is desirable to extend battery life.

[0003] CN 101 577 488 A discloses an efficient multimode DC / DC converter in a wide voltage conversion range.

[0004] US 8 975 916 B1 discloses a self-modulated voltage reference circuit that can generate a reference voltage.

[0005] US 2014 / 0 191 741 A1 discloses a power supply system having a regulator circuit responsive to an input signal at the input node to generate an output signal at the output node at a desired level. SUMMARY OF THE INVENTION

[0006] The problem addressed by the patent application is solved by the independent patent claims. Advantageous embodiments are described in the dependent patent claims. SUMMARY OF EMBODIMENTS OF THE INVENTION

[0007] In one embodiment, a method includes determining a desired operating mode of a pulse frequency modulation (PFM) voltage converter as a function at least in part of a voltage difference between an input voltage to the PFM voltage converter and an output voltage generated by the PFM voltage converter, and generating an indication of the desired operating mode. The method further includes autonomously switching to the desired operating mode of the PFM converter when a current operating mode deviates from the desired operating mode.

[0008] In another embodiment, a pulse frequency modulation (PFM) voltage converter includes control logic for determining a desired operating mode of the PFM converter as a function, at least in part, of the input voltage to the PFM voltage converter and the output voltage provided by the voltage converter. The voltage converter is configured to transition to the desired operating mode of the PFM converter when a current operating mode differs from the desired operating mode.

[0009] In another embodiment, a pulse frequency modulation (PFM) voltage converter includes a mode controller for evaluating an output voltage of the PFM voltage converter and an input voltage of the PFM voltage converter to select an operating mode based on one or more transition threshold voltages at the input voltage and the output voltage. A voltage comparator compares a reference voltage to the output voltage and provides a voltage comparator output. A selection circuit is coupled to the mode controller and provides the voltage comparator output to a switched low-drop-out (LDO) controller responsive to the mode controller selecting an LDO mode of operation and provides the voltage comparator output to an inverse controller responsive to the mode controller selecting a buck mode, a boost mode, or an inverse mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention and its numerous objects, features and advantages may be better understood by those skilled in the art by reference to the accompanying drawings. Fig. 1 illustrates a voltage converter according to an embodiment of the invention. Fig. Figure 2 illustrates an embodiment of transition thresholds used to determine the appropriate mode (buck, inverse, or boost) depending on the input and output voltage. Fig. Figure 3 illustrates a high-level flow diagram of the operation of the mode controller in one embodiment in which the operating modes may be down, inverse, or up. Fig. Figure 4 illustrates an embodiment of transition thresholds used to determine the appropriate mode (buck or switched LDO) depending on the input and output voltage. Fig. Figure 5 illustrates a high-level timing diagram showing the operation of the mode controller in an embodiment where the operating modes may be buck or switched LDO.

[0011] The use of the same reference numerals in different drawings indicates similar or identical elements. DETAILED DESCRIPTION

[0012] Voltage converters monitor the generated output voltage and adjust the operation of the voltage converter to maintain the output voltage at the target voltage level. This requires a comparator that compares the output voltage to the target voltage and provides an indication of the comparison.

[0013] Fig. 1 illustrates one embodiment of a voltage converter 100 that uses a battery as the voltage source Vin 101. In one embodiment, the voltage converter 100 is a pulse frequency modulation (PFM) voltage converter that includes the buck converter 103, which operates in buck mode, boost mode, or inverse mode. A mode controller 107 compares the output voltage 109 and the input voltage 101 and determines the desired operating mode of the voltage converter, as described below. Each type of power converter (buck, boost, inverse, and LDO) has an optimal range of input and output voltages at which the converter operates efficiently and precisely. A voltage comparator 111 compares the output voltage Vin 109 with a reference voltage 119 corresponding to the target voltage for the PFM voltage converter and activates a feedback signal whenever the output voltage falls below the target voltage.When the output voltage is guaranteed to be below the input voltage, in one embodiment, the voltage converter operates in either buck mode or low-drop-out (LDO) mode with a switched LDO converter 105. The selection circuit 115 selects either the inverting converter 103 or the LDO converter 105 as the destination for the output of the voltage comparator 111 based on the output of the mode controller 107. Note that the voltage converter 100 uses the same voltage comparator 111 for all modes (buck, inverting, boost, LDO). If different comparators were used for different modes, comparator skews would result in less accurate control of the output voltage when the mode switches autonomously.

[0014] In boost mode, transistor M1 is on, transistor M2 is off, and transistors M3 and M4 switch according to standard boost operation. In buck mode, M3 is on, M4 is off, and M1 and M2 switch according to standard buck operation. In inverse mode, the four switches are used in this order: M1 and M4 are on; M1 and M3 are on; then M2 and M3 are on. In switched LDO operation, only switch M5 is used. Each time the LDO receives a feedback signal from voltage comparator 111 indicating that the output voltage is below the target voltage, LDO controller 117 outputs a single pulse of fixed width and fixed current. This causes the LDO to add a known, fixed charge to the output with each pulse, enabling accurate coulomb counting in switched LDO mode.

[0015] The mode controller 107 evaluates Vin and Vin in response to each buck, boost, or LDO pulse. For example, the mode controller compares the difference between Vin and Vin to a programmed threshold to determine the best or preferred mode for system operation. Built-in hysteresis can be used to avoid continuous mode switching near the threshold. The mode controller only needs to perform one comparison for each current pulse and therefore has a negligible impact on system efficiency, even at light loads. The mode controller can be essentially turned off between the buck, inverse, boost, and LDO converter pulses to conserve power.

[0016] The operating mode can be changed dynamically as the input and / or output voltages change. In most practical battery-powered systems, the battery voltage changes over time. Both the buck converter and the switched-mode LDO operate in the same PFM feedback loop with the voltage comparator, allowing seamless transitions between modes. The frequency of the current pulses applied to the output increases when more charge is needed to maintain the output voltage at the target voltage. The frequency of the current pulses can be decreased when less charge is needed to maintain the output voltage at the target voltage.

[0017] The coulomb count is maintained across modes because both the buck converter 103 and the switched LDO converter 105 produce a fixed charge per pulse in a PFM system. The coulomb count can provide an indication of how much charge has been delivered by the battery and can thus be used to determine remaining battery life. Because the buck, boost, and buck converters all provide pulses of a fixed size, the number of pulses can be used to determine the charge transferred from the battery. Likewise, in switched LDO mode, the converter provides a fixed-size pulse. A conventional, non-switched LDO would not have this ability to maintain the coulomb count.

[0018] In one embodiment, when the input voltage may be higher or lower than the output voltage, the entire inverter 103 is used to allow the voltage converter to operate in buck, boost, or inverse mode to optimize efficiency. While the entire inverter is in use, the LDO converter 105 can be completely turned off. When the entire inverter is in use, the mode controller 107 determines the operating mode of the inverter (buck mode, boost mode, or inverse mode). Fig. Figure 2 shows an example of input and output voltages associated with the different operating modes of the PFM voltage converter. As shown in Fig. As shown in Figure 2, the PFM voltage converter operates in buck mode when the input voltage is sufficiently higher than the output voltage in region 201. When the output voltage and the input voltage are closer together, as shown in region 203, the PFM voltage converter operates in inverse mode. When the output voltage is greater than the input voltage, as shown in region 205, the PFM voltage converter operates in boost mode. The system is configured to autonomously switch between buck, boost, or inverse modes depending on the output voltage and the input voltage. That is, the system switches between modes automatically. Fig. Figure 2 shows an example of the threshold output voltage and threshold input voltages (lines 207 and 209) used to determine the appropriate inverse mode for different input voltage and output voltage values. Hysteresis can be used to ensure that switching does not occur too frequently when the voltage ratio is close to the transition thresholds of lines 207 or 209. The threshold values ​​can be programmed according to the requirements of the specific application.

[0019] The mode controller 107 includes analog and / or digital logic to determine the appropriate mode based on the input and output voltages. For example, the mode controller may use an analog comparator 108 and additional analog and / or digital logic 110. The digital logic may use state machines, a programmed microcontroller, or a suitable combination of control logic. The comparison process may use the analog comparator 108 or convert the input and output voltages to digital values ​​and compare them digitally. The mode controller 107 determines when to switch to a different mode based on the values ​​of the input voltage and the output voltage and the transition thresholds, which may, for example, be Fig. 2. The mode controller 107 provides the desired mode via signal line 116 to the inverse controller 104, which in turn controls transistors M1-M4 according to the desired mode. In addition, the inverse controller receives an input from voltage comparator 111 to indicate when the output voltage is below the target voltage, which is used to adjust the pulse frequency to maintain the target output voltage. Although not illustrated, other indications (high or low voltage) may also be provided to the inverse controller 104. The output of the mode controller 107 selects the setting of switch 115.

[0020] Fig. Figure 3 illustrates a high-level flow diagram showing the operation of the mode controller 107 in an embodiment in which the voltage converter can operate in buck, boost, or inverse modes. In 301, the mode controller waits for a pulse-active signal 121 (see Fig. 1) from the inverse control logic, which indicates that the pulse provided by the inverse converter is active. In one embodiment, the pulse-active signal 121 is asserted for the duration of the pulse. The pulse-active signal 121 wakes up a portion of the mode control from a low-power state. The analog portion of the mode control, such as comparator 108, turns on in response to the asserted pulse-active signal 121 and remains on while the pulse-active signal 121 is asserted. This allows some settling time on the analog circuitry before sampling the comparator output. When the pulse-active signal is deasserted, the transition is used as a clock for the digital circuitry 110 to close the voltage difference between the input voltage and the output voltage provided by comparator 108 and determine the appropriate mode of operation.

[0021] In a broader sense, the mode comparator could also be implemented in other ways. As long as the mode comparator only consumes power during or shortly after the end of each pulse, the mode comparator should have a negligible impact on system efficiency. In another embodiment, an analog-to-digital converter (ADC) monitors the input and output voltages and uses the beginning of the pulse signal, the end of the pulse signal, or another signal during the pulse to clock the ADC. The digital voltage values ​​can be used to determine the appropriate operating mode. The basic idea is that as the time between pulses increases (when the output current is very low), the time between mode comparator events should also increase so that the system does not waste power by constantly running the mode comparator.

[0022] At 303, the mode controller evaluates the output voltage and the input voltage to determine the desired operating mode. The evaluation may involve comparing the two voltages to determine a voltage difference. As mentioned above, this can be done using a combination of analog and digital circuits. From the voltage difference, a desired operating mode can then be determined in 305. The Fig. The selection of the desired operating mode 201, 203, or 205 shown in Figure 2 is based on the voltage difference between the input and output voltages and the threshold voltages shown at 207 and 209. At 307, the mode control determines whether a change in operating mode is required. That is, the control logic determines whether the desired operating mode matches the current operating mode. For example, the desired operating mode may be buck mode and the current operating mode is buck mode. If the desired and current operating modes are the same, the mode control takes no action and returns to the low power state at 309 to wait for the next active pulse signal at 301. If a mode switch is required, e.g.From buck mode to inverse mode, as the battery ages and the battery voltage decreases, the mode controller goes to state 311 and signals the inverse controller 104 of the new mode via signal line(s) 116. The mode controller then transitions to the low power state at 309, e.g., by de-energizing a substantial portion of the analog and digital circuitry, and waits for the next active pulse indication at 301. To extend battery life, embodiments of the voltage converter described herein attempt to reduce the quiescent current to zero to extend battery life. It should be noted that while . Fig. 3 describes the mode control functionality as part of the mode control and separate from the inverse control, other embodiments may combine the control functionality for the inverse control and the mode control.

[0023] If the input voltage is guaranteed to always exceed the output voltage, at least until the end of battery life, the system is configured to autonomously transition between buck and LDO modes. In this case, the inverse controller 104 can be wired (or otherwise configured) to operate only in buck mode, and the voltage converter will autonomously transition between buck mode and switched LDO mode. The mode controller 107 determines when to transition between switched LDO mode and buck mode. In other embodiments, the LDO converter may not be a switched LDO converter, but rather a conventional LDO converter. Thus, the LDO converter may or may not be switched in LDO mode. Of course, using a conventional LDO would prevent the coulomb count from continuing when transitioning between buck and LDO modes.

[0024] Fig. Figure 4 illustrates one embodiment of transition thresholds to determine when to operate in buck mode and when to use LDO mode depending on the input and output voltage. As shown in Fig. 4, the PFM voltage converter 100 operates in buck mode when the input voltage in region 401 is sufficiently higher than the output voltage. When the output voltage and the input voltage are closer together, as shown in region 403, the voltage converter operates in LDO mode. The system switches autonomously between buck and LDO mode depending on the output voltage and the input voltage. In the example of Fig. For example, in Figure 4, line 405 illustrates the transition threshold. Hysteresis can be used to ensure that switching does not occur too frequently when the voltage ratio is close to line 405. Threshold 405 can be programmed according to the requirements of the particular application. Note that mode controller 107 includes logic for determining the appropriate mode based on the input and output voltage and communicates this information to inverse controller 104 via signal line 116. In switched LDO mode, mode controller 107 controls switch 115 to provide the output of voltage comparator 111 to switched LDO controller 117.The switched LDO controller 117 controls the transistor M5 to generate a fixed pulse responsive to a predetermined signal from the voltage comparator 111 indicating that the output voltage is below the target output voltage corresponding to the reference voltage 119.

[0025] Some embodiments include an additional feature that prevents the converter from transitioning from buck mode to LDO mode until the system detects that the buck converter is having difficulty providing the required output current. In PFM mode, the pulse typically ends when the voltage converter reaches the programmed peak current. A timer 123 (see Fig. 1) Counts up to a maximum allowable on-time for the current pulse. In one embodiment, if the buck converter has three consecutive pulses where it reaches the maximum allowable on-time before reaching the programmed peak current, this means that the buck converter is struggling to provide the required output current and LDO mode is appropriate. Since buck converters generally have better efficiency than LDO converters, it is better to remain in buck mode even after the mode control transition threshold voltage is reached, as long as the buck converter is still able to supply the required load. The battery voltage may temporarily drop due to a short high-power operation, such as a radio transmission, and recover after the operation is complete. If possible, remaining in buck mode allows for more efficient converter operation for as long as possible.

[0026] Fig. Figure 5 illustrates a high-level timing diagram showing the operation of the mode controller 107 when the voltage converter 100 is operating only in buck mode or in switched LDO mode. At 501, the mode controller waits for an indication 121 (see Fig. 1) from the inverse controller or from the switched LDO controller that the pulse is active. In one embodiment, comparator 108 compares the input and output voltages during the buck or LDO pulse in response to the pulse-active signal, and logic 110 responds to the deactivation of the pulse-active signal to sample the voltage difference. Thus, signal line(s) 121 may include a pulse-active indication from both controller 104 and controller 117. The pulse-active indication may be used to wake up a portion of the mode controller from a low-power state. At 503, the mode controller evaluates the output voltage and the input voltage and provides an indication of the evaluation. The evaluation may include a comparison operation with analog circuitry, digital circuitry, or a combination.The voltage difference between the input and output voltages and the value of the transition threshold voltage at the sampled input and output voltages determines the desired operating mode (401 or 403 in . Fig. 4) at 505. The transition threshold voltages are in Fig. 4 at 405. At 507, the mode controller determines whether a mode change is required based on whether the desired mode matches the current mode. For example, the desired mode may be buck mode and the current mode is buck mode. If the desired and current modes are the same, the mode controller need not take any action and returns to the low power state at 509 and waits for the next pulse-active indication at 501. If a mode switch is required, e.g., from buck mode to switched LDO mode as the battery ages and the battery voltage drops, the mode controller goes to state 511 and further determines whether the buck converter is having difficulty providing the required output current.If this pulse is the third or other suitable number of pulses where the buck converter has reached the maximum allowable turn-on time before reaching the programmed peak current, indicating that the buck converter is struggling, the mode controller switches the mode by updating the switch position of switch 115 to switched LDO mode in 515 and updates the buck converter via signal line 116 so that the voltage converter is now operating in LDO mode. This requires the buck controller 104 to track that the three consecutive pulses with this condition have occurred. Signal lines 121 may include a control signal to indicate that the consecutive pulses with this condition have occurred. In some embodiments, step 511 is omitted. Via an additional signal line (not shown in . Fig.1), the switched LDO controller can be informed that the switched LDO converter is now active. The mode controller then transitions to the low-power state at 509, for example, by de-energizing a significant portion of the circuit, and waits for the next active pulse indication at 301.

[0027] When the converter is in LDO mode, the switched LDO converter generates fixed-width, fixed-current pulses that respond to the output of voltage comparator 111. The LDO controller turns on M5 as much as needed to provide the programmed DC current. The output current equals (Vin-Vout) / resistance_M5. Because the input and output voltages approach each other, the resistance of M5 would need to be very low to maintain the desired current. When the input voltage gets very close to the output voltage or drops below the target output voltage, the LDO controller 117 detects this low battery condition and switches to an LDO bypass mode. Battery capacity can decrease, for example, due to a sudden increase in demand from the circuits powered by the battery or due to age. The LDO feedback loop senses how much M5 turns on with each pulse.If three consecutive pulses require M5 to be turned on stronger than a set threshold for the M5 gate voltage, the LDO converter enters LDO bypass mode. Of course, other embodiments may use more or fewer consecutive pulses to determine whether to switch to LDO bypass mode. In LDO bypass mode, the switch (M5) is turned on strongly and remains on. Transitions into and out of LDO bypass mode are autonomous and based on the output voltage and the input voltage. The LDO converter exits LDO bypass mode when the voltage comparator determines that the output voltage recovers to a level above the target voltage.

[0028] Thus, various aspects have been described related to an improved voltage converter that autonomously switches between voltage conversion modes. The description of the invention contained herein is illustrative and is not intended to limit the scope of the invention, as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description presented herein without departing from the scope of the invention, as set forth in the following claims.

Claims

[1] Method comprising: Determining a desired operating mode of a pulse frequency modulation (PFM) voltage converter (100) as a function, at least in part, of a voltage difference between an input voltage to the PFM voltage converter (100) and an output voltage generated by the PFM voltage converter (100); Generating a display of the desired operating mode; autonomously switching to the desired operating mode of the PFM voltage converter (100) in response to a current operating mode different from the desired operating mode; wherein the current operating mode is one of a buck mode and a low drop-out (LDO) mode and the desired operating mode is one of the buck mode and the LDO mode; Using a switched LDO converter (105) in LDO mode; and Maintain a coulomb count for buck mode and LDO mode. [2] The method of claim 1, further comprising determining the voltage difference only once for each current pulse of the PFM voltage converter (100). [3] The method of claim 2, further comprising determining the voltage difference in response to a pulse-active signal indicative of the current pulse. [4] The method of claim 2, further comprising an operating circuit that determines the desired mode of operation in a low power state for a portion of the time between successive current pulses. [5] Pulse frequency modulation (PFM) voltage converter (100), comprising: a mode controller (107) for determining a desired operating mode of the PFM voltage converter (100) as a function of an input voltage for the PFM voltage converter (100) and an output voltage supplied by the PFM voltage converter (100); and a switched LDO converter (105) for use in LDO mode; wherein the PFM voltage converter (100) is configured to transition to the desired operating mode responsive to a current operating mode different from the desired operating mode; wherein the current operating mode is one of a buck mode and a low drop-out (LDO) mode, and the desired operating mode is one of the buck mode and the LDO mode; and wherein the PFM voltage converter (100) is configured to maintain a coulomb count for the buck mode and the LDO mode. [6] PFM voltage converter (100) according to claim 5, wherein the mode control (107) comprises: a comparator (111) for comparing the output voltage of the PFM voltage converter (100) with the input voltage of the PFM voltage converter (100) and producing an indication of a difference. [7] PFM voltage converter (100) according to claim 5 or 6, wherein the input voltage comes from a battery. [8] The PFM voltage converter (100) of claim 5, wherein the switched LDO converter (105) generates a current pulse of a fixed width by turning on a transistor in the switched LDO converter (105), the transistor being coupled between an input voltage node and an output voltage node. [9] The PFM voltage converter (100) of any one of claims 5 to 8, wherein the mode controller (107) determines a desired mode once for each current pulse of the PFM voltage converter (100), and wherein the mode controller (107) enters a low power state between successive current pulses. [10] The PFM voltage converter (100) of claim 9, wherein the mode controller (107) evaluates the output voltage and the input voltage in response to a signal indicative of each current pulse to determine the desired mode. [11] Method comprising: Determining a desired operating mode of a pulse frequency modulation (PFM) voltage converter (100) as a function, at least in part, of a voltage difference between an input voltage to the PFM voltage converter (100) and an output voltage generated by the PFM voltage converter (100), wherein the PFM voltage converter (100) comprises a voltage comparator (111), an inverse converter (103) and a mode control (107); Generating a display of the desired operating mode; autonomously switching to the desired operating mode of the PFM voltage converter (100) in response to a current operating mode different from the desired operating mode; wherein the current operating mode is one of a buck mode and a low drop-out (LDO) mode and the desired operating mode is one of the buck mode and the LDO mode; Using a switched LDO converter (105) in LDO mode; Selecting as the destination for the output of the voltage comparator (111) either the inverting converter (103) or the switched LDO converter (105) based on the output of the mode controller (107); and Outputting a single pulse of fixed width and fixed current each time the switched LDO converter (105) receives a feedback signal from the voltage comparator (111) indicating that the output voltage is below a target voltage. [12] Pulse frequency modulation (PFM) voltage converter (100), comprising: a voltage comparator (111); an inverting converter (103); a selection circuit (115); an LDO controller (117); a mode controller (107) for determining a desired operating mode of the PFM voltage converter (100) as a function of an input voltage for the PFM voltage converter (100) and an output voltage supplied by the PFM voltage converter (100); and a switched LDO converter (105) for use in LDO mode; wherein the PFM voltage converter (100) is configured to transition to the desired operating mode responsive to a current operating mode different from the desired operating mode; wherein the current operating mode is one of a buck mode and a low drop-out (LDO) mode and the desired operating mode is one of the buck mode and the LDO mode; wherein the selection circuit (115) is configured to select either the inverting converter (103) or the switched LDO converter (105) as the destination for the output of the voltage comparator (111) based on the output of the mode controller (107); and wherein the LDO controller (117) is configured to output a single fixed-width, fixed-current pulse each time the switched LDO converter (105) receives a feedback signal from the voltage comparator (111) indicating that the output voltage is below a target voltage.

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