EFUSE CIRCUIT, METHOD, DESIGN AND STRUCTURE

Abstract

eFuse structure (500A, 500B), comprising a circuit (100B, 100D): an eFuse (R1) and a first program device (PD0) connected in series between a bit line (BL) and a program node (PN); and a second program device (PD1) connected in parallel with the first program device (PDo), wherein the first program device (PDo) and the second program device (PD1) are separately controllable by a first signal (E0) on a first signal line (WL0) and by a second signal (E1) on a second signal line (WL1), and wherein the first signal line (WL0), the eFuse (R1) and the second signal line (WL1) are arranged in the eFuse structure (500A) between the first (PDo) and the second program device (PD1), or wherein the first program device (PD0), the eFuse (R1) and the second program device (PD1) are arranged in the eFuse structure (500B) between the first (WL0) and the second signal line (WL1).

Description

STATE OF THE ART

[0001] Integrated circuits (ICs) sometimes incorporate one-time programmable (“OTP”) memory elements to provide non-volatile memory (“NVM”) in which data is not lost when the IC is powered off. One type of NVM incorporates an electrical fuse (eFuse) integrated into the IC using a narrow strip (also called a “link”) of conductive material (metal, polysilicon, or the like) connected at both ends to other circuit elements. To program an eFuse, a programming current is applied to destructively modify (i.e., fuse) the link, thereby increasing the resistance of the eFuse. To determine the state of an eFuse, a sensing circuit is typically connected to the link, and a comparison is made with a reference resistor device.

[0002] From US patent 2012 / 0039105 A1, a memory cell matrix is ​​known with a configuration in which at least one series of memory cells with a fuse device having a resistance value that varies depending on the current flow, and a plurality of cell transistors arranged in parallel with the fuse device, are provided. In the semiconductor device in question, the number of switched-on cell transistors among the plurality of cell transistors can be controlled by an externally applied write control signal, an internal logic circuit, and a word line driver circuit.

[0003] US Patent 2018 / 0033483 A1 describes a high-speed memory circuit architecture for arrays of resistive change elements. An array of resistive change elements is organized into rows and columns, with each column served by one word line and each row by two bit lines. Each row of resistive change elements contains a pair of reference elements and a read amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by reading the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features / elements are not shown to scale. Indeed, the dimensions of the various elements may have been enlarged or reduced as desired for clarity of explanation. Fig. 1A - 1D are diagrams of unstressed eFuse circuits in accordance with some embodiments. Fig. Figure 2 is a flowchart of an unclaimed method for determining a state of an eFuse in accordance with some embodiments. Fig. 3A and Fig. 3B are diagrams of an eFuse in accordance with some embodiments. Fig. 4A - 4G are diagrams of eFuse structures in accordance with some embodiments. Fig. 5A and Fig. 5B are diagrams of eFuse structures in accordance with some embodiments. Fig. Figure 6 is a diagram of an eFuse structure in accordance with some embodiments. Fig. Figure 7 is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments. Fig. Figure 8 is a block diagram of a manufacturing system for an integrated circuit (IC) and an IC manufacturing flow associated therewith in accordance with some embodiments. Fig. Figure 9 is a flowchart of an unclaimed method for generating an assembly diagram of an IC in accordance with some embodiments. DETAILED DESCRIPTION

[0005] In various embodiments, a circuit comprises an eFuse and a first program device connected in series between a bit line and a program node, and a second program device connected in parallel with the first program device. Because they are independently controllable, the first and second program devices allow an eFuse read current to be smaller than a program current, thereby reducing the energy consumed during read operations compared to approaches where a single program device is used for both programming and reading operations.

[0006] In various embodiments, an IC layout diagram and a resulting unstressed IC structure include an eFuse and first and second program devices, which feature arrangements that enable a reduction in program current path resistance and area requirement compared to arrangements based on a single eFuse and a single program device. In various embodiments, fin field-effect transistors (FinFETs) are configured as the program device to realize these advantages.

[0007] Fig. Figures 1A-1D are diagrams of the respective eFuse circuits 100A-100D in accordance with some embodiments. Each of the circuits 100A-100D has an eFuse Rfuse that is coupled between a program node PN and a bit line BL.

[0008] In the Fig. In the embodiment shown in Figure 1A, the circuit 100A comprises program devices PDo and PD1, which are connected in parallel between the eFuse Rfuse and a program node PN, which is configured to carry a reference voltage VSS. The program device PDo is configured to receive a signal E0 on a signal line WL0 and is connected in series with the eFuse Rfuse between the bit line BL and the program node PN. The program device PD1 is configured to receive a signal E1 on a signal line WL1 and is connected in series with the eFuse Rfuse between the bit line BL and the program node PN.

[0009] In the Fig. In the embodiment shown in Figure 1B, circuit 100B is a non-restrictive example of circuit 100A, in which the program device PDo has a type n metal oxide semiconductor (NMOS) transistor N0 configured to receive the signal E0 at a gate coupled to the signal line WL0, and in which the program device PD1 has an NMOS transistor N1 configured to receive the signal E1 at a gate coupled to the signal line WL1.

[0010] In the Fig. In the embodiment shown in Figure 1C, the circuit 100C comprises program devices PDo and PD1, which are connected in parallel between the eFuse Rfuse and a program node PN, which is configured to carry a power supply voltage VDDQ. The program device PDo is configured to receive a signal E0 on a signal line WL0 and is connected in series with the eFuse Rfuse between the program node PN and the bit line BL. The program device PD1 is configured to receive a signal E1 on a signal line WL1 and is connected in series with the eFuse Rfuse between the program node PN and the bit line BL.

[0011] In the Fig. In the embodiment shown in Figure 1D, the circuit 100D is a non-limiting example of the circuit 100C, in which the program device PDo has a p-type metal oxide semiconductor (PMOS) transistor P0 configured to receive the signal E0 at a gate coupled to the signal line WL0, and in which the program device PD1 has a PMOS transistor P1 configured to receive a signal E1 at a gate coupled to the signal line WL1.

[0012] Consideration is being given to coupling two or more circuit elements based on a direct electrical connection, a resistive or reactive electrical connection, or an electrical connection that has one or more additional circuit elements and is thereby able to be controlled, i.e., made resistive or open, for example by a transistor or other switching device.

[0013] In each of the in Fig. In the embodiments shown in 1A - 1D, the eFuse Rfuse is connected between the bit line BL and the program devices PDo and PD1. In various embodiments, the eFuse Rfuse is connected between the program nodes PN and the program devices PDo and PD1, and program devices PDo and PD1 are connected between the eFuse Rfuse and the bit line BL.

[0014] In some embodiments, a circuit 100A-100D is a section of one or an entire bit cell of a plurality of bit cells, in which each of the bit cells is coupled to the bit line BL. In some embodiments, the bit line BL is a bit line of a plurality of bit lines. In some embodiments, a circuit 100A-100D is a section of one or an entire bit cell of a plurality of bit cells of a memory circuit (not shown). In some embodiments, the signal lines WL0 and WL1 are word lines of a memory circuit, and the signals E0 and E1 are word line signals configured to select a circuit 100A-100D, comprising a bit cell, in a programming or reading operation.In some embodiments, a memory circuit includes one or more read amplifiers (not shown) configured to determine a programmed state of a circuit 100A - 100D in a read operation.

[0015] The eFuse Rfuse is a circuit device comprising a conductive element capable of being permanently changed and thereby programmed by a current exceeding a predetermined current level. In an unprogrammed state, the eFuse Rfuse exhibits low resistance relative to a resistance in a programmed state. In some embodiments, the eFuse Rfuse includes an eFuse R1, which is described below in relation to Fig. 3A and Fig. 3B is discussed.

[0016] Each of the program devices PDo and PD1 is an integrated circuit (IC) capable of switching between conducting and resistive states in response to an input signal, for example, one of the signals E0 or E1, received at an input pin (unlabeled) coupled to a respective signal line WL0 or WL1. In a conducting state, the program device PDo or PD1 has a low-impedance current path between two current path pins (unlabeled), and in a resistive state, the program device PDo or PD1 has a high-impedance current path between the two current path pins.

[0017] In the conducting state, the program device PDo or PD1 is able to exhibit the low-resistance current path only for current values ​​up to a predetermined current saturation level, and exhibits a path with a significantly higher relative resistance for current values ​​above the saturation level. During operation, the program device PDo or PD1 thus limits the value of the current flowing between the two current path terminals in response to an increasing voltage difference across the two current path terminals.

[0018] In various embodiments, the program devices PDo and PD1 are either the same or different program devices. The same program devices have low-impedance current paths that exhibit essentially the same resistance value and essentially the same saturation level. In other embodiments, different program devices have low-impedance current paths that exhibit either essentially different resistance values ​​and / or essentially different saturation levels.

[0019] In various embodiments, one or both of the program devices PDo or PD1 comprise a transfer gate, a MOS transistor, a field-effect transistor (FET), a FinFET, a bipolar transistor, or other suitable IC components capable of switching between conducting and resistive states in response to an input signal. In various embodiments, the program devices PDo and PD1 comprise FinFETs having the same number of fins and the same number of gates, or FinFETs having different numbers of fins and / or gates. In various embodiments, the program devices PDo and PD1 comprise the FinFETs FF1 and FF2, which are described below with respect to Fig. 4A - 4G are discussed, or the FinFETs 600FF1 and 600FF2, which are subsequently referred to in relation to Fig. 6 are discussed.

[0020] Since the program devices PDo and PD1 respond to separate input signals, they can be controlled independently. In various embodiments, one or both program devices PDo or PD1 are configured to respond to an input signal that has logic levels corresponding to the respective conducting and resistive states.

[0021] In the embodiment described in Fig. As shown in Figure 1B, each of the NMOS transistors N0 and N1 is configured to respond in the conducting state to the corresponding signal E0 or E1, which has a high logic level, and in the resistive state to the corresponding signal E0 or E1, which has a low logic level. In the embodiment shown in Fig. As shown in 1D, each of the PMOS transistors P0 and P1 is configured to respond in the conducting state to the corresponding signal E0 or E1, which has the low logic level, and in the resistive state to the corresponding signal E0 or E1, which has the high logic level.

[0022] Through the configurations discussed above, each of the circuits 100A - 100D is able to couple the eFuse Rfuse to the program node PN via two parallel low-impedance paths, provided by each of the program devices PDo and PD1 being in the conducting state in response to a first configuration of the input signals E0 and E1; to couple the eFuse Rfuse to the program node PN via a single parallel low-impedance path, provided by one of the program devices PDo and PD1 being in the conducting state and the other of the program devices PDo or PD1 being in the resistive state in response to a second configuration of the input signals E0 and E1; and to couple the eFuse Rfuse to the program node PN via two parallel high-impedance paths, provided bythat each of the program devices PDo and PD1 is in a resistive state in response to a third configuration of the input signals E0 and E1, to decouple from the program node PN.

[0023] Due to the parallel configuration of the program devices PDo and PD1, the total path resistance between the eFuse Rfuse and the program node PN, according to the first configuration of input signals E0 and E1, is lower than the total path resistance between the eFuse Rfuse and the program node PN, according to the second configuration of input signals E0 and E1. Since a program device PDo or PD1, when conducting, limits the value of any current flowing between the two current path terminals, during operation the current Ifuse, according to the second configuration of input signals E0 and E1, is limited based on the saturation level of a single program device PDo or PD1, and the current Ifuse, according to the first configuration of input signals E0 and E1, is limited based on the combined saturation levels of the program devices PDo and PD1.

[0024] In various embodiments, one or more of the circuits 100A - 100D have one or more program devices (not shown) in addition to, and connected in parallel with, the program devices PDo and PD1. If present, each additional program device is configured to further couple the eFuse Rfuse to the program node PN by providing an additional low-impedance path on the corresponding signal line WL0 or WL1 in response to one of the input signals E0 or E1 received. This reduces the overall path resistance compared to embodiments in which a circuit 100A - 100D does not have one or more program devices in addition to the program devices PDo and PD1, and increases the current Ifuse in response to one or both of the first or second configurations of the input signals E0 or E1.

[0025] In some embodiments, the first configuration of input signals E0 and E1 corresponds to a programming operation, and the second configuration of input signals E0 and E1 corresponds to a read operation. Each of the circuits 100A - 100D thus provides a total path resistance in the programming operation that is lower than that in the read operation, and provides a larger current Ifuse in the programming operation than in the read operation.

[0026] In some embodiments, which are in Fig. As shown in Figure 1B, the programming operation corresponds to the first configuration of signals E0 and E1, in which each signal has a high logic level, and the read operation corresponds to the second configuration of signals E0 and E1, in which one signal E0 or E1 has the high logic level and the other signal E0 or E1 has the low logic level. In some embodiments, which are shown in Fig. In 1D, the programming operation corresponds to the first configuration of signals E0 and E1, in which each of signals E0 and E1 has the low logic level, and the reading operation corresponds to the second configuration of signals E0 and E1, in which one of signals E0 or E1 has the high logic level and the other of signals E0 or E1 has the low logic level.

[0027] In some embodiments, the third configuration of the input signals E0 and E1 corresponds to a disabled state in which each of the circuits 100A - 100D causes the current Ifuse to be limited to a low value, for example a leakage current level, with respect to the current limits in the programming and reading operations based on the parallel high-impedance paths provided by the programming devices PDo and PD1. In some embodiments, which are described in Fig. As shown in 1B, the canceled state corresponds to the third configuration of signals E0 and E1, in which each of signals E0 and E1 has the low logic level. In some embodiments, which are shown in Fig. In 1D, the canceled state corresponds to the third configuration of signals E0 and E1, in which each of signals E0 and E1 has the high logic level.

[0028] In the Fig. In embodiments 1A-1D, circuits 100A-100D are configured to receive signals E0 and E1 on signal lines WLo and WL1 from one or more circuits (not shown) outside of circuits 100A-100D. In various embodiments, one or more of the circuits 100A-100D include one or more circuits (not shown) configured to generate signals E0 and E1 on signal lines WL0 and WL1.

[0029] Through the parallel programming device configuration discussed above, each of the circuits 100A - 100D is able to be selected to perform a read operation in which the current Ifuse is lower than a current Ifuse in a programming operation, thus consuming less energy during read operations than in approaches in which a single programming device is used to provide a read current during read operations that is the same as a programming current during programming operations.

[0030] Fig. Figure 2 is a flowchart of an unclaimed method 200 for determining a state of an eFuse in accordance with one or more embodiments. The method 200 is usable with a circuit, e.g., a circuit 100A - 100D, which is described above with reference to Fig. 1A - 1D are discussed.

[0031] The sequence in which the operations of procedure 200 are performed in Fig. Figure 2 is for illustrative purposes only; the operations of procedure 200 can be performed in sequences that differ from those shown in Figure 2. Fig. The two illustrated versions differ. In some embodiments, the following occur before, between, during and / or after the events shown. Fig. The two illustrated operations are additional, not shown. Fig. The two illustrated operations were performed.

[0032] In some embodiments, the operations of method 200 are a subset of operations of a method for operating a memory circuit. In some embodiments, the eFuse is part of a bit cell of a memory circuit, and determining the state of the eFuse corresponds to determining a logical state of the bit cell.

[0033] In some embodiments of Operation 210, a programming operation is performed by turning on a first program device and a second program device to cause a program current to flow into the eFuse. The first and second program devices are connected in parallel, and each of the first and second program devices is connected in series with the eFuse between a program node and a bit line. Turning on the first and second program devices causes them to provide parallel low-impedance paths between the program node and the bit line, so that the program current is the sum of the currents flowing in the two parallel paths.

[0034] In various embodiments, switching on the first and second program devices includes switching on one or more additional program devices, causing the one or more additional program devices to provide one or more additional parallel low-impedance paths between the program node and the bit line, such that the program current is the sum of the currents flowing in more than two parallel paths.

[0035] In various embodiments, switching on the first and second program devices includes switching on the first and second program devices that are coupled between the eFuse and the program node or between the eFuse and the bit line. In various embodiments, executing the programming operation includes applying a power supply voltage to the program node and a reference voltage to the bit line, or applying the reference voltage to the program node and the power supply voltage to the bit line.

[0036] In various embodiments, switching on the first program device and the second program device to cause a program current to flow in the first eFuse includes switching on the program devices PDo and PD1 in a circuit 100A - 100D to cause a current Ifuse to flow into the eFuse Rfuse, which is coupled between the program node PN and the bit line BL, which is described above in relation to Fig. 1A - 1D are discussed.

[0037] Causing the program current to flow into the eFuse includes causing the program current to be of a magnitude sufficient to permanently increase the resistance value of the eFuse from that of an unprogrammed state to that of a programmed state. In some embodiments, causing the program current to flow into the eFuse includes causing the program current to flow into eFuse R1, which is described below with respect to Fig. 3A and Fig. 3B is discussed.

[0038] In some embodiments, the first program device is switched on in response to a first signal, and the second program device is switched on in response to a second signal. In some embodiments, the first and second signals are word line signals received by the first and second program devices on first and second word lines. In some embodiments, the first and second signals are the signals E0 and E1 received on respective word lines WL0 and WL1, as described above. Fig. 1A - 1D are discussed.

[0039] In some embodiments, executing the programming operation involves storing a logical value in a bit cell selected from a plurality of bit cells of a memory circuit. In some embodiments, storing the logical value in the bit cell is part of storing data, e.g., identification, security, or circuit configuration data, in the memory of an IC.

[0040] In some embodiments, during Operation 220, the execution of a program or read operation by the eFuse is canceled by switching off the first and second program devices. Switching off the first and second program devices causes them to provide parallel high-impedance paths between the program node and the bit line, so that any current flowing through the eFuse has a low value, e.g., a leakage current level, relative to the program current in Operation 210 and the read current in Operation 230.

[0041] In various embodiments, switching off the first and second program devices includes switching off one or more additional program devices, causing the one or more additional program devices to provide one or more additional parallel high-impedance paths between the program node and the bit line.

[0042] In various embodiments, switching off the first and second program devices includes switching off the first and second program devices that are coupled between the eFuse and the program node, or that are coupled between the eFuse and the bit line. In various embodiments, switching off the first and second program devices to deactivate the eFuse includes switching off the program devices PDo and PD1 in a circuit 100A - 100D to deactivate the eFuse Rfuse, which is coupled between the program node PN and the bit line BL, as described above. Fig. 1A - 1D are discussed, coupled, to be deactivated.

[0043] In some embodiments, the first program device is switched off in response to the first signal, and the second program device is switched off in response to the second signal. In some embodiments, the first program device is switched off in response to one of the signals E0 or E1 received on a corresponding word line WL0 or WL1, and the second program device is switched off in response to the other of the signals E0 or E1 received on the other of the word lines WL0 or WL1, as described above. Fig. 1A - 1D are discussed.

[0044] Operation 230 performs a read operation by turning on the first program device to cause a read current to flow through the eFuse, and by turning off the second program device. Turning on the first program device causes it to provide a low-impedance path between the program node and the bit line, and turning off the second program device causes it to provide a high-impedance path between the program node and the bit line, so that the read current is essentially equal to the current flowing through the low-impedance path.

[0045] Since the read current is based on the low-impedance path provided by the first program device, and the program current is based on the parallel low-impedance paths provided by the first and second program devices, the program current is greater than the read current.

[0046] In various embodiments, switching on the first programming device and / or switching off the second programming device includes switching on or off one or more additional programming devices, such that the program stream is based on a number of parallel paths greater than the number of parallel paths on which the read stream is based, thereby making the program stream greater than the read stream.

[0047] In various embodiments, switching on the first program device and switching off the second program device comprises switching on the first program device and switching off the second program device, which is coupled between the eFuse and the program node or between the eFuse and the bit line. In various embodiments, performing the read operation comprises applying the power supply voltage to the program node and the reference voltage to the bit line, or applying the reference voltage to the program node and the power supply voltage to the bit line. In various embodiments, the power supply voltage has the same or a different value than a value of the power supply voltage applied during operation 210, and / or the reference voltage has the same or a different value than a value of the reference voltage applied during operation 210.

[0048] In various embodiments, switching on the first program device and switching off the second program device to cause a read current to flow in the eFuse includes switching on one of the program devices PDo or PD1 and switching off the other of the program devices PDo or PD1 in a circuit 100A - 100D to cause the current Ifuse to flow into the eFuse Rfuse, which is located between the program node PN and the bit line BL, as described above. Fig. 1A - 1D are discussed, are coupled.

[0049] Causing the read current to flow into the eFuse includes causing the read current to be of a sufficiently large magnitude to distinguish the resistance value of the eFuse in the unprogrammed state from the resistance value of the eFuse in the programmed state. In some embodiments, causing the read current to flow into the eFuse includes causing the read current to flow into eFuse R1, which is described below with respect to Fig. 3A and Fig. 3B is discussed.

[0050] In various embodiments, causing the read current to flow comprises one or more of the following steps: generating a voltage based on the resistance value of the eFuse, applying a current having the read current value to a reference resistor device, generating a voltage based on a resistance value of the reference resistor device, comparing the voltages based on the resistance values ​​of the eFuse and the reference resistor element using a read amplifier, and generating a signal indicating a result of the comparison of the voltages based on the resistance values ​​of the eFuse and the reference resistor device.

[0051] In some embodiments, the first program device is switched on in response to the first signal, and the second program device is switched off in response to the second signal. In some embodiments, the first program device is switched on in response to one of the signals E0 or E1 received on a corresponding word line WL0 or WL1, and the second program device is switched off in response to the other of the signals E0 or E1 received on the other word line WL0 or WL1, as described above. Fig. 1A - 1D are discussed.

[0052] In some embodiments, Operation 240 repeats Operation 220 to cancel the execution of a program or read operation by the eFuse by switching off both the first and second program devices, as discussed above in relation to Operation 220.

[0053] By performing some or all of the operations of Method 200, the state of an eFuse is determined using a parallel program device configuration such that performing a read operation uses a read current that is less than a program current used in a programming operation, thus using less energy during read operations than approaches in which a single programming device is used to provide a read current in read operations that is equal to a program current provided in programming operations.

[0054] Fig. 3A and Fig. 3B are diagrams of the eFuse R1 in accordance with some embodiments, which are considered to be the ones above in relation to Fig. 1A - 1D discussed eFuse Rfuse are usable. Each of the Fig. 3A and Fig. Figure 3B shows a top view of a construction diagram of the eFuse R1 and the directions X and Y.

[0055] The eFuse R1 is an IC structure according to the invention comprising a conductive element C1 extending along a specific direction between contact areas C2 and C3. In the Fig. In the embodiment shown in 3A, the eFuse R1 has a horizontal orientation, meaning that the conductive element C1 extends along the X-direction. In the embodiment shown in Fig. In the embodiment shown in 3B, the eFuse R1 has a vertical orientation, which means that the conductive element C1 extends along the Y direction.

[0056] Both the conductive element C1 and the contact areas C2 and C3 correspond to an area in an IC assembly diagram used in a manufacturing process to define a segment of one or more conductive materials, non-limiting examples including metal, for example copper or aluminum, or polysilicon. In some embodiments, one or more elements from the group comprising the conductive element C1, the contact area C2, and the contact area C3 are segments of a two-layer metal in an IC manufacturing process.

[0057] The conductive element C1 is designed to be capable of being destructively altered and thereby programmed by a current greater than a predetermined current level, by having a sufficiently small cross-sectional area so that, in operation, the predetermined current level corresponds to a current density capable of generating a destructive temperature through self-heating, and by having a sufficient length so that the thermal resistance in the segment withstands heat dissipation into the contact areas C2 and C3, thus making it possible to reach the destructive temperature.

[0058] In various embodiments, the conductive element C1 is compatible with IC manufacturing processes by having a width (not shown) that is greater than or equal to a minimum width for the conductive layer in which the conductive element C1 is formed, and by having a length (not shown) that is greater than or equal to a minimum length for the conductive layer in which the conductive element C1 is formed.

[0059] The conductive element C1 and the contact areas C2 and C3 have shapes and relative dimensions that are described in the Fig. 3A and Fig. Figure 3B is shown for illustrative purposes. In various embodiments, the conductive element C1 and the contact areas C2 and C3 have shapes and relative dimensions that differ from those shown in the Fig. 3A and Fig. The figures shown in 3B differ.

[0060] Based on the shapes and relative dimensions of the conductive element C1 and the contact areas C2 and C3, and its ability to be programmed as discussed above, the eFuse R1 exhibits a low resistance in the unprogrammed state compared to its resistance in the programmed state. In some embodiments, the resistance of the eFuse R1 in the unprogrammed state ranges from less than 1 Ω to 500 Ω. In some embodiments, the resistance of the eFuse R1 in the unprogrammed state ranges from approximately 5 Ω to 200 Ω. In some embodiments, the resistance of the eFuse R1 in the programmed state ranges from 1 kΩ to more than 100 MΩ. In some embodiments, the resistance of the eFuse R1 in the programmed state ranges from 10 kΩ to 10 MΩ.

[0061] A circuit 100A - 100D, which has an eFuse R1 as eFuse Rfuse, which is described above in relation to the Fig. As discussed in 1A - 1D, it is thus designed to realize the advantages discussed above in relation to circuits 100A - 100D.

[0062] Fig. 4A - 4G are diagrams of the eFuse structures 400A - 400G in accordance with some embodiments. Each of the Fig. 4A - 4G shows a top view of an IC assembly diagram of a respective eFuse structure 400A - 400G and the directions X and Y.

[0063] Each of the eFuse structures 4004 - 400G comprises the eFuse R1 and, according to the invention, two or more FinFETs FF1 - FF4. In each of the in Fig. In the embodiments shown in 4A - 4G, the eFuse R1 is capable of either the above-mentioned Fig. 3A discussed horizontal alignment or the above in relation to Fig. 3B discussed exhibiting a vertical orientation.

[0064] The FinFETs FF1 and FF2 are capable of being used as NMOS transistors N0 and N1 of circuit 100B, or as PMOS transistors P0 and P1 of circuit 100D, and the FinFETs FF3 and FF4 are capable of being used as additional parallel transistors as described above. Fig. 1B and Fig. 1D are discussed. Consequently, all two or more FinFETs FF1 - FF4 are either type n or type p FinFETs.

[0065] Each of the FinFETs FF1 - FF4 is represented in an IC schematic diagram of an IC structure according to the invention, comprising fin structures F1 and F2 extending along the X-direction and gate structures G1 and G2 extending along the Y-direction, wherein each of the fin structures F1 and F2 intersects with each of the gate structures G1 and G2. In some embodiments, the FinFETs FF1 - FF4 have fin structures F1 and F2 extending along the X-direction as well as gate structures G1 and G2 extending along the X-direction.

[0066] In the embodiments described in Fig. As shown in Figures 4A-4G, each of the FinFETs FF1-FF4 has, for illustrative purposes, two fin structures F1 and F2 and two gate structures G1 and G2. In various embodiments, one or more of the FinFETs FF1-FF4 have only one of the fin structures F1 or F2, or one or more fin structures (not shown) in addition to the fin structures F1 and F2, and / or only one of the gate structures G1 and G2, or one or more gate structures (not shown) in addition to the gate structures G1 and G2.

[0067] In the embodiments described in Fig. As shown in Figures 4A-4G, each of the FinFETs FF1-FF4 has, for illustrative purposes, two fin structures F1 and F2 and two gate structures G1 and G2. In various embodiments, one or more of the FinFETs FF1-FF4 have a number of fin structures that differs from the number of fin structures of one or more of the other FinFETs FF1-FF4, and / or one or more of the FinFETs FF1-FF4 have a number of gate structures that differs from the number of gate structures of one or more of the other FinFETs FF1-FF4.

[0068] The illustrations of Fig. 4A - 4G are simplified for clarity. The IC assembly diagrams of the eFuse structures 400A - 400G, featuring the FinFETs FF1 - FF4, include additional components (not shown) beyond the fin structures F1 and F2 and the gate structures G1 and G2 within and between the FinFETs FF1 - FF4 and the eFuse R1. Non-restrictive examples of these additional components include type n and / or type p active regions within which the fin structures F1 and F2 are located, fin structure components, gate structure components, source / drain regions and contacts, and polysilicon, metal, or other conductive regions.

[0069] Consequently, the eFuse structures comprise 400A - 400G, which correspond to the IC assembly diagrams, each of which is in Fig. 4A - 4G are depicted, correspond to IC structural features in addition to those defined by the depicted structural elements, as below in relation to an IC manufacturing system 800, an IC manufacturing flow associated therewith and Fig. 8 is discussed further.

[0070] In the IC assembly diagram of the eFuse structure 400A, which is in Fig. As shown in Figure 4A, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the Y direction, with the eFuse R1 positioned between the FinFETs FF1 and FF2. In the IC assembly diagram of the eFuse structure 400B, shown in Figure 4A, the FinFETs FF1 and FF2 are aligned along the Y direction. Fig. As shown in Figure 4B, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the X direction, with the eFuse R1 positioned between the FinFETs FF1 and FF2.

[0071] In the IC assembly diagram of the eFuse structure 400C, which is in Fig. As shown in Figure 4C, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the Y-direction, with the eFuse R1 positioned between the FinFETs FF1 and FF2, and the FinFETs FF3 and FF4 are aligned along the X-direction, with the eFuse R1 positioned between the FinFETs FF3 and FF4. In some embodiments, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the X-direction, and the FinFETs FF3 and FF4 and the eFuse R1 are aligned along the Y-direction.

[0072] In the IC assembly diagram of the eFuse structure 400D, which is in Fig. As shown in the 4D diagram, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the Y direction, with the FinFET FF2 positioned between the FinFET FF1 and the eFuse R1. In the IC assembly diagram of the eFuse structure 400E, which is shown in Fig. As shown in Figure 4E, the FinFETs FF1 and FF2 and the eFuse R1 are aligned along the Y direction, with the FinFET FF1 positioned between the eFuse R1 and the FinFET FF2.

[0073] In the IC assembly diagrams of the eFuse structures 400F and 400G, which are in Fig. In the diagrams 4F and 4G, the FinFETs FF1–FF3 and the eFuse R1 are aligned along the Y-direction, with the FinFET FF2 and the eFuse R1 positioned between the FinFETs FF1 and FF3. In various embodiments, an IC schematic of one or more of the eFuse structures 400F or 400G includes one or more FinFETs (not shown), for example, FinFET FF4, in addition to the FinFETs FF1–FF3.

[0074] In the Fig. In embodiments 4D-4G, the eFuse R1 and two or more of the FinFETs FF1-FF3 are aligned in the Y direction. In various embodiments, an IC assembly diagram of one or more of the eFuse structures 400D-400G comprises two or more of the FinFETs FF1-FF3 aligned in the X direction.

[0075] A circuit 100B or 100D, which includes the eFuse R1 as eFuse Rfuse and the FinFETs FF1 and FF2 either as NMOS transistors N0 and N1 or as PMOS transistors P0 and P1, which are described above in relation to Fig. 1B and Fig. 1D are discussed, and in accordance with one of the embodiments of the Fig. Once 4A - 4G is set up, it is able to realize the advantages discussed above with regard to the 100A - 100D circuits.

[0076] An IC structure set up according to an IC assembly diagram in accordance with one of the embodiments of the Fig. 4A - 4G includes parallel program current paths and greater routing flexibility than approaches in which an eFuse is programmed by a single program device, and is therefore able to exhibit a lower program current path resistance compared to approaches in which an eFuse is programmed by a single program device.

[0077] Fig. 5A and Fig. Figure 5B shows diagrams of the eFuse structures 500A and 500B in accordance with some embodiments of the invention. Each of the Fig. 5A and Fig. Figure 5B shows a top view of an IC assembly diagram of a respective eFuse structure 500A or 500B and the directions X and Y.

[0078] Each of the eFuse structures 500A and 500B has the signal lines WL0 and WL1, which are described above in relation to Fig. Sections 1A - 1D discuss the eFuse R1, which is mentioned above in relation to Fig. 3A and Fig. Section 3B discusses the FinFETs FF1 and FF2, which were mentioned above in relation to Fig. Sections 4A-4G discuss the signal lines WL2 and WL3 and the bit lines BLo and BL1. Signal line WL2 can be used as signal line WL0, signal line WL3 can be used as signal line WL1, and each of the bit lines BLo and BL1 can be used as bit line BL, as described above. Fig. 1A - 1D is discussed. In each of the in Fig. 5A and Fig. In the embodiments shown in 5B, the eFuse R1 is able to perform either the above-mentioned functions with regard to Fig. 3A discussed horizontal alignment or the above in relation to Fig. 3B discussed exhibiting a vertical orientation.

[0079] In the Fig. In the embodiment shown in Figure 5A, the IC assembly diagram of the eFuse structure 500A includes the signal line WL0, which is arranged between first pairs of FinFETs FF1 and eFuses R1, the signal line WL1, which is arranged between the first pair of eFuses R1 and a first pair of FinFETs FF2, the signal line WL2, which is arranged between second pairs of FinFETs FF1 and eFuses R1, and the signal line WL3, which is arranged between the second pair of eFuses R1 and a second pair of FinFETs FF2.

[0080] In the Fig. In the embodiment shown in Figure 5B, the IC assembly diagram of the eFuse structure 500B comprises a first pair of FinFETs FF1 arranged between the signal line WL0 and a first pair of eFuses R1, a first pair of FinFETs FF2 arranged between the first pair of eFuses R1 and the signal line WL1, a second pair of FinFETs FF1 arranged between the signal line WL2 and a second pair of eFuses R1, and a second pair of FinFETs FF2 arranged between the second pair of eFuses R1 and the signal line WL3.

[0081] In the Fig. 5A and Fig. In the embodiments shown in Figure 5B, each of the IC assembly diagrams corresponding to eFuse structures 500A and 500B comprises the bit line BL0, which is aligned in the Y direction across the first two of the eFuses R1, and the bit line BL1, which is aligned in the Y direction across the second two of the eFuses R1. In some embodiments, an eFuse structure 500A or 500B is a section of a memory circuit in which a specific memory cell includes an eFuse R1 and corresponding FinFETs FF1 and FF2.

[0082] For the sake of clarity, the illustrations of Fig. 5A and Fig. 5B is simplified insofar as the FinFETs FF1 and FF2 do not show fin structures F1 and F2 and gate structures G1 and G2, and the assembly diagrams of the relevant eFuse structures 500A and 500B do not show any assembly elements in addition to the FinFETs FF1 and FF2, the eFuse R1, the signal lines WL0 - WL3 and the bit lines BLo and BL1. As a non-limiting example, at a position where a particular bit line BLo or BL1 is arranged above a particular eFuse R1, an IC assembly diagram of the eFuse structure 500A or 500B includes one or more conductive areas (not shown), such that an eFuse structure 500A or 500B, fabricated based on the IC assembly diagram, provides an electrical connection between the relevant bit line BLo or BL1 and a conductive segment defined by one of the contact areas C2 or C3 of the eFuse R2, which are described above in relation to Fig. 3A and Fig. 3B are discussed, exhibits.

[0083] Additional non-restrictive examples of structural elements that are in Fig. 5A and Fig. 5B, which are not shown but are included in some embodiments of the IC flowcharts of the eFuse structures 500A and / or 500B, comprise the active areas of type n and / or type p, within which the fin structures F1 and F2 are arranged, fin structure components, gate structure components, source / drain areas and contacts, and polysilicon, metal or other conductive areas.

[0084] Consequently, the eFuse structures comprise 500A and 500B, which correspond to the IC assembly diagrams shown in the respective [documents / sections]. Fig. 5A and Fig. 5B are shown, corresponding IC structural features in addition to those defined by the illustrated structural elements, as below in relation to an IC manufacturing system 800, an IC manufacturing flow associated therewith and Fig. 8 is discussed further.

[0085] In the Fig. 5A and Fig. In the embodiments shown in Figure 5B, each of the IC diagrams of the respective eFuse structures 500A and 500B comprises four eFuses R1 arranged in two rows and two columns. In various embodiments, an IC diagram of an eFuse structure 500A or 500B comprises fewer or more than four eFuses R1, fewer or more than two rows of eFuses R1, and fewer or more than two columns of eFuses R1. In some embodiments, an IC diagram of an eFuse structure 500A or 500B comprises a single eFuse R1.

[0086] In the Fig. 5A and Fig. In the embodiments shown in Figure 5B, each of the IC diagrams of the respective eFuse structures 500A and 500B comprises signal lines WL0–WL3 aligned along the X direction, bit lines BLo and BL1 aligned along the Y direction, and FinFETs FF1 and FF2 as well as eFuse R1 aligned along the Y direction. In some embodiments, an IC diagram of an eFuse structure 500A or 500B comprises signal lines WL0–WL3 aligned along the Y direction, bit lines BLo and BL1 aligned along the X direction, and FinFETs FF1 and FF2 as well as eFuse R1 aligned along the X direction.

[0087] In the Fig. 5A and Fig. In the embodiments shown in 5B, each of the IC assembly diagrams of the respective eFuse structures 500A and 500B corresponds to the IC assembly diagram of the eFuse structure 400A, which is shown above in relation to Fig. 4A is discussed. In embodiments in which signal lines WL0 - WL3 are arranged along the Y direction, bit lines BLo and BL1 are arranged along the X direction, and FinFETs FF1 and FF2 as well as eFuse R1 are arranged along the X direction, an IC assembly diagram of an eFuse structure 500A or 500B corresponds to the IC assembly diagram of the eFuse structure 400B discussed above with respect to Fig. 4B is discussed.

[0088] In various embodiments, an IC assembly diagram of an eFuse structure 500A or 500B corresponds to an IC assembly diagram of one of the eFuse structures 400C - 400G in that it includes one or both of the FinFETs FF3 or FF4, as shown in the respective Fig. 4C - 4G shown.

[0089] A circuit 100B or 100D comprising the eFuse R1 as eFuse Rfuse and the FinFETs FF1 and FF2, configured in accordance with one of the embodiments of the Fig. 5A or Fig. 5B is therefore able to realize the advantages discussed above with regard to the 100A - 100D circuits.

[0090] Fig. Figure 6 is a diagram of an eFuse structure 600 in accordance with some embodiments. Fig. Figure 6 shows a top view of an IC assembly diagram of the eFuse structure 600, comprising FinFETs 600FF1 and 600FF2, a conductive eFuse element 600C1 arranged between the FinFETs 600FF1 and 600FF2, a word line 600WL0 arranged between the FinFET 600FF1 and the conductive eFuse element 600C1, and a word line 600WL1 arranged between the conductive eFuse element 600C1 and the FinFET 600FF2.

[0091] The word lines 600WL0 and 600WL1 can be used as the signal lines WL0 and WL1, which are referred to above. Fig. 1A - 1D are discussed, and the conductive eFuse element 600C1 is usable as conductive element C1, which is discussed above in relation to Fig. 3A and Fig. 3B is discussed. The FinFETs 600FF1 and 600FF2 can be used as the FinFETs FF1 and FF2 mentioned above in relation to Fig. 4A - 4G are discussed, arranged in accordance with the IC structure diagram of the eFuse 500A, which is referred to above. Fig. 5A is discussed. In some embodiments, the FinFETs 600FF1 and 600FF2 are arranged in accordance with the IC layout diagram of the eFuse structure 500B, which is discussed above in relation to Fig. 5B is discussed.

[0092] The FinFETs 600FF1 and 600FF2 each comprise the active regions 600A1 and 600A2, which are used to define an active region of an IC structure in which fin structures 600F are formed. Each of the FinFETs 600FF1 and 600FF2 has gate structures 600G that are arranged perpendicular to and overlap each of the fin structures 600F. The fin structures 600F correspond to fin structures F1 and F2 of the FinFETs FF1–FF4, and the gate structures 600G correspond to gate structures G1 and G2 of the FinFETs FF1–FF4, which are described above in relation to Fig. 4A - 4G are discussed.

[0093] In the embodiment described in Fig. As shown in Figure 6, each of the FinFETs 600FF1 and 600FF2 has twelve fin structures 600F and twelve gate structures 600G. In various embodiments, one or both of the FinFETs 600FF1 or 600FF2 have fewer or more than twelve fin structures 600F and / or fewer or more than twelve gate structures 600G.

[0094] In the embodiment described in Fig. As shown in Figure 6, each of the FinFETs 600FF1 and 600FF2 has the same number of fin structures 600F and gate structures 600G. In various embodiments, one of the FinFETs 600FF1 or 600FF2 has a greater number of fin structures 600F than the other. In various embodiments, one of the FinFETs 600FF1 or 600FF2 has a greater number of gate structures than the other.

[0095] The illustration of Fig. Figure 6 is simplified for clarity. IC assembly diagrams showing an IC assembly diagram of the eFuse structure 600 include component elements (not shown) in addition to the FinFETs 600FF1 and 600FF2, the word lines 600WL0 and 600WL1, and the conductive eFuse element 600C1. Non-restrictive examples of additional component elements include fin structure components, gate structure components, source / drain regions and contacts, eFuse contact regions, and polysilicon, metal, or other conductive regions.

[0096] Consequently, an eFuse structure comprises 600, which corresponds to the IC assembly diagram shown in Fig. Figure 6 corresponds to IC structural features in addition to those defined by the illustrated structural elements, as shown below in relation to an IC manufacturing system 800, an IC manufacturing flow in connection therewith and Fig. 8 is discussed further.

[0097] A circuit 100B or 100D, comprising the conductive eFuse element 600C1 in the eFuse Rfuse, the FinFETs 600FF1 and 600FF2 either as NMOS transistors N0 and N1 or as PMOS transistors P0 and P1, and the word lines 600WL0 and 600WL1 as signal lines WL0 and WL1, arranged in accordance with the embodiment of Fig. 6, is thus able to realize the advantages discussed above with regard to the 100A - 100D circuits and with regard to the IC assembly diagram of the eFuse structure 500A.

[0098] By featuring two FinFETs with independently configurable numbers of fin and gate structures instead of a single program device, an IC structure corresponding to the IC assembly diagram implementation form of Fig. 6. able to have a reduced area compared to approaches in which an eFuse is programmed by a single programming device.

[0099] Fig. Figure 7 is a block diagram of an Electronic Design Automation (EDA) 700 system in accordance with some embodiments.

[0100] In some embodiments, the EDA system 700 incorporates an APR system. Unclaimed methods for designing assembly diagrams described herein represent wire guidance arrangements in accordance with one or more embodiments and are, in accordance with some embodiments, for example, implementable using the EDA system 700.

[0101] In some embodiments, the EDA system 700 is a multi-purpose data processing device comprising a hardware processor 702 and a non-volatile, computer-readable storage medium 704. The storage medium 704 is, among other things, encoded with, that is, stores, computer program code 706, i.e., a set of executable instructions. The execution of the instructions 706 by the hardware processor 702 constitutes (at least in part) an EDA tool that implements a section of, or a complete, unclaimed method 900, described below with respect to Fig. 9 is described (hereinafter referred to as the listed processes and / or procedures).

[0102] The processor 702 is electrically coupled to the computer-readable storage medium 704 via a bus 708. The processor 702 is also electrically coupled to an I / O interface 710 via the bus 708. A network interface 712 is likewise electrically coupled to the processor 702 via the bus 708. The network interface 712 is connected to a network 714, enabling the processor 702 and the computer-readable storage medium 704 to communicate with external elements via the network 714. The processor 702 is configured to execute computer program code 706, which is encoded in the computer-readable storage medium 704, to enable the system 700 to execute a portion or all of the listed processes and / or procedures.In one or more embodiments, the 702 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0103] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or a corresponding device or apparatus). For example, the computer-readable storage medium 704 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, random-access memory (RAM), read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0104] In one or more embodiments, the storage medium 704 stores computer program code 706, which is configured to cause the system 700 (in which the execution (at least partially) represents the EDA tool) to be usable for executing a section or all of the listed processes and / or procedures. In one or more embodiments, the storage medium 704 also stores information that enables the execution of a section or all of the listed processes and / or procedures. In one or more embodiments, the storage medium 704 stores the library 707 of standard cells comprising standard cells disclosed herein, for example, a memory cell comprising an eFuse R1, as described above in relation to Fig. 3A and Fig. 3B discussed.

[0105] The EDA system 700 includes the input / output (I / O) interface 710. The I / O interface 710 is connected to an external circuit. In one or more embodiments, the I / O interface 710 includes a keyboard, a keypad, a mouse, a control ball, a touchpad, and / or cursor direction keys for transmitting information and commands to the processor 702.

[0106] The EDA system 700 also includes the network interface 712, which is connected to the processor 702. The network interface 712 enables the system 700 to communicate with the network 714, to which one or more other computer systems are connected. The network interface 712 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-1364. In one or more embodiments, one or more of the processes and / or methods listed are implemented in two or more systems 700.

[0107] The System 700 is configured to receive information through the I / O interface 710. The information received through the I / O interface 710 comprises one or more elements from the group consisting of commands, data, design rules, libraries of standard cells, and / or other parameters for processing by the processor 702. The information is transmitted to the processor 702 via the bus 708. The EDA System 700 is also configured to receive information related to a user interface (UI) through the I / O interface 710. This information is stored on the computer-readable medium 704 as the user interface (UI) 742.

[0108] In some embodiments, one or all of the listed processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, one or all of the listed processes and / or methods are implemented as a software application that forms part of an additional software application. In some embodiments, one or all of the listed processes and / or methods are implemented as an add-on module (plug-in) of a software application. In some embodiments, at least one of the listed processes and / or methods is implemented as a software application that forms part of an additional EDA tool. In some embodiments, one or all of the listed processes and / or methods are implemented as a software application used by the EDA System 700.In some embodiments, the assembly diagram, which has standard cells, is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable assembly creation tool.

[0109] In some embodiments, the processes are implemented as functions of a program stored on a non-volatile, computer-readable recording medium. Examples of a non-volatile, computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, for example, one or more elements from the group comprising an optical disc, such as a DVD; a magnetic disk, such as a hard disk; a semiconductor memory, such as a ROM; a RAM; a memory card; and the like.

[0110] Fig. Figure 8 is a block diagram of an IC fabrication system 800 and an associated IC fabrication flow in accordance with some embodiments. In some embodiments based on a build-up diagram, at least one (A) or more semiconductor masks or (B) at least one component in a layer of an integrated semiconductor circuit is fabricated using the fabrication system 800.

[0111] In Fig. 8 comprises an IC manufacturing system 800 units, such as a design house 820, a mask house 830, and an IC manufacturer / fabricator (“fab”) 850, which cooperate with each other with respect to design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 860. The units in the system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each unit interacts with one or more of the other units and provides or receives services from one or more of the other units.In some embodiments, two or more of the units Design House 820, Mask House 830, and IC Manufacturer 850 are owned by a single larger company. In some embodiments, two or more of the units Design House 820, Mask House 830, and IC Manufacturer 850 are located in a common facility and share resources.

[0112] The design house (or design team) 820 generates an IC design assembly diagram 822. The IC design assembly diagram 822 has various geometric structures, e.g., an IC assembly diagram that is in Fig. 3A, 3B, 4A - 4G, 5A, 5B or 6 shown and designed for an IC component 860, e.g. the eFuse R1 or eFuse structures 400A - 400G, 5004, 500B or 600, as above in relation to Fig. 3A, 3B, 4A - 4G, 5A, 5B, and 6 are discussed. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 860 to be manufactured. The different layers combine to form various IC functions. For example, one section of the IC design flowchart 822 includes various IC functions, such as an active area, a gate electrode, source and drain, metal traces or vias of an interlayer connection, and openings for contact fields to be formed in a semiconductor substrate (such as a silicon wafer), and various metal layers arranged on the semiconductor substrate. The design house 820 implements a suitable design procedure to form the IC design flowchart 822.The design process comprises either a logical design and / or a physical design, or site and routing. The IC design diagram 822 is contained in one or more data files, which include information about the geometric structures. For example, the IC design diagram 822 can be expressed in a GDSII file format or a DFII file format.

[0113] The mask house 830 comprises the data preparation 832 and the mask fabrication 844. The mask house 830 uses the IC design assembly diagram 822 to fabricate one or more masks 845, which are used to fabricate the various layers of the IC device 860 according to the IC design assembly diagram 822. The mask house 830 performs the mask data preparation 832, in which the IC design assembly diagram 822 is translated into a representative data file (“RDF”). The mask data preparation 832 provides the RDF to the mask fabrication 844. The mask fabrication 844 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reed plate) 845 or a semiconductor wafer 853. The design layout diagram 822 is processed by the mask data preparation 832 to meet the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 850. Fig. Figure 10 illustrates the mask data preparation 832 and the mask production 844 as separate elements. In some embodiments, the mask data preparation 832 and the mask production 844 can be referred to together as mask data preparation.

[0114] In some embodiments, the mask data preparation 832 includes near-field optical correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those caused by diffraction, interference, other process effects, and the like. The OPC adapts the IC design layout diagram 822. In some embodiments, the mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliaries, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, reverse lithography technology (ILT) is also used, which treats OPC as a reverse image preparation problem.

[0115] In some embodiments, the mask data preparation 832 includes a mask rule checker (MRC) that verifies the IC design assembly diagram 822, which has undergone OPC processes, against a set of mask creation rules that include certain geometric and / or connection constraints to ensure sufficient clearances, accommodate variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design assembly diagram 822 to compensate for constraints encountered during mask fabrication 844, which could undo some of the modifications made by the OPC to comply with mask creation rules.

[0116] In some embodiments, the mask data preparation 832 includes a lithography process check (LPC) that simulates the processing performed by the IC manufacturer 850 to manufacture the IC device 860. The LPC simulates this processing based on the IC design assembly diagram 822 to create a simulated manufactured device, such as the IC device 860. The process parameters of the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of field (DOF), mask defect improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, OPC and / or MRC are repeated after a simulated manufactured device has been created by LPC if the simulated device does not sufficiently meet the design rules with respect to its shape in order to further refine the IC design assembly diagram 822.

[0117] It is understood that the above description of the mask data preparation 832 has been simplified for clarity. In some embodiments, the data preparation 832 includes additional functions, such as a logical operation (LOP), to modify the IC design assembly diagram 822 according to the manufacturing rules. Furthermore, the processes performed on the IC design assembly diagram 822 during the data preparation 832 can be executed in a variety of different sequences.

[0118] Following mask data preparation 832 and during mask fabrication 844, a mask 845 or a group of masks 845 is fabricated based on the modified IC design assembly diagram 822. In some embodiments, mask fabrication 844 includes performing one or more lithographic exposures based on the IC design assembly diagram 822. In some embodiments, an electron beam (E-beam) or a mechanism consisting of multiple E-beams is used to form a structure on a mask (photomask or reticle) 845 based on the modified IC design assembly diagram 822. The mask 845 can be formed using various technologies. In some embodiments, the mask 845 is formed using a binary technology. In some embodiments, a mask structure has opaque and transparent areas.A beam of radiation, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) with which a wafer has been coated, is blocked by the opaque area and penetrates the transparent areas. In one example, a binary mask version of the 845 mask has a transparent substrate (e.g., quartz glass) and an opaque material (e.g., chromium) with which the opaque areas of the binary mask are coated. In another example, the 845 mask is formed using a phase-shift technology. In a phase-shift mask (PSM) version of the 845 mask, various features in the structure formed on the phase-shift mask are configured to exhibit an appropriate phase difference to improve resolution and image quality.In various examples, the phase-shift mask can be a damped PSM or an alternating PSM. The mask(s) produced by mask fabrication 844 are used in a variety of processes. For example, such a mask is used in an ion implantation process to form different doped regions in the semiconductor wafer 853, in an etching process to form different etched regions in the semiconductor wafer 853, and / or in other suitable processes.

[0119] IC Manufacturer 850 provides wafer manufacturing 852. IC Manufacturer 850 is an IC manufacturing company that has one or more facilities for manufacturing a variety of different IC products. In some embodiments, IC Manufacturer 850 is a semiconductor manufacturer. For example, there might be one manufacturing facility for front-end manufacturing of a variety of IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility provides back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility provides other services to the manufacturing company.

[0120] IC manufacturer 850 uses masks 845, produced by mask house 830, to fabricate IC device 860. Thus, IC manufacturer 850 uses, at least indirectly, IC design assembly diagram 822 to fabricate IC device 860. In some embodiments, IC manufacturer 850 fabricates semiconductor wafer 853 using masks 845 to form IC device 860. In some embodiments, IC fabrication includes performing one or more lithographic exposures, at least indirectly based on IC design assembly diagram 822. Semiconductor wafer 853 has a silicon substrate or other suitable substrates on which material layers are formed. The semiconductor wafer 853 further exhibits one or more different doped regions, dielectric properties, multi-level interconnections and the like (which are formed in successive manufacturing steps).

[0121] Details relating to an integrated circuit (IC) manufacturing system (e.g. System 800 from Fig. 8) and an IC manufacturing flow related thereto can be found, for example, in US Patent No. 9,256,709, granted on February 9, 2016, US Pre-grant Publication No. 20150278429, published on October 1, 2015, US Pre-grant Publication No. 20140040838, published on February 6, 2014, and US Patent No. 7,260,442, granted on August 21, 2007, which are incorporated herein by reference in their entirety.

[0122] Fig. Figure 9 is a flowchart of an unclaimed method 900 for generating a schematic diagram of an IC in accordance with some embodiments. The operations of method 900 are capable of, as part of a method for forming one or more IC devices comprising one or more eFuse structures, for example eFuse R1 or eFuse structures 400A - 400G, 5004, 500B or 600, which are described above in relation to Fig. 3A, 3B, 4A - 4G, 5A, 5B and 6 are discussed and are to be manufactured based on the generated IC assembly diagram. Non-restrictive examples of IC components include memory circuits, logic devices, processing devices, signal processing circuits and the like.

[0123] In some embodiments, some or all of the operations of Method 900 can be performed as part of an APR method. In some embodiments, some or all of the operations of Method 900 can be performed by an APR system, for example, a system included in the EDA system 700, which is described above in relation to Fig. 7 is discussed and set up to carry out the APR procedure.

[0124] Some or all of the operations of Procedure 900 can be performed as part of a design procedure in a design house, e.g., Design House 820, which is described above in relation to Fig. 8 is discussed, to be carried out.

[0125] In some embodiments, part or all of the method 900 is executed by a computer processor. In some embodiments, part or all of the method 900 is executed by a processor 702 of the EDA system 700, which is described above in relation to Fig. 7 is discussed.

[0126] In some embodiments, the operations of method 900 are performed in the Fig. The operations of method 900 are performed in the order shown in Figure 9. In some embodiments, the operations of method 900 are performed in a different order than that shown in Figure 9. Fig. The sequence shown in 9 is carried out. In some embodiments, one or more operations are performed before, between, during and / or after the execution of one or more operations of method 900.

[0127] In Operation 910, an eFuse and first and second program devices are arranged in a cell diagram. The arrangement of the eFuse and the first and second program devices includes arranging components in the cell diagram to ensure that the first and second program devices, constructed based on the IC diagram, are aligned parallel to each other and in series with the eFuse. In some embodiments, the arrangement of the eFuse and the first and second program devices includes arranging components in the cell diagram to ensure that the eFuse and the first program device, constructed based on the IC diagram, are connected in series between a bit line and a program node, and to ensure that the eFuse and the second program device, constructed based on the IC diagram, are connected in series between the bit line and the program node.

[0128] In some embodiments, the arrangement of the eFuse and the first and second program devices includes arranging the eFuse and the first and second program devices in a memory cell of a memory circuit. In some embodiments, the arrangement of the eFuse and the first and second program devices includes arranging one or more program devices in the cell in addition to the first and second program devices.

[0129] In some embodiments, the arrangement of the eFuse and the first and second program devices includes the arrangement of the eFuse R1, which is described above in relation to Fig. 3A and Fig. 3B is discussed. In some embodiments, the arrangement of the eFuse and the first and second program devices includes the arrangement of the program devices PDo and PD1, which are discussed above in relation to Fig. 1A - 1D are discussed.

[0130] In some embodiments, the arrangement of the eFuse and the first and second program devices includes the arrangement of two or more FinFET devices in the cell. In other embodiments, the arrangement of the eFuse and the first and second program devices includes the arrangement of two or more FinFET devices in accordance with one or more of the IC layout diagrams shown in Fig. 3A, 3B, 4A - 4G, 5A, 5B or 6 are shown, and according to the respective eFuse structures 400A - 400G, 500A, 500B or 600.

[0131] In some embodiments, the arrangement of the eFuse and the first and second program devices includes the arrangement of one or more components to cause the IC component, fabricated according to the IC assembly diagram, to have an electrical connection between the eFuse and a bit line located above the cell. In various embodiments, the bit line is the bit line BL discussed above with reference to FIG. 1A-1D, or one of the bit lines BLo or BL1 discussed above with reference to FIG. Fig. 5A and Fig. 5B are discussed.

[0132] In some embodiments of Operation 920, the first and second word lines are arranged in the cell's assembly diagram. Arranging the first and second word lines involves placing components to ensure that the IC, fabricated based on the IC assembly diagram, has an electrical connection between the first program device and the first word line, as well as an electrical connection between the second program device and the second word line.

[0133] In some embodiments, the arrangement of the first and second word lines includes the arrangement of components to cause the IC device, fabricated based on the IC assembly diagram, to have an electrical connection between a gate of a first FinFET and the first word line, and an electrical connection between a second FinFET and the second word line. In various embodiments, the first and second FinFETs are the FinFETs FF1 and FF2, which are referred to above in relation to Fig. 4A - 5B are discussed, or the FinFETs 600FF1 and 600FF2, which are mentioned above in relation to Fig. 6 are discussed.

[0134] In various embodiments, the arrangement of the first and second word lines includes the arrangement of the signal lines WLo and WL1 or WL2 and WL3, which are discussed above in relation to 1A - 1D, 5A and 5B.

[0135] In Operation 930, the IC assembly diagram is stored in a storage device in some embodiments. In various embodiments, storing the IC assembly diagram in the storage device includes storing the IC assembly diagram in non-volatile, computer-readable memory or a cell library, e.g., a database, and / or includes storing the IC assembly diagram over a network. In some embodiments, storing the IC assembly diagram in the storage device includes storing the IC assembly diagram over the network 714 of the EDA system 700, which is described above in relation to Fig. 7 is discussed.

[0136] In some embodiments, Operation 940 involves fabricating at least one or more semiconductor masks or at least one component in a layer of a semiconductor IC based on the IC assembly diagram. The fabrication of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described above in relation to... Fig. 8 discussed.

[0137] In some embodiments, Operation 950 involves performing one or more manufacturing operations based on the IC assembly diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC assembly diagram. Performing one or more manufacturing operations, e.g., one or more lithographic exposures, based on the IC assembly diagram, is described above in relation to Fig. 8 discussed.

[0138] By performing some or all of the operations of procedure 900, an IC assembly diagram is generated in which parallel program devices with an eFuse in one cell are contained. IC assembly diagrams and IC components manufactured based on these IC assembly diagrams are thus able to implement the features discussed above with regard to circuits 100A - 100D and the IC assembly diagrams of the eFuse structures 400A - 400G, 500A, 500B and 600.

[0139] In some unclaimed embodiments, a circuit comprises an eFuse and a first program device connected in series between a bit line and a program node, and a second program device connected in parallel with the first program device; the first program device and the second program device being independently controllable. In some embodiments, both the first program device and the second program device have an NMOS transistor coupled between the eFuse and the program node, configured to carry a reference voltage. In some embodiments, both the first program device and the second program device have a PMOS transistor coupled between the eFuse and the program node, configured to carry a power supply voltage.In some embodiments, the circuit includes a read amplifier coupled to the bit line, wherein, during a read operation of the read amplifier, the first program device is configured to have a low-impedance path between the eFuse and the program node in response to a first signal, and the second program device is configured to have a high-impedance path between the eFuse and the program node in response to a second signal. In some embodiments, the eFuse, the first program device, and the second program device are contained within a first bit cell, and the bit line is shared by the first bit cell and a second bit cell. In some embodiments, both the first program device and the second program device include a FinFET.

[0140] In some embodiments, the unclaimed method for determining a state of an eFuse comprises performing a read operation by switching on a first programming device to cause a first current to flow through the eFuse, and switching off a second programming device, wherein the second programming device is connected in parallel with the first programming device and in series with the eFuse. In some embodiments, the method comprises performing a programming operation by switching on the first programming device and the second programming device to cause a second current to flow through the eFuse, wherein the second current is greater than the first current.In some embodiments, the first program device is switched on during the read operation and switched on during the programming operation in response to a first signal, and the second program device is switched off during the read operation and switched on during the programming operation in response to a second signal. In some embodiments, performing the read operation further includes using a read amplifier to compare a resistance of the eFuse with a reference resistance based on a first current.

[0141] In some embodiments, an IC structure of an eFuse comprises a first FinFET electrically connected to the eFuse and a second FinFET electrically connected in parallel to the first FinFET, wherein the eFuse, the first FinFET, and the second FinFET are aligned along a first direction. In some embodiments, the eFuse is located between the first FinFET and the second FinFET. In some embodiments, the eFuse extends along a second direction perpendicular to the first direction. In some embodiments, both the first FinFET and the second FinFET have at least one fin extending in the second direction. In some embodiments, the IC structure further comprises a third FinFET electrically connected in parallel to the first FinFET and the second FinFET, wherein the eFuse and the third FinFET are aligned along a second direction perpendicular to the first direction.In some embodiments, both the first FinFET and the second FinFET have one or more fins and one or more gates, wherein the number of fins of the first FinFET is greater than or equal to the number of gates of the first FinFET, and the number of fins of the second FinFET is less than the number of gates of the second FinFET. In some embodiments, the IC structure further comprises a first word line coupled to a gate of the first FinFET and a second word line coupled to a gate of the second FinFET. In some embodiments, at least either the first word line is arranged between the eFuse and the first FinFET and / or the second word line is arranged between the eFuse and the second FinFET.In some embodiments, at least either the first FinFET is arranged between the eFuse and the first word line and / or the second FinFET is arranged between the eFuse and the second word line. In some embodiments, the eFuse, the first FinFET, and the second FinFET are contained within a bit cell of a plurality of bit cells, the eFuse is electrically connected to a bit line, and the bit line is electrically connected to each of the bit cells of the plurality of bit cells.

Claims

[1] eFuse structure (500A, 500B), comprising a circuit (100B, 100D): an eFuse (R1) and a first program device (PD0) connected in series between a bit line (BL) and a program node (PN); and a second program device (PD1) connected in parallel with the first program device (PDo), wherein the first program device (PDo) and the second program device (PD1) are separately controllable by a first signal (E0) on a first signal line (WL0) and by a second signal (E1) on a second signal line (WL1), and wherein the first signal line (WL0), the eFuse (R1) and the second signal line (WL1) are arranged in the eFuse structure (500A) between the first (PDo) and the second program device (PD1), or wherein the first program device (PD0), the eFuse (R1) and the second program device (PD1) are arranged in the eFuse structure (500B) between the first (WL0) and the second signal line (WL1). [2] eFuse structure (500A, 500B) according to claim 1, wherein both the first program device (PDo) and the second program device (PD1) comprise an NMOS transistor (N0, N1) coupled between the eFuse (R1) and the program node (PN), wherein the program node (PN) is configured to carry a reference voltage. [3] eFuse structure (500A, 500B) according to claim 1, wherein both the first program device (PDo) and the second program device (PD1) comprise a PMOS transistor (P0, P1) coupled between the eFuse (R1) and the program node (PN), wherein the program node (PN) is configured to carry a power supply voltage. [4] eFuse structure (500A, 500B) according to one of the preceding claims, further comprising a read amplifier coupled to the bit line (BL), wherein during a read operation of the read amplifier the first program device (PDo) is configured to have a low-impedance path between the eFuse (R1) and the program node (PN) in response to the first signal (WL0), and the second program device (PD1) is configured to have a high-impedance path between the eFuse (R1) and the program node (PN) in response to the second signal (WL1). [5] eFuse structure (500A, 500B) according to any one of the preceding claims, wherein the eFuse (R1), the first program device (PDo) and the second program device (PD1) are contained in a first bit cell, and The bit line (BL) is shared by the first bit cell and a second bit cell. [6] eFuse structure (500A, 500B) according to one of the preceding claims, wherein both the first program device (PDo) and the second program device (PD1) comprise a FinFET (FF1, FF2). [7] IC structure encompassing: an eFuse (R1) comprising a conductive element (C1, 600C1); a first FinFET (FF1, 600FF1) which has fin structures (F1, F2) and is electrically connected to the eFuse (R1); and a second FinFET (FF2, 600FF2) electrically connected in parallel with the first FinFET (F1) and having fin structures (F1, F2), wherein the conductive element (C1, 600C1) of the eFuse (R1), the fin structures (F1, F2) of the first FinFET (FF1, 600FF1) and the fin structures (F1, F2) of the second FinFET (FF2) are aligned along a first direction (x). [8] IC structure according to claim 7, wherein the eFuse (R1) is arranged between the first FinFET (FF1, 600FF1) and the second FinFET (FF2, 600FF2). [9] IC structure according to claim 7 or 8, wherein the eFuse (R1) extends along a second direction (y) perpendicular to the first direction (x). [10] IC structure according to claim 9, wherein both the first FinFET (FF1, 600FF1) and the second FinFET (FF2, 600FF2) have at least one fin extending in the second direction (y). [11] IC structure according to any one of claims 7 to 10 above, further comprising a third FinFET (FF3) which is electrically connected in parallel with the first FinFET (FF1, 600FF1) and the second FinFET (FF2, 600FF2), wherein the eFuse (R1) and the third FinFET (FF3) are aligned perpendicular to the first direction (x) along a second direction (y). [12] IC structure according to any one of claims 7 to 11 above, wherein both the first FinFET (FF1, 600FF1) and the second FinFET (FF2, 600FF2) comprise one or more fins and one or more gates, a number of one or more fins of the first FinFET (FF1, 600FF1) is greater than or equal to a number of one or more gates of the first FinFET (FF1, 600FF1), and the number of one or more fins of the second FinFET (FF2, 600FF2) is less than the number of one or more gates of the second FinFET (FF2, 600FF2). [13] IC structure according to any one of claims 7 to 12 above, further comprising: a first word line (600WL0) coupled with a gate of the first FinFET (FF1, 600FF1); and a second word line (600WL1) coupled with a gate of the second FinFET (FF2, 600FF2). [14] IC structure according to claim 13, wherein at least either the first word line (WL0, 600WL0) is arranged between the eFuse (R1) and the first FinFET (FF1, 600FF2), and / or the second word line (WL1, 600WL1) is arranged between the eFuse (R1) and the second FinFET (FF2, 600F2). [15] IC structure according to claim 13 or 14, wherein at least either the first FinFET (FF1, 600FF1) is arranged between the eFuse (R1) and the first word line (WL0, 600WL0), and / or the second FinFET (FF2, 600FF2) is arranged between the eFuse (R1) and the second word line (WL1, 600WL1). [16] IC structure according to any one of claims 7 to 15 above, wherein the eFuse (R1), the first FinFET (FF1, 600FF1) and the second FinFET (FF2, 600FF2) are contained in a bit cell of a plurality of bit cells, the eFuse (R1) is electrically connected to a bit line (BL), and The bit line (BL) is electrically connected to each of the bit cells of the plurality of bit cells.

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