Semiconductor structure with air gap and method for sealing the air gap

Abstract

Method for fabricating a semiconductor structure comprising the following steps: Receiving a substrate (202) with an active region and an isolation region; Forming gate stacks (208) on the substrate (202) extending from the active area to the isolation area; Manufacturing an inner gate spacer (214) and an outer gate spacer (216) on side walls of the gate stacks (208); Forming an interplane dielectric layer (220) on the substrate (202); Removing the outer gate spacer (216) in the isolation area, so that an air gap (402) is created between the inner gate spacer (214) and the interplane dielectric layer (220); and Performing an ion implantation process on the interplane dielectric layer (220), thereby expanding the interplane dielectric layer (220) to cap the air gap (402).

Description

PRIORITY INFORMATION BACKGROUND

[0001] The IC (integrated semiconductor circuit) industry has experienced rapid growth. Technological advances in IC materials and designs have produced generations of ICs, each generation featuring smaller and more complex circuits than the previous one. However, these advances have also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are necessary to realize these advancements. ICs can contain electronic components, such as transistors, capacitors, or the like, fabricated on a substrate. Interconnect structures, such as vias and conductive traces, are then fabricated over the electronic components to create connections between the electronic components and to external components.To reduce the parasitic capacitance of interconnect structures, they can be fabricated in dielectric layers using a low-k dielectric material. However, due to the small dimensions required in modern technology nodes, the parasitic capacitance remains unacceptable even with low-k dielectric materials. To address these problems, a circuit structure and a fabrication method are needed.

[0002] US 2015 / 0228754A1 describes a method for fabricating a semiconductor device, comprising: forming a gate structure over a substrate, forming a multilayer sidewall spacer with a first sacrificial spacer covering sidewalls of the gate structure, and a second sacrificial spacer on a sidewall of the first sacrificial spacer and recessed deeper than an upper surface of the gate structure, forming an air gap with a narrower wide upper section than a middle and a lower section by removing the first and second sacrificial spacers, and forming a cover layer covering the upper section of the air gap.

[0003] US 2015 / 0263122A1 describes a method for forming a FinFET device. A semiconductor fin is formed on a semiconductor substrate. A gate structure with a gate dielectric layer and an overlying gate material layer is formed over the semiconductor fin. Sidewall spacers are formed adjacent to opposite sides of the gate structure. The sidewall spacers comprise a first insulating layer adjacent to the gate structure and a second insulating layer separated from the first insulating layer by an air gap.

[0004] US 5,736,446 A describes a method for fabricating a MOS device with an air gap structure on the gate side. A nitride spacer to reserve the air gap space is formed on the substrate adjacent to the gate structure. An amorphous silicon spacer to form the sidewall spacer and seal the air gap is formed adjacent to the nitride spacer. The upper portion of the amorphous silicon spacer is heavily doped during source / drain implantation. After removal of the nitride spacer, the doped amorphous silicon spacer is oxidized by a wet oxidation process to form a doped oxide spacer. The growing doped oxide spacer closes the opening for the nitride spacer, which is created by the heavily doped upper portion with a higher oxidation rate than other portions.

[0005] US 2013 / 0093019A1 describes a transistor comprising a gate structure over a substrate, having a width, length, and height that define two opposing sidewalls of the gate structure. The transistor further comprises at least one electrically conductive channel between a source region and a drain region, extending through the sidewalls of the gate structure; a dielectric layer arranged over the gate structure and portions of the electrically conductive channel that lie outside the gate structure; and an air gap beneath the dielectric layer. The air gap is arranged adjacent to the sidewalls of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a flowchart showing an embodiment of a method for manufacturing a semiconductor structure or part thereof according to aspects of the present invention. Fig. 2A is a top view of a semiconductor structure configured according to some embodiments, at a manufacturing stage. The Fig. 2B, Fig. 2C and Fig. 2D views are cross-sectional views of the semiconductor structure of Fig. 2A along the dotted lines A - A', B - B' or C - C', which is designed according to some embodiments. Fig. Figure 3 is a top view of the semiconductor structure, which is designed according to some embodiments, at a different manufacturing stage. The Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. Figure 9 shows cross-sectional views of the semiconductor structure, which is formed according to some embodiments and manufacturing stages. DETAILED DESCRIPTION

[0007] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples. For instance, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] The present invention provides a semiconductor structure with an air gap between an interlayer dielectric layer (ILD layer) and a gate spacer. The present invention also provides a method for producing and sealing the air gap. In particular, the method comprises removing a sacrificial gate spacer on an STI element (STI: shallow trench insulation) and performing ion implantation on the ILD layer, such that an upper part of the ILD layer is stretched to cap the air gap.

[0010] Now let's move on to... Fig. 1, in which a flowchart of an embodiment of a method 100 is shown, which is used to produce a semiconductor structure with an air gap arranged between the gate spacer and the ILD layer and capped by the stretched ILD layer. Fig. 2A is a top view, Fig. 2B is a sectional view along the dashed line A - A', Fig. 2C is a sectional view along the dashed line B - B', and Fig. 2D is a sectional view along the dashed line or C - C' of a semiconductor structure 200 at a manufacturing stage according to some embodiments. Fig. Figure 3 is a top view of a later manufacturing stage. Fig. 4, Fig. 5, Fig. 6, Fig. 7 to Fig. Figure 8 shows cross-sectional views of the semiconductor structure 200 along the dashed line B - B' at different manufacturing stages, and Fig. Figure 9 is a sectional view of the semiconductor structure 200 along the dashed line A - A', configured according to various aspects of the present invention, at a manufacturing stage, according to some embodiments. The method 100 and the IC structure 200 are referred to collectively by reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. 9 described.

[0011] In the Fig. In 2A to 2D, the process 100 begins with a step 102 in which a semiconductor substrate 202 is provided. The semiconductor substrate 202 comprises silicon. In some other embodiments, the semiconductor substrate 202 comprises germanium, silicon germanium, or other suitable semiconductor materials. The semiconductor substrate 202 can alternatively be made from the following materials: another suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenide, or gallium indium phosphide.

[0012] The semiconductor substrate also features various doped regions, such as n-wells and p-wells. In one embodiment, the semiconductor substrate 202 has an epitaxial semiconductor layer. In another embodiment, the semiconductor substrate 202 has a buried dielectric insulating material produced by a suitable method, such as the SIMOX process (SIMOX: separation by oxygen implantation). In some embodiments, the semiconductor substrate 202 can be a semiconductor-on-insulator, such as silicon-on-insulator (SOI).

[0013] Let's stick with the Fig. 2A to 2D, in which the process 100 continues to a step 104 in which STI structural elements 204 (STI: shallow trench insulation) are fabricated on the semiconductor substrate 202. In some embodiments, the STI structural elements 204 are fabricated by a process comprising the following steps: etching to create trenches; filling the trenches with a dielectric material by deposition; and polishing to remove excess dielectric material and planarize the top surface. The etching process may include one or more etching steps performed on the semiconductor substrate 202 through openings in a soft mask (such as a photoresist layer fabricated by a lithographic process) or in a hard mask patterned by a lithographic and etching process.

[0014] The etching process is performed on the semiconductor substrate 202 through the openings in a structured mask layer, creating trenches. Suitable etching methods such as dry etching, wet etching, and / or other etching techniques, e.g., reactive ion etching (RIE), can be used for the etching process. In some embodiments, the etching process comprises multiple etching steps with different etching chemicals designed to etch the substrate to create trenches with a specific trench profile for improved device performance and structure density. In some examples, the semiconductor material of the substrate can be etched using a dry etching process with a fluorine-based etchant. The trenches can be filled by deposition with one or more dielectric materials.Suitable dielectric filler materials include semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, fluorosilicate glass (FSG), dielectric low-k materials, and / or combinations thereof. In various embodiments, the dielectric material is deposited by high-density plasma chemical vapor deposition (HDP-CVD), sub-pressure chemical vapor deposition (SACVD), high-aspect-ratio resorption (HARP), flowable CVD (FCVD), and / or spin deposition. A chemical-mechanical polishing / planarization (CMP) process is then performed to remove excess dielectric material and planarize the top surface of the semiconductor structure.

[0015] Following step 104, active regions are defined on the semiconductor substrate 202, which are enclosed by the STI structural elements 204. In some embodiments, the active regions are three-dimensional, such as active fin regions 206, which are produced in step 106.

[0016] In the Fig. In steps 2A to 2D, process 100 continues to step 106, in which the active fin areas 206 are manufactured. The active fin areas 206 are extended over the STI structural elements 204, as shown in Fig. 2D is shown. In some embodiments, step 106 includes the recession of the STI structural elements 204. The recession comprises one or more etching steps (such as dry etching, wet etching, or a combination thereof) to selectively re-etch the STI structural elements 204. For example, a wet etching process using hydrofluoric acid can be employed if the STI structural elements 204 are silicon oxide. The active fin regions 206 are aligned along a first direction (x-direction) and spaced apart from each other in a second direction (y-direction).

[0017] Various doping processes can be performed on the semiconductor substrate 202 to create different doped wells, such as n- and p-wells, at the current stage or before step 106. Different doped wells can be created by respective ion implantations in the semiconductor substrate 202.

[0018] In the Fig. In steps 2A to 2D, the process 100 continues to step 108, in which gate stacks 208 are fabricated on the semiconductor substrate 202. Each gate stack 208 comprises a gate electrode 210 and a dielectric gate layer 212. In the present embodiment, the gate stacks 208 have elongated shapes and are oriented in the second direction (y-direction). The gate stacks 208 can each be arranged over several active fin regions 206. In particular, the gate stacks 208 are arranged on the active fin regions 206 and are extended onto the STI structural elements 204. Thus, each gate stack 208 comprises parts that rest on the active fin regions 206 and parts that rest on the STI structural elements 204.Step 108 further comprises the fabrication of an inner gate spacer 214, an outer gate spacer 216, source / drain (S / D) structural elements 218, and an interplane dielectric layer (ILD layer) 220. Step 108 also comprises several further steps. In the present embodiment, step 108 further comprises steps 110, 112, 114, 116, and 118, which are described later with reference to the following. Fig. 1 and 2A to 2D will be described in more detail.

[0019] Procedure 100 (or step 108) includes step 110, in which dummy gates are manufactured (which are in the Fig. Figures 2A to 2D are not shown because they are to be replaced by the gate stacks 208 in step 118 and are located at the positions of the gate stacks 208. The dummy gates can have a dielectric material layer (such as silicon oxide) and polysilicon. The fabrication of the dummy gates includes depositing the dummy gate materials (such as producing a silicon oxide layer and depositing a polysilicon layer) and structuring the dummy gate materials by lithography and etching. A hard mask can be produced on the dummy gate materials, which is used as an etching mask during the fabrication of the dummy gates. The gate hard mask can have a suitable material such as silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, other suitable materials, and / or combinations thereof. In one embodiment, the gate hard mask has multiple layers, such as silicon oxide and silicon nitride.In some embodiments, the structuring process for producing the dummy gates includes the following steps: producing a structured photoresist layer on the hard mask by lithography; etching the hard mask using the structured resist layer as an etching mask; and etching the gate materials using the structured hard mask as an etching mask to produce the dummy gates.

[0020] Method 100 further comprises a step 112 in which gate spacers, comprising the inner gate spacer 214 and the outer gate spacer 216, are fabricated on sidewalls of the dummy gates. The gate spacers (the inner gate spacer 214 and the outer gate spacer 216) can comprise any suitable dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor carbide, a semiconductor oxide nitride, other suitable dielectric materials, and / or combinations thereof. The inner gate spacer 214 comprises a first dielectric material, and the outer gate spacer 216 comprises a second dielectric material having a different composition than the first dielectric material to achieve etch selectivity.In some embodiments, the first dielectric material is SiCN, SiOCN, SiOC, or a combination thereof, and the second dielectric material is a low-k dielectric material, such as fluorosilicate glass (FSG), carbon-doped silicon dioxide, xerogel, aerogel, amorphous fluorocarbon, polyimide, another suitable low-k dielectric material, or a combination thereof. Fabrication of the gate spacers involves depositing the first and second dielectric materials and performing anisotropic etching, such as dry etching.

[0021] The process 100 then proceeds to step 114, in which the S / D structural elements 218 are fabricated. The S / D structural elements 218 can be either lightly doped drain structural elements (LDD structural elements) or heavily doped source and drain structural elements (S / D structural elements). For example, each field-effect transistor has source and drain structural elements fabricated on the respective active fin regions, between which the corresponding gate stack 208 is arranged. A channel is fabricated in a portion located below the gate stack and extending between the corresponding S / D structural elements 218.

[0022] In some embodiments, the S / D structural elements 218 are raised S / D structural elements produced by selective epitaxial growth for a strain effect with improved support mobility and device performance. The dummy gates, i.e., the inner gate spacer 214 and the outer gate spacer 216, restrict the fabrication of the S / D structural elements 218 to the source and drain regions. In some embodiments, the S / D structural elements 218 are fabricated by one or more epitaxial growth processes in which Si structural elements, SiGe structural elements, SiC structural elements, and / or other suitable structural elements are grown in a crystalline state on the active fin regions 206. Alternatively, the source and drain regions are embedded by an etching process prior to epitaxial growth. For a suitable epitaxial growth process, CVD deposition methods, e.g.,Vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy and / or other suitable methods may be used. Gaseous and / or liquid precursors that interact with the composition of the active fin regions 206 may be used for the epitaxial growth process.

[0023] The S / D structural elements 218 can be doped in situ by introducing dopant species such as p-type dopants, like boron or BF₂, n-type dopants, like phosphorus or arsenic, and / or other suitable dopants, including combinations thereof, during the epitaxy process. If the S / D structural elements 218 are not doped in situ, an implantation process (i.e., a transition implantation process) is performed to introduce the appropriate dopant into the S / D structural elements 218. In one embodiment, the S / D structural elements 218 in an n-type field-effect transistor (nFET) comprise SiC or Si doped with phosphorus, while the S / D structural elements 218 in a p-type field-effect transistor (pFET) comprise Ge or SiGe doped with boron. In some alternative embodiments, the S / D structural elements 218 have more than one semiconductor material layer.For example, a silicon germanium layer is epitaxially grown, and a silicon layer is epitaxially grown on top of the silicon germanium layer. Subsequently, one or more annealing processes can be performed to activate the S / D structural elements 218. Suitable annealing methods include rapid thermal annealing (RTA), laser annealing, other suitable annealing methods, or a combination thereof.

[0024] The process 100 then proceeds to step 116, in which an ILD layer 220 is fabricated on the semiconductor substrate 202 such that it covers the S / D structural elements 218. The S / D structural elements 218 and the active fin regions 206 are in Fig. Figure 2A is not shown, so the structural elements (such as the S / D structural elements 218) located beneath the ILD layer 220 are visible. The ILD layer 220 encloses the dummy gates, i.e., the inner gate spacer 214 and the outer gate spacer 216, so that the dummy gates can be removed and a replacement gate can be fabricated in the resulting gate cavity. In the present embodiment, the composition of the ILD layer 220 is selected such that the strain required for air gap sealing is effectively achieved by an ion implantation process. The ILD layer 220 comprises one or more suitable dielectric materials, such as SiN, SiOC, SiOCN, SiCN, Si, SiGe, SiO2, TiO2, Al2O3, Ge, W, TaN, TiN, HfO2, ZrO2, La2O3, or a combination thereof. The fabrication of the ILD layer 220 involves deposition (such as CVD or HDP-CVD) and CMP to provide a planarized top surface.In some embodiments, step 116 also includes the fabrication of an etch stop layer 222 to provide an etch stop during the steps for making contacts with the S / D structural elements 218. The etch stop layer 222 has a different composition than the ILD layer 220 to achieve a desired etch selectivity. In some embodiments, the etch stop layer 222 comprises SiCN, SiOCN, SiOC, SiN, or a combination thereof.

[0025] Method 100 then proceeds to step 118 for gate replacement. In step 118, the dummy gates are replaced by gate stacks 208, which comprise a high-k dielectric material and a metal. Step 118 includes performing an etching process to selectively remove the dummy gates, creating gate cavities; depositing gate materials (comprising a high-k dielectric material and a metal) in the gate cavities; and performing a CMP process to remove the excess gate materials from the ILD layer 220. Specifically, the gate stacks 208 comprise the gate electrode 210 and the dielectric gate layer 212. The gate electrode 210 comprises a metal, a metal alloy, or a combination thereof. The dielectric gate layer 212 comprises a high-k dielectric material. Since the dielectric gate layer 212 is deposited conformally in the gate cavities, it is U-shaped, as shown in the Fig. 2B and Fig. 2C is shown.

[0026] The dielectric gate layer 212 and the gate electrode 210 can each have a plurality of sublayers. In some embodiments, the dielectric gate layer 212 comprises a high-k dielectric material that is a metal oxide or a metal nitride, such as LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO₃, LaSiO₃, AlSiO₃, HfTaO, HfTiO₃, (Ba,Sr)TiO₃ (BST), Al₂O₃ 33Si3N4, oxide nitrides (e.g., SiON), or other suitable high-k dielectric materials. The dielectric gate layer 212 may also include an interface layer deposited between the high-k dielectric material layer and the active fin region. The interface layer may comprise silicon oxide, silicon nitride, silicon oxide nitride, and / or another suitable material. The interface layer is deposited using a suitable method such as ALD, CVD, ozone oxidation, and the like. The high-k dielectric layer is deposited on the interface layer (if present) using a suitable method such as ALD, CVD, metal-organic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or other suitable methods.

[0027] The gate electrode 210 can comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or other suitable materials. In some embodiments, different metallic materials are used for nFETs and pFETs with respective work functions. For example, the gate electrode 210 can comprise a capping layer, a work function metal layer, and a filler metal layer. In other embodiments, the capping layer comprises titanium nitride, tantalum nitride, or another suitable material deposited by a suitable deposition process such as ALD. The filler metal layer comprises aluminum, copper, silicide, another suitable metal, or a metal alloy deposited by PVD or another suitable deposition process.

[0028] The work function layer (WF layer) comprises a conductive layer of a metal or metal alloy with a suitable work function to improve the device performance of the corresponding FET. The work function layer (WF layer) differs for pFETs and nFETs and is referred to as an n-WF metal and a p-WF metal, respectively. The choice of WF metal depends on the FET being fabricated on the active region. For example, an n-WF metal is a metal with a first work function that reduces the threshold voltage of the associated nFET. An n-WF metal, for instance, has a work function of approximately 4.2 eV or less. A p-WF metal is a metal with a second work function that reduces the threshold voltage of the associated pFET. A p-WF metal, for instance, has a work function of approximately 5.2 eV or more.In some embodiments, the n-WF metal is tantalum (Ta). In other embodiments, the n-WF metal comprises titanium-aluminum (TiAl), titanium-aluminum nitride (TiAlN), or combinations thereof. In some embodiments, the p-WF metal is titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-WF metal comprises TiN, TaN, tungsten nitride (WN), titanium-aluminum (TiAl), or combinations thereof.

[0029] In Fig. 3. Method 100 can include a step 120 for producing a structured mask layer 302 on the semiconductor structure 200 with openings 304 to define areas in which one or more air gaps are to be produced. In the present embodiment, the air gap is produced only on the STI structural elements 204, but not on the active fin areas 206. Fig. Figure 3 is a top view of the semiconductor structure 200. The structured mask layer 302 is in Fig. Figure 3 is shown transparently for better viewing. The structured mask layer 302 can be a soft mask, such as a photoresist produced by a lithographic process, or alternatively a hard mask produced by deposition, a lithographic process, and etching.

[0030] In Fig. 4 the procedure 100 continues to a step 122 in which the outer gate spacer 216 is removed, creating an air gap 402 between the inner gate spacer 214 and the ILD layer 220. Fig. Figure 4 is a sectional view of the semiconductor structure 200 along the x-direction on the STI structural element 204 (along the dashed line A - A' of Fig. 3, but at a different manufacturing stage where the air gap 402 is produced in step 122). In some embodiments, the outer gate spacer 216 is removed by an etching process using the mask layer 302 as an etch mask, such that only the portions of the outer gate spacer 216 on the STI structural elements 204 are removed, while the portions of the outer gate spacer 216 in the active fin regions 206 remain. The ILD layer 220 between adjacent gate stacks 208 extends over a width d1. The air gap 402 has a height h1 and a width d2. In some examples, the ratio d2 / d1 is greater than 10%. In some examples, the ratio d2 / d1 is between 10% and 30%. In other examples, the height h1 is less than 200 nm, the width d1 is 5 nm to 50 nm, and the width d2 is less than 10 nm.

[0031] The etching process can be dry etching, wet etching, or a combination thereof. The openings 304 of the structured mask layer 302 are configured to define the areas for creating the air gaps, but the etching process is still designed with etch selectivity over other structural elements, such as the inner gate spacer 214, the etch stop layer 222, and also the ILD layer 220. Furthermore, the composition of the outer gate spacer 216 differs from the compositions of these other structural elements, and an etchant is chosen for the etching process that selectively removes the outer gate spacer 216 without significantly etching other structural elements, such as the inner gate spacer 214 and the etch stop layer 222.

[0032] In Fig. In step 5, the procedure 100 continues to step 124, in which an ion implantation process is performed on the ILD layer 220, stretching the ILD layer 220 to close the air gap 402. During the ion implantation process, one or more dopants are introduced into an upper part 502 of the ILD layer 220, transforming the upper part 502 into an implanted part, while a lower part 504 of the ILD layer 220 remains as a non-implanted part. The ion implantation process increases the volume of the upper part 502, stretches the upper part 502 laterally, and seals the air gap 402. The extended part 506 of the upper part 502 serves as a cap to seal the air gap 402 and is therefore also referred to as the extended cap 506.In some embodiments, the ion implantation process is performed using the structured mask 302 to restrict implantation to the desired areas. The structured mask layer 302 can be removed after step 124. When the upper part 502 of the ILD layer 220 is stretched, the corresponding part of the etch stop layer 222 is pressed so that it reaches the inner gate spacer 214, thereby capping the air gap 402.

[0033] After the ion implantation process, the upper part 502 of the ILD layer 220 has a height h2 and an upper width d1 + 2 · d2. The air gap 402 is defined between the ILD layer 220 and the gate stack 208. Specifically, the air gap 402 extends vertically and horizontally between the inner gate spacer 214 and the etch stop layer 222. To seal the air gap 402, the ILD layer 220 must be stretched by d2 at each edge to reach the inner gate spacer 214. In other words, the upper surface of the ILD layer 220 stretches horizontally from its original width d1 to a stretched width d1 + 2 · d2. The stretched volume is proportional to d2 / d1. If, for example, the stretched part above the air gap 402 is a triangle, the final volume above the original volume of the upper part 502 is equal to d2 / d1.The volume expansion of the upper part 502 of the ILD layer 220 is associated with the doping concentration and, in some embodiments, is proportional to the doping concentration. For example, if the relative volume expansion of the upper part 502 can reach d2 / d1, the air gap is sealed. The ratio d2 / d1 is greater than 10% in the present embodiment, or 10 to 30% in other embodiments. The ion implantation process is designed to have a doping concentration high enough to ensure that the air gap 402 is sealed by expansion. In some embodiments, the doping concentration is controlled by a combination of ion beam current and implantation duration of the implantation process such that the ILD layer 220 is expanded (e.g., by more than 10%), thus sealing the air gap 402.Therefore, in some embodiments, the ion implantation process has a high dosage, such as the doping concentration in the upper part 502, which is 1E11 to 1E17 atoms / cm. 2 amounts.

[0034] In some embodiments, the ion implantation process is carried out by changing an implantation tilt angle from 60° to -60° while the semiconductor substrate 202 is rotated in different directions for implantation, thereby controlling the shape of the stretched cap 506 of the upper part 502 of the ILD layer 220. The shape of the stretched cap 506 is also related to the height h2 of the upper part 502, which is controlled by the implantation energy. The height h2 is controlled to a range, e.g., less than 50 nm, for a maximized air gap volume 402 and with an effective sealing effect. By controlling a combination of the dosage, ion beam current, implantation duration, implantation energy, and implantation inclination angle, the ILD layer 220 expands to effectively seal the air gap 402 and achieve various shapes of the expanded cap 506, such as a triangular shape, which in Fig. 6 is shown, or a square shape which is in Fig. 7 is shown, or an arc shape that is in Fig. 8 is shown.

[0035] In some embodiments, the ion implantation process comprises the introduction of a first dopant species from the group consisting of nickel (Ni), fluorine (F), boron fluoride (BF), germanium (Ge), cobalt (Co), argon (Ar), arsenic (As), gallium (Ga), antimony (Sb), indium (In), or a combination thereof, into the ILD layer 220. In some embodiments, the ion implantation process comprises the introduction of the first dopant species and further a second dopant species selected from the group consisting of carbon (C), phosphorus (P), silicon (Si), hydrogen (H), nitrogen (N), oxygen (O), or a combination thereof. In this case, the collective doping concentration in the upper part 502 can be between 1E11 and 1E17 atoms / cm² in some embodiments. 2 be.

[0036] In another method, an air gap can be sealed by deposition. If the deposited sealing layer has high uniformity, it fills the air gap and destroys it. If the deposited sealing layer has low uniformity, it experiences a charging effect, so that if the structural density is uneven, the sealing layer fills the air gap unevenly. In the disclosed method, the air gap is sealed by laterally stretching the ILD layer when the dopant is introduced into the ILD layer by an ion implantation process. Furthermore, the ion implantation process is designed by a combination of the ion beam current, implantation duration, implantation energy, and implantation inclination angle such that the ILD layer 220 expands to effectively seal the air gap 402 and that the volume of the air gap 402 is maximized.By adjusting the combination of the aforementioned process parameters, the upper part 502 of the ILD layer 220 is stretched to give the stretched cap 506 different shapes, such as a triangular shape, which is in . Fig. 6 is shown, or a square shape which is in Fig. 7 is shown, or an arc shape that is in Fig. Figure 8 shows how to balance the sealing effect and the air gap volume. For example, the triangular shape of Fig. 6. The largest air gap volume, the square shape of Fig. 7 has the greatest sealing effect, and the arched shape of Fig. 8 has an air gap volume that is larger than that of Fig. 7 is, and a sealing effect that is better than that of Fig. 6 is.

[0037] Method 100 may include further steps before, during, or after the steps described above. For example, method 100 includes a step 126 for producing contacts 902 that are mounted on the S / D structural elements 218, as shown in Fig. Figure 9 is shown. It should be noted that Fig.Figure 9 shows a cross-sectional view of the semiconductor structure 200, cut along the active fin region 206, where the ILD layer 220 is not implanted and therefore not stretched. The contacts 902 are conductive structural elements that electrically connect the corresponding S / D structural elements 218 to an overlying interconnect structure 904 to form an integrated circuit. The contacts 902 are pins made of a conductive material (such as a metal or metal alloy), e.g., tungsten (W), aluminum (Al), an aluminum alloy, copper (Cu), cobalt (Co), nickel (Ni), another suitable metal or metal alloy, or a combination thereof. It should be noted that the ILD layer 220 is not implanted and is not stretched in the active fin regions 206.In some embodiments, the contacts 902 also include a barrier layer that covers the contact holes to improve material integration, e.g., to increase adhesion and reduce inter-diffusion. The barrier layer may comprise more than one layer, such as titanium and titanium nitride (Ti / TiN), tantalum and tantalum nitride (Ta / TaN), copper silicide, or other suitable materials. The fabrication of the contacts 902 in some embodiments comprises the following steps: structuring the ILD layer 220 to create contact holes; depositing a barrier layer to cover the contact holes; depositing one or more conductive materials on the barrier layer in the contact holes; and performing a CMP process to remove excess conductive material and planarize the top surface.

[0038] Method 100 can also include a step 128 for fabricating the interconnect structure 904 on the semiconductor structure 200. The interconnect structure 904 has various conductive structural elements for connecting the different component structural elements (such as the gate stack 208 and the S / D structural elements 218) to form a functional circuit. In particular, the interconnect structure 904 includes several metal layers for providing horizontal electrical routing and vias for providing vertical electrical routing. The interconnect structure 904 also has several ILD layers 906 for isolating the various conductive structural elements from one another. The several ILD layers 906 can, for example, comprise a low-k dielectric material or other suitable dielectric materials, such as silicon oxide.In some illustrative examples, the interconnect structure 904 comprises a first metal layer 910, a second metal layer 914 above the first metal layer 910, and a third metal layer 918 above the second metal layer 914. Each metal layer has a plurality of metal conductors. The interconnect structure 904 further comprises vias 908, 912, and 916 for establishing vertical connections between metal conductors in adjacent metal layers or between the first metal conductors of the first metal layer 910 and components (such as the gate stacks 208 or the contacts 902 of the S / D structural elements 218). In various embodiments, the conductive structural elements (such as the metal conductors and vias) of the interconnect structure 904 comprise aluminum, copper, an aluminum-silicon-copper alloy, titanium, titanium niride, tungsten, polysilicon, metal silicide, or combinations thereof.For the 904 interconnect structure, an aluminum compound produced by deposition and etching or a copper compound produced by a damascene process can be used. In the copper compound, the conductive structural elements contain copper and may also include a barrier layer. The copper interconnect structure is produced by a damascene process. A damascene process includes the following steps: deposition of an ILD layer; structuring the ILD layer to create grooves; deposition of various conductive materials (such as a barrier layer and copper); and performing a CMP process.

[0039] In Process 100, a lithographic process and a structured hard mask are used in separate steps and are described together below. The structured mask layer can be a hard mask that is deposited and structured. The hard mask comprises a dielectric material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor carbide, a semiconductor oxide nitride, or a combination thereof. The hard mask layer can be fabricated by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density post-processing (HDP-CVD), or other suitable deposition methods. Fabrication of the hard mask includes deposition, fabrication of a structured photoresist layer, and etching of the hard mask using the structured photoresist layer as an etching mask. The etching process for structuring the hard mask layer can include wet etching, dry etching, or a combination thereof.For example, the silicon oxide layer in the hard mask layer can be etched with a dilute hydrogen fluoride solution, and the silicon nitride layer in the hard mask layer can be etched with a phosphoric acid solution.

[0040] A photoresist layer contains a light-sensitive material that causes a change in the layer's properties (such as a chemical change) when exposed to light, such as ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light. This change in properties can be used to selectively remove exposed or non-exposed portions of the resist layer using a development process. This method of creating a structured resist layer is called a lithographic process. A lithographic process may include spin coating of a resist layer, pre-curing the resist layer, mask adjustment, exposure, post-exposure curing, development, rinsing, and drying (e.g., post-curing).Alternatively, a lithographic process can be implemented, supplemented or replaced by other processes, such as maskless photolithography, electron beam writing and ion beam writing.

[0041] A semiconductor structure with an air gap and a method for its fabrication are disclosed. The method comprises removing an outer gate spacer to create an air gap; and performing an ion implantation process to introduce one or more dopant species into an ILD layer, such that the ILD layer is stretched to fill the air gap. Different applications of the present invention may have different advantages. No particular advantage is required for all embodiments, and different embodiments may offer different advantages. One of the advantages of some embodiments is that the air gap is sealed without deposition to achieve an optimized sealing effect and a larger air gap volume.Furthermore, the ion implantation process, through a combination of ion beam current, implantation duration, implantation energy, and implantation tilt angle, is designed to cause the ILD layer to expand effectively, sealing the air gap and maximizing its volume. By adjusting the combination of these process parameters, the expanded ILD cap can take on various shapes, such as triangular, square, or arc-shaped, to balance the sealing effect with the air gap volume.

[0042] Thus, the present invention provides a method for fabricating a semiconductor structure according to some embodiments. The method comprises the following steps: receiving a substrate with an active region and an insulated region; fabricating gate stacks on the substrate extending from the active region to the insulated region; fabricating an inner gate spacer and an outer gate spacer on the sidewalls of the gate stacks; fabricating an interplane dielectric layer (ILD layer) on the substrate; removing the outer gate spacer in the insulated region, creating an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the ILD layer, thereby stretching the ILD layer to close the air gap.

[0043] The present invention provides a further method according to some embodiments. The method comprises the following steps: receiving a substrate with an STI structural element (STI: shallow trench insulation) and an active region; fabricating a gate stack on the substrate, an inner gate spacer, and an outer gate spacer on sidewalls of the gate stack; and fabricating an interplane dielectric layer (ILD layer) on the substrate, wherein the gate stack extends from the active region to the STI structural element. The method further comprises: removing a portion of the outer gate spacer on the STI structural element, creating an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process on the ILD layer, thereby stretching the ILD layer to close the air gap.

[0044] The present invention also provides a semiconductor structure according to some embodiments. The semiconductor structure comprises: a substrate with an active region and an insulated region; gate stacks on the substrate extending from the active region to the insulated region; a gate spacer on the sidewalls of the gate stacks; and an interplane dielectric layer (ILD layer) on the substrate, defining an air gap between the ILD layer and the gate spacer, wherein the ILD layer has an upper portion extending laterally to the gate spacer and capping the air gap.

Claims

[1] Method for fabricating a semiconductor structure comprising the following steps: Receiving a substrate (202) with an active region and an isolation region; Forming gate stacks (208) on the substrate (202) extending from the active area to the isolation area; Manufacturing an inner gate spacer (214) and an outer gate spacer (216) on side walls of the gate stacks (208); Forming an interplane dielectric layer (220) on the substrate (202); Removing the outer gate spacer (216) in the isolation area, so that an air gap (402) is created between the inner gate spacer (214) and the interplane dielectric layer (220); and Performing an ion implantation process on the interplane dielectric layer (220), thereby expanding the interplane dielectric layer (220) to cap the air gap (402). [2] Method according to claim 1, wherein carrying out the ion implantation process comprises carrying out the ion implantation process to introduce a dopant species from the group consisting of nickel, fluorine, boron fluoride, germanium, cobalt, argon, arsenic, gallium, antimony, indium and a combination thereof into the interplane dielectric layer (220). [3] Method according to claim 1, wherein carrying out the ion implantation process comprises carrying out the ion implantation process to introduce a dopant species from the group consisting of carbon, phosphorus, silicon, hydrogen, nitrogen, oxygen and a combination thereof into the interplane dielectric layer (220). [4] A method according to any of the preceding claims, wherein carrying out the ion implantation process is carrying out the ion implantation process using a high dosage with a doping concentration of 1E11 to 1E17 atoms / cm³ 2 includes. [5] A method according to any of the preceding claims, further comprising producing a structured material layer (302) in an opening (304) to expose the interplane dielectric layer (220) and the outer gate spacer (216) in the insulation area prior to removing the outer gate spacer (216) in the insulation area, wherein removing the outer gate spacer (216) in the insulation area comprises performing an etching process to selectively remove the outer gate spacer (216) through the opening (304) of the structured material layer (302). [6] Method according to claim 5, wherein carrying out the ion implantation process comprises carrying out the ion implantation process at the interplane dielectric layer (220) through the opening (304) of the structured material layer (302). [7] Method according to any of the preceding claims, wherein the manufacture of the inner gate spacer (214) and the outer gate spacer (216) comprises: Deposition of a first dielectric material layer on the substrate (202) and the gate stacks (208); Deposition of a second dielectric material layer on the first dielectric material layer, wherein the second dielectric material layer has a different composition than the first dielectric material layer; and Performing an anisotropic etching process on the first and second dielectric material layers. [8] Method according to claim 7, wherein the production of the interplane dielectric layer comprises: Forming an etch stop layer (222) on the substrate (202) and on side walls of the outer gate spacer (216); Producing a third dielectric material layer on the etch stop layer (222), wherein the third dielectric material layer has a different composition than the etch stop layer (222); and Performing a chemical-mechanical polishing process on the third dielectric material layer. [9] Method according to claim 8, wherein the third dielectric material layer comprises SiN, SiOC, SiOCN, SiCN, Si, SiGe, W, TiN, HfO2, ZrO2, La2O3 or a combination thereof. [10] Method for producing a semiconductor structure comprising the following steps: Receiving a substrate (202) with a flat trench insulation structural element (204) and an active area (206), a gate stack (208) on the substrate (202), an inner gate spacer (214) and an outer gate spacer (216) on side walls of the gate stack (208); Forming an interplane dielectric layer (220) on the substrate (202), wherein the gate stack (208) extends from the active area (206) to the flat trench insulation structural element (204); Removing part of the outer gate spacer (216) on the flat trench insulation structural element (204) so ​​that an air gap (402) is created between the inner gate spacer (214) and the interplane dielectric layer (220); and Performing an ion implantation process on the interplane dielectric layer (220), thereby expanding the interplane dielectric layer (220) to cap the air gap (402). [11] Method according to claim 10, wherein carrying out the ion implantation process comprises carrying out the ion implantation process to introduce a first dopant species and a second dopant species into the interplane dielectric layer (220), wherein the first dopant species is selected from the group consisting of nickel, fluorine, boron fluoride, germanium, cobalt, argon, arsenic, gallium, antimony, indium or a combination thereof, and the second dopant species is selected from the group consisting of carbon, phosphorus, silicon, hydrogen, nitrogen, oxygen or a combination thereof. [12] Method according to claim 10 or 11, wherein carrying out the ion implantation process is carrying out the ion implantation process using a high dose with a collective doping concentration of 1E11 to 1E17 atoms / cm³ 2 includes. [13] Method according to any one of claims 10 to 12, further comprising producing a structured material layer (302) with an opening (304) for exposing part of the interplane dielectric layer (220) and part of the outer gate spacer (216) on the flat trench insulation structural element (204), wherein the removal of part of the outer gate spacer (216) comprises performing an etching process for selectively etching part of the outer gate spacer (216) through the opening (304) of the structured material layer (302). [14] Method according to claim 13, wherein carrying out the ion implantation process comprises carrying out the ion implantation process on the part of the interplane dielectric layer (220) through the opening (304) of the structured material layer (302). [15] Method according to claim 14, wherein performing the ion implantation process comprises performing the ion implantation process by changing an implantation tilt angle from 60° to -60° while the substrate (202) rotates. [16] Method according to any one of claims 10 to 15, wherein carrying out the ion implantation process comprises carrying out the ion implantation process with such an ion beam current and such an implantation duration that the interplane dielectric layer (220) is laterally extended by more than 10%. [17] Semiconductor structure with: a substrate with an active area and an isolation area; Gate stacks on the substrate, extending from the active area to the isolation area; a gate spacer on the side walls of the gate stacks; and an interplane dielectric layer on the substrate, defining an air gap between the interplane dielectric layer and the gate spacer, wherein the interplane dielectric layer has an upper part that extends laterally to the gate spacer and caps the air gap, wherein: the interplane dielectric layer (220) has a lower part (502) and an upper part (504), the lower part (502) of the interplane dielectric layer (220) has a dielectric material, and the upper part (504) of the interplane dielectric layer comprises the dielectric material doped with nickel, fluorine, boron fluoride, germanium, cobalt, argon, arsenic, gallium, antimony, indium or a combination thereof. [18] Semiconductor structure according to claim 17, wherein the dielectric material is selected from the group consisting of SiN, SiOC, SiOCN, SiCN, Si, SiGe, SiO2, TiO2, Al2O3, Ge, W, TaN, TiN, HfO2, ZrO2 and La2O3. [19] Semiconductor structure according to claim 17 or 18, wherein the upper part (504) of the interplane dielectric layer has an arc shape over the air gap (402).

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