Formation and structure of conductive contact characteristics

Abstract

Method for a semiconductor process, wherein the method comprises: Formation of a dielectric weld layer (50) along a side wall of an opening (42, 44, 46) in a dielectric layer (38, 40); Formation of a barrier layer (58) on the dielectric weld layer (50); Etching back a section of the barrier layer (58) to expose a side face of an upper section (54) of the dielectric weld layer (50), wherein the dielectric weld layer (50) leaves an upper section of the side wall exposed; and Forming a conductive material (66) on the side surface of the upper section (54) of the dielectric weld layer (50) and on the barrier layer (58) and along the corresponding upper section of the side wall.

Description

GENERAL STATE OF THE ART

[0001] The semiconductor integrated circuit (IC) industry is experiencing exponential growth. Technological advances in IC materials and construction have produced generations of ICs, each generation featuring smaller and more complex circuitry than the previous one. As ICs have evolved, functional density (e.g., the number of interconnected devices per unit area) has generally increased, while geometric size (e.g., the smallest component or trace that can be manufactured) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs.

[0002] Along with the miniaturization of devices, manufacturers have begun using new and different materials and / or combinations of materials to facilitate this miniaturization. Minimization—alone and in combination with new and different materials—has also introduced challenges that may not have existed with previous generations of devices featuring larger geometries.

[0003] US 2007 / 0262451A1 discloses a transistor gate comprising a substrate with a pair of spacers arranged on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed output work metal conformally deposited on the high-k dielectric, and along a section of the side walls of the spacer comprising a second output work metal conformally deposited on the recessed output work metal, and an electrode metal deposited on the second output work metal.

[0004] US 2016 / 0308016A1 discloses a semiconductor device comprising a substrate with an active pattern, a gate electrode crossing the active pattern, and a source / drain region. A source / drain contact on the source / drain region is enclosed by a spacer, and a conductive column of the source / drain contact is enclosed by a barrier layer.

[0005] US 2017 / 0012107A1 discloses integrated circuits and methods for their fabrication and includes the formation of an exit work layer that lies above a substrate and a plurality of dielectric columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of this disclosure are best understood from the following detailed description in conjunction with the accompanying figures. Note that, in accordance with industry practice, various features are not drawn to scale. The dimensions of the various features may have been arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 is a flowchart of an exemplary method for forming conductive features according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 shows cross-sectional views of corresponding preliminary structures during an exemplary procedure for forming conductive features according to some embodiments. DETAILED DESCRIPTION

[0007] An improved manufacturing process and improved structures are specified in independent claims 1, 9, and 19. The following disclosure provides many different embodiments or examples for realizing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and also embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself establish any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, for the sake of simplicity, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used here to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the words used herein to describe spatial relations may be interpreted accordingly.

[0009] In general, the present disclosure provides embodiments relating to conductive features, such as metallic contacts, vias, conductor tracks, etc., and methods for forming these conductive features. In some examples, a barrier layer and / or a welding layer formed in an opening through a dielectric layer is removed (e.g., etched) to create a height difference in the opening that is lower than the top surface of the dielectric. Similarly, removal (e.g., etching) is performed to eliminate redundant structures of the barrier layer and / or the welding layer at corners of the opening to improve profile control and dimensional accuracy. This helps, among other things, to reduce the formation of voids during the deposition and / or adhesion of a conductive material to / on the barrier layer.

[0010] The embodiments described herein are presented in the context of forming conductive features within the framework of front-end-of-line (FEOL) and / or middle-end-of-line (MEOL) processing for transistors. Implementations of some aspects of this disclosure may be used in other processes and / or with other devices. For example, embodiments may be implemented within the framework of back-end-of-line (BEOL) processing. Several variations of the exemplary methods and structures are described. Although embodiments of the method may be described in a specific sequence, various other embodiments of the method may be carried out in any logical order and may include fewer or more steps than those described herein.In some figures, some reference symbols of components or features depicted therein may be omitted to avoid obscuring other components or features; this serves the purpose of simplifying the representation of the figures.

[0011] Fig. Figure 1 represents an exemplary flowchart of a process 100 that is carried out to form a semiconductor device structure according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 shows views of corresponding preliminary structures at corresponding phases during an exemplary process for forming conductive features according to some embodiments. The preliminary structures, as described below, are used in the realization of field-effect transistors (FETs). Other structures may be implemented in other embodiments.

[0012] As shown in the figures and described herein, the devices are field-effect transistors (FETs), which can be planar FETs or FinFETs. In other implementations, the devices can be vertical-gate all-around (VGAA) FETs, horizontal-gate all-around (HGAA) FETs, bipolar junction transistors (BJTs), diodes, capacitors, inductors, resistors, etc. According to planar FETs and / or FinFETs, gate stacks 32 are formed on active regions of the semiconductor substrate 30, as shown in Fig. Figure 2 shows that in planar FETs, the active regions can be a section on the top surface of the semiconductor substrate 30, bounded by isolation regions. In FinFETs, the active regions can be three-dimensional fins projecting between isolation regions on the semiconductor substrate 30. The semiconductor substrate 30 can be a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or another substrate. The semiconductor material of the semiconductor substrate 30 can be an elemental semiconductor, such as silicon (e.g., crystalline silicon, such as Si). <100> or you <111> ) or germanium, a compound or alloy semiconductor, the like, or a combination thereof. The semiconductor material of the semiconductor substrate 30 may be doped, for example with a p-type or n-type dopant, or undoped.Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of the semiconductor substrate can comprise an elemental semiconductor, such as silicon (Si) and germanium (Ge); a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0013] The gate stacks 32 can be functional gate stacks, as in a gate-first process, or dummy gate stacks, as in a replacement-gate process. In the replacement-gate process, each gate stack 32 can comprise a dielectric layer over the active region, a gate layer over the dielectric layer, and in some cases, a mask layer over the gate layer. The gate stack 32 is subsequently replaced by a metallic gate structure, which may comprise a high k-value dielectric material. A high k-value dielectric material can have a k-value greater than approximately 7.0 and be a metal oxide or metal silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), multilayer layers thereof, or a combination thereof. The gate layer (e.g., gate electrode) can be silicon (e.g.,The dielectric layer, gate layer, and mask layer may consist of or comprise polysilicon (which may be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, TiN, TaN, TaC, Co), a combination thereof (such as a silicide, which may be subsequently formed), or multiple layers thereof. The mask layer may consist of or comprise silicon nitride, silicon oxynitride, silicon carbon nitride, the like, or a combination thereof. Processes for forming or depositing the dielectric layer, gate layer, and mask layer include thermal and / or chemical growth, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), molecular beam deposition (MBD), atomic layer deposition (ALD), physical vapor deposition (PVD), and other deposition methods.The layers for the gate stack 32 can then be structured to form the gate stack 32, for example, by photolithography and one or more etching processes. For example, a photoresist can be applied to the mask layer (or the gate layer, for example, if no mask layer is used), such as by spin coating, and structured by exposing the photoresist using a suitable photomask. Then, exposed or unexposed sections of the photoresist can be removed, depending on whether a positive or negative resist is used. The structure of the photoresist can then be transferred to the layers of the gate stack 32, for example, by one or more suitable etching processes. The one or more etching processes can include reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof.Etching can be performed anisotropically. The photoresist is then removed, for example, in an ashing or wet removal process.

[0014] Gate spacers 34 are formed on the semiconductor substrate 30 along the sidewalls of the gate stacks 32 and over the active regions. The gate spacers 34 can be formed, for example, by conformal deposition of one or more layers and anisotropic etching of these layers. The gate spacers 34 can comprise or be silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multilayer layers thereof, or a combination thereof.

[0015] Source / drain regions 36 are formed on opposite sides of the gate stack 32 in the active areas. In some examples, the source / drain regions 36 are formed by implanting dopants into the active areas using the gate stack 32 and gate spacers 34 as masks. Consequently, the source / drain regions 36 can be formed by implantation on opposite sides of each gate stack 32. In other examples, the active areas can be provided with recesses using the gate stack 32 and gate spacers 34 as masks, and epitaxial source / drain regions 36 can grow epitaxially in the recesses. Epitaxial source / drain regions 36 can be raised relative to the active area. The epitaxial source / drain regions 36 can be doped by in-situ doping during epitaxial growth and / or by implantation after epitaxial growth.The epitaxial source / drain regions 36 can comprise or be silicon germanium, silicon carbide, silicon phosphorus, silicon carbon phosphorus, germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The epitaxial source / drain regions 36 can be formed in the recesses by a suitable epitaxial growth or deposition process. In some examples, the epitaxial source / drain regions 36 can have facets that may correspond to crystal planes of the substrate 30. Consequently, the source / drain regions 36 can be formed by epitaxial growth and possibly with implantation on opposite sides of each gate stack 32.

[0016] An interlayer dielectric (ILD) 38 is formed between the gate stacks 32 and over the semiconductor substrate 30. The first ILD 38 is deposited over the active regions, gate stacks 32, and gate spacers 34. In some examples, an etch stop layer (not shown) can be conformally deposited over the active regions, gate stacks 32, and gate spacers 34. Generally, an etch stop layer can provide a mechanism for stopping an etching process, for example, during the formation of contacts or vias. An etch stop layer can be formed from a dielectric material with a different etch selectivity than adjacent layers, such as the first ILD 38.The etch stop layer may comprise or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, the like, or a combination thereof, and may be deposited by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or any other deposition method. The first ILD 38 may comprise or be silicon dioxide, a dielectric material with a low k-value (e.g., a material with a lower dielectric constant than silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiOxCy, spin-on glass, spin-on polymers, silicon-carbon material, a compound thereof, a composite material thereof, the like, or a combination thereof.The first ILD 38 can be deposited using spin-on CVD, flow CVD (FCVD), PECVD, physical vapor deposition (PVD), or another deposition method. The first ILD 38 can be planarized after deposition. A planarization process, such as chemical-mechanical polishing (CMP), can be performed to planarize the first ILD 38.

[0017] A second interlayer dielectric (ILD) 40 is formed above the first ILD 38, as shown in Fig. Figure 3 shows that the second ILD 40 is deposited over the first ILD 38. The second ILD 40 is made from a similar material to that used to form the first ILD 38. The second ILD 40 can be planarized after deposition, for example by CMP. The thickness of the first and second ILD 38,40 can range from approximately 50 nm to approximately 1200 nm. The combined thickness of the first and second ILD 38,40 can range from approximately 100 nm to approximately 2400 nm.

[0018] Referring again to process 100, which in Fig. As shown in Figure 1, a structuring process is carried out in step 106 to form openings 42, 44 and 46 through the second ILD 40 and the first ILD 38, as shown in Figure 4. The first opening 42 exposes a gate stack 32 and an adjacent source / drain region 36. The first opening 42 therefore serves to form a composite conductive feature between the exposed gate stack 32 and the adjacent source / drain region 36. The second opening 44 exposes a source / drain region 36 and therefore serves to form a conductive feature to the exposed source / drain region 36. The third opening 46 exposes a gate stack 32 and therefore serves to form a conductive feature to the exposed gate stack 32. The openings 42, 44, and 46 can be formed, for example, by suitable photolithography and etching processes.

[0019] In step 108, a weld layer 50 is formed in the openings 42, 44, and 46, followed by a first barrier layer 52, which is formed conformally to it. In some embodiments, the weld layer 50 is also called a wetting layer or adhesion layer. The weld layer 50 is structured such that it is formed on the side walls of the openings 42, 44, and 46, while the underlying source / drain area 36, ​​as shown in Fig. 5 shown, is left exposed for the subsequent healing process. Subsequently, the first barrier layer 52 is formed conformally on the weld layer 50 in the openings 42, 44, 46, as well as on the exposed source / drain areas 36, exposed gate stacks 32, side walls of the first ILD 38 and second ILD 40, and the top surface of the second ILD 40, as shown in Fig. Figure 6 shows. In some embodiments, the first barrier layer 52 is also called the adhesive layer or anti-reflection coating (ARC) layer, as required.

[0020] In one example, the weld layer 50 can be or comprise a dielectric material including silicon, such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, the like, or multilayer layers thereof. The adhesion layer 50 can be formed by PECVD, low-pressure CVD (LPCVD), flow CVD, ALD, or another deposition method. It is assumed that the dielectric material provided by the weld layer 50 can provide good interfacial bonding between the ILDs 38, 40, and the first barrier layer 52, with good interfacial adhesion and integration, as discussed in more detail below. The dielectric material from the weld layer 50 can include silicon elements and other elements, such as nitrogen, oxygen, and / or carbon elements.Thus, the silicon elements from the weld layer 50 can possess binding energy to bond to the first and second ILDs 38, 40, which can also contain silicon elements. Therefore, by using a dielectric material comprising silicon for the weld layer 50, good interfacial adhesion and integration can be achieved.

[0021] Furthermore, since the selected weld layer 50 is a dielectric material, it is structured to expose the underlying source / drain region 36. This allows the first barrier layer 52, which is subsequently formed on top of it, to come into contact with the source / drain region 36. As a result, during the subsequent curing process, the source / drain region 36 can be transformed into a silicide material through a chemical reaction between the first barrier layer 52 and the source / drain region 36.

[0022] In some embodiments, the weld layer 50, which is described herein in Fig. 8 is designed to be a silicon nitride material with a thickness in the range of about 0.5 nm to about 10 nm.

[0023] The first barrier layer 52 can be or comprise a metal-containing material, for example titanium, cobalt, nickel, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition process. The first barrier layer 52 can be or comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition process.

[0024] In step 110, a curing process can be carried out to promote the reaction of the source / drain regions 36 with the first barrier layer 52 in order to form silicide regions 55 (e.g., a silicide region with a metal-containing material that reacts with a semiconductor material (e.g., Si and / or Ge)) on the source / drain regions 36, as shown in Fig. Figure 7 shows that in some examples, if the first barrier layer 52 is a layer of titanium or titanium nitride, the silicide region 55 is a titanium silicide material. Even if the silicide regions 55 in Fig. 7 shown to be formed only on the source / drain areas 36, note that the silicide area 55 may be formed at other locations, such as above the gate stacks 32 or other locations on the substrate 30 as required.

[0025] In step 112, after the silicide regions 55 have been formed, the first barrier layer 52, which was formed on the substrate 30, can be removed, as shown in Fig. Figure 8 shows that the first barrier layer 52 can be removed from the substrate 30 by suitable etching methods, such as reactive ion etch (RIE), neutral beam etch (NBE), wet etching, or another etching process. In some examples, the weld layer 50 remains on the substrate 30 for interface protection.

[0026] In step 114, a second barrier layer 58 is formed on the weld layer 50, the exposed silicide area 55, the exposed first and second ILD 38, 40 and other exposed areas of the substrate 30, as shown in Fig. Figure 9 shows that the second barrier layer 58 can be conformally deposited onto the weld layer 50 and the substrate, similar to the first barrier layer 52. The second barrier layer 58 can be or comprise titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, the like, or a combination thereof, and can be deposited by ALD, CVD, or another deposition method. In some examples, the second barrier layer 58 has a thickness in the range of 5 nm to approximately 80 nm.

[0027] In one example, the second barrier layer 58 is selected from a material that shares a similar element with the weld layer 50, thus enhancing the interfacial adhesion between the weld layer 50 and the second barrier layer 58. For instance, if the weld layer 50 comprises silicon elements and other elements, such as nitrogen, oxygen, and / or carbon elements, the silicon elements may possess binding energy to bond to the first and second ILDs 38, 40, which may also contain silicon elements. Simultaneously, the other elements (e.g., nitrogen, oxygen, and / or carbon elements) from the weld layer 50 bond to the second barrier layer 58, which is selected to contain at least nitrogen, oxygen, or carbon elements.Thus, a good selection of materials between the weld layer 50 and the second barrier layer 58 can enhance the interfacial integration and adhesion between the two, thereby improving the overall structural integrity and behavior of the device. For example, good interfacial adhesion and integration can be achieved by using a dielectric material for the weld layer 50 that includes silicon and other elements similar to those in the second barrier layer 58.

[0028] In step 116, a removal process is carried out to remove a section of the second barrier layer 58 and a section of the weld layer 50 from the substrate 30, as shown in Fig. 10 shown. The removal process is an etching process, which includes a dry etching process or a wet etching process.

[0029] In some embodiments, the ablation process, as described here, for etching the second barrier layer 58 is a wet etching process to remove an upper portion of the second barrier layer 58 near the corners of the openings 42, 44, 46 from the substrate 30. The ablation process involves removing the second barrier layer 58 to a depth 88 below a top surface 67 of the second ILD 40, thus removing any excess second barrier layer that may have accumulated at the corner 59 of the opening 42, 44, 46. A top surface of the barrier layer 58 is located further below than the top surface 67 of the second ILD 40 as well as a top surface of the weld layer 50. By removing the upper portions of the second barrier layer 58 at upper areas (e.g.,At the corners 59) of the openings 42, 44, 46, a wider width 80 of the openings 42, 44, 46 can be obtained without the weld layer 50 and the second barrier layer 58, compared to the shorter width 81 at the weld layer 50 and the even shorter width 82 at the second barrier layer 58. Note that a section of the weld layer 50 is also removed during the ablation process, which can facilitate a widening of the width 80 of the openings 42, 44, 46 for subsequent processes. The wider widths 80, 81 of the openings 42, 44, 46 can provide a wider process window for the conductive metal filler layer subsequently formed therein—with a lower probability of voids or seams forming within it.In some examples, the shorter width 81 is smaller than the wider width 80 by a measure in the range of about 5% to about 15% of the wider width 80, and the even shorter width 82 is smaller than the wider width 80 by a measure in the range of about 8% to about 30% of the wider width 80.

[0030] In some examples, the etching process is a wet etching process. The wet etching process may involve immersing the substrate 30 in a solution comprising deionized (DI) water and a suitable chemical. The chemical reaction between the solution and the second barrier layer 58 primarily etches the second barrier layer 58 and a section of the weld layer 50 located on the top surface 67 of the second ILD 40 until a predetermined process time is reached or the desired depth 88 is formed in the openings 42, 44, 46, as shown in Fig. Figure 10 shows suitable examples of chemicals included in the DI water. Suitable examples include hydrogen peroxide (H₂O₂), ammonium hydroxide (NH₄OH), HNO₃, H₂SO₄, HCl, dilute HF, and the like. In some examples, the chemical used in the DI water to etch the second barrier layer 58 includes H₂O₂. It is assumed that the H₂O₂ in the DI water can react with the Ti / Ta elements from the second barrier layer 58 to remove a section of the second barrier layer 58 from the substrate 30.

[0031] The chemical in the DI solution can have a concentration of 0.1% to 50%. The solution temperature during immersion can range from approximately 20°C to approximately 90°C. The substrate 30 can be immersed in the solution for a duration of approximately 5 seconds to approximately 120 seconds to form the depth 59 in a range of 1 nm to 50 nm. Optionally, the semiconductor substrate 30 can be rinsed in isopropyl alcohol (IPA) after immersion in the solution to dry it.

[0032] In some examples, the second barrier layer 58 is back-etched (e.g., abraded) to expose an upper section 54 of the weld layer 50 in the openings 42, 44, 46. The upper section 54 of the weld layer 50 exposed by the second barrier layer 58 has a depth 60 between approximately 15 nm and approximately 25 nm. As discussed above, excess second barrier layer 58 forming at corners 59 of the openings 42, 44, 46 can potentially increase the probability of early closure of the openings 42, 44, 46 during subsequent deposition processes. However, the second barrier layer 58 can also facilitate the nucleation and growth of the metallic materials of the subsequently injected metallic conductive filler material 66.Thus, the thickness of the second barrier layer 58 can be balanced to allow the growth of the subsequent metallic conductive filler material 66 while simultaneously preventing the openings 42, 44, and 46 from becoming blocked. By removing the second barrier layer 58 to expose a section of the underlying weld layer 50, the second barrier layer 58 formed at the corners 59 can be removed, and the upper section of the openings 42, 44, and 46 can be widened. This facilitates the insertion of the metallic conductive filler material 66 without premature sealing, thus preventing voids. Since a certain amount of the second barrier layer 58 remains in the openings 42, 44, and 46, nucleation sites and adhesion surfaces remain, allowing the metal elements to adhere during the subsequent deposition process.In some examples, the second barrier layer 58 exposes the depth 60 of the weld layer 50, as in . Fig. Figure 10 shows that in some examples, the depth 60 lies in a range of approximately 15 nm to approximately 25 nm.

[0033] In the examples where a dry etching process is used for the material removal process, the dry etching process may include RIE, NBE, inductively coupled plasma (ICP) etching, the like, or a combination thereof. Example etching gases that can be used for a plasma etching process include a halogenated gas or another etching gas. The volumetric flow rate of the etching gas(es) in a plasma etching process can range from approximately 10 sccm to approximately 100 sccm. A plasma etching process can achieve a DC substrate bias in the range of approximately 10 kV to approximately 500 kV. The power of a plasma etching process can range from approximately 200 W to approximately 2000 W. The pressure of a plasma etching process can range from approximately 5 mTorr to approximately 50 mTorr. The depth of the etching process can be controlled over the duration of the etching process used for the etching.The duration of a plasma etching process to achieve a depth of 88 in a range of 15 nm to about 35 nm can, in some examples, range from about 10 seconds to about 600 seconds.

[0034] In step 118, a metallic conductive filler material 66 is formed in the openings 42, 44 and 46 and on the second barrier layer 58 and the upper section 54 of the weld layer 50, as shown in Fig. Figure 11 shows that the metallic conductive filler material 66 can be or comprise a metal, such as cobalt, tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and can be deposited by CVD, ALD, PVD, or another deposition process. The removal of the second barrier layer 58 can allow for larger dimensions (e.g., widths 80, 81) at the upper sections of the openings 42, 44, and 46, compared to the second barrier layer 58 of the lower section, which has a shorter width 82 at the openings 42, 44, and 46. Thus, the larger dimensions at the upper sections of the openings 42, 44, and 46 allow the metallic conductive filler material 66 to enclose the openings. 42 , 44, 46 without a void in the metallic conductive filling material 66 in the openings 42, 44, 46.

[0035] In some examples, excess metallic conductive filler material 66 can be removed, as in Fig. Figure 12 shows that after the metallic conductive filler material 66 has been deposited, excess metallic conductive filler material 66 above the top surface 67 of the second ILD 40 can be removed, for example, by a planarization process such as CMP. The planarization process can remove excess metallic conductive filler material 66 from above the top surface 67 of the second ILD 40. This forms conductive features 70, 72, 74, encompassing the metallic conductive filler material 66, accordingly in the openings 42, 44, and 46. The top surfaces of the conductive features 70, 72, 74, and the second ILD 40 can be coplanar. Accordingly, conductive features 70, 72, 74, comprising the metallic conductive filler material 66, second barrier layers 58 and the weld layer 50 (and possibly silicide regions 55), can be configured to form corresponding gate stacks 32 and / or source / drain regions 36. Fig.As can be seen from Figure 12, the widths of the metallic conductive filler material 66 of the conductive features 70, 72 and 74 on their upper surfaces can be increased by removing the second barrier layer 58 and the weld layer 50, which can increase the area with which corresponding subsequent conductive features can come into contact.

[0036] As shown above, aspects of some embodiments can be applied to front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes. Conductive features 70, 72, 74, including the processes by which the conductive features 70, 72, 74 were formed, can realize aspects of various embodiments within the scope of FEOL and / or MEOL. Other conductive features formed within the scope of FEOL and / or MEOL can similarly incorporate aspects according to some embodiments. For example, replacement gate stacks can be formed according to some embodiments. For replacement gate stacks, for example, conformal layers, such as a dielectric layer and / or an exit work setting layer(s), formed where a dummy gate stack has been removed, can be deposited and removed according to the same or similar processes as shown and described above.In other examples, aspects of the above can be integrated into conductive features that are formed in intermetallization dielectrics (IMDs) as part of a back-end-of-line (BEOL) processing process.

[0037] Several embodiments offer advantages. By removing a portion of a barrier layer at the top of an opening or recess, conductive material forming a conductive feature can be more easily deposited within the opening or recess without creating a void. Particularly when conductive features are small, voids can lead to increased resistance or even complete failure of the conductive feature, such as the inability to establish electrical contact. Consequently, minimizing void formation can be advantageous, especially in small technology nodes, such as advanced technologies with small dimensions.Furthermore, the heights of weld layers and barrier layers in conductive features can be adjusted based on different requirements regarding process control and the performance of devices.

[0038] In one embodiment, a semiconductor process method comprises forming a dielectric weld layer along a side wall of an opening in the dielectric layer, forming a barrier layer on the dielectric weld layer, back-etching a portion of the barrier layer to expose a side face of an upper portion of the dielectric weld layer, the dielectric weld layer leaving an upper portion of the side wall exposed, and forming a conductive material on the side face of the upper portion of the dielectric weld layer and on the barrier layer and along the corresponding upper portion of the side wall. In one embodiment, the barrier layer is wet-etched using a solution comprising at least one of H₂O₂, H₂SO₄, HNO₃, NH₄OH, or a combination thereof.In one embodiment, a section of the conductive material is in direct contact with the side surface of the upper section of the dielectric weld layer. In one embodiment, the barrier layer comprises at least one of titanium nitride, titanium oxide, tantalum nitride, and tantalum oxide. In one embodiment, the dielectric weld layer is a silicon-containing dielectric material. In one embodiment, the dielectric weld layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride. In one embodiment, the side surface of the upper section of the dielectric weld layer, which is exposed by etching back the section of the barrier layer, is exposed to a depth in the range of approximately 15 nm to approximately 25 nm.In one embodiment, an upper surface of the barrier layer is located further down than an upper surface of the dielectric weld layer on the side wall of the opening of the dielectric layer.

[0039] In another embodiment, a structure comprises a dielectric layer with a side wall, wherein the dielectric layer is located above a substrate, a dielectric weld layer along the side wall, the dielectric weld layer leaving an upper portion of the side wall uncovered, a barrier layer along the dielectric weld layer, the barrier layer leaving an upper portion of the dielectric weld layer uncovered, and a conductive material along the barrier layer and along the corresponding upper portions of the side wall and the dielectric weld layer. In one embodiment, the conductive material has an upper width in contact with the dielectric weld layer that is wider than a lower width in contact with the barrier layer. In one embodiment, the conductive material is in direct contact with the upper portion of the dielectric weld layer.In one embodiment, a depth is defined between corresponding top surfaces of the dielectric weld layer and the barrier layer, the depth being approximately 15 nm to. The diameter is 25 nm. In one embodiment, an upper surface of the barrier layer is located further down than an upper surface of the dielectric weld layer. In one embodiment, the conductive material comprises at least one of cobalt, tungsten, copper, aluminum, gold, and silver. In one embodiment, a silicide region is formed under the conductive material along an underside of the barrier layer. In one embodiment, the dielectric weld layer is a silicon-containing dielectric material. In one embodiment, the dielectric weld layer comprises at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride. In one embodiment, the barrier layer comprises at least one of titanium nitride, titanium oxide, tantalum nitride, and tantalum oxide.

[0040] In yet another embodiment, a structure comprises a dielectric layer, a conductive material formed within the dielectric layer and laterally bound by a barrier layer, and a dielectric weld layer laterally between the barrier layer and the dielectric layer. The barrier layer and the dielectric weld layer have differing heights along a side wall of the dielectric layer, the barrier layer leaving an upper portion of the dielectric weld layer exposed, and the dielectric weld layer leaving an upper portion of the side wall exposed, with the conductive material extending along the corresponding upper portion of the side wall. In one embodiment, the differing heights define a step height in the range of 15 nm to 25 nm.

Claims

[1] Method for a semiconductor process, the method comprising: Formation of a dielectric weld layer (50) along a side wall of an opening (42, 44, 46) in a dielectric layer (38, 40); Formation of a barrier layer (58) on the dielectric weld layer (50); Etching back a section of the barrier layer (58) to expose a side face of an upper section (54) of the dielectric weld layer (50), wherein the dielectric weld layer (50) leaves an upper section of the side wall exposed; and Forming a conductive material (66) on the side surface of the upper section (54) of the dielectric weld layer (50) and on the barrier layer (58) and along the corresponding upper section of the side wall. [2] Method according to claim 1, wherein the etching back of the section of the barrier layer (58) comprises: Wet soaking of the barrier layer (58) using a solution comprising at least one of H2O2, H2SO4, HNO3, NH4OH or a combination thereof. [3] Method according to claim 1 or 2, wherein a section of the conductive material (66) is in direct contact with the side surface of the upper section (54) of the dielectric weld layer (50). [4] Method according to any of the preceding claims, wherein the barrier layer (58) comprises at least one of titanium nitride, titanium oxide, tantalum nitride and tantalum oxide. [5] Method according to any of the preceding claims, wherein the dielectric welding layer (50) is a silicon-containing dielectric material. [6] Method according to claim 5, wherein the dielectric welding layer (50) comprises at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide and silicon oxynitride. [7] Method according to any of the preceding claims, wherein the side surface of the upper section (54) of the dielectric weld layer (50) exposed by etching back the section of the barrier layer (58) is exposed to a depth (59, 60, 88) in a range of about 15 nm to about 25 nm. [8] Method according to one of the preceding claims, wherein an upper surface of the barrier layer (58) is located further down than an upper surface of the dielectric weld layer (50) on the side wall of the opening (42, 44, 46) of the dielectric layer (38, 40). [9] Structure, comprehensive: a dielectric layer (38, 40) with a side wall, wherein the dielectric layer (38, 40) is located above a substrate (30); a dielectric weld layer (50) along the side wall, wherein the dielectric weld layer (50) leaves an upper section of the side wall free; a barrier layer (58) along the dielectric weld layer (50), wherein the barrier layer (58) leaves an upper section (54) of the dielectric weld layer (50) free; and a conductive material (66) along the barrier layer (58) and along the corresponding upper sections of the side wall and the dielectric weld layer (50). [10] Structure according to claim 9, wherein the conductive material (66) has an upper width that is in contact with the dielectric welding layer (50) which is wider than a lower width that is in contact with the barrier layer (58). [11] Structure according to claim 9 or 10, wherein the conductive material (66) is in direct contact with the upper section (54) of the dielectric weld layer (50). [12] Structure according to any one of the preceding claims 9 to 11, wherein a depth (59, 60, 88) is defined between corresponding top surfaces of the dielectric weld layer (50) and the barrier layer (58), wherein the depth (59, 60, 88) is about 15 nm to 25 nm. [13] Structure according to any one of the preceding claims 9 to 12, wherein a top surface of the barrier layer (58) is located further down than a top surface of the dielectric weld layer (50). [14] Structure according to any one of the preceding claims 9 to 13, wherein the conductive material (66) comprises at least one of cobalt, tungsten, copper, aluminium, gold, silver and alloys thereof. [15] Structure according to any one of the preceding claims 9 to 14, further comprising: a silicide region (55) along an underside of the barrier layer (58) beneath the conductive material (66). [16] Structure according to any one of the preceding claims 9 to 15, wherein the dielectric weld layer (50) is a silicon-containing dielectric material. [17] Structure according to claim 16, wherein the dielectric welding layer (50) is silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride or multilayer layers thereof. [18] Structure according to any one of the preceding claims 9 to 17, wherein the barrier layer (58) is titanium nitride, titanium oxide, tantalum nitride, tantalum oxide or a combination thereof. [19] Structure, comprehensive: a dielectric layer (38, 40); a conductive material (66) formed in the dielectric layer (38, 40) and laterally bound by a barrier layer (58); and a dielectric weld layer (50) laterally between the barrier layer (58) and the dielectric layer (38, 40), wherein the barrier layer (58) and the dielectric weld layer (50) have different heights along a side wall of the dielectric layer (38, 40), wherein the barrier layer (58) leaves an upper section (54) of the dielectric weld layer (50) free, and wherein the dielectric weld layer (50) leaves an upper section of the side wall free, wherein the conductive material (66) runs along the corresponding upper section of the side wall. [20] Structure according to claim 19, wherein the differing heights define a step height in a range of about 15 nm to about 25 nm.

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