FINFET DEVICE AND METHOD FOR FORMING THE SAME

Abstract

Procedure comprising: Forming semiconductor stripes (1005, 1007, 1105) over a substrate (101, 201); Forming isolation regions (103, 1401) above the substrate (101, 201) and between adjacent semiconductor strips (1005, 1007, 1105); performing a first recessing process on the isolation regions (103, 1401) to expose first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); forming the first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) to form formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); Performing a second recessing process on the isolation regions (103, 1401) to expose second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) below the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); and Forming the second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) to form formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105), wherein the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) and the formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips form fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901), and wherein the fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) extend from uppermost surfaces of the insulation regions (103, 1401), wherein the side walls of the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) have a first slope, and wherein the side walls of the formed second sections (3201b, 3203b,3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) have a second pitch which differs from the first pitch.,

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconducting material layers successively over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] A transistor is an element commonly used in semiconductor devices. For example, there can be a large number of transistors (e.g., hundreds, thousands, or millions of transistors) on a single integrated circuit (IC). For example, a common transistor type used in semiconductor device manufacturing is a metal-oxide-semiconductor field-effect transistor (MOSFET). A planar transistor (e.g., planar MOSFET) typically has a gate dielectric disposed over a channel region in a substrate and a gate electrode formed over the gate dielectric. A source region and a drain region of the transistor are formed on either side of the channel region.

[0003] Multi-gate field-effect transistors (MuGFETs) are a recent development in semiconductor technology. One type of MuGFET is called a fin field-effect transistor (FinFET), which is a transistor structure featuring a fin-shaped semiconductor material raised vertically from the semiconductor surface of an integrated circuit.

[0004] US 2007 / 0231997 A1 discloses a multi-body thick field-effect transistor comprising a silicon body formed on a substrate. US 2014 / 0252557 A1 discloses semiconductor device structures and methods for forming a semiconductor device. US 2016 / 0379831 A1 discloses a method comprising forming a silicon capping layer on a semiconductor fin, forming an interlayer over the silicon capping layer, forming a high-k gate dielectric over the interlayer, and forming a purge metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1 is a perspective view of a fin field effect transistor ("FinFET") device according to some embodiments. Fig. 2A-16A are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 17A and Fig. 17B are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 18A, Fig. 18B and Fig. 18C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 19A, Fig. 19B and Fig. 19C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 20A, Fig. 20B and Fig. 20C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 21A, Fig. 21B and Fig. 21C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 22A, Fig. 22B and Fig. 22C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 23C is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 24A, Fig. 24B and Fig. 24C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 25A, Fig. 25B and Fig. 25C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 26A, Fig. 26B and Fig. 26C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 27A, Fig. 27B and Fig. 27C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 28A, Fig. 28B and Fig. 28C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 29A, Fig. 29B and Fig. 29C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 30A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 31A, Fig. 31B and Fig. 31C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 32A-34A are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 35A, Fig. 35B and Fig. 35C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 36A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 37A, Fig. 37B and Fig. 37C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 38A-42A are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments. Fig. 43A, Fig. 43B and Fig. 43C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 44A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 45A, Fig. 45B and Fig. 45C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 46A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 47A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 48A, Fig. 48B and Fig. 48C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 49A is a cross-sectional view of intermediate steps in the fabrication of a FinFET device according to some embodiments. Fig. 50A, Fig. 50B and Fig. 50C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Fig. 51 is a flowchart illustrating a method of forming a fin structure according to some embodiments. Fig. 52 is a flowchart illustrating a method of forming a fin structure according to some embodiments. Fig. 53 is a flowchart illustrating a method of forming a fin structure according to some embodiments. Fig. 54 is a flowchart illustrating a method of forming a fin structure according to some embodiments. DETAILED DESCRIPTION

[0006] The invention is defined by claim 1, which defines a method, claim 8, which defines a method, and claim 15, which defines an apparatus. Embodiments of the invention are provided in the dependent claims, the description, and the figures. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure.For example, in the following description, forming a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the components used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0008] Embodiments are described with respect to a specific context, namely a fin field-effect transistor (FinFET) device and a method of forming the same. Various embodiments presented herein are explained in the context of a FinFET device formed using a gate-last process. In other embodiments, a gate-first process may be applied. Various embodiments explained herein enable controlling stress in a channel of a FinFET device at a fin bottom, reducing or eliminating the wobble / bend effect of the fin, and enabling a FinFET device with a uniform threshold voltage (Vt) along a fin height. Various embodiments explained herein further enable improving device performance, such as a drive current of a FinFET device.

[0009] Fig. 1 illustrates an example of a fin field-effect transistor (FinFET) 100 in a three-dimensional view. The FinFET 100 includes a fin 105 on a substrate 101. The substrate 101 has isolation regions 103, and the fin 105 protrudes above and between adjacent isolation regions 103. A gate dielectric 107 is disposed along the sidewalls and above a top surface of the fin 105, and a gate electrode 109 is disposed above the gate dielectric 107. The source / drain regions 111 and 113 are disposed on opposite sides of the fin 105 with respect to the gate dielectric 107 and the gate electrode 109. The Fig. The FinFET 100 illustrated in Figure 1 is for illustration purposes only and is not intended to limit the scope of the present disclosure. As such, many variations are possible, such as epitaxial source / drain regions, multiple fins, multilayer fins, etc. Fig. 1 further illustrates reference cross-sections used in subsequent figures. Cross-section AA extends across a channel, the gate dielectric 107, and the gate electrode 109 of the FinFET 100. Cross-section CC lies in a plane parallel to cross-section AA and extends across fin 105 outside the channel. Cross-section BB is perpendicular to cross-sections AA and BB and extends along a longitudinal axis of fin 105 and, for example, in a direction of current flow between source / drain regions 111 and 113. The subsequent figures refer to these reference cross-sections for clarity.

[0010] Fig. 2A-22A, 24A-29A, 17B-22B, 24B-29B, and 18C-29C are cross-sectional views of intermediate stages in the fabrication of a FinFET device 200 according to some embodiments. In Fig. 2A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C are figures ending with an “A” designation along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1 shown cross section CC.

[0011] Referring to Fig. 2A, in some embodiments, the process of forming the FinFET device 200 begins with forming a mask 203 over a substrate 201. The substrate 201 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 201 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulating layer. The insulating layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 201 may include silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0012] Substrate 201 may further include integrated circuit devices (not shown). As one of ordinary skill in the art will appreciate, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, or the like, or combinations thereof, may be formed in and / or on substrate 201 to create the structural and functional design requirements for FinFET device 200. The integrated circuit devices may be formed using any suitable techniques.

[0013] In some embodiments, the substrate 201 may include a first region 205 and a second region 207. As described in more detail below, p-type devices are formed in the first region 205 and n-type devices are formed in the second region 207. The n-type devices may be NMOS devices, such as n-type FinFET devices. The p-type devices may be PMOS devices, such as p-type FinFET devices. Accordingly, the first region 205 may also be referred to as PMOS region 205, and the second region 207 may also be referred to as NMOS region 207.

[0014] Further referring to Fig. 2A, a mask 203 is formed over the substrate 201. In some embodiments, the mask 203 may be removed in subsequent doping steps (see Fig. 3A and Fig. 4A) to protect the substrate 201 during the doping process. In some embodiments, the mask 203 may comprise one or more mask layers. As shown in Fig. 2A, in some embodiments, the mask 203 may include a first mask layer 203A and a second mask layer 203B over the first mask layer 203A. The first mask layer 203A may comprise an oxide such as silicon oxide or the like, and may be formed using any suitable process such as thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. The second mask layer 203B may comprise a nitride such as silicon nitride, silicon oxynitride, a combination thereof, or the like, and may be formed using any suitable method such as thermal nitriding, ALD, CVD, a combination thereof, or the like.

[0015] With reference to Fig. 3A, a mask 301 is formed over the mask 203. The mask 301 is patterned to expose portions of the mask 203 that are disposed over the PMOS region 205 of the substrate 201. In some embodiments, the mask 301 comprises a photoresist and may be formed using a spin-on technique. In some embodiments, the mask 301 may be patterned using acceptable photolithography techniques. Subsequently, a doping process 303 is performed on the PMOS region 205 of the substrate 201 to form a well 305 in the substrate 201 while protecting the NMOS region 207 of the substrate 201 with the mask 301. In some embodiments, the doping process 303 may include an ion implantation process or the like. In some embodiments, n-type impurities are implanted into the substrate 201 to form the well 305, which is an n-type well.The n-type impurities may be phosphorus, arsenic, or the like. After implanting the impurities, an annealing process may be performed on the substrate 201 to activate the implanted impurities.

[0016] With reference to Fig. 4A, after performing the doping process 303, the mask 301 (see Fig. 3A). In some embodiments where the mask 301 includes the photoresist, the mask 301 may be removed using an ashing process followed by a wet cleaning process or other suitable photoresist removal processes. Subsequently, a mask 401 is formed over the mask 203. The mask 401 is patterned to expose portions of the mask 203 that are disposed over the NMOS region 207 of the substrate 201. In some embodiments, the mask 401 includes a photoresist and may be formed using a spin-on technique. In some embodiments, the mask 401 may be patterned using acceptable photolithography techniques. Subsequently, a doping process 403 is performed on the NMOS region 207 of the substrate 201 to form a well 405 in the substrate 201, while the PMOS region 205 of the substrate 201 is protected with the mask 401.In some embodiments, doping process 403 may include an ion implantation process or the like. In some embodiments, p-type impurities are implanted into substrate 201 to form well 405, which is a p-type well. The p-type impurities may be boron, BF2, or the like. After implanting the impurities, an annealing process may be performed on substrate 201 to activate the implanted impurities.

[0017] With reference to Fig. 5A, after performing the doping process 403, the mask 401 ( Fig. 4A). In some embodiments where the mask 401 includes the photoresist, the mask 401 may be removed using an ashing process followed by a wet cleaning process or other suitable photoresist removal processes. After removing the mask 401, the mask 203 is removed to expose the substrate 201. In some embodiments, the mask 203 may be removed using a chemical mechanical polishing (CMP) process, an etching process, a grinding process, a combination thereof, or the like. After removing the mask 203, a semiconductor layer 501 is formed over the substrate 201. In some embodiments, the semiconductor layer 501 may comprise similar materials as the material described above with reference to Fig. 2A, and the description will not be repeated here. In one embodiment, the semiconductor layer 501 is a silicon layer. In some embodiments, the semiconductor layer 501 may be grown epitaxially over the substrate 201. Accordingly, the semiconductor layer 501 may also be referred to as an epitaxial semiconductor layer 501.

[0018] With reference to Fig. 6A, the mask 601 is formed over the semiconductor layer 501 and patterned to expose a portion of the mask 601 disposed over the PMOS region 205 of the substrate 201. The mask 601 may comprise an oxide such as silicon oxide or the like and may be formed using any suitable process such as thermal oxidation, ALD, CVD, or a combination thereof. In some embodiments, the mask 601 may be patterned using suitable photolithography and etching techniques.

[0019] With reference to Fig. 7A, an exposed portion of the semiconductor layer 501 is recessed without completely removing the semiconductor layer 501 above the PMOS region 205 of the substrate 201. In some embodiments, the remaining portion of the semiconductor layer 501 above the PMOS region 205 of the substrate 201 may have a thickness T1 between approximately 1 nm and approximately 10 nm. In some embodiments, the semiconductor layer 501 may be recessed using a suitable etch process while using the mask 601 as an etch mask.

[0020] Referring to Fig. 8A, a semiconductor layer 801 is formed over the PMOS region 205 of the substrate 201. In some embodiments, the semiconductor layer 801 comprises SiGe and is epitaxially grown over the remaining portion of the semiconductor layer 501 in the PMOS region 205. In some embodiments, the semiconductor layer 801 comprising SiGe may be formed by low-pressure CVD (LPCVD) using suitable Ge and Si precursors. The Ge precursors may include GeH4, GeH3CH3, (GeH3)2CH2, a combination thereof, or the like. The Si precursors may include SiH2Cl2, SiH4, a combination thereof, or the like.

[0021] With reference to Fig. 9A, after forming the semiconductor layer 801, the mask 601 is removed. In some embodiments, the mask 601 (see Fig. 8A) using a CMP process, an etching process, a grinding process, a combination thereof, or the like. In some embodiments where the mask 601 comprises silicon oxide, the mask 601 is removed by an etching process using diluted HF. In some embodiments, after removing the mask 601, a polishing process is performed on the semiconductor layers 501 and 801. The polishing process may include a CMP process, an etching process, a grinding process, a combination thereof, or the like. In some embodiments, after performing the polishing process, a semiconductor layer 901 is formed over the semiconductor layers 501 and 801. In some embodiments, the semiconductor layer 901 has a thickness between approximately 1 nm and approximately 10 nm. In some embodiments, the semiconductor layer 901 may be formed using similar materials and methods as those described above with reference to Fig. 5A, and the description will not be repeated here. In some embodiments where semiconductor layers 501 and 901 are silicon layers and semiconductor layer 801 is a SiGe layer, an interface between semiconductor layers 501 and 901 may not be detectable (as in Fig. 9A by a dashed line), while an interface between the semiconductor layers 801 and 901 is detectable (as in Fig. 9A by a solid line). In some embodiments, the semiconductor layer 901 may prevent Ge-out diffusion from the semiconductor layer 801 during a subsequent patterning process for forming semiconductor stripes (see Fig. 10A). Accordingly, the semiconductor layer 901 can also be referred to as a buffer layer.

[0022] Further referring to Fig. 9A, after forming the semiconductor layer 901, a mask 903 is formed over the semiconductor layer 901. In some embodiments, the mask 903 includes a first mask layer 903A and a second mask layer 903B over the first mask layer 903A. In some embodiments, the first semiconductor layer 903A may be formed using similar materials and methods as those described above with reference to Fig. 2A, and the description will not be repeated here. In some embodiments, the second semiconductor layer 903B may be formed using similar materials and methods as those described above with reference to Fig. 2A, and the description will not be repeated here.

[0023] With further reference to Fig. 8A and Fig. 9A, in some embodiments, the semiconductor layer 801 comprising SiGe comprises a uniform Ge concentration throughout. In such embodiments, the uniform Ge concentration is between approximately 15 at. % and approximately 40 at. %. In other embodiments, the semiconductor layer 801 comprising SiGe has a non-uniform Ge concentration, with the Ge concentration increasing from a lowest Ge concentration at a bottom surface 801b of the semiconductor layer 801 to a highest Ge concentration at a top surface 801t of the semiconductor layer 801. In some embodiments, the Ge concentration at the bottom surface 801b of the semiconductor layer 801 is between approximately 10 at. % and approximately 20 at. %. In some embodiments, the Ge concentration at the top surface 801t of the semiconductor layer 801 is between approximately 25 at. % and approximately 35 at. %.In yet other embodiments, the semiconductor layer 801 comprising SiGe has a non-uniform Ge concentration, with a lower portion 8011 of the semiconductor layer 801 having a uniform Ge concentration and an upper portion 8012 of the semiconductor layer 801 having a non-uniform Ge concentration. In such embodiments, the Ge concentration increases from a low Ge concentration at an interface 801i between the lower portion 8011 and the upper portion 8012 of the semiconductor layer 801 to a high Ge concentration at the upper surface 801t of the semiconductor layer 801. In some embodiments, the uniform Ge concentration of the lower portion 8011 of the semiconductor layer 801 is between approximately 15 atomic % and approximately 40 atomic %. In some embodiments, the Ge concentration at the interface 801i is between approximately 10 atomic % and approximately 20 atomic %.In some embodiments, the Ge concentration at the top surface 801t of the semiconductor layer 801 is between about 25 atomic % and about 35 atomic %.

[0024] Fig. 10A shows the formation of semiconductor stripes 1005 in PMOS region 205 and semiconductor stripes 1007 in NMOS region 207. First, mask layers 903A and 903B are patterned, wherein openings in mask layers 903A and 903B expose portions of semiconductor layers 501, 801, and 901 in which trenches 1001 and 1003, respectively, are to be formed. Next, a patterning process may be performed, wherein the patterning process creates trenches 1001 in PMOS region 205 and trenches 1003 in NMOS region 207 through the openings in mask 903. The remaining portions of the substrate 201 and the semiconductor layers 501, 801, and 901 that lie beneath the patterned mask 903 form the semiconductor stripes 1005 in the PMOS region 205. The remaining portions of the substrate 201 and the semiconductor layers 501 and 901 that lie beneath the patterned mask 903 form the semiconductor stripes 1007 in the NMOS region 207.The patterning process may be one or more acceptable etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like. In some embodiments, the patterning process includes a first etching process performed on the PMOS region 205 while the NMOS region 207 is protected by a mask (not shown), followed by a second etching process performed on the NMOS region 207 while the PMOS region 205 is protected by a mask (not shown), wherein the first etching process is different from the second etching process. In other embodiments, the second etching process may be performed before the first etching process.

[0025] Referring to Fig. 11A is a conformal lining 1101 on side walls and lower surfaces of trenches 1001 and 1003 (see Fig. 10A), which are subsequently filled with an insulating material 1103. In some embodiments, the liner 1101 may comprise a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal semiconductor (e.g., silicon) oxide, a semiconductor (e.g., silicon) oxynitride, a polymer thereof, or the like. Formation of the liner 1101 may comprise any suitable method, such as ALD, CVD, high-density plasma CVD (HDP-CVD), physical vapor deposition (PVD), a combination thereof, or the like. In some embodiments, the insulating material 1103 may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, a combination thereof, or the like, and may be formed by HDP-CVD, flowable CVD (FCVD) (e.g.,a CVD-based material deposition in a remote plasma system and post-bake to convert it to another material such as an oxide), a combination thereof, or the like. Other insulating materials formed by any acceptable methods may also be used. In some embodiments, after the insulating material 1103 is deposited, an annealing process may be performed on the insulating material 1103. In such embodiments, the liner 1101 may prevent (or at least reduce) the diffusion of the semiconductor material from the semiconductor stripes 1005 and 1007 (e.g., Si or Ge) into the insulating material 1103 during the annealing process.

[0026] Referring to Fig. 12A, a first planarization process, such as a CMP process, is performed to remove excess insulation material 1103 so that top surfaces of remaining portions of the insulation material 1103 are coplanar with the top surfaces of the liner 1101.

[0027] Referring to Fig. 13A, a second planarization process, such as a CMP process, is performed to remove excess insulation material 1103 such that top surfaces of remaining portions of insulation material 1103 are coplanar with a top surface of mask layer 903A. The second planarization process further removes mask layer 903B and portions of liner 1101. In some embodiments, the second planarization process differs from the first planarization process.

[0028] Fig. 14A shows the recess of the insulation material 1103 and the liner 1101. The remaining portions of the insulation material 1103 and the liner 1101 form shallow trench isolation (STI) regions 1401. The insulation material 1103 and the liner 1101 are recessed such that upper portions of the semiconductor stripes 1105 and 1107 protrude between adjacent STI regions 1401. Furthermore, the upper surfaces of the STI regions 1401 may have a flat surface, as shown, a convex surface, a concave surface (such as a dome), or a combination thereof. The upper surfaces of the STI regions 1401 may be formed flat, convex, and / or concave by a suitable etching. The insulation material 1103 and the liner 1101 may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material 1103 and the liner 1101.In some embodiments, oxide removal may be performed using a CERTAS® etch, a SICONI tool from Applied Materials, or dilute hydrofluoric acid (dHF). In some embodiments, the recessing process further removes portions of the patterned semiconductor layer 901 (see FIG. Fig. 13A) from the semiconductor strips 1005 and 1007.

[0029] Referring to Fig. 15A, one or more etching processes are performed on exposed portions of the semiconductor stripes 1005 and 1007 (see Fig. 14A) to form fins 1501 and 1503, respectively. In some embodiments, a similar etch process is performed on the exposed portions of semiconductor stripes 1005 and 1007. In such embodiments, an oxide layer, such as a silicon oxide layer (not shown), may be formed over the exposed portions of semiconductor stripes 1007 to compensate for the etch rate difference between semiconductor stripes 1005 and 1007. In other embodiments, two different etch processes are performed on the exposed portions of semiconductor stripes 1005 and 1007. In some embodiments, one or more etch processes may include an anisotropic etch process, such as a reactive ion etch (RIE) or the like. In some embodiments, the etch chemistry and other parameters of the RIE process may be tuned to tune the etch rates of the RIE process.In some embodiments, an etch rate along a crystallographic direction <100> , R. 100 , greater than an etching rate along a crystallographic direction <110> , R 110 which is greater than an etching rate along a crystallographic direction <111> , R 111 , is. In some embodiments, R 100 :R 110 :R 111 equal to 600:400:1. In some embodiments, where the top surfaces of semiconductor layers 501 and 801 are crystallographic planes (100), the RIE process changes the slopes of the sidewalls of the exposed portions of semiconductor stripes 1005 and 1007 such that the widths of fins 1501 and 1503 decrease as fins 1501 and 1503 extend away from the respective adjacent STI regions 1401. Forming semiconductor stripes 1005 and 1007 into fins 1501 and 1503, respectively, as described above with reference to Fig. 14A and Fig. 15A, enables controlling strain in channels of the FinFET device 200 at fin bottoms and reducing or eliminating the fin wobble / bend effect and enables the FinFET device 200 to have a uniform threshold voltage (Vt) along fin heights.

[0030] Fig. 16A shows an enlarged view of a Fig. 15A. In some embodiments, the fin 1501 has a height H1 between about 30 nm and about 60 nm. In some embodiments, a width of the fin 1501 decreases as the fin 1501 extends away from the adjacent STI regions 1401. In some embodiments, a portion of the fin 1501 farthest from the adjacent STI regions 1401 has a width W1 between about 2 nm and about 10 nm. In some embodiments, a portion of the fin 1501 closest to the adjacent STI regions 1401 has a width W2 between about 4 nm and about 14 nm. In some embodiments, the width W2 is greater than the width W1. In some embodiments where the fin 1501 comprises SiGe, the fin 1501 has a uniform Ge concentration. In such embodiments, the uniform Ge concentration is between about 15 at.% and about 40 at.%.In other embodiments where the fin 1501 comprises SiGe, the fin 1501 has a non-uniform Ge concentration, with the Ge concentration increasing as the fin 1501 extends away from the adjacent STI regions 1401. In some embodiments, a Ge concentration of a portion of the fin 1501 closest to adjacent STI regions 1401 is between about 10 atomic % and about 20 atomic %. In some embodiments, a Ge concentration of a portion of the fin 1501 farthest from adjacent STI regions 1401 is between about 25 atomic % and about 35 atomic %. In some embodiments, sidewalls of fin 1501 form an angle θ1 with the top surfaces of adjacent STI regions 1401. In some embodiments, angle θ1 is between approximately 80 degrees and approximately 90 degrees. In some embodiments, fins 1503 (see FIG. Fig. 15A) have similar shapes and sizes to the Finns 1501, and the description is not repeated here.

[0031] Referring to Fig. 17A and Fig. 17B, ​​a dielectric layer 1701 is formed on sidewalls and top surfaces of fins 1501 and 1503. In some embodiments, dielectric layer 1701 may also be formed over STI regions 1401. In other embodiments, the top surfaces of STI regions 1401 may be free of dielectric layer 1701. Dielectric layer 1701 may comprise an oxide such as silicon oxide or the like and may be deposited according to acceptable techniques (e.g., using ALD, CVD, PVD, a combination thereof, or the like) or thermally grown (e.g., using thermal oxidation or the like). A gate electrode layer 1703 is formed over dielectric layer 1701, and a mask 1705 is formed over gate electrode layer 1703.In some embodiments, the gate electrode layer 1703 may be deposited over the dielectric layer 1701 and then planarized using, for example, a CMP process. Subsequently, the mask 1705 may be deposited over the gate electrode layer 1703. The gate electrode layer 1703 may be made of, for example, polysilicon, although other materials having high etch selectivity with respect to the material of the STI regions 1401 may also be used. The mask 1705 may comprise one or more layers of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using any suitable method such as thermal oxidation, thermal nitriding, ALD, PVD, CVD, a combination thereof, or the like.In the illustrated embodiment, a single dielectric layer 1701, a single gate electrode layer 1703, and a single mask 1705 are formed over the PMOS region 205 and the NMOS region 207. In other embodiments, different dielectric layers, different gate electrode layers, and different masks may be formed separately in the PMOS region 205 and the NMOS region 207.

[0032] Referring to Fig. 18A, Fig. 18B and Fig. 18C, the mask 1705 (see Fig. 17A and Fig. 17B) may be patterned using acceptable photolithography and etching techniques to form a patterned mask 1801 in the PMOS region 205 and a patterned mask 1803 in the NMOS region 207. The pattern of masks 1801 and 1803 is then transferred to the gate electrode layer 1703 and the dielectric layer 1701 by an acceptable etching technique to form gates 1805 in the PMOS region 205 and gates 1807 in the NMOS region 207. The pattern of gates 1805 and 1807 covers channel regions of fins 1501 and 1503, while exposing the source / drain regions of fins 1501 and 1503, respectively. The gates 1805 and 1807 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the fins 1501 and 1503, respectively. A size of the gates 1805 and 1807 and a distance between the gates 1805 and 1807 may depend on a region of a die in which the gates 1805 and 1807 are formed.In some embodiments, gates 1805 and 1807 may have a larger size and a larger pitch when located in an input / output region of a die (e.g., where input / output circuitry is disposed) than when located in a logic region of a die (e.g., where logic circuitry is disposed). As described in more detail below, in some embodiments, gates 1805 and 1807 are sacrificial gates and are subsequently replaced with replacement gates. In such embodiments, gates 1805 and 1807 may also be referred to as sacrificial gates. In other embodiments, gates 1805 and 1807 are not replaced and are present in the final FinFET device 200.

[0033] With further reference to Fig. 18A, Fig. 18B and Fig. 18C, lightly doped source / drain (LDD) regions 1809 are formed in the fins 1501 in the PMOS region 205 and LDD regions 1811 are formed in the fins 1503 in the NMOS region 207. Similar to the above-described Fig. 3A and Fig. 4A, a mask (not shown) such as a photoresist is formed over the NMOS region 207 while the PMOS region 205 is exposed, and p-type impurities are implanted into the exposed fins 1501 to form the LDD regions 1809 in the PMOS region 205. The p-type impurities may be any of the impurities described above with reference to Fig. 4A. During the implantation of the LDD regions 1809, the gates 1805 and the patterned mask 1801 act as a combined mask to prevent (or at least reduce) dopants from being implanted into channel regions of the exposed fins 1501. Thus, the LDD regions 1809 may be substantially formed into source / drain regions of the exposed fins 1501. The mask is then removed using a suitable removal process. In some embodiments where the mask comprises a photoresist, the mask may be removed using, for example, an ashing process followed by a wet cleaning process. After the implantation process, an annealing process may be performed to activate the implanted impurities.Similarly, a second mask (not shown), such as a photoresist, is formed over the PMOS region 205 while the NMOS region 207 is exposed, and n-type impurities are implanted into the exposed fins 1503 to form the LDD regions 1811 in the NMOS region 207. During the implantation of the LDD regions 1811, the gates 1807 and the patterned mask 1803 act as a combined mask to prevent (or at least reduce) dopants from being implanted into channel regions of the exposed fins 1503. Thus, the LDD regions 1811 are essentially formed into source / drain regions of the exposed fins 1503. The second mask is then removed using a suitable removal method. In some embodiments where the second mask comprises a photoresist, the second mask may be removed using, for example, an ashing process followed by a wet cleaning process.The n-type impurities may be any of those described above with reference to . Fig. 3A. After the implantation process, an annealing process can be performed to activate the implanted impurities.

[0034] Fig. 19A-19C and 20A-20C illustrate the formation of spacers 2001 on sidewalls of the gates 1805 according to some embodiments. First, with reference to Fig. 19A-19C, a dielectric layer 1901 is covered on exposed surfaces of the gates 1805 and 1807, the patterned masks 1801 and 1803, the fins 1501 and 1503, and the STI regions 1401. In some embodiments, the dielectric layer 1901 may comprise silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carboxynitride (SiOCN), a combination thereof, or the like, and may be formed using CVD, ALD, a combination thereof, or the like.

[0035] With reference to Fig. 20A-20C, a patterning process is performed to remove excess portions of the dielectric layer 1901 in the PMOS region 205 to form the spacers 2001 on the sidewalls of the gates 1805. In some embodiments, a mask 2003 is formed over the dielectric layer 1901 in the NMOS region 207 while exposing the PMOS region 205. In some embodiments, the mask 2003 may, for example, comprise a photoresist or the like and may be formed using a spin-on coating or the like. Subsequently, an etching process is performed on the dielectric layer 1901 using the mask 2003 as an etch mask. The etching process may be anisotropic. The etching process removes lateral portions of the dielectric layer 1901 so that remaining vertical portions of the dielectric layer 1901 form the spacers 2001 on the sidewalls of the gates 1805.In the illustrated embodiment, the etching process completely removes the dielectric layer 1901 from the fins 1501. In other embodiments, portions of the dielectric layer 1901 remain on the sidewalls of the fins 1501 and form spacers (not shown) on the sidewalls of the fins 1501.

[0036] Fig. 21A-21C and 22A-22C illustrate the formation of epitaxial source / drain regions 2201 in the PMOS region 205. Referring to Fig. 21A-21C, after forming the spacers 2001, a patterning process is performed on the fins 1501 in the PMOS region 205 to form recesses 2101 in the source / drain regions of the fins 1501, while the NMOS region 207 is protected by the mask 2003. In some embodiments, the patterning process may include a suitable anisotropic dry etching process, while the patterned mask 1801, the gates 1805, the spacers 2001, the mask 2003, and / or the STI regions 1401 are used as a combined mask. The suitable anisotropic dry etching process may include reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like.

[0037] Referring to Fig. 22A, Fig. 22B and Fig. 22C, epitaxial source / drain regions 2201 are formed in the recesses 2101 (see Fig. 21A, Fig. 21B and Fig. 21C). In some embodiments, the epitaxial source / drain regions 2201 are epitaxially grown in the recesses 2101 using metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), and selective epitaxial growth (SEG), a combination thereof, or the like. In some embodiments where the fins 1501 comprise SiGe, the epitaxial source / drain regions 2201 may comprise SiGe:B or the like. The epitaxial source / drain regions 2201 may have surfaces raised from the respective surfaces of the fins 1501 and may have facets. In some embodiments, the epitaxial source / drain regions 2201 may extend beneath the fins 1501. In some embodiments, the material of the epitaxial source / drain regions 2201 may be implanted with suitable dopants, such as p-type dopants.In some embodiments, the implantation process is similar to the process used to form the well 405 as described above with reference to FIG. Fig. 4A, and the description will not be repeated here. In other embodiments, the material of the epitaxial source / drain regions 2201 may be doped in situ during growth. After forming the epitaxial source / drain regions 2201, the mask 2003 is removed using a suitable mask removal process. In some embodiments where the mask 2003 includes the photoresist, the mask 2003 may be removed using an ashing process followed by a wet cleaning process or other suitable photoresist removal processes.

[0038] With further reference to Fig. 22A, Fig. 22B and Fig. 22C, in the illustrated embodiment, each of the epitaxial source / drain regions 2201 is physically separated from other epitaxial source / drain regions 2201. In other embodiments, adjacent epitaxial source / drain regions 2201 may be merged. One such embodiment is shown in Fig. 23C, in which adjacent epitaxial source / drain regions 2201 are merged to form a common epitaxial source / drain region 2201.

[0039] With reference to Fig. 24A, Fig. 24B and Fig. 24C, after forming the epitaxial source / drain regions 2201 in the PMOS region 205, the epitaxial source / drain regions 2401 are formed in the NMOS region 207. In some embodiments, the epitaxial source / drain regions 2401 are formed in the NMOS region 207 using similar methods as the epitaxial source / drain regions 2201 described above with reference to Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B and Fig. 22C, and the description will not be repeated here. In some embodiments, during the formation of the epitaxial source / drain regions 2401 in the NMOS region 207, the PMOS region 205 is protected by a mask (not shown). In some embodiments, the dielectric layer 1901 in the NMOS region 207 is patterned to form spacers 2403 along the sidewalls of the gates 1807. The dielectric layer 1901 in the NMOS region 207 may be patterned using similar techniques as the dielectric layer 1901 in the PMOS region 205 described above with reference to Fig. 20A, Fig. 20B and Fig. 20C, and the description is not repeated here. Subsequently, the source / drain regions of the fins 1503 in the NMOS region 207 are etched to form recesses (shown as connected to the epitaxial source / drain regions 2401 in Fig. 24B and Fig. 24C filled) similar to the recesses 2101 (see Fig. 21B and Fig. 21C). The recesses in the source / drain regions of the fins 1503 may be formed using similar methods as the recesses 2101 described above with reference to Fig. 21A, Fig. 21B and Fig. 21C, and the description is not repeated here.

[0040] With further reference to Fig. 24A, Fig. 24B and Fig. 24C, the epitaxial source / drain regions 2401 are epitaxially grown in the recesses in the NMOS region 207 using MOCVD, MBE, LPE, VPE, SEG, a combination thereof, or the like. In some embodiments where the fins 1503 are formed of silicon, the epitaxial source / drain regions 2401 may include silicon, SiC, SiC:P, Si:P, SiAs:P, or the like. In some embodiments, the material of the epitaxial source / drain regions 2401 may be implanted with suitable dopants, such as n-type dopants. In some embodiments, the implantation process is similar to the process used to form the well 305, as described above with reference to Fig. 3A, and the description will not be repeated here. In other embodiments, the material of the epitaxial source / drain regions 2401 may be doped in situ during growth. After forming the epitaxial source / drain regions 2401, the mask protecting the PMOS region 205 is removed using a suitable mask removal process. In some embodiments where the mask includes the photoresist, the mask may be removed using an ashing process followed by a wet cleaning process or other suitable photoresist removal processes. In some embodiments, the epitaxial source / drain regions 2401 are formed in the PMOS region 205 before the epitaxial source / drain regions 2401 are formed in the NMOS region 207.In other embodiments, the epitaxial source / drain regions 2401 are formed in the NMOS region 207 before the epitaxial source / drain regions 2401 are formed in the PMOS region 205. In the illustrated embodiment, each of the epitaxial source / drain regions 2401 is physically separated from other epitaxial source / drain regions 2401. In other embodiments, adjacent epitaxial source / drain regions 2401 may be separated similarly to the arrangement shown in FIG. Fig. 22A, Fig. 22B and Fig. 22C shown common epitaxial source / drain region 2201.

[0041] Referring to Fig. 25A, Fig. 25B and Fig. 25C, an etch stop layer (ESL) 2501 and an interlayer dielectric (ILD) 2503 are deposited over the gates 1805 and 1807 and over the epitaxial source / drain regions 2201 and 2401. In some embodiments, the ILD 2503 is a flowable film formed by flowable CVD. In some embodiments, the ILD 2503 is formed from a dielectric material such as silicon oxide, SiOC, ZrO2, HfO2, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectrics, ultra-low-k dielectrics, high-k dielectrics, a combination thereof, or the like, and may be deposited by any suitable method such as CVD, PECVD, a spin-on-glass process, a combination thereof, or the like.In some embodiments, the ESL 2501 is used as a stop layer while the ILD 2503 is patterned to form openings for subsequently formed contact plugs. Accordingly, a material for the ESL 2501 may be selected such that the material of the ESL 2501 has a lower etch rate than the material of the ILD 2503. In some embodiments, the ESL 2501 may comprise silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carboxynitride (SiOCN), a combination thereof, or the like, and may be formed using CVD, ALD, a combination thereof, or the like. In some embodiments, a planarization process, such as a CMP process, may be performed to align the top surface of the ILD 2503 with the top surfaces of the patterned masks 1801 and 1803.In other embodiments, planarization may also remove masks 1801 and 1803 or portions thereof from gates 1805 and 1807, respectively.

[0042] Referring to Fig. 26A, Fig. 26B and Fig. 26C, in some embodiments, the patterned masks 1801 and 1803 and the gate electrode layers 1703 of the gates 1805 and 1807 are removed using one or more suitable etch processes to form recesses 2601 in the PMOS region 205 and recesses 2603 in the NMOS region 207. Each of the recesses 2601 exposes a channel region of a respective fin 1501 in the PMOS region 205. Each of the recesses 2603 exposes a channel region of a respective fin 1503 in the NMOS region 207. In the illustrated embodiment, the dielectric layers 1701 remain over the channel regions of the fins 1501 and 1503. In other embodiments, the dielectric layers 1701 may also be removed during the formation of the recesses 2601 and 2603.

[0043] With further reference to Fig. 27A, Fig. 27B and Fig. 27C, a gate dielectric layer 2701, a work function layer 2703 and a gate electrode layer 2705 are formed in the recesses 2601 (see Fig. 26B) is formed in the PMOS region 205, while the NMOS region is protected by a mask (not shown). In some embodiments, the gate dielectric layer 2701 is conformally deposited in the recesses 2601. In some embodiments, the gate dielectric layer 2701 comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layer 2701 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 2701 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation of the gate dielectric layer 2701 may comprise molecular beam deposition (MBD), ALD, PECVD, a combination thereof, or the like.

[0044] In some embodiments where the dielectric layers 1701 are not removed over the channel regions of the fins 1501 while the recesses 2601 are formed, the dielectric layers 1701 may act as interface layers between the gate dielectric layer 2701 and the channel regions of the fins 1501. In some embodiments where the dielectric layers 1701 are removed over the channel regions of the fins 1501 while the recesses 2601 are formed, one or more interface layers may be formed over the channel regions of the fins 1501 before the gate dielectric layer 2701 is formed, with the gate dielectric layer 2701 formed over the one or more interface layers. The interface layers help buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material.In some embodiments, the interfacial layers comprise a chemical silicon oxide, which can be formed through chemical reactions. For example, a chemical oxide can be formed using deionized water + ozone (O3), NH4OH + H2O2 + H2O (APM), or other methods. Other embodiments can use a different material or different processes (e.g., a thermal oxidation or deposition process) to form the interfacial layers.

[0045] After forming the gate dielectric layer 2701, the work function layer 2703 is formed over the gate dielectric layer. In some embodiments, the work function layer 2703 comprises TiN, WN, TaN, Ru, Co, a combination thereof, or the like, and may be formed using ALD, CVD, PVD, combinations thereof, or the like. After forming the work function layer 2703, remaining portions of the recesses 2601 (see Fig. 26B) is filled with a gate electrode layer 2705. In some embodiments, the gate electrode layer 2705 comprises Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, or the like, and may be formed using ALD, CVD, PVD, plating, combinations thereof, or the like. After filling the recesses 2601 with the gate electrode layer 2705, a planarization process such as a CMP process may be performed to remove the excess portions of the gate dielectric layer 2701, the work function layer 2703, and the gate electrode layer 2705, which excess portions are located above the top surface of the ILD 2503.The portions of the gate dielectric layer 2701, the work function layer 2703, and the gate electrode layer 2705 that remain in the recesses 2601 in combination with the respective dielectric layers 1701 form gates 2707 in the PMOS region 205. The gates 2707 may also be referred to as replacement gates.

[0046] With further reference to Fig. 27A, Fig. 27B and Fig. 27C, a gate dielectric layer 2709, a work function layer 2711 and a gate electrode layer 2713 are formed in the recesses 2603 (see Fig. 26B) is formed in the NMOS region 207, while the PMOS region 205 is protected by a mask (not shown). In some embodiments, the gate dielectric layer 2709 is conformally deposited in the recesses 2603. In some embodiments, the gate dielectric layer 2709 may be formed using similar materials and methods as the gate dielectric layer 2701, and the description will not be repeated here. In some embodiments, where the dielectric layers 1701 are not removed over the channel regions of the fins 1503 while the recesses 2603 are formed, the dielectric layers 1701 may act as interface layers between the gate dielectric layer 2709 and the channel regions of the fins 1503.In some embodiments where the dielectric layers 1701 over the channel regions of the fins 1503 are removed while the recesses 2603 are formed, one or more interface layers may be formed over the channel regions of the fins 1503 before the gate dielectric layer 2709 is formed, wherein the gate dielectric layer 2709 is formed over the one or more interface layers.

[0047] After forming the gate dielectric layer 2709, the work function layer 2711 is formed over the gate dielectric layer. In some embodiments, the work function layer 2711 comprises Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, a combination thereof, or the like, and may be formed using ALD, CVD, PVD, combinations thereof, or the like. After forming the work function layer 2711, remaining portions of the recesses 2603 (see Fig. 26B) is filled with a gate electrode layer 2713. In some embodiments, the gate electrode layer 2713 may be formed using similar materials and processes as the gate electrode layer 2705, and the description will not be repeated here. After filling the recesses 2603 with the gate electrode layer 2713, a planarization process, such as a CMP process, may be performed to remove the excess portions of the gate dielectric layer 2709, the work function layer 2711, and the gate electrode layer 2713, which excess portions are located above the top surface of the ILD 2503. The portions of the gate dielectric layer 2709, the work function layer 2711, and the gate electrode layer 2713 remaining in the recesses 2603 in combination with the respective dielectric layers 1701 form gates 2715 in the NMOS region 207.The 2715 gates can also be referred to as replacement gates.

[0048] With further reference to Fig. 27A, Fig. 27B and Fig. 27C, in the illustrated embodiment, gates 2707 are formed in PMOS region 205 before gates 2715 are formed in NMOS region 207. In other embodiments, gates 2715 are formed in NMOS region 207 before gates 2707 are formed in PMOS region 205.

[0049] Referring to Fig. 28A, Fig. 28B and Fig. 28C, an ILD 2801 is deposited over the ILD 2503. In some embodiments, the ILD 2801 may be formed using similar materials and methods as those described above with reference to Fig. 25A, Fig. 25B and Fig. 25C, and the description will not be repeated here. In some embodiments, the ILD 2801 and the ILD 2503 are formed from the same material. In other embodiments, the ILD 2801 and the ILD 2503 are formed from different materials. The ESL 2501 and the ILDs 2503 and 2801 are patterned to form openings 2803 and 2805 in the PMOS region 205 and openings 2807 and 2809 in the NMOS region 207. In some embodiments, the ESL 2501 and the ILDs 2503 and 2801 may be patterned using acceptable photolithography and etching techniques. The openings 2803 expose the respective gates 2707 in the PMOS region 205. The openings 2805 expose the respective epitaxial source / drain regions 2201 in the PMOS region 205. The openings 2807 expose the respective gates 2715 in the NMOS region 207.Openings 2809 expose the respective epitaxial source / drain regions 2401 in the NMOS region 207. As described in more detail below, openings 2803, 2805, 2807, and 2809 are filled with one or more conductive materials to form contact plugs that provide electrical connections to the epitaxial source / drain regions 2201 and 2401 and the gates 2707 and 2715.

[0050] With further reference to Fig. 28A, Fig. 28B and Fig. 28C, self-aligned layers 2811 and 2813 are formed through openings 2805 and 2809, respectively. In some embodiments, a metallic material is deposited in openings 2805 and 2809. The metallic material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, and a combination thereof, or the like, and may be formed using PVD, sputtering, or the like. An annealing process is then performed to form self-aligned layers 2811 and 2813. In some embodiments, the annealing process causes the metallic material to react with semiconductor materials of epitaxial source / drain regions 2201 and 2401 to form self-aligned layers 2811 and 2813, respectively.

[0051] Referring to Fig. 29A, Fig. 29B and Fig. 29C are the openings 2803, 2805, 2807 and 2809 (see Fig. 28A, Fig. 28B and Fig. 28C) are filled with one or more conductive materials to form contact plugs 2901, 2903, 2905, and 2907, respectively. In some embodiments, a liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings 2803, 2805, 2807, and 2809. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like, and may be CVD, PVD, ALD, a combination thereof, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, a combination thereof, or the like, and may be formed using CVD, PVD, ALD, an electrochemical plating process, an electroless plating process, a combination thereof, or the like.A planarization process, such as a CMP process, may be performed to remove excess portions of the liner and conductive material from a top surface of the ILD 2801. The remaining portions of the liner and conductive material form contact plugs 2901, 2903, 2905, and 2907 in the openings 2803, 2805, 2807, and 2809, respectively. Contact plugs 2901 and 2905 are physically and electrically coupled to the gates 2707 and 2715, respectively. Contact plugs 2903 and 2907 are physically coupled to the self-aligned layers 2811 and 2813, respectively. The contact plugs 2903 and 2907 are electrically coupled to the epitaxial source / drain regions 2201 and 2401 via the self-aligned layers 2811 and 2813, respectively.

[0052] Fig. 30A, Fig. 31A, Fig. 31B and Fig. 31C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 3000 according to some embodiments. In Fig. 30A, Fig. 31A, Fig. 31B and Fig. 31C are figures ending with an “A” designation, along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 3000 may be the same as described above with reference to Fig. 2A-22A, 24A-29A, 17B-22B, 24B-29B, and 18C-29C for forming the FinFET device 200, with like features being designated by like reference numerals, and their description will not be repeated here.

[0053] Referring to Fig. 30A, the process of forming the FinFET device 3000 begins with the formation of a structure that is Fig. 14A. In some embodiments, one or more etching processes described above with reference to Fig. 15A, on exposed portions of the semiconductor strips 1005 (see Fig. 14A) in the PMOS region 205 to form fins 1501, while exposed portions of the semiconductor stripes 1007 (see Fig. 14A) in the NMOS region 207 may be protected with a mask (not shown). In such embodiments, the exposed portions of the semiconductor stripes 1007 form fins 3001 in the NMOS region 207. With reference to Fig. 31A, Fig. 31B and Fig. 31C, the above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 30A to form the FinFET device 3000, and the description is not repeated here.

[0054] Fig. 32A-35A, 35B, and 35C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 3200 according to some embodiments. In Fig. 32A-35A, 35B and 35C are figures ending with an “A” designation along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 3200 may be similar to those described above with reference to Fig. 2A-22A, 24A-29A, 17B-22B, 24B-29B, and 18C-29C for forming the FinFET device 200, with like features being designated by like reference numerals, and their description will not be repeated here.

[0055] In some embodiments, the process of forming the FinFET device 3200 begins with forming a structure that Fig. 13A. Referring to Fig. 32A and Fig. 32B are formed after the structure is formed from Fig. 13A, the insulating material 1103 and the liner 1101 are recessed to expose upper portions of the semiconductor stripes 1005 in the PMOS region 205 and upper portions of the semiconductor stripes 1007 in the NMOS region 207, respectively, to form fins 3201 in the PMOS region 205 and fins 3203 in the NMOS region 207. The remaining portions of the insulating material 1103 and the liner 1101 form STI regions 1401.

[0056] Firstly, referring to Fig. 32A, the recess process comprises a first recess process that exposes the upper portions 3201a of the fins 3201 and the upper portions 3203a of the fins 3203. In some embodiments, the first recess process may comprise an etch process, such as a CERTAS® etch process, a SICONI etch process from Applied Materials, a dilute hydrofluoric acid (dHF) etch process, or the like. In some embodiments, the etch process of the first recess process is selected such that the etch process also exposes the semiconductor stripes 1005 and 1007 (see Fig. 13A) and narrows the widths of the upper portions of the semiconductor stripes 1005 and 1007. In such embodiments, the widths of the upper portions 3201a of the fins 3201 are less than the widths of the upper portions of the semiconductor stripes 1005, and the widths of the upper portions 3203a of the fins 3203 are less than the widths of the upper portions of the semiconductor stripes 1007. In some embodiments, the upper portions 3203a of the fins 3203 have uniform widths. With reference to Fig. 33A, the recessing process further includes a second recessing process that exposes the lower portions 3201b of the fins 3201 and the lower portions 3203b of the fins 3203.

[0057] In some embodiments, the second recess process may include an etching process, such as a CERTAS® etching process, a SICONI etching process from Applied Materials, a dilute hydrofluoric acid (dHF) etching process, or the like. In some embodiments, the second recess process is different from the first recess process. In some embodiments, the etching process of the second recess process is different from the etching process of the first recess process. In some embodiments, the etching process of the second recess process is selected such that the etching process substantially does not etch the semiconductor stripes 1005 and 1007. In such embodiments, the widths of the lower portions 3201b of the fins 3201 are substantially equal to the widths of the semiconductor stripes 1005, and the widths of the lower portions 3203a of the fins 3203 are substantially equal to the widths of the semiconductor stripes 1007.In some embodiments, the lower portions 3203b of the fins 3203 have uniform widths. Forming the semiconductor strips 1005 and 1007 into fins 3201 and 3203, respectively, as described above with reference to FIG. Fig. 32A and Fig. 33A, enables controlling strain in channels of the FinFET device 3200 at fin bottoms and reducing or eliminating the fin wobble / bend effect and enables the FinFET device 3200 to have a uniform threshold voltage (Vt) along fin heights.

[0058] Fig. 34A shows an enlarged view of a Fig. 33A. In some embodiments, a width W3 of the lower portion 3201b of the fin 3201 is greater than a width W4 of the upper portion 3201a of the fin 3201. In some embodiments, the width W3 is between about 4 nm and about 15 nm. In some embodiments, the width W4 is between about 2 nm and about 10 nm. In some embodiments, the lower portion 3201b of the fin 3201 has a height H2 between about 20 nm and about 40 nm. In some embodiments, the upper portion 3201a of the fin 3201 has a height H3 between about 20 nm and about 40 nm. In some embodiments where the fin 3201 comprises SiGe, the fin 3201 has a uniform Ge concentration. In such embodiments, the height H2 is greater than the height H3. In some embodiments, the Ge concentration in the fin 3201 is between about 15 atomic % and about 40 atomic %.In other embodiments where fin 3201 comprises SiGe, fin 3201 has a non-uniform Ge concentration. In such embodiments, height H2 is less than height H3. In some embodiments where fin 3201 has a non-uniform Ge concentration, the Ge concentration increases as fin 3201 extends away from adjacent STI regions 1401. In some embodiments, a Ge concentration of a portion of fin 3201 closest to adjacent STI regions 1401 is between about 10 atomic % and about 20 atomic %. In some embodiments, a Ge concentration of a portion of fin 3201 farthest from adjacent STI regions 1401 is between about 25 atomic % and about 35 atomic %.In other embodiments, fin 3201 has a non-uniform Ge concentration, with the lower portion 3201b of fin 3201 having a uniform Ge concentration and the upper portion 3201a of fin 3201 having a non-uniform Ge concentration. In some embodiments, the lower portion 3201b of fin 3201 has a uniform Ge concentration between approximately 15 atomic % and approximately 40 atomic %. In some embodiments, the Ge concentration increases as the upper portion 3201a of fin 3201 extends from the lower portion 3201b of fin 3201. In some embodiments, a Ge concentration of a portion of the upper portion 3201a of the fin 3201 closest to the lower portion 3201b of the fin 3201 is between about 10 atomic % and about 20 atomic %.In some embodiments, a Ge concentration of a portion of the upper portion 3201a of the fin 3201, which is farthest from the lower portion 3201b of the fin 3201, is between approximately 25 atomic % and approximately 35 atomic %. In some embodiments, the fins 3203 (see FIG. Fig. 33A) have similar shapes and sizes to the 3201 fins, and the description is not repeated here.

[0059] With reference to Fig. 35A, Fig. 35B and Fig. 35C, the provisions above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 33A to form the FinFET device 3200, and the description is not repeated here.

[0060] Fig. 36A, Fig. 37A, Fig. 37B and Fig. 37C are cross-sectional views of intermediate stages in the fabrication of a FinFET device 3600 according to some embodiments. In Fig. 36A, Fig. 37A, Fig. 37B and Fig. 37C are figures ending with an “A” designation, along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 3600 may be the same as described above with reference to Fig. 32A-35A, 35B and 35C for forming the FinFET device 3200, wherein like features are designated by like reference numerals and their description is not repeated here.

[0061] In some embodiments, the process of forming the FinFET device 3600 begins with forming a structure that Fig. 13A. With reference to Fig. 36, the above with reference to Fig. 32A and Fig. 33A described recess process on the PMOS region 205 of the structure of Fig. 13A to form the fins 3201, while the NMOS region 207 of the structure of Fig. 13A is protected with a mask (not shown). In addition, the above-mentioned Fig. 14A described recess process on the NMOS region 207 of the structure of Fig. 13A to expose portions of the semiconductor stripes 1007 in the NMOS region 207, while the PMOS region 205 of the structure of Fig. 13A with a mask (not shown). The exposed portions of the semiconductor stripes 1007 form fins 3601 in the NMOS region 207. With reference to Fig. 37A, Fig. 37B and Fig. 37C, the provisions above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 36A to form the FinFET device 3600, and the description is not repeated here.

[0062] Fig. 38A-43A, 43B, and 43C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 3800 according to some embodiments. In Fig. 38A-43A, 43B and 43C are figures ending with an “A” designation along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 3800 may be the same as described above with reference to Fig. 2A-22A, 24A-29A, 17B-22B, 24B-29B, and 18C-29C for forming the FinFET device 200, with like features being designated by like reference numerals, and their description will not be repeated here.

[0063] In some embodiments, the process of forming the FinFET device 3800 begins with forming a structure that Fig. 13A. Referring to Fig. 38A-41A are formed after the structure of Fig. 13A different process steps on the structure of Fig. 13A to form the fins 3901 in the PMOS region 205 and the fins 3903 in the NMOS region 207. Referring to Fig. 38A, a first recess process is performed on the insulation material 1103 and the liner 1101 to expose first portions 3801a of the semiconductor stripes 1005 in the PMOS region 205 and first portions 3803a of the semiconductor stripes 1007 in the NMOS region 207. In some embodiments, the first recess process may include a first etch process, such as a CERTAS® etch process, a SICONI etch process from Applied Materials, a dilute hydrofluoric acid (dHF) etch process, or the like. In some embodiments, the first etch process of the first recess process is selected such that the first etch process substantially does not etch the semiconductor stripes 1005 and 1007.In such embodiments, the widths of the first portions 3801a of the semiconductor strips 1005 are substantially equal to the widths of the semiconductor strips 1005, and the widths of the first portions 3803a of the semiconductor strips 1007 are substantially equal to the widths of the semiconductor strips 1007.

[0064] Referring to Fig. 39A, the first portions 3801a of the semiconductor strips 1005 are deformed to form upper portions 3901a of the fins 3901 in the PMOS region 205, and the first portions 3803a of the semiconductor strips 1007 are deformed to form upper portions 3903a of the fins 3903 in the NMOS region 207. In some embodiments, the first portions 3801a of the semiconductor strips 1005 and the first portions 3803a of the semiconductor strips 1007 are deformed using one or more etch processes. In some embodiments, a similar etch process is performed on the first portions 3801a of the semiconductor strips 1005 and the first portions 3803a of the semiconductor strips 1007. In such embodiments, an oxide layer such as a silicon oxide layer (not shown) may be formed over the first portions 3803a of the semiconductor stripes 1007 to compensate for the etch rate difference between the semiconductor stripes 1005 and 1007.In other embodiments, two different etching processes are performed on the first portions 3801a of the semiconductor stripes 1005 and the first portions 3803a of the semiconductor stripes 1007. In some embodiments, the one or more etching processes may comprise an anisotropic etching process, such as a reactive ion etch (RIE) or the like. In some embodiments, the etch chemistry and other parameters of the RIE process may be tuned to tune the etch rates of the RIE process. In some embodiments, an etch rate along a crystallographic direction <100> , R. 100 , greater than an etching rate along a crystallographic direction <110> , R 110 which is greater than an etching rate along a crystallographic direction <111> , R 111 , is. In some embodiments, R 100 :R 110 :R 111equal to 600:400:1. In some embodiments where the top surfaces of semiconductor layers 501 and 801 are crystallographic planes (100), the RIE process changes the slopes of the sidewalls of the first portions 3801a of semiconductor stripes 1005 and the slopes of the sidewalls of the first portions 3803a of semiconductor stripes 1007 such that the widths of the top portions 3901a of fins 3901 decrease as the top portions 3901a of fins 3901 extend away from a top surface of the insulating material 1103, and the widths of the top portions 3903a of fins 3903 decrease as the top portions 3903a of fins 3903 extend away from a top surface of the insulating material 1103.

[0065] Referring to Fig. 40A, after forming the upper portions 3901a of the fins 3901 in the PMOS region 205 and the upper portions 3903a of the fins 3903 in the NMOS region 207, a second recessing process is performed on the insulation material 1103 and the liner 1101 to expose second portions 3801b of the semiconductor stripes 1005 in the PMOS region 205 and second portions 3803b of the semiconductor stripes 1007 in the NMOS region 207. In some embodiments, the second etching process is similar to the first described above with reference to Fig. 38A, and the description will not be repeated here. In some embodiments, an etch process of the second recess process is selected such that the etch process substantially does not etch the semiconductor stripes 1005 and 1007. In such embodiments, the widths of the second portions 3801b of the semiconductor stripes 1005 are substantially equal to the widths of the semiconductor stripes 1005, and the widths of the second portions 3803a of the semiconductor stripes 1007 are substantially equal to the widths of the semiconductor stripes 1007. In some embodiments, the etch process of the second recess process is the same as the etch process of the first recess process. After performing the first recess process and the second recess process, remaining portions of the insulation material 1103 and the liner 1101 form STI regions 1401.

[0066] Referring to Fig. 41A, after performing the second etch process, the second portions 3801b of the semiconductor stripes 1005 are reshaped to form lower portions 3901b of the fins 3901 in the PMOS region 205, and the second portions 3803b of the semiconductor stripes 1007 are reshaped to form lower portions 3903b of the fins 3903 in the NMOS region 207. In some embodiments, the second portions 3801b of the semiconductor stripes 1005 and the second portions 3803a of the semiconductor stripes 1007 are reshaped using one or more etch processes. In some embodiments, the forming process for forming the lower portions 3901b of the fins 3901 in the PMOS region 205 and the lower portions 3903b of the fins 3903 in the NMOS region 207 may be similar to the forming process for forming the upper portions 3901a of the fins 3901 in the PMOS region 205 and the upper portions 3903a of the fins 3903 in the NMOS region 207 described above with reference to Fig. 39A, and the description is not repeated here. In some embodiments, the one or more etch processes of the forming process for forming the lower portions 3901b of the fins 3901 in the PMOS region 205 and the lower portions 3903b of the fins 3903 in the NMOS region 207 differ from the one or more etch processes of the forming process for forming the upper portions 3901a of the fins 3901 in the PMOS region 205 and the upper portions 3903a of the fins 3903 in the NMOS region 207. In such embodiments, sidewalls of the upper portions 3901a of the fins 3901 and sidewalls of the lower portions 3901b of the fins 3901 have different slopes, and sidewalls of the upper portions 3903a of the fins 3903 and sidewalls of the lower portions 3903b of the fins 3903 have different gradients.After the forming process, the widths of the lower portions 3901b of the fins 3901 decrease as the lower portions 3901b of the fins 3901 extend away from the upper surfaces of the adjacent STI regions 1401, and the widths of the lower portions 3903b of the fins 3903 decrease as the lower portions 3903b of the fins 3903 extend away from the upper surfaces of the adjacent STI regions. Forming the semiconductor strips 1005 and 1007 into fins 3901 and 3903, respectively, as described above with reference to FIG. Fig. 38A-41A, enables controlling strain in channels of the FinFET device 3800 at fin bottoms and reducing or eliminating the fin wobble / bend effect and enables the FinFET device 3800 to have a uniform threshold voltage (Vt) along fin heights.

[0067] Fig. 42A shows an enlarged view of a Fig. 41A. In some embodiments, the lower portion 3901b of the fin 3901 has a height H4 between approximately 20 nm and approximately 50 nm. In some embodiments, the upper portion 3901a of the fin 3901 has a height H5 between approximately 5 nm and approximately 30 nm. A portion of the lower portion 3901b of the fin 3901 closest to the adjacent STI regions 1401 has a width W5, and a portion of the lower portion 3901b of the fin 3901 farthest from the adjacent STI regions 1401 has a width W6. In some embodiments, the width W5 is greater than the width W6. In some embodiments, the width W5 is between about 4 nm and about 15 nm. In some embodiments, the width W6 is between about 3 nm and about 12 nm.The sidewalls of the lower portion 3901b of the fin 3901 form an angle θ2 with the uppermost surfaces of adjacent STI regions 1401. In some embodiments, the angle θ2 is between approximately 85 degrees and approximately 90 degrees. A portion of the upper portion 3901a of the fin 3901 closest to the adjacent STI regions 1401 has a width W6, and a portion of the upper portion 3901a of the fin 3901 farthest from the adjacent STI regions 1401 has a width W7. In some embodiments, the width W6 is greater than the width W7. In some embodiments, the width W7 is between approximately 2 nm and approximately 10 nm. The sidewalls of the upper portion 3901a of the fin 3901 form an angle θ3 with a plane parallel to the uppermost surfaces of adjacent STI regions 1401. In some embodiments, the angle θ3 is between approximately 70 degrees and approximately 85 degrees.In some embodiments, the angle θ2 is different from the angle θ3.

[0068] With further reference to Fig. 42A, in some embodiments where fin 3901 comprises SiGe, fin 3901 has a uniform Ge concentration. In such embodiments, height H4 is greater than height H5. In some embodiments, the Ge concentration in fin 3901 is between about 15 at. % and about 40 at. %. In other embodiments where fin 3901 comprises SiGe, fin 3901 has a non-uniform Ge concentration. In such embodiments, height H4 is less than height H5. In some embodiments where fin 3901 has a non-uniform Ge concentration, the Ge concentration increases as fin 3901 extends away from adjacent STI regions 1401. In some embodiments, a Ge concentration of a portion of the fin 3901 closest to adjacent STI regions 1401 is between about 10 atomic % and about 20 atomic %.In some embodiments, a Ge concentration of a portion of fin 3901 farthest from adjacent STI regions 1401 is between approximately 25 at.% and approximately 35 at.%. In other embodiments, fin 3901 has a non-uniform Ge concentration, with lower portion 3901b of fin 3901 having a uniform Ge concentration and upper portion 3901a of fin 3901 having a non-uniform Ge concentration. In some embodiments, lower portion 3901b of fin 3901 has a uniform Ge concentration between approximately 15 at.% and approximately 40 at.%. In some embodiments, the Ge concentration increases as upper portion 3901a of fin 3901 extends from lower portion 3901b of fin 3901.In some embodiments, a Ge concentration of a portion of the upper portion 3901a of the fin 3901 closest to the lower portion 3901b of the fin 3901 is between about 10 atomic % and about 20 atomic %. In some embodiments, a Ge concentration of a portion of the upper portion 3901a of the fin 3901 farthest from the lower portion 3901b of the fin 3901 is between about 25 atomic % and about 35 atomic %. In some embodiments, the fins 3903 (see FIG. Fig. 41A) have similar shapes and sizes to the Finns 3901, and the description is not repeated here.

[0069] With reference to Fig. 43A, Fig. 43B and Fig. 43C, the provisions above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 41A to form the FinFET device 3800, and the description is not repeated here.

[0070] Fig. 44A, Fig. 45A, Fig. 45B and Fig. 45C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 4400 according to some embodiments. In Fig. 44A, Fig. 45A, Fig. 45B and Fig. 45C are figures ending with an “A” designation, along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 4400 may be similar to those described above with reference to Fig. 38A-43A, 43B and 43C for forming the FinFET device 3800, wherein like features are designated by like reference numerals and their description is not repeated here.

[0071] In some embodiments, the process of forming the FinFET device 4400 begins with forming a structure that Fig. 13A. With reference to Fig. 44A, the provisions above with reference to Fig. 38A-41A on the PMOS region 205 of the structure of Fig. 13A to form the fins 3901, while the NMOS region 207 of the structure of Fig. 13A is protected with a mask (not shown). In addition, the above-mentioned Fig. 14A described recess process on the NMOS region 207 of the structure of Fig. 13A to expose portions of the semiconductor stripes 1007 in the NMOS region 207, while the PMOS region 205 of the structure of Fig. 13A with a mask (not shown). The exposed portions of the semiconductor stripes 1007 form fins 4401 in the NMOS region 207. With reference to Fig. 45A, Fig. 45B and Fig. 45C, the provisions above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 44A to form the FinFET device 4400, and the description is not repeated here.

[0072] Fig. 46A-48A, 48B, and 48C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 4600 according to some embodiments. In Fig. 46A-48A, 48B and 48C are figures ending with an “A” designation along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1 shown cross section CC.

[0073] In some embodiments, the process of forming the FinFET device 4400 begins with forming a structure that Fig. 33A. Referring to Fig. 46A shows various process steps on the structure of Fig. 33A to form fins 4601 in PMOS region 205 and fins 4603 in NMOS region 207. In some embodiments, the lower portions 3201b of fins 3201 are deformed to form lower portions 4601b of fins 4601 in PMOS region 205, and the second portions 3203b of semiconductor stripes 3203 are deformed to form lower portions 4603b of fins 4603 in NMOS region 207. In some embodiments, the forming process for forming the lower portions 4601b of the fins 4601 in the PMOS region 205 and the lower portions 4603b of the fins 4603 in the NMOS region 207 may be similar to the forming process for forming the fins 1501 in the PMOS region 205 and the fins 1503 in the NMOS region 207 described above with reference to Fig. 15A, and the description will not be repeated here. After performing the forming process, the widths of the lower portions 4601b of the fins 4601 decrease as the lower portions 4601b of the fins 4601 extend away from the adjacent STI regions 1401, and the widths of the lower portions 4603b of the fins 4603 decrease as the lower portions 4603b of the fins 4603 extend away from the adjacent STI regions 1401. Forming the semiconductor strips 1005 and 1007 into fins 4601 and 4603, respectively, as described above with reference to Fig. 46A, enables controlling strain in channels of the FinFET device 4600 at fin bottoms and reducing or eliminating the fin wobble / bend effect, and enables the FinFET device 4600 to have a uniform threshold voltage (Vt) along fin heights.

[0074] Fig. 47A shows an enlarged view of a Fig. 46A. In some embodiments, the lower portion 4601b of the fin 4601 has a height H6 between approximately 10 nm and approximately 30 nm. In some embodiments, the upper portion 3201a of the fin 4601 has a height H7 between approximately 20 nm and approximately 50 nm. In some embodiments, the height H6 is less than a height H7. A portion of the lower portion 4601b of the fin 4601 closest to the adjacent STI regions 1401 has a width W8, and a portion of the lower portion 4601b of the fin 4601 farthest from the adjacent STI regions 1401 has a width W9. In some embodiments, the width W8 is greater than the width W9. In some embodiments, the width W8 is between about 4 nm and about 15 nm. In some embodiments, the width W9 is between about 3 nm and about 10 nm.The sidewalls of the lower portion 4601b of the fin 4601 form an angle θ4 with the uppermost surfaces of adjacent STI regions 1401. In some embodiments, the angle θ4 is between approximately 80 degrees and approximately 90 degrees. In some embodiments, the upper portion 3201a of the fin 4601 has a width of W9.

[0075] With further reference to Fig. 47A, in some embodiments where fin 4601 comprises SiGe, fin 4601 has a uniform Ge concentration. In some embodiments, the Ge concentration in fin 4601 is between about 15 at. % and about 40 at. %. In other embodiments where fin 4601 comprises SiGe, fin 4601 has a non-uniform Ge concentration. In some embodiments where fin 4601 has a non-uniform Ge concentration, the Ge concentration increases as fin 4601 extends away from adjacent STI regions 1401. In some embodiments, a Ge concentration of a portion of fin 4601 closest to adjacent STI regions 1401 is between about 10 at. % and about 20 at. %.In some embodiments, a Ge concentration of a portion of fin 4601 farthest from adjacent STI regions 1401 is between approximately 25 atomic % and approximately 35 atomic %. In other embodiments, fin 4601 has a non-uniform Ge concentration, with lower portion 4601b of fin 4601 having a uniform Ge concentration and upper portion 3201a of fin 4601 having a non-uniform Ge concentration. In some embodiments, lower portion 4601b of fin 4601 has a uniform Ge concentration between approximately 15 atomic % and approximately 40 atomic %. In some embodiments, the Ge concentration increases as upper portion 3201a of fin 4601 extends from lower portion 4601b of fin 4601.In some embodiments, a Ge concentration of a portion of the upper portion 3201a of the fin 4601 closest to the lower portion 4601b of the fin 4601 is between about 10 atomic % and about 20 atomic %. In some embodiments, a Ge concentration of a portion of the upper portion 3201a of the fin 4601 farthest from the lower portion 4601b of the fin 4601 is between about 25 atomic % and about 35 atomic %. In some embodiments, the fins 4603 (see FIG. Fig. 46A) have similar shapes and sizes to the fins 4601, and the description is not repeated here.

[0076] With reference to Fig. 48A, Fig. 48B and Fig. 48C, the provisions above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 46A to form the FinFET device 4600, and the description is not repeated here.

[0077] Fig. 49A, Fig. 50A, Fig. 50B and Fig. 50C are cross-sectional views of an intermediate stage in the fabrication of a FinFET device 4900 according to some embodiments. In Fig. 49A, Fig. 50A, Fig. 50B and Fig. 50C are figures ending with an “A” designation, along the Fig. 1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are along the Fig. 1; and figures ending with a “C” designation are shown along the reference cross-section BB shown in Fig. 1. In some embodiments, the process steps for forming the FinFET device 4900 may be similar to those described above with reference to Fig. 46A-48A, 48B and 48C for forming the FinFET device 4600, wherein like features are designated by like reference numerals and their description is not repeated here.

[0078] In some embodiments, the process of forming the FinFET device 4900 begins with forming a structure that Fig. 13A. With reference to Fig. 49A, the provisions above with reference to Fig. 32A, Fig. 33A and Fig. 46A described process steps on the PMOS region 205 of the structure of Fig. 13A to form the fins 4601 in the PMOS region 205, while the NMOS region 207 of the structure of Fig. 13A is protected with a mask (not shown). In addition, the above-mentioned Fig. 14A described recess process on the NMOS region 207 of the structure of Fig. 13A to expose portions of the semiconductor stripes 1007 in the NMOS region 207, while the PMOS region 205 of the structure of Fig. 13A with a mask (not shown). The exposed portions of the semiconductor stripes 1007 form fins 4901 in the NMOS region 207. With reference to Fig. 50A, Fig. 50B and Fig. 50C, the above with reference to Fig. 17A-22A, 24A-29A, 17B-22B, 24B-29B and 18C-29C described process steps on the structure of Fig. 49A to form the FinFET device 4900, and the description is not repeated here.

[0079] Fig. 51 is a flowchart illustrating a method 5100 for forming a fin structure according to some embodiments. The method 5100 begins with step 5101, in which semiconductor stripes (such as those shown in Fig. 10A) over a substrate (such as the one shown in Fig. 10A) as described above with reference to Fig. 2A-10A. In step 5103, insulation areas (such as the lining 1101 and the insulation material 1103 shown in Fig. 10A) between adjacent semiconductor strips as described above with reference to Fig. 11A-13A. In step 5105, the isolation regions are recessed to expose upper portions of the semiconductor strips, as described above with reference to Fig. 14A. In step 5107, the upper portions of the semiconductor strips are formed to form fins (such as those shown in Fig. 15A) extending over the isolation regions as described above with reference to Fig. 15A.

[0080] Fig. 52 is a flowchart illustrating a method 5200 for forming a fin structure according to some embodiments. The method 5200 begins with step 5201, in which semiconductor stripes (such as those shown in Fig. 10A) over a substrate (such as the one shown in Fig. 10A) as described above with reference to Fig. 2A-10A. In step 5203, insulation regions (such as the lining 1101 and the insulation material 1103 shown in Fig. 10A) between adjacent semiconductor strips as described above with reference to Fig. 11A-13A. In step 5205, a first recess process is performed on the isolation regions to form first sections (such as those shown in Fig. 32A to expose and reshape the upper portions 3201a) of the semiconductor strips as described above with reference to Fig. 32A. In step 5207, a second recess process is performed on the isolation regions to form second sections (such as those shown in Fig. 33A) below the deformed first portions of the semiconductor strips, wherein the deformed first portions of the semiconductor strips and the second portions of the semiconductor strips form fins (such as those shown in Fig. 33A) extending over the isolation regions as described above with reference to Fig. 33A.

[0081] Fig. 53 is a flowchart illustrating a method 5300 for forming a fin structure according to some embodiments. The method 5300 begins with step 5301, in which semiconductor stripes (such as those shown in Fig. 10A) over a substrate (such as the one shown in Fig. 10A) as described above with reference to Fig. 2A-10A. In step 5303, insulation regions (such as the lining 1101 and the insulation material 1103 shown in Fig. 10A) between adjacent semiconductor strips as described above with reference to Fig. 11A-13A. In step 5305, a first recess process is performed on the isolation regions to form first sections (such as those shown in Fig. 38A, as described above with reference to Fig. 38A. In step 5307, the first portions of the semiconductor strips are deformed to form deformed first portions (such as those shown in Fig. 39A, as described above with reference to Fig. 39A. In step 5309, a second recess process is performed on the isolation regions to form second sections (such as those shown in Fig. 40A illustrated second sections 3801b) of the semiconductor strips under the formed first sections of the semiconductor strips, as described above with reference to Fig. 40A. In step 5311, the second portions of the semiconductor strips are deformed to form deformed second portions (such as those shown in Fig. 41A, wherein the formed first portions of the semiconductor strips and the formed second portions of the semiconductor strips form fins (such as those shown in Fig. 41A) extending over the isolation areas as described above with reference to Fig. 41A.

[0082] Fig. 54 is a flowchart illustrating a method 5400 for forming a fin structure according to some embodiments. The method 5400 begins with step 5401 in which semiconductor stripes (such as those shown in Fig. 10A) over a substrate (such as the one shown in Fig. 10A) as described above with reference to Fig. 2A-10A. In step 5403, insulation regions (such as the liner 1101 and the insulation material 1103 shown in Fig. 10A) between adjacent semiconductor strips as described above with reference to Fig. 11A-13A. In step 5405, a first recess process is performed on the isolation regions to form first portions (such as those shown in Fig. 32A to expose and reshape the upper portions 3201a) of the semiconductor strips as described above with reference to Fig. 32A. In step 5407, a second recess process is performed on the isolation regions to form second sections (such as those shown in Fig. 33A illustrated lower portions 3201b) of the semiconductor strips under the formed first portions of the semiconductor strips, as described above with reference to Fig. 33A. In step 5409, the second portions of the semiconductor strips are deformed to form deformed second portions (such as those shown in Fig. 46A, wherein the formed first portions of the semiconductor strips and the formed second portions of the semiconductor strips form fins (such as those shown in Fig. 46A) extending over the isolation regions as described above with reference to Fig. 46A.

[0083] According to one embodiment, a method comprises: forming semiconductor strips over a substrate; forming isolation regions over the substrate and between adjacent semiconductor strips; performing a first recessing process on the isolation regions to expose first portions of the semiconductor strips; reshaping the first portions of the semiconductor strips to form reshaped first portions of the semiconductor strips; performing a second recessing process on the isolation regions to expose second portions of the semiconductor strips under the reshaped first portions of the semiconductor strips; and reshaping the second portions of the semiconductor strips to form reshaped second portions of the semiconductor strips,wherein the deformed first portions of the semiconductor strips and the deformed second portions of the semiconductor strips form fins, and wherein the fins extend away from the uppermost surfaces of the isolation regions. In one embodiment, the first recessing process and the second recessing process comprise the same etching process. In one embodiment, the deforming of the first portions of the semiconductor strips comprises a first etching process. In one embodiment, the deforming of the second portions of the semiconductor strips comprises a second etching process.which is different from the first etching process. In one embodiment, forming the first portions of the semiconductor strips comprises changing slopes of sidewalls of the first portions of the semiconductor strips. In one embodiment, forming the second portions of the semiconductor strips comprises changing slopes of sidewalls of the second portions of the semiconductor strips. In one embodiment, the sidewalls of the formed first portions of the semiconductor strips have a first slope, and the sidewalls of the formed second portions of the semiconductor strips have a second slope that is different from the first slope.

[0084] According to another embodiment, a method comprises: forming semiconductor strips over a substrate; forming isolation regions between adjacent semiconductor strips; performing a first recessing process on the isolation regions to expose first portions of the semiconductor strips, wherein performing the first recessing process further comprises: deforming the first portions of the semiconductor strips to form deformed first portions of the semiconductor strips; performing a second recessing process on the isolation regions to expose second portions of the semiconductor strips under the deformed first portions of the semiconductor strips; and deforming the second portions of the semiconductor strips to form deformed second portions of the semiconductor strips, wherein the deformed first portions of the semiconductor strips and the deformed second portions of the semiconductor strips form fins, and wherein theuppermost surfaces of the fins are uppermost surfaces of the isolation regions. In one embodiment, the first recess process and the second recess process comprise different etching processes. In one embodiment, forming the first portions of the semiconductor strips comprises narrowing the first portions of the semiconductor strips without changing slopes of sidewalls of the first portions of the semiconductor strips. In one embodiment, forming the second portions of the semiconductor strips comprises changing slopes of sidewalls of the second portions of the semiconductor strips. In one embodiment, forming the second portions of the semiconductor strips comprises an anisotropic etching process. In one embodiment, the anisotropic etching process is a reactive ion etching process. In one embodiment, the widths of the formed second portions of the semiconductor strips decrease as the formed second portions of theSemiconductor stripes extend from the top surfaces of the isolation regions.

[0085] According to yet another embodiment, a device comprises: a substrate; an isolation region above the substrate; and a fin above the substrate and adjacent to the isolation region, a top surface of the fin located above a top surface of the isolation region, the fin comprising: a first portion, a first sidewall of the first portion having a first slope; and a second portion between the first portion and the substrate, a second sidewall of the second portion having a second slope, wherein the first sidewall and the second sidewall are on the same side of the fin, the first slope being different from the second slope. In one embodiment, the first portion of the fin has a uniform width. In one embodiment, a width of the first portion of the fin decreases as the first portion of the fin extends away from the second portion of the fin.In one embodiment, a width of the second portion of the fin decreases as the second portion of the fin extends away from the isolation region. In one embodiment, a first height of the first portion of the fin is greater than a second height of the second portion of the fin. In one embodiment, a first height of the first portion of the fin is less than a second height of the second portion of the fin.

[0086] The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes and enable the creation of structures that, for example, have pitches smaller than what is otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers can then be used to pattern the fins.

Claims

[1] Procedure comprising: Forming semiconductor stripes (1005, 1007, 1105) over a substrate (101, 201); Forming isolation regions (103, 1401) above the substrate (101, 201) and between adjacent semiconductor strips (1005, 1007, 1105); performing a first recessing process on the isolation regions (103, 1401) to expose first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); forming the first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) to form formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); Performing a second recessing process on the isolation regions (103, 1401) to expose second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) below the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); and Forming the second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) to form formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105), wherein the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) and the formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips form fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901), and wherein the fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) extend from uppermost surfaces of the insulation regions (103, 1401), wherein the side walls of the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) have a first slope, and wherein the side walls of the formed second sections (3201b, 3203b,3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) have a second pitch which differs from the first pitch., [2] The method of claim 1, wherein performing the first recess process comprises performing a first etching process using first etching agents, and wherein performing the second recess process comprises performing a second etching process using the first etching agents. [3] The method of claim 1 or 2, wherein the forming of the first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) comprises a first etching process. [4] The method of claim 3, wherein the forming of the second portions (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) comprises a second etching process different from the first etching process. [5] Method according to one of the preceding claims, wherein the forming of the first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) comprises changing slopes of the side walls of the first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105). [6] Method according to one of the preceding claims, wherein the forming of the second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) comprises changing slopes of the side walls of the second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105). [7] Method according to one of the preceding claims, wherein the fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) comprise SiGe and have a non-uniform Ge concentration, and wherein the Ge concentration in the fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) starting from the insulation regions (103, 1401) in the extension direction (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) the fin increases. [8] Procedure comprising: Forming semiconductor stripes (1005, 1007, 1105) over a substrate (101, 201); Forming isolation regions (103, 1401) between adjacent semiconductor strips (1005, 1007, 1105); Performing a first recessing process on the isolation regions (103, 1401) to expose first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105), wherein performing the first recessing process further comprises reshaping the first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) to form reshaped first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105); Performing a second recessing process on the isolation regions (103, 1401) to expose second portions (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) below the formed first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105);and forming the second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) to form formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105), wherein the formed first sections (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) and the formed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips form fins, and wherein uppermost surfaces of the fins (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) lie above uppermost surfaces of the insulation regions (103, 1401); [9] The method of claim 8, wherein the first recessing process and the second recessing process comprise different etching processes. [10] The method of claim 8 or 9, wherein the forming of the first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105) comprises narrowing the first portions (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the semiconductor strips (1005, 1007, 1105). [11] The method according to any one of claims 8 to 10, wherein the forming of the second portions (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) comprises changing slopes of the sidewalls of the second portions (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105). [12] The method according to any one of claims 8 to 11, wherein the forming of the second portions (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) comprises an anisotropic etching process. [13] The method of claim 12, wherein the anisotropic etching process is a reactive ion etching process. [14] Method according to one of claims 8 to 13, wherein the widths of the deformed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) decrease the further the deformed second sections (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the semiconductor strips (1005, 1007, 1105) extend away from the uppermost surfaces of the isolation regions (103, 1401). [15] Device comprising: a substrate (101, 201); an isolation region (103, 1401) above the substrate (101, 201); and a fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) above the substrate (101, 201) and adjacent to the isolation region (103, 1401), wherein a top surface of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) lies above a top surface of the insulation region (103, 1401), the fin comprising: a first section (3201a, 3203a, 3801a, 3803a, 3901a, 3903a), wherein a first side wall of the first section (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) has a first slope; a second section (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) between the first section (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) and the substrate (101, 201), wherein a second sidewall of the second section (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) has a second slope, wherein the first sidewall and the second sidewall are on a same side of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) and wherein the first gradient is different from the second gradient; wherein the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) comprises SiGe and has a non-uniform Ge concentration, and wherein the Ge concentration in the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) starting from the insulation region (103, 1401) in the extension direction (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) the fin increases. [16] The device of claim 15, wherein the first portion of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) has a uniform width. [17] Device according to claim 15 or 16, wherein a width of the first portion (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) decreases, the further the first portion of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) moves away from the second portion (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901). [18] Device according to one of claims 15 to 17, wherein a width of the second portion (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) decreases, the further the second portion of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) moves away from the isolation region (103, 1401). [19] Device according to one of claims 15 to 18, wherein a first height of the first portion (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) is greater than a second height of the second portion (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901). [20] Device according to one of claims 15 to 19, wherein a first height of the first portion (3201a, 3203a, 3801a, 3803a, 3901a, 3903a) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901) is smaller than a second height of the second portion (3201b, 3203b, 3801b, 3803b, 3901b, 3903b) of the fin (105, 1501, 1503, 3001, 3201, 3203, 3601, 3901, 3903, 4401, 4601, 4603, 4901).

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