BUILDING ELEMENT WITH IMPROVED HEAT DISPENSING AND METHOD FOR MANUFACTURING A BUILDING ELEMENT

Abstract

Component (10) comprising a semiconductor body (2), a converter layer (5), a filler layer (4) and an intermediate layer (3) arranged in a vertical direction between the semiconductor body and the converter layer, wherein - the semiconductor body has a surface (2V) facing the converter layer which is structured and has vertical depressions (2T), - the vertical depressions are filled with a material of the filler layer that has a higher thermal conductivity than silicone, - the intermediate layer (3) or the semiconductor body (2) has a higher mechanical hardness than the filler layer, and extends beyond the filler layer (4) in certain areas along the vertical direction, and - the structured surface (2V) of the semiconductor body (2) has local elevations (2H) and local depressions (2T), wherein the structured surface (2V) is formed exclusively by the surface of an n-conducting or p-conducting semiconductor layer (22).

Description

[0001] A component with improved heat dissipation and thus improved efficiency is specified. Furthermore, a method for manufacturing such a component is specified.

[0002] The efficiency and lifetime of a light-emitting component depend, among other things, on whether the component is sufficiently cooled during operation. A converter layer is often attached to a structured surface of a semiconductor body of the component using a silicone-based bonding layer. However, roughening the semiconductor body to achieve high coupling efficiency can create thermal barriers that impede cooling of a converter layer of the component. Such thermal barriers are located particularly in the recesses of the semiconductor body, which are filled with the bonding layer material.

[0003] To avoid thermal barriers, roughening the semiconductor body can be omitted. However, this leads to a deterioration in optical outcoupling, since total internal reflection occurs more frequently on a flat surface when light is to be transferred to a material with a lower refractive index. Alternatively, it is conceivable to add thermally conductive particles to the material of the bonding layer. However, there is a high risk that the thermally conductive particles could lead to unwanted optical scattering, causing the outcoupled light to be reflected back to the semiconductor body.

[0004] Document US 2018 / 0 114 800 A1 describes an LED arrangement and a method for producing an LED array, in which a separation trench structure is first formed to separate a semiconductor structure into a plurality of semiconductor bodies. The separation trench structure is then filled with an electrically insulating material such as silicon oxide to form an insulation layer in a subsequent process step. Documents US 2016 / 0 197 244 A1 and US 2010 / 0 072 489 A1 describe various embodiments of a semiconductor component.

[0005] One object is to provide a component, in particular an optoelectronic component, with increased efficiency. Another object is to provide a reliable and cost-effective method for producing a component, in particular a component described here.

[0006] These objects are achieved by the component according to the independent claim and by the method for producing a component, in particular a component described here. Further embodiments of the component or of the method for producing the component are the subject of the further claims.

[0007] According to at least one embodiment of the component, it comprises a carrier and a semiconductor body arranged on the carrier. The semiconductor body comprises a first semiconductor layer, a second semiconductor layer, and an active zone, wherein the active zone is arranged vertically between the first semiconductor layer and the second semiconductor layer. In particular, the active zone is designed to generate electromagnetic radiation, for example, in the infrared, visible, or ultraviolet spectral range. The first semiconductor layer and the second semiconductor layer can be n-conducting or p-conducting, or vice versa. The first semiconductor layer and the second semiconductor layer can each be formed as a single layer or as a layer sequence and / or have a plurality of sublayers arranged one above the other.

[0008] The semiconductor body, in particular, has a diode structure. The active zone is, for example, a pn junction zone. The component can be a semiconductor chip. The carrier is, for example, the chip carrier, in particular the sole chip carrier of the component. The carrier can be a substrate, in particular a growth substrate. It is also possible for the carrier to be different from a growth substrate and / or different from a circuit board.

[0009] The semiconductor body can be formed from a III / V compound semiconductor material. A III / V compound semiconductor material comprises an element from the third main group, such as B, Al, Ga, In, and an element from the fifth main group, such as N, P, As. In particular, the term "III / V compound semiconductor material" encompasses the group of binary, ternary, or quaternary compounds that contain at least one element from the third main group and at least one element from the fifth main group, for example, nitride and phosphide compound semiconductors. Such a binary, ternary, or quaternary compound can additionally comprise, for example, one or more dopants and additional constituents. The semiconductor body can also be formed from a II / VI compound semiconductor material.

[0010] According to at least one embodiment of the component, the semiconductor body has a structured surface facing away from the carrier. The structured surface has vertical depressions and vertical elevations, which, for example, have a vertical depth or an average vertical height between 0.2 µm and 5 µm inclusive, for example between 1 µm and 5 µm inclusive or between 1 µm and 3 µm inclusive. The structured surface can be provided with a passivation layer such that the passivation layer extends conformally to the structured surface. The passivation layer can have a vertical layer thickness between 30 nm and 1 µm inclusive, for example between 40 nm and 700 nm inclusive or between 100 nm and 700 nm inclusive. The passivation layer can be formed from SiO2 and / or Al2O3.

[0011] A lateral direction is understood to be a direction that runs, in particular, parallel to a main extension surface of the active zone or the semiconductor body. A vertical direction is understood to be a direction that is, in particular, perpendicular to the main extension surface of the active zone or the semiconductor body. The vertical direction and the lateral direction are approximately orthogonal to one another.

[0012] According to at least one embodiment of the component, it comprises a converter layer arranged on the structured surface of the semiconductor body. In particular, the converter layer is a prefabricated converter plate. The converter layer can comprise phosphors that can convert the wavelength of the electromagnetic radiation generated by the semiconductor body during operation of the component. This conversion generates heat, which should preferably be dissipated via the semiconductor body and the component's carrier.

[0013] According to at least one embodiment of the component, the fill layer is configured to adapt the refractive index between the semiconductor body and the converter layer or between the semiconductor body and the intermediate layer. Furthermore, the structured surface of the semiconductor body can suppress effects related to total internal reflection. For example, the refractive index of the fill layer differs by at most 30%, 20%, 10%, or at most 5% from the refractive index of the conversion layer or the intermediate layer. In particular, the fill layer has a lower refractive index than the conversion layer and / or the intermediate layer.

[0014] According to at least one embodiment of the component, it has an intermediate layer arranged vertically between the semiconductor body and the converter layer. The intermediate layer can be formed by a connecting layer and / or by the passivation layer. The intermediate layer can also be formed by a protective layer or a planarization layer.

[0015] The intermediate layer can be single-layered or multi-layered. If the intermediate layer is single-layered, it can be made of a single material. If the intermediate layer is multi-layered, it can comprise a plurality of sublayers arranged one above the other, which are made, in particular, of different materials.

[0016] In at least one embodiment of the component, it comprises a semiconductor body, a converter layer, a fill layer, and an intermediate layer arranged vertically between the semiconductor body and the converter layer. The semiconductor body has a surface facing the converter layer, which is structured and has vertical depressions. The vertical depressions are filled with a material of the fill layer that has a higher thermal conductivity than silicone and / or epoxy resin. As a result, during operation of the component, thermal paths can be generated between the converter layer and the semiconductor body through the depressions, wherein the thermal paths dissipate heat significantly better than silicone and / or epoxy resin. In particular, the intermediate layer and / or the semiconductor body have / have a higher mechanical hardness than the fill layer.

[0017] The material of the fill layer makes it easier to form thermal paths through the recesses during component operation, allowing heat to be transferred from the converter layer into the semiconductor body not only via the raised portions of the semiconductor body but also via the recesses of the semiconductor body. In the transition region between the semiconductor body and the converter layer, the heat is thus distributed relatively evenly, effectively transferring heat into the semiconductor body over a larger area. The use of the fill layer thus enables the lowest possible thermal resistance between the converter layer and the component. This enables a higher operating current and thus greater light output.

[0018] The fill layer is preferably formed from a dielectric that has a higher thermal conductivity than polymers such as silicone or epoxy. In particular, the fill layer is designed to be transparent and, in particular, permeable to the radiation generated by the semiconductor body. By using a highly thermally conductive material that fills the recesses of the structured surface of the semiconductor body, heat dissipation can be significantly improved without negatively impacting the coupling-out efficiency of the component. In particular, the fill layer is free of additional thermally conductive particles embedded in the fill layer material.

[0019] Particularly when polishing a surface made of materials of varying hardness, the softer material is generally removed more severely, so that in the worst case, the surface is not flat but sags slightly in some areas. This phenomenon is known as "dishing." After the polishing step, it is often desirable to planarize the polished surface, which allows the converter layer to be easily attached to the polished surface while saving material. In this case, the intermediate layer or a connecting layer can be designed to be particularly thin, which minimizes the thermal resistance in the transition region between the semiconductor body and the converter layer.

[0020] If the semiconductor body or the intermediate layer has a higher mechanical hardness than the filling layer, the semiconductor body or the intermediate layer can serve in particular as a polishing stop layer during the processing of the filling layer, thereby simplifying a method for producing such a component.

[0021] According to at least one embodiment of the component, the semiconductor body has a higher mechanical hardness than the fill layer. Along the vertical direction, the semiconductor body protrudes beyond the fill layer in some regions. In this case, the structured surface of the semiconductor body can be free of a passivation layer.

[0022] According to at least one embodiment of the component, the intermediate layer has a higher mechanical hardness than the fill layer. The intermediate layer extends into the recesses in some regions, conforming to the structured surface of the semiconductor body. The intermediate layer protrudes beyond the fill layer in some regions along the vertical direction.

[0023] According to at least one embodiment of the component, the semiconductor body is configured to generate electromagnetic radiation of a first peak wavelength during operation of the component. The converter layer is configured to convert the electromagnetic radiation of a first peak wavelength into electromagnetic radiation of a second peak wavelength, wherein the second peak wavelength is greater than the first peak wavelength. For example, the semiconductor body is configured to generate electromagnetic radiation in the ultraviolet or blue spectral range during operation of the component, wherein this radiation is partially or completely converted in the converter layer into radiation of a longer wavelength, for example in the yellow, green, or red spectral range.

[0024] According to at least one embodiment of the component, the material of the fill layer has a thermal conductivity of at least 0.5 W / (m·K). For example, the thermal conductivity of the fill layer is at least 0.75 W / (mK), 1 W / (m·K), 1 W / (mK) or at least 5 W / (mK). The thermal conductivity of the material of the fill layer can be between 0.5 W / (mK) and 150 W / (mK), for example between 1 and 100 W / (m·K), between 1 W / (mK) and 10 W / (mK) or between 1 W / (mK) and 5 W / (m·K). The fill layer is, for example, formed homogeneously from one material and can be free of additional filler particles or heat-conducting particles.

[0025] According to at least one embodiment of the component, the material of the fill layer has a lower thermal conductivity than the semiconductor body. Semiconductor materials based on GaN, for example, can have a particularly high thermal conductivity, approximately around 100 W / (m K). The semiconductor body of the component is thus particularly suitable for heat conduction for cooling the converter layer.

[0026] According to at least one embodiment of the component, the vertical recesses have an average vertical depth of between 0.2 µm and 5 µm inclusive. The filling layer can be formed such that it fills at least 50%, 60%, or at least 70% of the vertical depth of the recesses, for example, between 50% and 90% inclusive or between 50% and 80% inclusive.

[0027] According to at least one embodiment of the component, the intermediate layer comprises a connecting layer or is formed from the connecting layer. The connecting layer is arranged in the vertical direction between the fill layer and the converter layer. In particular, the connecting layer is different from a connecting layer based on silicone or an epoxy material. The connecting layer is in particular radiation-permeable, for example transparent to the electromagnetic radiation generated in the semiconductor body. The connecting layer can be formed from glass or from an adhesive. It is also possible for the connection to be made of a thin silicone-based layer with a layer thickness of less than 1 µm, 0.5 µm, 0.2 µm, 0.1 µm, or 0.05 µm, approximately between 10 nm and 1 µm inclusive.

[0028] According to at least one embodiment of the component, the intermediate layer comprises or is formed from a passivation layer. The passivation layer extends in regions conforming to the structured surface of the semiconductor body and is arranged in regions between the fill layer and the semiconductor body in the vertical direction. In particular, the passivation layer has a higher mechanical hardness than the fill layer. The passivation layer can be formed from Al2O3.

[0029] According to at least one embodiment of the component, it comprises a planarization layer that, in plan view, completely covers the fill layer and has a flat or planar surface facing the converter layer. The planarization layer and the passivation layer can be formed from the same material, such as Al2O3, or from different materials.

[0030] A flat surface is understood in particular to mean a surface that is flat and, within the manufacturing tolerances, has a roughness of at most 1 µm, 0.5 µm, 0.3 µm or 0.1 µm, for example, between 0.05 µm and 1 µm inclusive. A planar surface is understood in particular to mean a surface that is particularly flat and, within the manufacturing tolerances, has a roughness of at most 100 nm, 50 nm, 30 nm, 20 nm or 10 nm, for example, between 1 nm and 100 nm inclusive.

[0031] In the presence of such a planarization layer, the converter layer can be attached to the semiconductor body using a particularly thin bonding layer. It is also possible for the converter layer to be attached to the semiconductor body using a direct bonding process. In a direct bonding process, planarized surfaces, such as the surfaces of the converter layer and the planarization layer or a protective layer arranged on the planarization layer, are brought into physical contact. The basis of the mechanical connection is predominantly or exclusively hydrogen bonds and / or van der Waals interactions in the immediate vicinity of a common interface between the planarized surfaces.To create covalent bonds between atoms or molecules on the surfaces in physical contact, a subsequent thermal treatment can be applied to achieve increased bond strength. Direct bonding thus occurs without the use of an additional bonding material, such as an adhesive layer or a solder layer.

[0032] According to at least one embodiment of the component, it contains a protective layer arranged between the converter layer and the semiconductor body. In particular, the protective layer has a constant vertical layer thickness along lateral directions. The protective layer, for example, directly or exclusively adjoins the converter layer, except for a connecting layer. In particular, the protective layer has a planar surface facing the converter layer.

[0033] In one embodiment, an electronic device contains the component described here. The electronic device can be a smartphone, touchpad, laser printer, recognition camera, display, or a system of LEDs, sensors, laser diodes, and / or detectors. The component can also be used in a light source. For example, the component is intended for general lighting, such as indoor or outdoor lighting. The component can be designed as a light source for a headlight, such as a vehicle headlight. For example, the component is a high-power LED.

[0034] In at least one embodiment of a method for producing a component comprising a semiconductor body, a converter layer, a fill layer, and an intermediate layer arranged vertically between the semiconductor body and the converter layer, the semiconductor body is provided with a structured surface. The structured surface has vertical depressions. The depressions are filled with a fill layer material that has a higher thermal conductivity than silicone. In addition, the fill layer material is selected such that the intermediate layer or the semiconductor body has a higher mechanical hardness than the fill layer. In a subsequent method step, the fill layer is polished, for example by means of a chemical-mechanical planarization process, wherein the intermediate layer or the semiconductor body serves as a polishing stop layer due to its higher mechanical hardness.After polishing, the intermediate layer or the semiconductor body protrudes beyond the fill layer in certain regions along the vertical direction. The converter layer is applied to the polished fill layer. The material of the fill layer is preferably selected with respect to thermal conductivity such that, during operation of the component, thermal paths between the converter layer and the semiconductor body can be generated through the recesses due to the material of the fill layer.

[0035] After polishing, the semiconductor body protrudes beyond the fill layer in certain regions along the vertical direction. The intermediate layer is applied to the partially free-standing semiconductor body after polishing the fill layer. The intermediate layer can be subsequently polished flat, for example, using a chemical-mechanical planarization process, resulting in a flat or planar surface facing away from the semiconductor body. In particular, the intermediate layer is continuous and formed from a single material. The intermediate layer thus has the same mechanical hardness throughout and can therefore be easily planarized.

[0036] According to at least one embodiment of the method, the intermediate layer is applied to the semiconductor body before the fill layer, so that the intermediate layer partially fills the recesses. The recesses can be completely filled with the material of the fill layer. In a subsequent method step, the fill layer is polished, with the underlying intermediate layer serving, in particular, as a polishing stop layer due to its higher mechanical hardness. After polishing, the intermediate layer protrudes beyond the fill layer in some regions along the vertical direction.

[0037] Compared to the filler layer, the intermediate layer is made of a harder material, allowing it to serve as a polishing stop layer. In particular, polishing uses abrasive particles that remove the filler layer, i.e., the softer layer, more quickly and the intermediate layer, i.e., the harder layer, more slowly or hardly at all. In particular, the abrasive particles exhibit a mechanical strength between that of the two materials to be polished. Ideally, this can result in the same layer thickness or a planar surface being achieved in the end, despite differences in the polishing removal rate, because the polishing automatically stops or slows down. In practice, however, a planar surface is hardly achievable due to the dishing effect.

[0038] According to at least one embodiment of the method, a planarization layer is applied to the fill layer and to the partially free-standing intermediate layer. The planarization layer can counteract the dishing effect mentioned here. The planarization layer can be subsequently polished flat, for example, by means of a chemical-mechanical planarization process, whereby it can have a flat or planar surface facing away from the semiconductor body.

[0039] The intermediate layer can be a hard passivation layer, for example made of Al2O3. The passivation layer can have a vertical layer thickness between 100 nm and 700 nm, for example between 200 nm and 400 nm. The fill layer is in particular formed from a softer material than the material of the passivation layer. The fill layer, for example made of SiO2, MgO or MgF2, can initially have a vertical layer thickness between 1 µm and 10 µm, or between 1 µm and 5 µm, which is then polished such that the passivation layer is exposed in certain regions. In a subsequent process step, a planarization layer, for example made of Al2O3, can be applied to the polished surface to compensate for dishing. The planarization layer can be subsequently polished so that it has a flat or planar surface facing away from the semiconductor body.

[0040] It is possible to apply an additional protective layer, such as SiO2, to the flat or planar surface of the planarization layer, particularly by means of a coating process. The protective layer can have a vertical, in particular constant, layer thickness. If necessary, the protective layer can be subsequently planarized.

[0041] According to at least one embodiment of the method, the converter layer is attached to the semiconductor body by means of a bonding material, in particular by means of glass solder. The bonding material can be made of a polymer or silicone. In this case, the two bonded surfaces can be designed so flat that the bonding layer is particularly thin, whereby the thermal resistance of the bonding layer is hardly significant. The vertical layer thickness of the bonding layer can be less than 1 µm, 0.5 µm, 0.2 µm, 0.1 µm, or 0.05 µm, approximately between 10 nm and 1 µm inclusive. Alternatively, the converter layer can be attached to the semiconductor body by means of a direct bonding process.

[0042] The method described here is particularly suitable for manufacturing a component described here. The features described in connection with the component can therefore also be used for the method, and vice versa.

[0043] Further embodiments and developments of the component or of the method for producing the component result from the following in connection with Fig. 1A to 12B explained embodiments.

[0044] They show: Fig. 1A schematic representation of a comparative example of a component with a silicone-based adhesive layer, Fig. 1B and Fig. 1C simulations to illustrate the heat distribution in a component according to Fig. 1A, Fig. 2A schematic representation of an embodiment of a component in sectional view, Fig. 2B a simulation to illustrate the heat distribution in a component according to Fig. 2A, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 schematic representations of various embodiments of a component in sectional views, Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D schematic representations of various steps of an embodiment of a method for producing a component in sectional views, and Fig. 8A, Fig. 8B, Fig. 8C, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 12A and Fig. 12B schematic representations of various steps of further embodiments of a method for producing a component in sectional views.

[0045] Identical, similar, or functionally identical elements are provided with identical reference numerals in the figures. The figures are schematic representations and therefore not necessarily to scale. Rather, comparatively small elements and, in particular, layer thicknesses may be exaggerated for clarity.

[0046] Fig. 1A shows a comparative example of a component 10 with a semiconductor body 2 and a converter layer 5, wherein the converter layer 5 is mechanically connected to the semiconductor body 2 by means of a connecting layer 3K. The semiconductor body 2 has a surface 2V facing the converter layer 5, which is structured and has depressions 2T and elevations 2H. The depressions 2T and the elevations 2H are provided with a passivation layer 32, wherein the passivation layer 32 extends substantially conformally with the structured surface 2V.

[0047] The component 10 is, in particular, a light-emitting component, such as an LED chip, wherein the semiconductor body 2 is configured to generate electromagnetic radiation of a first peak wavelength, which, during operation of the component, is scattered at the structured surface 2V and coupled into the converter layer 5. The converter layer 5 contains, in particular, phosphors that at least partially convert the radiation of a first peak wavelength into electromagnetic radiation of a second peak wavelength, wherein the second peak wavelength is longer than the first peak wavelength. Since the radiation of a first peak wavelength is shorter and thus more energetic than the radiation of a second peak wavelength, a large amount of heat is released in the converter layer 5, which heat is to be dissipated from the converter layer 5 during operation of the component 10.

[0048] On the one hand, the heat can be dissipated directly to the environment of the component 10, for example via a front side 10V of the component 10, which is formed, for example, by a surface of the converter layer 5 and can be designed as a radiation exit surface of the component 10. On the other hand, the heat can be dissipated via the connecting layer 3K, the passivation layer 32, and the semiconductor body 2, for example to a heat sink on which the component 10 is arranged. The heat sink can be a metal body or a circuit board. Heat dissipation to the heat sink proves to be much more effective than heat dissipation to the environment of the component 10, since the ambient air conducts heat relatively poorly. Good heat dissipation plays a crucial role in achieving high efficiency of the component 10. If the converter layer 5 is heated too much, both the efficiency and the service life of the component 10 can be negatively affected.

[0049] According to the comparative example of component 10 according to Fig. 1A, the connecting layer 3K is a silicone-based connecting layer. In this case, the recesses 2T are essentially filled with silicone. However, silicone has a relatively low thermal conductivity, namely approximately 0.15 W / (m K). Thermal barriers can thus form, particularly in the areas of the recesses 2T, which block heat conduction from the converter layer 5 to the semiconductor body 2. This makes cooling of the converter layer 5 more difficult overall.

[0050] Fig. Figure 1B shows a simulation of the heat distribution in the immediate vicinity of an elevation 2H, which is approximately Fig. 1A. It has been found that, in this case, thermal paths 4W form primarily through the elevations 2H of the semiconductor body 2. Due to the comparatively poorer thermal conductivity in the depressions 2T, hardly any heat exchange takes place between the converter layer 5 and the semiconductor body 2. This leads to the heat not being evenly distributed within the converter layer 5 and in a transition region between the semiconductor body 2 and the converter layer 5, and thus the heat dissipation is not optimal. Fig. Figure 1C shows a simulation of the heat distribution in a transition region between the converter layer 5 and the semiconductor body 2. It is shown in the Fig. 1C that the heat conduction from the converter layer 5 to the semiconductor body 2 is hindered or blocked, particularly in the recesses 2T, which are filled with silicone.

[0051] The simulations show that the thermal resistance is approximately 3 K / W when the converter layer 5 lies flat on the roughened peaks. This corresponds to the thermal resistance of a silicon layer with a thickness of 0.5 µm. For a component with a thickness of 1 mm 2 luminous surface at a current of 3 A, this means a temperature increase of 3 °C. For a high-performance chip operating at 5-10 A / mm 2 This corresponds to a temperature increase of 5-10 °C. This temperature increase would have a significant impact on the efficiency and lifetime of the component.

[0052] The Fig. The embodiment of a component 10 shown in Figure 2A essentially corresponds to the one shown in Fig. 1A. In contrast, the component 10 does not have a silicone-based connecting layer 3K. Instead of the connecting layer 3K, the component 10 according to Fig. 2A, a filling layer 4 and an intermediate layer 3. The filling layer 4 at least partially fills the depressions 2T. Along the vertical direction, the semiconductor body 2, in particular the majority of the elevations 2H of the semiconductor body 2, extends beyond the filling layer 4 in the direction of the converter layer 5. The filling layer 4 thus does not run conformally with the structured surface 2V. The filling layer 4 is formed from a material that preferably has a higher thermal conductivity compared to silicone or an epoxy resin. For example, the filling layer 4 is formed from a dielectric, such as SiO2, MgO, MgF2, or Al2O3. SiO2 has a thermal conductivity of approximately 1 W / (m·K). In particular, the filling layer 4 can have a lower thermal conductivity than the semiconductor body 2 or than the material of the elevations 2H.The filling layer 4 is formed from a material which in particular has a lower mechanical hardness than the material of the semiconductor body 2 or the elevations 2H.

[0053] According to Fig. 2A, the fill layer 4 in the regions of the depressions 2T does not extend conformally with the structured surface 2V of the semiconductor body 2. Rather, the material of the fill layer 4 completely fills the depressions 2T up to a vertical height at which the elevations 2H protrude beyond the fill layer 4. Both the fill layer 4 and the elevations 2H directly border the intermediate layer 3.

[0054] The intermediate layer 3 can be a connecting layer 31 formed from a material with a higher thermal conductivity than silicone or epoxy resin. In particular, the connecting layer 31 is a radiation-permeable, particularly transparent, connecting layer, such as a glass connection or a glass solder connecting layer. It is possible for the intermediate layer 3 to have a higher thermal conductivity than the filler layer 4. By means of the intermediate layer 3 embodied as a connecting layer 31, the converter layer 5 is mechanically stably attached to the semiconductor body 2.

[0055] Due to the relatively high thermal conductivity of the filling layer 4, during operation of the component 10, thermal paths 4W can be formed from the converter layer 5 through the recesses 2T to the semiconductor body 2. Thus, thermal paths 4W are formed not only outside the recesses 2T but also within the recesses 2T, which are thus distributed over the entire structured surface 2V, whereby a relatively uniform heat distribution is achieved in the transition region between the semiconductor body 2 and the converter layer 5. A simulation of the heat distribution in a component 10 according to Fig. 2A is in the Fig. 2B is shown schematically. In contrast to the Fig. 1C shows Fig. 2B shows a significant improvement in the heat distribution on the structured surface 2V without negatively affecting the output efficiency.

[0056] According to Fig. 2A, the filling layer 4 directly adjoins the structured surface 2V of the semiconductor body 2 and thus directly adjoins the semiconductor body 2. Alternatively, it is possible for the structured surface 2V to be provided with a passivation layer 32. Such a passivation layer 32 is shown, for example, in the Fig. 1A. The passivation layer 32 may have a higher thermal conductivity and / or a higher mechanical hardness than the fill layer 4. For example, the passivation layer 32 is formed from Al2O3.

[0057] The Fig. The depressions 2T shown in FIG. 2A have a vertical depth, in particular an average vertical depth, which is between 0.2 µm and 7 µm, approximately between 1 µm and 5 µm, or between 1 µm and 3 µm. Accordingly, the elevations 2H can have a vertical height, in particular an average vertical height, which is approximately the same as the vertical depth of the depressions 2T.

[0058] For example, the fill layer 4 has a local maximum layer thickness that is smaller than the maximum height of the elevations 2H or the maximum depth of the depressions 2T. In other words, the fill layer 4 only partially fills the depressions 2T. The elevations 2H protrude in some regions beyond the fill layer 4 in the direction of the converter layer 5. In a plan view of the structured surface 2V, the fill layer 4 can still be continuous. The tips of the elevations 2H protrude beyond the fill layer 4 and can be viewed as isolated islands on the fill layer 4.

[0059] The Fig. The embodiment of a component 10 shown in Figure 3 essentially corresponds to the Fig. 2. In contrast, the component 10 according to Fig. 3 has a planarization layer 33. The planarization layer 33 is formed from a material that, in particular, has a higher mechanical hardness than SiO2 or than the material of the fill layer 4. In plan view, the planarization layer 33 can completely cover the depressions 2T and the elevations 2H, i.e., the structured surface 2V. The planarization layer 33 has a surface facing the converter layer 5, which is, in particular, flat or planar. Such a surface allows savings in connecting material, whereby the connecting layer 31 can be designed to be particularly thin. The heat dissipation from the converter layer 5 to the semiconductor body 2 can thereby be further improved.

[0060] According to Fig. 3, the intermediate layer 3 can be formed exclusively from the connecting layer 31 or exclusively from the planarization layer 33. It is also possible for the intermediate layer 3 to have two sublayers arranged one above the other, one of which is the connecting layer 31 and the other of which is the planarization layer 33.

[0061] Deviating from the Fig. 3, the component 10 can be free of a connecting layer 31. In this case, the converter layer 5 is in particular directly adjacent to the flat or planar surface of the planarization layer 33. For example, the converter layer 5 can be mechanically attached to the planarization layer 33 by means of a direct bonding process. In this case, the converter layer 5 can have a planar surface facing the semiconductor body 2. The converter layer 5 and the planarization layer 33 can have a common planar interface formed by overlapping the planar surfaces of the converter layer 5 and the planarization layer 33, wherein the common interface is in particular free of a connecting material, such as an adhesive or a solder material.

[0062] The Fig. The embodiment of a component 10 shown in Figure 4 essentially corresponds to the Fig. 2. In contrast, the component 10 according to Fig. 4 has a passivation layer 32 arranged between the semiconductor body 2 and the fill layer 4. The passivation layer 32 extends, in particular, conformally with the structured surface 2V of the semiconductor body 2 and does not completely fill the recesses 2T. The passivation layer 32 merely extends into the recesses 2T and out of the recesses 2T. In plan view, the passivation layer 32 can completely cover the structured surface 2V.

[0063] In particular, the passivation layer 32 protrudes in some areas beyond the filling layer 4. In plan view, the filling layer 4 can be formed continuously, wherein the filling layer 4 can have a plurality of openings from which the tips of the passivation layer 32 grow. Fig. 4 shows that the semiconductor body 2 or the majority of the elevations 2H do not protrude from the filling layer 4. Along the vertical direction, the filling layer 4 may protrude beyond the semiconductor body 2 and, in a plan view of the structured surface 2, may cover the semiconductor body 2 in some areas, but not completely. Fig. 4, it is possible for the semiconductor body 2 or the majority of the elevations 2H to protrude in regions beyond the filling layer 4 in the direction of the converter layer 5.

[0064] According to Fig. 4, the intermediate layer 3 can be formed exclusively from the passivation layer 32 or exclusively from the connecting layer 31. It is also possible for the intermediate layer 3 to have two sublayers arranged one above the other, one of which is the connecting layer 31 and the other of which is the passivation layer 32.

[0065] The Fig. The embodiment of a component 10 shown in Figure 5 essentially corresponds to the Fig. 4. In contrast, the component 10 according to Fig. 5 additionally comprises a planarization layer 33. In particular, the planarization layer 33 and the passivation layer 32 have surfaces facing the converter layer 5, which together form a common, particularly flat or planar surface. The passivation layer 32 and the planarization layer 33 are thus flush with one another along the vertical direction and thus have a hybrid surface. The passivation layer 32 and the planarization layer 33 can be formed from the same material or from different materials. For example, the passivation layer 32 and the planarization layer 33 have substantially the same hardness and / or the same removal rate during polishing.

[0066] According to Fig. 5, the intermediate layer 3 can be formed exclusively from the passivation layer 32 or exclusively from the planarization layer 33 or in some regions from the passivation layer 32 and in some regions from the planarization layer 33.

[0067] According to Fig. 5, the converter layer 5 directly adjoins the passivation layer 32 and the planarization layer 33. The converter layer 5 can be mechanically stably attached to the common, in particular planar, surface of the passivation layer 32 and the planarization layer 33 on the semiconductor body 2 by means of a direct bonding process. Fig. 5, it is possible for a connecting layer 31 to be used to attach the converter layer 5 to the passivation layer 32 and / or to the planarization layer 33. Furthermore, it is possible for the planarization layer 33 to be designed such that, in plan view, it completely covers the passivation layer 32.

[0068] The Fig. The embodiment of a component 10 shown in Figure 6 essentially corresponds to the Fig. 4. In contrast, in the Fig. 6 shows that the component 10 has a carrier 1 on which the semiconductor body 2 is arranged. The carrier 1 can be a substrate, a semiconductor substrate, a sapphire substrate, in particular a growth substrate on which the semiconductor body 2 has been grown epitaxially. However, the carrier 1 can be different from a growth substrate. The component can be free of a growth substrate, which is removed after the growth of the semiconductor body. For example, the carrier 1 is a metal, plastic, or ceramic body. The component 10 has a rear side 10R formed by an exposed surface of the carrier 1. A front side of the carrier 1 directly adjoins, for example, a rear side 2R of the semiconductor body 2. The carrier 1 is, in particular, a chip carrier.

[0069] The semiconductor body 2 has a first, in particular p-conducting semiconductor layer 21, a second, in particular n-conducting semiconductor layer 22, and an active zone 23 arranged between the first semiconductor layer 21 and the second semiconductor layer 22. The first semiconductor layer 21 faces the carrier 1. The second semiconductor layer 22 faces away from the carrier 1. It is also possible for the first semiconductor layer 21 to be n-conducting and the second semiconductor layer 22 to be p-conducting. Both the first semiconductor layer 21 and the second semiconductor layer 22 can be embodied as a single layer or as a layer sequence comprising several sublayers.

[0070] An active zone 23 is understood to mean, in particular, an active region in the semiconductor body 2 in which electromagnetic radiation is generated during operation of the component 10. In particular, the active zone 23 comprises a pn junction zone, a quantum well structure, or a multiple quantum well structure. For example, the semiconductor body 2 is based on GaN, InGaN, InGaAlN, InGaP, InGaAlP, or AlGaAs. The semiconductor body 2 can also be formed from another III / V or II / VI compound semiconductor material. All in the Fig. 1 to 5 shown components 10 can have a Fig. 6 illustrated semiconductor body 2 and carrier 1. The component 10 can be arranged on a heat sink, wherein the carrier 1 is in particular directly adjacent to the heat sink.

[0071] The Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D show some steps of a method for manufacturing a component 10. According to Fig. 7A, a semiconductor body 2 is provided with a structured surface 2V having local elevations 2H and local depressions 2T. The local elevations 2H and the local depressions 2T may have a vertical height or a vertical depth between 1 µm and 3 µm inclusive. A lateral distance between two peaks of the elevations 2H may be between 2 µm and 6 µm inclusive. The structured surface 2V is exclusively formed by a surface of a Fig. 6, wherein the semiconductor layer 22 can be n-conductive or p-conductive. The semiconductor body 2 is based in particular on GaN.

[0072] According to Fig. 7B, the fill layer 4 is applied to the semiconductor body 2. The fill layer 4 can completely cover the structured surface 2V and, in particular, completely fill the depressions 2T. In particular, the fill layer 4 initially protrudes beyond the elevations 2H along the vertical direction. The fill layer 4 can be formed from SiO2.

[0073] The fill layer 4 is subsequently polished such that the elevations 2H now protrude beyond the fill layer 4, approximately by a height between 50 nm and 500 nm or between 50 nm and 200 nm. In particular, the semiconductor body 2 has a higher mechanical hardness than the fill layer 4. During polishing, particles can be used whose mechanical hardness is comparable to that of the fill layer 4 and, in particular, is lower than that of the semiconductor body 2. For example, the particles have a higher, the same, or slightly lower mechanical hardness than the fill layer. The semiconductor body 2 can serve as a polishing stop layer. While the material of the semiconductor body 2 is not removed, the fill layer 4 can still be removed, so that the elevations 2H protrude beyond the fill layer 4. In the Fig. 7C shows that the fill layer 4 has a substantially flat, exposed surface. However, it is possible for the exposed surface of the fill layer 4 to be curved in some areas, such as having a concave shape.

[0074] According to Fig. 7D, the converter layer 5 is mechanically attached to the polished filling layer 4 or to the structured surface 2V of the semiconductor body 2 by means of an intermediate layer 3 designed as a connecting layer 31. The Fig. The embodiment of a component 10 shown in Figure 7D corresponds to the Fig. 2 illustrated embodiment.

[0075] The Fig. The embodiment of a method step shown in Figure 8A essentially corresponds to the one shown in Fig. 7C. In contrast, after polishing the fill layer 4, a planarization layer 33 is applied to the fill layer 4 such that the planarization layer 33 covers the fill layer 4 and the elevations 2H, in particular completely covers them.

[0076] According to Fig. 8A, the planarization layer 33 initially runs in regions conforming to the elevations 2H. In a subsequent process step, the planarization layer 33 is formed according to Fig. 8B is polished or ground flat such that it has a flat or planar surface facing away from the semiconductor body 2, which can have an average roughness, in particular less than 100 nm, 50 nm, 30 nm, 10 nm or less than 5 nm, approximately between 100 nm and 1 nm inclusive. In particular, the planarization layer 33 forms the intermediate layer 3.

[0077] According to Fig. 8C, the converter layer 5 is mechanically attached to the planarization layer 33 by means of a connecting layer 31. The Fig. The embodiment of a component 10 shown in Figure 8C corresponds to the Fig. 3. Due to the planarization layer 33 with the flat or planar surface, the connecting layer 31 can be designed to be particularly thin. In particular, the connecting layer 31 has a substantially constant vertical layer thickness along the lateral directions.

[0078] The Fig. The embodiment of a method step shown in Figure 9A essentially corresponds to the one shown in Fig. 8B. In contrast, before the converter layer 5 is attached, a protective layer 34 is formed on the planarization layer 33. The protective layer 34 can be an oxide layer, for example, an SiO2 layer. In particular, the protective layer 34 has a lower mechanical hardness than the planarization layer 33. Due to the lower mechanical hardness, the protective layer 34 can be planarized particularly easily, for example, by means of a chemical-mechanical planarization process. If the planarization layer 33 is already planarized, for example, from Al2O3, and the protective layer 34 is formed as a thin layer on the planarized planarization layer 33, the step of planarizing the protective layer 34 can be omitted.For example, the protective layer 34 has a flat or planar surface facing away from the semiconductor body 2, which has a lower roughness than a surface of the planarization layer 33 facing away from the semiconductor body 2.

[0079] According to Fig. 9B, the converter layer 5 is mechanically attached to the protective layer 34 by means of a connecting layer 31. As shown in the Fig. 9B, the intermediate layer 3 can be formed by a layer sequence of the planarization layer 33, the protective layer 34 and / or the connecting layer 31 or exclusively by one of these layers. Fig. The embodiment of a component 10 shown in Figure 9B essentially corresponds to the Fig. 8C, however, with the protective layer 34.

[0080] Deviating from the Fig. 8C and Fig. 9B, it is possible that the component 10 is free of a connection layer 31.

[0081] In particular, the converter layer 5 can directly adjoin a planar surface of the planarization layer 33 or the protective layer 34. In this case, the converter layer 5 can be mechanically attached to such a planar surface using a direct bonding method. With the aid of the protective layer 34, a particularly planar surface can be created, which facilitates the attachment of the converter layer 5, in particular using the direct bonding method.

[0082] The Fig. The embodiment of a method step shown in Figure 10A essentially corresponds to the one shown in Fig. 7A. In contrast, the structured surface 2V is provided with a passivation layer 32, which in particular conforms to the structured surface 2V. A vertical layer thickness of the passivation layer 32 can be between 30 nm and 300 nm, for example, between 40 nm and 200 nm.

[0083] Analogous to Fig. 7B is in accordance with Fig. 10B, the filling layer 4 is formed on the passivation layer 32, wherein the filling layer 4 first completely covers the passivation layer 32 and then according to Fig. 10C is polished such that the passivation layer 32 protrudes beyond the fill layer 4 in some regions, approximately by a height of between 50 nm and 500 nm or between 50 nm and 200 nm. In particular, the passivation layer 32 has a higher mechanical hardness than the fill layer 4 and can serve as a polishing stop layer during polishing. In particular, the intermediate layer 3 is formed by the passivation layer 32, approximately exclusively by the passivation layer 32.

[0084] According to Fig. 10D, the converter layer 5 is attached to the semiconductor body 2 by means of a connecting layer 31. The Fig. The embodiment of a component 10 shown in Figure 10D corresponds to the Fig. 4 illustrated embodiment.

[0085] The Fig. The embodiment of a method step shown in Figure 11A essentially corresponds to the one shown in Fig. 10C. In contrast to this, analogous to the embodiment shown in the Fig. In the embodiment shown in Figure 8A, a planarization layer 33 is formed on the passivation layer 32 to counteract the dishing effect. For example, the passivation layer 32 protrudes 100 nm above the fill layer 4. In this case, the planarization layer 33 should be thicker than 100 nm. For example, the planarization layer 33 has a vertical layer thickness of 200 nm.

[0086] Analogous to the Fig. 8B is shown in accordance with Fig. 11B, the planarization layer 33 is polished such that it has a flat or planar surface facing away from the semiconductor body 2. Across the peaks of the elevations 2H, the sum of the layer thicknesses of the passivation layer 32 and the planarization layer 33 can be, for example, between 50 nm and 150 nm, such as around 70 nm, 90 nm, or 100 nm.

[0087] According to Fig. 11B, the planar or flat surface facing away from the semiconductor body 2 is designed as a hybrid surface, which is formed in some areas from the surface of the planarization layer 33 and in some areas from the surface of the passivation layer 32. Deviating from this, it is possible for the planar or flat surface facing away from the semiconductor body 2 to be formed exclusively from the surface of the planarization layer 33.

[0088] On the planar or flat surface, the converter layer 5 can be bonded by means of a connecting layer 31 or according to Fig. 11C using a direct bonding process. Fig. The embodiment of a component 10 shown in Figure 11C corresponds to the Fig. 5 illustrated embodiment.

[0089] The Fig. 12A and Fig. 12B essentially correspond to the embodiments shown in the Fig. 11B and Fig. 11C. In contrast, the component 10 has a protective layer 34 which is analogous to the one shown in the Fig. 9A and Fig. 9B is flat or planar. The protective layer 34 shown in connection with the Fig. 9A and Fig. 9B described features of the protective layer 34 can therefore also be used for the Fig. 12A and Fig. 12B illustrated embodiments can be used. List of reference symbols 10 Component 10V surface / front of the component 10R Surface / back of the component 1 Substrate / Growth substrate / Carrier 2 semiconductor bodies 21 first semiconductor layer 22 second semiconductor layer 23 active zone 2V surface / front of the semiconductor body 2R Surface / back of the semiconductor body 2T recess of the semiconductor body / intermediate layer 2H Increase in the semiconductor body / intermediate layer 3 Intermediate layer 31 Connection layer 32 Passivation layer 33 Planarization layer 34 protective layer 3K adhesive layer 4 Filling layer 4W thermal paths 5 Converter layer

Claims

[1] Component (10) with a semiconductor body (2), a converter layer (5), a filling layer (4) and an intermediate layer (3) arranged in the vertical direction between the semiconductor body and the converter layer, wherein - the semiconductor body has a surface (2V) facing the converter layer, which is structured and has vertical depressions (2T), - the vertical recesses are filled with a material of the filling layer that has a higher thermal conductivity than silicone, - the intermediate layer (3) or the semiconductor body (2) has a higher mechanical hardness than the filling layer and protrudes in regions beyond the filling layer (4) along the vertical direction, and - the structured surface (2V) of the semiconductor body (2) has local elevations (2H) and local depressions (2T), wherein the structured surface (2V) is formed exclusively by the surface of an n-conductive or p-conductive semiconductor layer (22). [2] Component (10) according to claim 1, wherein the semiconductor body (2) has a higher mechanical hardness than the filling layer (4) and projects beyond the filling layer in regions along the vertical direction, wherein tips of the local elevations (2H) project beyond the filling layer (4) and are formed as isolated islands on the filling layer (4), and wherein - in plan view of the structured surface (2V) - the filling layer (4) is designed to be continuous. [3] Component (10) according to claim 1, wherein the intermediate layer (3, 32) has a higher mechanical hardness than the filling layer (4) and extends partially into the depressions (2T), wherein - the intermediate layer extends in conformity with the structured surface (2V) of the semiconductor body (2) and projects beyond the filling layer in some regions along the vertical direction, - the intermediate layer (3) comprises or is formed from a passivation layer (32), wherein the filling layer (4) has a plurality of openings from which tips of the passivation layer (32) grow, and - in plan view of the structured surface (2V) the filling layer (4) is continuous. [4] Component (10) according to one of the preceding claims, wherein the semiconductor body (2) is configured to generate electromagnetic radiation of a first peak wavelength during operation of the component, wherein the converter layer is configured to convert the electromagnetic radiation of a first peak wavelength into electromagnetic radiation of a second peak wavelength, and wherein the second peak wavelength is greater than the first peak wavelength. [5] Component (10) according to one of the preceding claims, wherein the material of the filling layer (4) has a thermal conductivity of at least 0.5 W / (m·K). [6] Component (10) according to one of the preceding claims, wherein the material of the filling layer (4) has a lower thermal conductivity than the semiconductor body (2). [7] Component (10) according to one of the preceding claims, wherein the vertical recesses (2T) have an average vertical depth of between 0.2 µm and 5 µm inclusive. [8] Component (10) according to one of the preceding claims, in which the intermediate layer (3) comprises a connecting layer (31) or is formed from a connecting layer (3), wherein the connecting layer (31) is arranged in the vertical direction between the filling layer (4) and the converter layer (5). [9] Component (10) according to one of the preceding claims, in which the intermediate layer (3) comprises a passivation layer (32) or is formed therefrom, wherein the passivation layer (32) extends in regions conforming to the structured surface (2V) of the semiconductor body (2), and wherein the passivation layer (32) is arranged in regions in the vertical direction between the filling layer (4) and the semiconductor body. [10] Component (10) according to one of the preceding claims, which has a planarization layer (33) which, in plan view, completely covers the filling layer (4) and has a flat or planar surface facing the converter layer (5). [11] Component (10) according to one of the preceding claims, which contains a protective layer (34) which is arranged between the converter layer (5) and the semiconductor body (2), wherein the protective layer has a constant vertical layer thickness along lateral directions and directly or exclusively adjoins the converter layer except for a connecting layer (31). [12] Electronic device or light source comprising a component (10) according to one of the preceding claims. [13] Method for producing a component (10) comprising a semiconductor body (2), a converter layer (5), a filling layer (4) and an intermediate layer (3) arranged vertically between the semiconductor body and the converter layer, comprising the following steps: A) providing the semiconductor body with a structured surface (2V) having vertical depressions (2T); B) filling the recesses with a material of the filling layer which has a higher thermal conductivity than silicone and is additionally selected such that the intermediate layer or the semiconductor body has a higher mechanical hardness than the filling layer; C) polishing the filling layer, wherein the intermediate layer or the semiconductor body serves as a polishing stop layer due to its higher mechanical hardness and, after polishing, protrudes in regions along the vertical direction beyond the filling layer; and D) applying the converter layer to the polished filling layer, wherein the structured surface (2V) of the semiconductor body (2) has local elevations (2H) and local depressions (2T), wherein the structured surface (2V) is formed exclusively by the surface of an n-conductive or p-conductive semiconductor layer (22). [14] Method according to claim 13, wherein - the semiconductor body (2) protrudes over the filling layer (4) in some areas along the vertical direction after polishing, - the intermediate layer (3) is applied to the partially free-standing semiconductor body after polishing the filling layer (4), - the intermediate layer is subsequently polished to a plane, whereby it has a flat or planar surface facing away from the semiconductor body, and - in plan view of the structured surface (2V) the filling layer (4) is continuous. [15] Method according to claim 13, wherein - the intermediate layer (3, 32) is applied to the semiconductor body (2) before the filling layer (4), so that the intermediate layer partially fills the recesses (2T), - the depressions are completely filled with the material of the filling layer, - the filling layer is polished, whereby the underlying intermediate layer serves as a polishing stop layer due to its higher mechanical hardness and, after polishing, protrudes in some areas along the vertical direction beyond the filling layer, and - in plan view of the structured surface (2V) the filling layer (4) is continuous. [16] Method according to the preceding claim, in which a planarization layer (33) is applied to the filling layer (4) and to the partially free-standing intermediate layer (3), wherein the planarization layer is subsequently polished flat, whereby it has a flat or planar surface facing away from the semiconductor body (2). [17] Method according to one of claims 13 to 16, wherein the converter layer (5) is attached to the semiconductor body (2) by means of a direct bonding process. [18] Method for producing a component (10) comprising a semiconductor body (2), a converter layer (5), a filling layer (4) and an intermediate layer (3) arranged vertically between the semiconductor body and the converter layer, comprising the following steps: A) providing the semiconductor body with a structured surface (2V) having vertical depressions (2T); B) filling the recesses with a material of the filling layer which has a higher thermal conductivity than silicone and is additionally selected such that the intermediate layer or the semiconductor body has a higher mechanical hardness than the filling layer; C) polishing the filling layer, wherein the intermediate layer or the semiconductor body serves as a polishing stop layer due to its higher mechanical hardness and, after polishing, protrudes in regions along the vertical direction beyond the filling layer; and D) Applying the converter layer to the polished filling layer, wherein the converter layer (5) is fixed to the semiconductor body (2) by means of glass solder.

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