Multi-bit level converter and methods for its operation

Abstract

Multi-bit level converter (10, 200), comprising: a plurality of level converters (10, 200), each configured to receive an input signal in a first voltage domain and to provide a corresponding output signal in a second voltage domain, each of the plurality of level converters (10, 200) comprising an enable node (240); and an enabling circuit (100) having an output terminal (104, 204, 205) connected to the enabling node (240) of each of the plurality of level converters (10, 200), and having a first network terminal configured to receive a first voltage in the first voltage domain; wherein each of the plurality of level converters (10, 200) is configured to output the corresponding output signal in response to an enable signal received by the enable circuit (100) and each has a second mains connection configured to receive a second voltage in the second voltage domain, and furthermore has: a first inverter (210) connected to the first network connection, wherein the first inverter has an input (202) connected to an input (202) of the level converter (10, 200); a first PMOS transistor (220) comprising a source connected to the second mains terminal and a gate connected to a first output (104, 204, 205, 304) of the level converter (10, 200); a second inverter (212) having an input (202) connected to an output (104, 204, 205, 304) of the first inverter (210); a first NMOS transistor (230) comprising a drain connected to a drain of the first PMOS transistor (220) and a gate connected to an output (104, 204, 205, 304) of the second inverter (212), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the first NMOS transistor (230); a second PMOS transistor (222) comprising a source connected to the second mains terminal and a gate connected to a drain of the first PMOS transistor (220) and a second output (104, 204, 205, 304) of the level shifter (10, 200); and a second NMOS transistor (232) comprising a drain connected to a drain of the second PMOS transistor (222) and a gate connected to the output (104, 204, 205, 304) of the first inverter (210), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the second NMOS transistor (232); wherein the first output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide the corresponding output signal in the second voltage domain and the second output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide a complementary output signal in the second voltage domain.

Description

BACKGROUND

[0001] Level shifters are commonly used components in digital circuits for communication between two different voltage domains, one being a low-voltage domain and the other a high-voltage domain. For example, a common type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. In some examples, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (typically ground), so that one of two data storage nodes can be occupied by the information to be stored, with the complementary information stored at the other data storage node. Each bit in the SRAM cell is stored on four of the transistors, forming two cross-connected inverters.The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its bit lines. In read mode, for example, the memory cell bit lines are pre-charged to a predefined threshold voltage. When the word line is released, a sampling amplifier connected to the bit lines samples and outputs stored information. A "dual-rail" SRAM architecture refers to an SRAM arrangement where the memory logic operates in a low-voltage domain (VCC), while the memory array operates in the high-voltage domain (VDD). Level shifters are used to convert the signals going to the SRAM cells to a higher voltage.

[0002] US 9,893,726 B2 discloses a level-shifting circuit comprising a static pull-down circuit that pulls an output node low in response to an input circuit receiving a first logic value at an input node. The input node is coupled to receive a signal from a circuit in a first voltage range, while the output node is configured to provide a corresponding signal in a second voltage range. The static pull-down circuit is implemented with a passgate featuring a series-connected pair of transistors. The level-shifting circuit also includes a dynamic pull-up circuit that, when active, pulls the output node high in response to the input circuit receiving a second logic value at its input node.The dynamic pull-up circuit includes a third and a fourth transistor coupled in series between the output node and a supply voltage node of the second voltage domain.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present revelation are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased as appropriate for the clarity of the discussion. Fig. Figure 1 is a block diagram illustrating aspects of an exemplary level converter in accordance with some embodiments. Fig. Figure 2 is a circuit diagram illustrating aspects of an exemplary multibit level converter and enable circuit in accordance with some embodiments. Fig. 3 is a circuit diagram that shows an example of the enable signal inverter of the in Fig. The circuit shown in section 2 is illustrated. Fig. Figure 4 is a circuit diagram illustrating aspects of another exemplary multibit level converter and an enabling circuit in accordance with some embodiments. Fig. Figure 5 is a block diagram illustrating aspects of an exemplary system-on-a-chip (SOC) that includes a level shifter in accordance with some embodiments. Fig. Figure 6 is a flowchart illustrating aspects of an exemplary procedure in accordance with some figures. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative expressions such as "below," "under," "lower," "above," "upper," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative expressions are intended to encompass various orientations of the component in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive expressions used herein may be interpreted accordingly.

[0007] A static random-access memory (SRAM) device has an array of memory cells containing transistors connected between an upper reference potential and a lower reference potential, so that one of two data storage nodes can be occupied by the information to be stored, with the complementary information stored at the other data storage node. For example, a typical SRAM memory cell array comprises six transistors. Each bit in the SRAM cell is stored on four of the transistors, forming two cross-connected inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during read and write operations by selectively connecting the cell to its respective bit lines.

[0008] In read mode, the memory cell bit lines are pre-charged, for example, to a predefined threshold voltage. When the word line is enabled, a sampling amplifier connected to the bit lines samples the stored information and outputs it.

[0009] A "dual-rail" SRAM architecture refers to an SRAM configuration where the memory logic operates in a low-voltage domain, while the memory array itself operates in a high-voltage domain. Known dual-rail SRAM configurations can reduce memory power dissipation, but memory access time can be negatively affected. Furthermore, loss and noise can increase as the voltage difference between the high- and low-voltage domains grows.

[0010] In some well-known applications, a single-bit level shifter with a enable signal for power isolation is used. The enable signal is received by an enable input terminal, which allows selective operation of the level shifter based on the enable signal. Each bit has its own level shifter, and each level shifter includes an enable input that receives the enable signal for selective operation of the level shifter. Some typical arrangements of such level shifter circuits require a minimum of five transistors per bit to implement the enable logic, which can consume excess area and power.

[0011] In accordance with aspects of the present disclosure, a multi-bit level converter is provided where the transistors of the enable function can be shared across multiple bits of logic. Accordingly, enable transistors are shared across multiple bits, thereby reducing the number of enable transistors required.

[0012] Fig. Figure 1 is a block diagram illustrating an example of a multi-bit level converter 10 in accordance with aspects of the present disclosure. Disclosed examples feature a plurality of level converters 200, each of which has a signal input terminal 202 configured to receive an input signal VIN in a first voltage domain PD1 and to provide a corresponding output signal VOUT in a second voltage domain PD2, which is higher than the first voltage domain PD1, at a signal output terminal 204 received by system components 20 in the second voltage domain PD2. The system components 20 may, for example, include a memory circuit, such as an SRAM memory array of memory cells, which receives the output signals VOUT in the second voltage domain PD2.

[0013] An enable circuit 100 has an output terminal 104, which is connected to an enable node of each of the plurality of level shifters 200. The level shifters 200 output the output signals VOUT, corresponding to the input signals VIN in the second voltage domain PD2, in response to an enable signal EN received by the enable circuit 100 at an enable input 102. In some examples, the enable circuit 100 receives the enable signal EN and processes or modifies it to output a transformed enable signal EN'. In the examples discussed below, for instance, the enable circuit 100 inverts the received enable signal EN, and therefore the transformed enable signal EN' is the complement of the enable signal EN.

[0014] In the Fig. In the example shown, the enabling circuit 100 comprises a mains terminal 12 that receives a supply voltage VDD in the first voltage domain PD1. Accordingly, the transformed enabling signal EN' is output in the first voltage domain PD1. The level shifters 200 each have a mains terminal 14 that receives a second supply voltage VCC in the second voltage domain PD2.

[0015] The level shifter converts the voltage level of the input signal VIN from VDD to VCC. VCC is higher than VDD to support, for example, a dual-rail SRAM configuration as described previously. Therefore, if the input signal VIN received by the level shifter 200 is a logic low (at ground voltage VSS), then the ground signal is provided at output terminal 204. If the input signal VIN is at a logic high (VDD), a logic high signal is output in the second voltage domain PD2 (VCC).

[0016] Fig. Figure 2 is a circuit diagram illustrating further aspects of the multi-bit level converter 10. In the Fig. In the example shown, the multi-bit level converter 10a is a two-bit level converter that includes two level converters 200a and 200b (collectively referred to as level converter 200) to provide each output bit in the second voltage domain PD2. Each of the level converters 200a and 200b has a first inverter 210 connected to the first line terminal VDD. The first inverters 210 each receive a signal input VIN1 and VIN2 at their respective input terminals 202 and provide inverted input signals VIN1_bar and VIN2_bar.

[0017] Each of the level converters 200a, 200b has a first PMOS transistor 220 comprising a source connected to the second network VCC and a gate connected to the first output 204 of the level converters 200a, 200b, to output the respective first output signals VOUT1, VOUT2. Each of the level converters 200a, 200b also has a first NMOS transistor 230 comprising a drain connected to a drain of the first PMOS transistor 220 and a gate connected to the inputs 202 of the level converters 200a, 200b via the first inverters 210 and second inverters 212.

[0018] Level shifters 200a and 200b each have a second PMOS transistor 222, the source of which is connected to the second power supply VCC, and a gate connected to a drain of the first PMOS transistor 220 and to a second output 205 of the level shifters, which outputs the complementary output signals VOUT1_bar and VOUT2_bar. Second NMOS transistors 232 each have a drain connected to a drain of the second PMOS transistor 222 and a gate connected to the level shifter input terminals 202 via the first inverter 210. As described below, the sources of the first and second NMOS transistors 230, 232 are each selectively connected to the circuit ground terminal in response to the enable signal EN received from the enable circuit 100 and are therefore sometimes referred to herein as enable node 240 of the level converter 200.

[0019] As mentioned previously, in some disclosed examples, the enable circuit 100 includes an enable signal inverter. In the example of Fig. 2. A release signal inverter 110 receives the release signal EN and outputs an inverse release signal EN_bar. The release signal inverter is connected to the VDD network terminal. Fig. Figure 3 illustrates an example of a CMOS implementation of the enable signal inverter 110, which includes a PMOS transistor 112. The PMOS transistor has a source connected to the first supply voltage VDD and a drain connected to the drain of an NMOS transistor 114. The NMOS transistor 114 has a source connected to the ground terminal. The gates of the PMOS and NMOS transistors 112 and 114 are connected to receive the enable signal EN, and the connected drains provide a node for outputting the EN_bar signal to the level shifter 200.

[0020] The enable circuit 100 further comprises first and second control transistors 250, 252, each of which receives the output EN_bar of the enable signal inverter 110. In the illustrated example, each of the level shifters 200 has the first and second control transistors 250, 252 connected between the respective first and second NMOS transistors 230, 232 (i.e., the enable nodes 240) and the ground terminal. Therefore, for each of the plurality of first control transistors 250, its source is connected to the ground terminal, its drain is connected to the first NMOS transistor 230 of the respective level shifter 200, and its gate is connected to the output of the enable signal inverter 110 to receive the reverse enable signal EN_bar.Similarly, in each of the majority of second control transistors 252, its source is connected to the ground terminal, its drain is connected to the second NMOS transistor 232 of a respective level converter 200, and its gate is connected to the output of the enable signal inverter 110 to receive the reverse enable signal EN_bar.

[0021] Furthermore, the enable circuit 100 includes a third control transistor 254, whose source is connected to the VDD mains terminal, while its drain is connected to the respective inverter 212 of each of the plurality of level shifters 200. The gate of the third control transistor 254 is connected to receive the reverse enable signal EN_bar. In the example of Fig. 2 are the first and second control transistors 250, 252 of the enable circuit 100, both NMOS transistors, and the third control transistor 254 of the enable circuit 100 is a PMOS transistor.

[0022] Therefore, each of the first and second control transistors 250, 252 is configured to selectively connect the enable nodes 240 of the corresponding level converter 200 to the ground terminal in response to the enable signal EN_bar. The third control transistor 254 is configured to connect the VDD mains terminal to the respective second inverter 212 of each of the plurality of level converters 200 in response to the enable signal EN_bar.

[0023] With regard to the level shifter 200a as an example, the level shifter 200a provides the output in the second voltage domain PD2 (VCC voltage level) according to the received input signal VIN1 in response to the enable signal EN, which could, for example, be a clocked signal. The output 104 of the enable circuit inverter 110 is received by each of the first, second, and third control transistors 250, 252, and 254 of the enable circuit 100. For example, it is assumed that both the input signal VIN1 and the enable signal EN are high (VDD). The output EN_bar of the enable circuit inverter 110 is low, which turns off the first and second NMOS control transistors 250 and 252 of the enable circuit 100 and isolates the level shifter 200 from ground.The third control transistor 254 of the enable circuit 100 is switched on by the low EN_bar signal, which connects the second inverter 212 of the level converter to the VDD supply voltage.

[0024] The high input signal VIN1 at signal input terminal 202 is output by the first inverter 210 as a low VIN1_bar signal, which switches off the second NMOS transistor 232. The low VIN1_bar signal is inverted by the first inverter 210, resulting in a high (VDD) signal that is received at the gate of the first NMOS transistor 230 and switches it on. The VOUT1 and VOUT1_bar signals at the level shifter indicate that output terminals 204, 205 (and the gates of the PMOS transistors 220, 222) are held at their previous levels, at least by the first control transistors 250, 252. When the enable signal EN becomes low, the high EN_bar signal switches off the third control transistor 254 and switches on the first and second control transistors 250, 252.As mentioned previously, the reversed VIN1_bar signal turns on the first NMOS transistor 230, which, together with the first control transistor 250, provides a path to ground for the second level-shift output terminal 205, thus pulling the VOUT1_bar signal low. The low VOUT1_bar signal turns on the second PMOS transistor 222, connecting the VCC supply voltage to the first level-shift output terminal 204, thereby pulling the VOUT1 signal high in the second voltage domain PD2 (i.e., VCC). The high VOUT1 signal also turns off the PMOS transistor 220.

[0025] When the VIN1 signal crosses low, the level shifter 220 is configured to output a low VOUT1 signal at the first output 204 and a high VOUT1 bar signal in the second voltage domain PD2 (VCC). As mentioned previously, when the enable signal EN is high, the output EN_bar of the enable circuit inverter 110 is low, which turns off the first and second NMOS control transistors 250 and 252 of the enable circuit 100. The third control transistor 254 of the enable circuit 100 is turned on by the low EN_bar signal, which connects the second inverter 212 of the level shifter to the VDD supply voltage.

[0026] The low input signal VIN1 at signal input terminal 202 is output by the first inverter 210 as a high VIN1_bar signal, which turns on the second NMOS transistor 232. The high VIN1_bar signal is inverted by the first inverter 210, resulting in a low signal that is received at the gate of the first NMOS transistor 230 and turns it off. The high VOUT1 and low VOUT1_bar signals at the level-shift signal output terminals 204 and 205 remain at their previous levels, at least due to the first and second control transistors 250 and 252, which are off. When the enable signal EN goes low, the high EN_bar signal turns off the third transistor 254 and turns on the first and second control transistors 250 and 252.As mentioned previously, the VIN1_bar signal turns on the second NMOS transistor 232, which, together with the second control transistor 252, provides a path to ground for the level-shift output terminal 204, thereby pulling the high VOUT1 signal low. The low VOUT1 signal turns on the first PMOS transistor 220, connecting the VCC supply voltage to the second level-shift output terminal 204, thus pulling the low VOUT1_bar signal high in the second voltage domain PD2 (i.e., VCC). The high VOUT1_bar signal also turns off the PMOS transistor 222.

[0027] Fig. Figure 4 is a circuit diagram illustrating an example of a four-bit level converter 10b, which has four level converters 200a, 200b, 200c, 200d (collectively referred to as level converter 200) to provide each output bit in the second voltage domain PD2. As with the two-bit level converter of Fig. 2 Each of the level converters 200 of the four-bit level converter has a first inverter 210, which each receive a signal input VIN1, VIN2, VIN3, VIN4 at their respective input terminals 202 and provide inverted input signals VIN1_bar, VIN2_bar, VIN3_bar, VIN4_bar.

[0028] Each of the level converters 200 has a first PMOS transistor 220 comprising a source connected to the second network VCC and a gate connected to a first output 304 of the level converters 200 to output the respective first output signals VOUT1, VOUT2, VOUT3, and VOUT4. Each of the level converters 200 also has a first NMOS transistor 230 comprising a drain connected to a drain of the first PMOS transistor 220 and a gate connected to the inputs 202 of the level converters 200a and 200b via inverters 210 and 212.

[0029] The level shifters 200 each further comprise a second PMOS transistor 222, which includes a source connected to the second network VCC and a gate connected to a drain of the first PMOS transistor 220 and a second output 205 of the level shifters, which outputs complementary output signals VOUT1_bar, VOUT2_bar, VOUT3_bar, VOUT4_bar. Second NMOS transistors 232 each have a drain connected to a drain of the second PMOS transistor 222 and a gate connected to the level shifter input terminals 202 via the first inverter 210. The sources of the first and second NMOS transistors 230, 232 are each connected to the circuit ground terminal in response to the enable signal EN received by the enable circuit 100, and therefore act as enable node 240 of the level converter 200.

[0030] The enable circuit 100 of the illustrated exemplary four-bit level converter comprises an enable signal inverter 110, which converts the signal in Fig. The CMOS enable signal inverter 110 shown in Figure 3 can be included. The enable signal inverter 110 receives the enable signal EN and outputs the inverse enable signal EN_bar. The enable signal inverter 110 operates in the first voltage domain PD1 (i.e., it is connected to the VDD network).

[0031] The enable circuit 100 further comprises a plurality of first and second control transistors 250, 252, each of which receives the output EN_bar of the enable signal inverter 110. In the illustrated example, each of the level shifters 200 has the first and second control transistors 250, 252 connected between the respective first and second NMOS transistors 230, 232 (i.e., the enable nodes 240) and the ground terminal. Therefore, for each of the plurality of first control transistors 250, its source is connected to the ground terminal, its drain is connected to the first NMOS transistor 230 of a respective level shifter 200, and its gate is connected to the output of the enable signal inverter 110 to receive the reverse enable signal EN_bar.Similarly, in each of the majority of second control transistors 252, its source is connected to the ground terminal, its drain is connected to the second NMOS transistor 232 of a respective level converter 200, and its gate is connected to the output of the enable signal inverter 110 to receive the reverse enable signal EN_bar.

[0032] The enable circuit 100 further comprises a third control transistor 254, whose source is connected to the VDD mains terminal, while its drain is connected to the respective second inverter 212 of each of the plurality of level shifters 200. The gate of the third control transistor 254 is connected to receive the reverse enable signal EN_bar. In the illustrated example, both the first and second control transistors 250 and 252 of the enable circuit 100 are NMOS transistors, and the third control transistor 254 of the enable circuit 100 is a PMOS transistor.

[0033] Therefore, each of the first and second control transistors 250, 252 is configured to selectively connect the enable nodes 240 of the corresponding level converter 200 to the ground terminal in response to the enable signal EN_bar. The third control transistor 254 is configured to connect the VDD mains terminal to the respective second inverter 212 of each of the plurality of level converters 200 in response to the enable signal EN_bar.

[0034] In the illustrated examples, the number of transistors required to implement the enable circuit 100 can be determined according to (nbit*2)+3 It must be determined where nbit is a number of level converters of the multi-bit level converter and where nbit is an integer >=2.

[0035] Again, in relation to Fig. Figure 2 illustrates an example of a two-bit level converter. Therefore, in the Fig. 2 in the embodiment shown, nbit = 2. Accordingly, the enable circuit 100 of the illustrated two-bit level converter has a total of seven transistors: transistors 212 and 214 of the enable signal inverter 110; the third control transistor 254; the first and second control transistors 250, 252 corresponding to the first level converter 200a; and the first and second control transistors 250, 252 corresponding to the second level converter 200b.

[0036] Fig. Figure 4 illustrates an example of a four-bit level converter, where nbit = 4. The enable circuit 100 of the illustrated four-bit level converter has a total of 11 transistors: transistors 212 and 214 of the enable signal inverter 110; the third control transistor 254; the first and second control transistors 250, 252 corresponding to the first level converter 200a; the first and second control transistors 250, 252 corresponding to the second level converter 200b; the first and second control transistors 250, 252 corresponding to the third level converter 200c; and the first and second control transistors 250, 252 corresponding to the fourth level converter 200d.

[0037] Some known multi-bit level converters may require a completely separate enable circuit for each bit of the level converter. In contrast, embodiments disclosed herein "share" some components of the enable circuit 100 under each bit of the level converter. For example, the enable signal inverter 110 and the third control transistor 254 are connected to each bit of the level converter, reducing the number of components required to implement the enable circuit 100 and thus the level converter 10 itself. Accordingly, the reduction in transistors compared to previous level converters according to (nbit*5)−[nbit*2)+3] It must be determined where nbit is a number of level converters of the multi-bit level converter and where nbit is an integer >=2.

[0038] For example, for the in Fig. In the two-bit level converter shown, the number of enable transistors is reduced from 10 to 7, compared to previous level converter arrangements. For a three-bit level converter, the number of enable transistors can be reduced from 15 to 9, and for the one shown in Fig. In the four-bit level converter shown, the number of enable transistors is reduced from 20 to 11. Therefore, by sharing enable logic components, significant area and power savings are achieved according to aspects of this disclosure.

[0039] Fig. Figure 5 illustrates an example of a system-on-a-chip (SOC) system 300, which employs a plurality of multi-bit level converters 200 in accordance with aspects of the disclosure. The SOC system 300 comprises a data bus 310 operating in the first voltage domain PD1, as well as a component 320 comprising logic circuits 322 operating in the second voltage domain PD2. The data bus 310 comprises a plurality of data lines 312 connected to the respective signal input terminals 202 of the multi-bit level converters 200. Data signals from the data bus 310 are output to the signal input terminals 202 of each of the multi-bit level converters 200, which operate to convert the data signals from the first voltage domain PD1 to the second voltage domain PD2 in response to the enable signal EN received by the enable circuit 100. As with the previously discussed embodiments, the components are "shared" in Fig. The 5 enabled circuits shown contain 100 components, such as the enabled signal inverters 110, which are connected to the level converters 200. This facilitates the implementation of the multi-bit level converters 200 (containing the enabled circuits 100) using fewer components.

[0040] Fig. Figure 6 is a process flow diagram illustrating aspects of an exemplary level conversion method 350 in accordance with disclosed embodiments. With regard to Fig. 6 in connection with the in Fig. In the multi-bit level converters illustrated in Figures 1-4, a plurality of level converters, such as level converters 200, are provided in a mode 352. In a mode 354, a respective input signal in a first voltage domain PD1 is received by each of the plurality of level converters 200 at, for example, signal input terminal 202. In a mode 356, an enable signal EN is received, as at the enable signal input terminal 102 of the enable circuit 100. In a mode 358, the enable signal EN is inverted by the enable signal inverter 110, resulting in the inverted enable signal EN_bar, which is output by the inverter 110. The inverted enable signal EN_bar is output in a mode 360 ​​to each of the plurality of level converters 200. In particular, the inverted enable signal EN_bar is output in accordance with Fig.The signals discussed in examples 1-4 are received by the first, second, and third transistors 250, 252, and 253. Each of the level shifters 200 has the first and second control transistors 250 and 252 connected between the respective second and first output terminals 205 and 204 (via the first and second NMOS transistors 230 and 232) and the ground terminal. The gates of each of the first and second transistors 250 and 252 are connected to the output of the enable signal inverter 110 to receive the inverse enable signal EN_bar. The third control transistor 254 is connected between the VDD mains terminal and each of the respective inverters 212 of each level shifter 200. The gate of the third control transistor 254 receives the inverse enable signal EN_bar.

[0041] In operation 362, an output signal VOUT at a first output terminal 204 is provided by each of the level converters 200 in a second voltage domain PD2, which is higher than the first domain PD1, in response to the reverse enable signal EN_bar, corresponding to the respective input signal VIN.

[0042] Disclosed embodiments therefore provide an enable circuit 100 for a multi-bit level converter 200, which consists of fewer transistors than were required for previous level converters. Some examples disclose a multi-bit level converter comprising a plurality of level converters, each configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level converters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level converters, and each of the plurality of level converters is configured to output the corresponding output signals in response to an enable signal received by the enable circuit.

[0043] In accordance with other aspects, a level-shift enable circuit comprises an inverter configured to receive a first supply voltage and has input and output terminals. The level-shift enable circuit further comprises a plurality of first control transistors, each having a source connected to a ground terminal, a gate connected to the output terminal of the inverter, and a drain connected to one of the plurality of level shifters. A plurality of second control transistors each have a source connected to a ground terminal, a gate connected to the output terminal of the inverter, and a drain connected to one of the plurality of level shifters.A third control transistor has a source configured to receive a second supply voltage higher than the first supply voltage, a gate connected to the output terminal of the inverter, and a drain connected to each of the plurality of level shifters.

[0044] In accordance with other aspects, a level-shifting method involves providing a plurality of level shifters. Each of the plurality of level shifters receives a given input signal in a first voltage domain. An enable signal is received, and vice versa. The reverse enable signal is output to each of the plurality of level shifters. An output signal corresponding to the given input signal is provided at a first output terminal by each of the level shifters in a second voltage domain, which is higher than the first voltage domain, in response to the reverse enable signal.

Claims

[1] Multi-bit level converter (10, 200), comprising: a plurality of level converters (10, 200), each configured to receive an input signal in a first voltage domain and to provide a corresponding output signal in a second voltage domain, each of the plurality of level converters (10, 200) comprising an enable node (240); and an enabling circuit (100) having an output terminal (104, 204, 205) connected to the enabling node (240) of each of the plurality of level converters (10, 200), and having a first network terminal configured to receive a first voltage in the first voltage domain; wherein each of the plurality of level converters (10, 200) is configured to output the corresponding output signal in response to an enable signal received by the enable circuit (100) and each has a second mains connection configured to receive a second voltage in the second voltage domain, and furthermore has: a first inverter (210) connected to the first network connection, wherein the first inverter has an input (202) connected to an input (202) of the level converter (10, 200); a first PMOS transistor (220) comprising a source connected to the second mains terminal and a gate connected to a first output (104, 204, 205, 304) of the level converter (10, 200); a second inverter (212) having an input (202) connected to an output (104, 204, 205, 304) of the first inverter (210); a first NMOS transistor (230) comprising a drain connected to a drain of the first PMOS transistor (220) and a gate connected to an output (104, 204, 205, 304) of the second inverter (212), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the first NMOS transistor (230); a second PMOS transistor (222) comprising a source connected to the second mains terminal and a gate connected to a drain of the first PMOS transistor (220) and a second output (104, 204, 205, 304) of the level shifter (10, 200); and a second NMOS transistor (232) comprising a drain connected to a drain of the second PMOS transistor (222) and a gate connected to the output (104, 204, 205, 304) of the first inverter (210), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the second NMOS transistor (232); wherein the first output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide the corresponding output signal in the second voltage domain and the second output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide a complementary output signal in the second voltage domain. [2] Multi-bit level converter (10, 200) according to claim 1, wherein the enable circuit (100) comprises an enable signal inverter (110) configured to receive the enable signal and an output (104, 204, 205, 304) configured to provide a complementary signal of the enable signal, wherein the enable signal inverter (110) is connected to the first network terminal. [3] Multi-bit level converter (10, 200) according to any of the preceding claims, further comprising: a data bus (310) having a plurality of data lines (312), each of the data lines (312) being connected to provide the input signal in the first voltage domain to a respective plurality of level shifters (10, 200); and a logic circuit (322) configured to receive the output signals in the second voltage domain from the plurality of level converters (10, 200). [4] Multi-bit level converter (10, 200) according to one of the preceding claims, wherein the enable circuit (100) comprises: a plurality of first control transistors (250), each of the first control transistors (250) having a source connected to the ground terminal, a drain connected to the first NMOS transistor (230) of each of the level shifters (10, 200), and a gate connected to the output (104, 204, 205, 304) of the enable signal inverter (110); and a plurality of second control transistors (252), each of the second control transistors (252) having a source connected to the ground terminal, a drain connected to the second NMOS transistor (232) of a respective level shifter (10, 200), and a gate connected to the output (104, 204, 205, 304) of the enable signal inverter (110). [5] Multi-bit level converter according to claim 4, wherein each of the first and second control transistors (252) is an NMOS transistor (114, 230, 232). [6] Multi-bit level converter (10, 200) according to claim 4 or 5, wherein the enable circuit (100) comprises a third control transistor (254) comprising a source connected to the first mains terminal, a drain connected to the second inverter (212) of each of the plurality of level converters (10, 200), and a gate connected to the output (104, 204, 205, 304) of the enable signal inverter (110). [7] Multi-bit level converter according to claim 6, wherein the third control transistor (254) is a PMOS transistor (112, 220, 222). [8] Multi-bit level converter (10, 200) according to any one of claims 4 to 7, wherein each of the first and second control transistors (252) is configured to connect the enable node (240) of the corresponding level converter (200) to the ground connection in response to the enable signal. [9] Multi-bit level converter (10, 200) according to claim 6 or 7, wherein the third control transistor (254) is configured to connect the second mains connection to each of the second inverters (212) of the plurality of level converters (10, 200) in response to the enable signal. [10] Multi-bit level converter (10, 200) according to any one of claims 4 to 9, wherein the enable circuit (100) comprises a number of transistors determined according to (nbit*2)+3, where nbit is a number of level converters (10, 200) of the plurality of level converters (10, 200) and where nbit is an integer >=2. [11] Multi-bit level converter (10, 200) according to one of the preceding claims, further comprising a data bus (310) having a plurality of data lines (312), wherein each of the plurality of level converters (10, 200) is connected to a respective plurality of data lines (312) and is configured to receive the input signal in the first voltage domain from the respective data line. [12] Procedure encompassing: Providing a plurality of level converters (10, 200) wherein each of the plurality of level converters (10, 200) comprises an inverter; Receiving a respective input signal in a first voltage domain by each of the plurality of level converters (10, 200); Receiving a release signal; Invert the received release signal; Outputting the inverted enable signal to each of the plurality of level converters (10, 200); Invert each of the respective input signals in the first voltage domain in response to the inverted enable signal; and Providing a control transistor (254) connected between a mains terminal in the first voltage domain and each of the inverters, the control transistor (254) having a gate configured to receive the inverted enable signal; wherein inverting each of the respective input signals in the first voltage domain in response to the inverted enable signal comprises connecting each of the inverters to the mains connection in the first voltage domain in response to receiving the inverted enable signal at the gate of the control transistor (254); and furthermore Providing an output signal in a second voltage domain higher than the first voltage domain at a first output terminal (204, 205) of each of the level shifters (10, 200), corresponding to the respective input signal in response to the inverted enable signal. [13] Method according to claim 12, further comprising: Providing a complementary output signal at a second output terminal of each of the level converters (10, 200) corresponding to the respective inverted input signal in the second voltage domain in response to the inverted enable signal. [14] Method according to claim 12 or 13, further comprising: Providing a plurality of first control transistors (250), wherein each of the plurality of level shifters (10, 200) has one of the first control transistors (250) connected between the first output terminal (204, 205) and a ground terminal, and each of the first control transistors (250) has a gate configured to receive the inverted enable signal; and Providing a plurality of second control transistors (252), wherein each of the plurality of level shifters (10, 200) has one of the second control transistors (252) connected between the second output terminal and the ground terminal, and each of the second control transistors (252) has a gate configured to receive the inverted enable signal; wherein providing the output signal at the first output terminal (204, 205) and providing the complementary output signal at the second output terminal of each of the level shifters (10, 200) includes connecting the first or second output terminal to the ground terminal in response to receiving the inverted enable signal at the gates of the first and second control transistors (250, 252).

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