Encapsulation with flexible connection scheme in the encapsulation and process

Abstract

Encapsulation (135) comprising the following: a cooling plate (146), a first encapsulation (92) comprising the following: a first component die (80) and a second component die (80) above the cooling plate (146); and a first encapsulation material (85) that encapsulates the first component die (80) and the second component die (80), a conductor track structure (88) on the first encapsulation material (85) and the first component die (80), a second encapsulation (65') on the first encapsulation (92) which is bonded to the first encapsulation (92), wherein the second encapsulation (65') comprises the following: Independent-Passive-Device-Dies (20) and a second encapsulation material (48) that encapsulates the independent passive device dies (20), a power module (134) on the second encapsulation (65') which is bonded to the second encapsulation (65'), a further second encapsulation (65') comprising further independent passive device dies (20) arranged above the second device die (80) and encapsulated in the second encapsulation material (48), a further power module (134) on the further second encapsulation (65') which is bonded to the further second encapsulation (65'), Through holes (130) passing through the first encapsulation (92), a screw (138) passing through one of the through holes (130), and a strut (142), on the second encapsulation (65') and the further second encapsulation (65'), wherein the cooling plate (146) is fastened by means of the screw (138) and the strut (142).

Description

GENERAL STATE OF THE ART

[0001] The encapsulation of integrated circuits is becoming increasingly complex, as more component dies are encapsulated within the same package to create systems with more features. These encapsulations often employ independent passive devices (IPDs), which are discrete components. The IPDs are frequently bonded to the front of integrated fan-out (InFO) packages and are the same height as the power modules. Consequently, the IPDs occupy the area that could otherwise be used to form the power modules, necessitating smaller solder balls for bonding them. This also results in a detrimental increase in the current density within the solder balls. An encapsulated integrated circuit is disclosed, for example, in US 2019 / 0115300 A1 and DE 10 2016 100 523 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of this disclosure are best understood by studying the following detailed description together with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not shown to scale. The dimensions of the various features may have been enlarged or reduced as desired for illustrative purposes. The Fig. Figures 1 to 6 represent cross-sectional views of intermediate stages in the formation of modules with independent passive devices (IPDs) according to some embodiments. The Fig. Figures 7 to 12 represent the flexible IPD design according to some embodiments. The Fig. Figures 13 to 21 show cross-sectional views of intermediate stages in the encapsulation of an integrated fan-out encapsulation (InFO encapsulation) containing an IPD according to some embodiments. Fig. Figure 22 shows a top view of an InFO encapsulation with an IPD component according to some embodiments. The Fig. Figures 23 to 28 show cross-sectional views of intermediate stages in forming a system with one or more IPD-containing INFO encapsulations according to some embodiments. The Fig. 29 and Fig. Figure 30 shows cross-sectional views of IPD-containing InFO encapsulations according to some embodiments. Fig. Figure 31 shows a top view of a recovered wafer with IPD-containing InFO encapsulations according to some embodiments. Fig. Figure 32 shows a top view of an exemplary layout of a recovered wafer according to some embodiments. Fig. Figure 33 shows a schematic cross-sectional view of some components of a system with an IPD-containing information encapsulation according to some embodiments. Fig. Figure 34 describes a process flow for forming an encapsulation according to some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples of implementing various features of the invention. For the sake of simplicity, certain examples of components and arrangements are described below. The following description may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or reference symbols may be repeated in the various examples in this disclosure.This repetition serves to simplify and clarify matters and does not in itself prescribe any relationship between the various embodiments and / or configurations explained.

[0004] Terms with spatial reference, such as "underlying," "below," "lower," "above," "upper," and the like, can also be used here to simplify the description in order to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the figures. In addition to the orientation shown in the figures, these terms with spatial reference are intended to encompass other orientations of the component during use or operation. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the descriptors with spatial reference used here can be interpreted accordingly.

[0005] According to some embodiments, an encapsulation containing independent passive devices (IPDs) and the method for forming such an encapsulation are provided. The intermediate steps in forming the encapsulation are illustrated according to some embodiments. Several variations of some embodiments are explained. The embodiments described here are intended to serve as examples that enable the manufacture or use of the subject matter of this disclosure, and those skilled in the art with a normal level of knowledge will readily recognize possible modifications that nevertheless remain within the intended scope of protection of the various embodiments. Similar reference numerals are used in the various views and embodiments to designate similar elements.While embodiments of methods may be described as being carried out in a specific order, others may be carried out in any sensible order. According to some embodiments of the present disclosure, an IPD encapsulation, which is an integrated fan-out encapsulation (InFO encapsulation), is formed by encapsulating IPDs therein. The IPD encapsulation is then bonded to a device encapsulation containing device dies and may be bonded between a power module and the device encapsulation.

[0006] The Fig. Figures 1 to 6 show cross-sectional views of intermediate stages in the formation of IPD modules according to some embodiments. Fig. 1. An IPD wafer of 100 is formed. The respective process is in process flow 200 in Fig. 34 is represented as process 202. The IPD wafer 100 contains a multitude of IPD dies 20 ( Fig. 5), wherein Fig. Figure 6 schematically shows the cross-sectional view of exemplary IPD dies 20 according to some embodiments. As in Fig. As shown in Figure 6, the IPD die 20 contains a passive component 22. The passive component 22 can be a capacitor, a resistor, an inductor, or the like. The passive component 22 can be formed on the substrate 21, which, according to some embodiments, can be a semiconductor substrate such as a silicon substrate. A conductive trace structure 24 is formed on the substrate 21. An IPD die 20 can contain a single type of passive component (such as a capacitor, resistor, inductor, or the like) and need not include any active components. The passive component 22 can be formed in or on the substrate 21, as with the conductive trace structure 24, which has multiple dielectric layers. The passive component 22 is connected to terminals 26, which can be metal pillars, metal contact pads, or the like.According to some embodiments, an IPD die 20 has only two terminals 26, each connected to one end of the passive component 22. According to some embodiments, an IPD die 20 has more than two terminals. A protective layer 28 is formed to cover the terminals 26. According to some embodiments of the present disclosure, the protective layer 28 is formed from a polymer such as polyimide, polybenzoxazole (PBO), or the like.

[0007] In Fig. 2. An IPD wafer 100 is glued over the protective layer 102 to a backside grinding belt (BG belt) 104 to protect the front surface of the wafer 100. Next, as in Fig. Figure 3 shows that the back side of the IPD wafer 100 is ground to thin it, with the grinding device 106 shown schematically. In a subsequent process, as shown in Fig. 4 shown, a die-mounting film (DAF, not shown, see DAF 46 in Fig. 16) A chip singulation band 110 is glued to the back of the IPD wafer 100 and to the DAF. The chip singulation band 110 and the protective band 104 are located on opposite sides of the IPD wafer 100. The frame 108 is used to hold the chip singulation band 110. Then the protective band 104 and the protective layer 102 are removed.

[0008] In Fig. 5. The IPD wafer 100 is sawn into a large number of IPD modules 120 (separated). The respective process is described in process flow 200 in Fig. Figure 34 is represented as process 204. Each of the multiple IPD modules 120 can contain one or more IPD dies. If the IPD modules 120 contain multiple uncut IPD dies 20, the layers in the multiple IPD dies 20 are continuously connected to form continuous layers. For example, the semiconductor substrates 21 of the multiple IPD dies 20 are continuously connected to each other, thus forming a continuous semiconductor substrate. The conductor structures 24 of the multiple IPD dies 20 are also continuously connected to each other to form a continuous conductor structure.

[0009] Fig. Figure 7 represents a section of the IPD wafer 100, which contains a plurality of IPD dies 20 arranged as an array. The IPD modules 120, with varying numbers of IPD dies 20, can be sawn from the IPD wafer 100. For example, IPD module 120A has an array of 4×5 IPD dies 20. IPD module 120B has an array of 2×2 IPD dies 20. IPD module 120C has a single IPD die 20. The number of IPD dies in the IPD module 120 depends on various factors, such as the size of the device die 80 ( Fig. 28) and the target value for capacitance, resistance, or inductance of the IPD module 120 or the like. For example, if a higher capacitance is required, the IPD module 120 can contain more IPD dies 20 (capacitor dies) which can be connected in parallel to achieve the desired capacitance. Fig. Figure 8 represents an exemplary IPD module 120 according to some embodiments.

[0010] The embodiments of the present disclosure offer flexibility in connecting IPD dies 20 when an IPD module 120 contains multiple IPD dies 20. Thus, Fig. Figure 9 shows an exemplary connection scheme for joining eight IPD dies 20 to form four IPD components, which can also be joined to form fewer IPD components, or each of the four IPD components can be used separately in the final construction. In the diagram shown in Fig. In the example shown in Figure 9, the terminals 26 of two adjacent IPD dies 20 are connected via rewiring lines (or contact pads) 52. If the IPD dies 20 are capacitor dies, the capacitance is at least doubled by connecting them using the rewiring lines 52.

[0011] According to some embodiments, the IPD dies can be 20, as in Fig. Figure 8 shows a square shape in plan view. According to alternative embodiments, the IPD dies 20 can be, as shown in Fig. Figure 12 shows an elongated shape. According to some embodiments, the length and width of IPD dies 20 are in the range between approximately 50 µm and approximately 2,000 µm.

[0012] The Fig. Figures 13 to 21 represent cross-sectional views of intermediate stages in the formation of an InFO encapsulation with IPD modules 120 according to some embodiments of the present disclosure. The corresponding processes are described in the Fig. The process flow shown in section 34 is also shown schematically.

[0013] In Fig. 13. A carrier 30 is provided and a release film 32 is applied to the carrier 30. The respective process is described in process flow 200 in Fig. Figure 34 is shown as process 206. The support 30 is made of a translucent material, and it can be a glass, ceramic, organic support, or the like. The release film 32 is in physical contact with the upper surface of the support 30. The release film 32 can be made of a light-to-heat conversion coating material (LTHC coating material). The release film 32 can be applied to the support 30 by coating. According to some embodiments of the present disclosure, the LTHC coating material can decompose under the influence of heat from light / radiation (such as from a laser beam) and thus detach the support 30 from the structure formed on it.

[0014] According to some embodiments, a dielectric buffer layer 34 is formed on the LTHC coating material 32. The dielectric buffer layer 34 can be formed from a polymer such as PBO, polyimide, benzocyclobutene (BCB), or another suitable polymer.

[0015] In Fig. 14. Backside redistribution layers (RDL - Redistribution Layer; and metal contact surfaces) 36 are formed. The respective process is described in process sequence 200 in Fig. 34 is depicted as process 208. The formation process can include the deposition of a (not shown) metal seed layer, the formation and structuring of a plating mask (such as a photoresist, not shown) on the metal seed layer, and the plating of a metallic material such as copper and / or aluminum onto the metal seed layer. The metal seed layer can include a titanium layer and a copper layer on the titanium layer, and it can be formed, for example, by physical vapor deposition (PVD). The metal seed layer and the plated metallic material can be formed from the same or different materials. The structured plating mask is then removed, followed by etching of the sections of the metal seed layer that were previously covered by the structured plating mask. The remaining sections of the metal seed layer and the plated metallic material are RDL 36.Then a dielectric layer 38 is formed on the RDL 36. The respective process is shown in process sequence 200 in . Fig. 34 is represented as process 210. The dielectric layer 38 can be formed from PBO, polyimide, or the like. Then, a structuring process is carried out to form openings 40 through which the metal contact surfaces / RDL 36 are exposed. This structuring process can include an exposure and a development process.

[0016] Fig. 15 represents the formation of metal posts 42. The respective process is shown in process flow 200 in Fig. 34 is shown as process 212. In the description, the metal posts 42 are also referred to as vias 42, since they extend through the subsequently distributed encapsulation material. The formation of the metal posts 42 can be similar to the formation of the RDL 36, except that the plated metal material of the metal posts 42 is significantly higher than that of the RDL 36. When the metal posts 42 are formed, vias 44 are simultaneously formed in the openings 40 ( Fig. 14).

[0017] Fig. 16 represents the placement / attachment of IPD modules 120. The respective process is described in process flow 200. Fig. Figure 34 is shown as process 214. The IPD modules 120 are attached to the dielectric layer 38 via DAF 46. Several IPD modules 120 can be placed on the dielectric layer 38. The IPD modules 120 can be identical or different from each other, for example, each having a different number of IPD dies 20. The passive components 22 in the IPD modules 120 are shown schematically. The IPD modules 120 can have the same type of passive component or different component types. For example, one of the IPD modules 120 can contain capacitor dies, while another IPD module 120 can have resistor dies.

[0018] Next, as in Fig. Figure 17 shows an encapsulation material 48 being distributed and then cured to encapsulate the IPD module 120 and the metal posts 42. The respective process is described in process sequence 200 in Fig. Figure 34 is shown as process 216. The encapsulating material 48 fills the gap between adjacent metal posts 42 and between metal posts 42 and IPD modules 120. The encapsulating material 48 may contain a molding compound, a mold underfill, an epoxy resin, and / or a resin. The encapsulating material 48 is distributed to such a height that its upper surface is higher than the upper ends of the terminals 26 and the dielectric layer 28. If the encapsulating material 48 is formed from a molding compound or mold underfill, it may contain a base material, which may be a polymer, a resin, an epoxy resin, or the like, and (not shown) filler particles in the base material. The filler particles may be dielectric particles made of SiO2, Al2O3, silicon dioxide, or the like, and they may be spherical. The spherical filler particles may also have the same or different diameters.

[0019] After the distribution of encapsulation material 48, as also in Fig. As shown in Figure 17, a planarization process such as chemical-mechanical polishing (CMP) or a mechanical grinding process is carried out to planarize the encapsulation material 48 and the dielectric layers 28 until the metal posts 42 and the terminals 26 are all exposed. Due to the planarization process, the top ends of the metal posts 42 are essentially the same height (coplanar) as the top surfaces of the terminals 26 and essentially coplanar with the top surface of the encapsulation material 48. The metal posts 42 are subsequently also referred to as vias 42, since they extend through the encapsulation material 48.

[0020] Fig. 18 represents the formation of a front-side rewiring structure that includes several RDLs and the corresponding dielectric layers. The respective process is described in process sequence 200 in Fig. 34 is presented as process 218. The training processes are briefly explained below. Fig. 18. A dielectric layer 50 is first formed. According to some embodiments of the present disclosure, the dielectric layer 50 is formed from a polymer such as PBO, polyimide, or the like. The formation process includes applying the dielectric layer 50 in a flowable form, curing the dielectric layer 50, and performing an exposure and development process to structure the dielectric layer 50. According to alternative embodiments of the present disclosure, the dielectric layer 50 is formed from an inorganic dielectric material such as silicon nitride, silicon oxide, or the like. The formation process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition methods.Then, for example, openings (occupied by RDL 52) are formed via an etching process. The vias 42 and the terminals 26 are exposed through the openings in the structured dielectric layer 50.

[0021] Next, the RDL 52 are formed. The RDL 52 have vias 52A formed in the dielectric layer 50 such that they are connected to the terminals 26 and the vias 42, and metal traces (metal conductors) 52B on the dielectric layer 50. According to some embodiments of the present disclosure, the RDL 52 are formed by means of a plating process, which may be essentially the same process as that used to form the RDL 36. Although only one layer of RDL 52 is shown, further RDLs may be formed. Then the dielectric layers 60 and 62 and the RDL 64 are formed. The dielectric layers 60 and 62 may be formed from one or more materials selected from the same group of possible materials as the dielectric layer 50.The dielectric layers 60 and 62 can, for example, be formed using PBO, polyimide, or BCB. The RDL 64 can also include some under-bump metallizations (UBM), which are likewise designated as RDL 64. According to some embodiments of the present disclosure, the RDL 64 are formed from nickel, copper, titanium, or several layers thereof. According to some embodiments, the RDL 64 have a titanium layer and a copper layer on the titanium layer. Although two layers of RDL 52 and 64 are shown, the front-facing RDL can include a single RDL layer or more than two RDL layers.

[0022] Fig. Figure 18 also describes the formation of electrical connectors 66 according to some embodiments. The respective process is described in the process flow 200 in Fig. 34 is represented as process 220. The formation of electrical connectors 66 can include placing solder balls on the exposed sections of the RDL 64 and subsequently reflowing the solder balls, and thus the electrical connectors 66 are solder regions. According to alternative embodiments of the present disclosure, the formation of electrical connectors 66 includes performing a plating step to form solder layers on the RDL 64 and subsequently reflowing the solder layers. The electrical connectors 66 can also have non-solder metal columns or metal columns and solder caps on the non-solder metal columns, which can also be formed by plating. In the description, the assembly, including the dielectric layer 34 and the overlying assembly, is collectively referred to as the composite encapsulation 65 or reclaimed wafer 65.

[0023] In Fig. 19 The regenerated wafer 65 is next placed on the tape 68, which is attached to a frame 70. According to some embodiments of the present disclosure, the electrical connectors 66 are in contact with the tape 68. Next, a light beam is directed onto the LTHC coating material 32, and the light beam penetrates the translucent carrier 30. According to some embodiments of the present disclosure, the light beam is a laser beam that illuminates the entire LTHC coating material 32.

[0024] As a result of exposure (such as laser irradiation), the carrier 30 can detach from the LTHC coating material 32, and thus the restored wafer 65 is unbonded (detached) from the carrier 30. The respective process is described in process flow 200 in Fig. 34 is represented as process 222. During exposure, the LTHC coating material 32 decomposes in response to the heat introduced by the light beam, allowing the support 30 to be separated from the recovered wafer 65. The remaining LTHC coating material 32 is then removed, for example, by plasma cleaning. The resulting recovered wafer 65 is in Fig. 20 shown.

[0025] After unbonding of the support 30, the dielectric buffer layer 34 is exposed as a surface section of the reconstructed wafer 65. Fig. In step 20, the dielectric buffer layer 34 is structured to form openings 74 through which the metal contact surfaces of the RDL 36 are exposed. The respective process is described in process sequence 200. Fig. 34 is shown as process 224. According to some embodiments of the present disclosure, the structuring is carried out by laser drill. In a subsequent process, the strip 68 and the frame 70 are removed from the recovered wafer 65, and the resulting recovered wafer 65 is in Fig. 21. The recovered wafer 65 is then separated into a multitude of identical IPD encapsulations 65', which are placed in the Fig. 21 and Fig. 22 are shown. The respective process is in process flow 200 in Fig. 34 is represented as process 226.

[0026] Fig. Figure 22 shows a top view (from above or below) of the IPD encapsulation 65'. The multiple electrical connectors 66 are also shown. According to some embodiments of the present disclosure, the corners of the IPD encapsulation 65' are trimmed. This can provide space for the subsequently inserted screws 138 ( Fig. 28).

[0027] The Fig. Figures 23 to 28 show cross-sectional views of intermediate stages in the formation of a system encapsulation with IPD encapsulations therein according to some embodiments of the present disclosure. The corresponding processes are described in the Fig. The process flow shown in section 34 is also shown schematically.

[0028] In Fig. 23. A carrier 76 and a release film 78 are provided. The carrier 76 and the release film 78 can be made of essentially the same material as the carrier 30 and the release film 32, respectively ( Fig. 14) The carrier 76 can also have a round shape in plan view. There may be an additional buffer layer (not shown) on the release film 78, and the additional buffer layer may (if present) be made of PBO, polyimide, BCB or the like.

[0029] Then, for example, component dies 80 (including 80A and 80B) are placed on the release foil 78 via DAF 82. The component dies 80 can have semiconductor substrates and integrated circuit components (such as active components, including transistors; not shown) on the front surface (the upward-facing surface) of the respective semiconductor substrates. According to some embodiments of the present disclosure, the component dies 80 can include logic dies, which may include central processing unit dies (CPU dies), graphics processing unit dies (GPU dies), mobile application dies, microcontroller dies (MCU dies), baseband dies (BB dies), application processor dies (AP dies), field-programmable gate array dies (FPGA dies), application-specific integrated circuit dies (ASIC dies), or the like. The component dies 80 can also include memory dies, input-output dies (IO dies) or the like.Memory dies can include high-bandwidth memory stacks (HBM stacks), hybrid memory cubes (HMC), dynamic random-access memory dies (DRAM dies), static random-access memory dies (SRAM dies), or the like.

[0030] According to some embodiments, the component dies 80A and 80B represent several component dies of different sizes, constructions and / or functions and may contain some or all of the above-mentioned die types in any combination. Fig. Figure 32, for example, represents an exemplary layout of component dies 80 placed on the same support 76. According to some embodiments of the present disclosure, the component 80 can be, as in Fig. Figure 32 shows a computation logic die 80-1, a memory die 80-2, and an I / O die 80-3. According to some embodiments, all component dies 80 are used in the same system, such as an AI system (AI - artificial intelligence), and the component dies 80 are not separated into different encapsulations, remaining all in the same end encapsulation. According to alternative embodiments, all of the illustrated component dies 80-1, 80-2, and 80-3 can represent a component die group functioning as a system, and several identical systems can be placed on the same carrier 76. According to these embodiments, the multiple systems are separated in a subsequent singulation process.

[0031] In Fig. In step 23, the component dies 80 are encapsulated in encapsulation material 85. The respective process is described in process sequence 200. Fig. Figure 34 is shown as process 228. According to some embodiments, the encapsulation material 85 comprises a molding compound, a mold underfill, an epoxy resin, a resin, or the like. If the encapsulation material 85 is formed from a molding compound or mold underfill, it may contain a base material, which may be a polymer, a resin, an epoxy resin, or the like, and (not shown) filler particles in the base material. A planarization process is carried out until the electrical connectors (such as metal pillars or metal contact pads; not shown) of the device dies 80 are exposed. In subsequent processes, a conductive trace structure 88 is formed on the encapsulation material 85 and the device dies 80. The respective process is described in process flow 200 in Figure 34. Fig. Figure 34 is shown as process 230. According to some embodiments of the present disclosure, the conductor track structure 88 has dielectric layers 86A and dielectric layers 86B on the dielectric 86A. Each of the dielectric layers 86B can be thicker than each of the dielectric layers 86A. The dielectric layers 86A can be formed from one or more photosensitive materials such as PBO, polyimide, or the like. The dielectric layers 86B can be formed from a non-photosensitive material such as molding compound or mold underfill.

[0032] In dielectric layers 86A, RDL 84A are formed, and in dielectric layers 86B, RDL 84B are formed. According to some embodiments, the RDL 84B are thicker and / or wider than the RDL 84A and can be used for longer electrical conductors, while the RDL 84A can be used for shorter electrical conductors. Electrical connectors 90 are formed on the surface of the conductor structure 88. The electrical connectors 90 and the RDL 84A and 84B are electrically connected to the component dies 80. Throughout this description, the structure on the release film 78 is referred to as the InFO encapsulation 92, which is also a reclaimed wafer.

[0033] In a subsequent process, the carrier 76 is unbonded from the InFO encapsulation 92. According to some embodiments of the present disclosure, the DAF 82 ( Fig. 23) for example, removed using a CMP process or a mechanical grinding process. According to alternative embodiments, the DAF 82 are not removed, and they are attached to the strip 94. Then the InFO encapsulation 92 is attached to the strip 94, which in turn is processed as described in Fig. 24 is shown attached to the frame 96. According to some embodiments, through holes 130 are formed that extend through the InFO encapsulation 92. The respective process is described in process sequence 200 in Fig. 34 is shown as process 232. The through holes 130 can be formed by laser drilling, drilling with a drill or the like. Fig. Figure 31 shows an exemplary distribution of through-holes 130. The component dies 80 (and the subsequently bonded IPD encapsulations 65') can be arranged as an array, and the through-holes 130 can be located at the corners of the component dies 80 and the IPD encapsulations 65'. According to other embodiments, no through-holes are formed.

[0034] In Fig. 25. The IPD encapsulations 65' are bonded to the InFO encapsulation 92, for example, via solder areas 66 and possibly some pre-solder in the form of parts of the electrical connectors 90. The respective process is described in process sequence 200. Fig. 34 is represented as process 234. Then, as in Fig. As shown in Figure 26, an underfill 132 is distributed between the IPD encapsulations 65' and the InFO encapsulation 92 to protect the solder areas 66. In a subsequent process, a cleaning process can be carried out, and the titanium layers (if formed) in the RDL 36 can be etched to expose the copper sections of the RDL 36. Next, as also shown in Fig. 26 shows the underfill 132 distributed in the gaps between the IPD encapsulations 65' and the InFO encapsulation 92.

[0035] Fig. Figure 27 represents the bonding of the power modules 134, for example via solder areas 136, to the IPD encapsulations 65'. The respective process is shown in process flow 200 in Fig. 34 is represented as process 236. To protect the solder areas 136, an underfill 139 is then distributed between the power modules 134 and the IPD encapsulations 65'. Throughout this description, the components on the tape 94 are collectively referred to as the composite encapsulation 135 or the reclaimed wafer 135. According to some embodiments of the present disclosure, the power modules 134 contain pulse-width modulation (PWM) circuits for power control. The power modules 134 provide the controlled power, for example, via the vias 42 and the conductor track structure 88 to the underlying component dies 80. The power modules 134 are also connected to the passive components in the IPD module 120 for current monitoring and storage.

[0036] Fig. Figure 28 describes the installation of a cooling plate (heat-dissipating plate) 146 on the regenerated wafer 135 using thermal interface material (TIM) 144, which is an adhesive with good thermal conductivity. The respective process is described in process flow 200 in Figure 28. Fig. 34 is shown as process 238. A strut 142 is installed using screws 138 and bolts 140. The respective process is also shown in process sequence 200 in Fig. 34 is shown as process 238. According to some embodiments, the lower surface of the strut 142 is in contact with the upper surfaces of the IPD encapsulations 65'. The strut 142 can be made of a metallic material such as copper, stainless steel, or the like. In one embodiment, Fig. As shown in the top view of Figure 31, the strut 142 can form a grid of several interconnected horizontal strips 142A and vertical strips 142B. The strut 142, the screws 138, and the bolts 140 are used together to fasten the reconstructed wafer 135 and the cooling plate 146, and to reduce warping in the reconstructed wafer 135.

[0037] Fig. Figure 29 represents the reconstructed wafer 135 according to alternative embodiments. These embodiments are similar to those in Fig. 28 embodiments shown, except that neither struts nor screws and bolts are installed. Fig. Figure 30 represents the reconstructed wafer 135 according to other alternative embodiments. These embodiments are similar to those described in Fig. 29 embodiments shown, except that no cooling plate is installed.

[0038] The Fig. 10 and Fig. Figure 11 shows a schematic top view of the IPD module 120 and the plumb area 136 (see Fig. 27) according to some embodiments. It should be noted that the connection with the terminals 26 ( Fig. 10 and Fig. 11), since the lot areas 136 (see also Fig. 28, Fig. 29 or Fig. 30) are located on the IPD module 120, while the terminals 26 are on the underside of the IPD module 120, the connection (such as the RDL 52) is flexible, and the connection can be placed in any desired position without disturbing the position of the solder areas 136. The IPD dies 20 in the IPD module 120 can therefore be grouped in any combination via the RDL 52 so that a desired number of passive components (such as capacitors) are present by means of parallel connection, series connection or combinations thereof.

[0039] Fig. Figure 32 shows a top view of an exemplary reclaimed wafer 135. According to some embodiments of the present disclosure, the logic compute dies 80-1, the IPD encapsulations 65', and the power modules 134 can be stacked to form multiple groups, and the groups of stacks are arranged as a multi-row, multi-column array. The memory dies 80-2 and the I / O dies 80-3 can be formed in the edge regions of the array. Connectors 148 are used to connect the reclaimed wafer 135 to external components for signal and / or power connections. According to some embodiments, the connectors 148 can be sockets.

[0040] Fig.Figure 33 schematically represents the relative vertical positions of the logic compute dies 80-1, the memory dies 80-2, the I / O dies 80-3, the IPD encapsulation 65', the power module 134, and the connector 148. It shows that the connectors 148 are formed on the conductor track structure 88, which is located on the component dies 80.

[0041] In the embodiments described above, certain processes and features are explained according to some embodiments of the present disclosure in such a way as to create a three-dimensional (3D) encapsulation. Other features and processes may also be included. For example, these may include test structures that are involved in the verification testing of the 3D packaging or the 3DIC components. The test structures may include, for example, test pads formed in a rewiring layer or on a substrate that enables the testing of the 3D packaging or 3DIC, the use of probes and / or probe cards, and the like. The verification testing can be performed on semi-finished assemblies as well as on the final assembly.In addition, the designs and methods disclosed here can be used in conjunction with testing methodologies, including intermediate verification of demonstrably defect-free products, to increase yield and reduce costs.

[0042] The embodiments of the present disclosure exhibit several advantageous features. IPD dies were typically bonded to the front face of InFO encapsulations and were exactly the same height as power modules. Consequently, the IPD dies competed with electrical connectors (such as solder areas) for chip area. This could lead to an undesirable reduction in the size of the solder areas and an undesirable increase in the current density in the solder areas. Furthermore, a lateral current path is required to connect the IPD dies and the power modules, and these lateral paths are long, resulting in power loss. In the embodiments of the present disclosure, IPD dies are encapsulated within IPD encapsulations, allowing them to be stacked directly beneath the power modules, thus saving space.Furthermore, the short vertical distance between the IPD dies and the power modules reduces the current path. In addition, the connection of the IPD dies is flexible, making it possible to create passive components with the desired values ​​for capacitance, resistance, and / or inductance.

[0043] According to some embodiments, the invention relates to an encapsulation as specified in claim 1. Optionally, the IPD die and the multiple IPD dies are electrically interconnected. Optionally, the IPD die comprises a passive component and has no active or additional passive components. Optionally, the second encapsulation and the power module form an encapsulation stack, and the encapsulation further comprises multiple encapsulation stacks identical to the encapsulation stack on the first encapsulation, which is bonded to the first encapsulation. Optionally, the encapsulation stack and the multiple encapsulation stacks together form an array. Optionally, the encapsulation further comprises a bolt, wherein the bolt and screw fasten the metal strut to the first encapsulation.Optionally, the encapsulation further comprises several first solder areas that bond the first encapsulation to the second encapsulation, and several second solder areas that bond the second encapsulation to the power module. Optionally, the encapsulation further comprises a second component die encapsulated in the first encapsulation material, wherein the first component die is part of a die array comprising several component dies identical to the first component die, and the second component die is located in a boundary region of the die array.

[0044] According to some embodiments, the invention relates to an encapsulation as specified in claim 10. Optionally, the encapsulation further comprises a through-hole connection in the first molding compound, wherein the through-hole connection electrically connects the multiple first and second rewiring lines to one another.

[0045] According to some embodiments, the invention relates to a method as specified in claim 12. Optionally, the encapsulation of the IPD die comprises encapsulating a first IPD module with several identical IPD dies, wherein the several identical IPD dies are not sawn apart. Optionally, the first rewiring lines connect the several identical IPD dies to one another. Optionally, during encapsulation, a second IPD module, identical to the first IPD module, is encapsulated in the molding compound, and the first IPD module is separated from the second IPD module by the molding compound. Optionally, the method further comprises attaching a cooling plate or a connector to the second encapsulation, wherein both the first and the second IPD modules are located in the same continuous molding compound area when the cooling plate or connector is attached. Optionally, the IPD die comprises a single capacitor and contains no active or other passive components.Optionally, the method further includes encapsulating a second and a third component die in the encapsulation material, wherein the first component die comprises a logic compute die, the second component die a memory die and the third component die an IO die.

Claims

[1] Encapsulation (135) comprising the following: a cooling plate (146), a first encapsulation (92) comprising the following: a first component die (80) and a second component die (80) above the cooling plate (146); and a first encapsulation material (85) that encapsulates the first component die (80) and the second component die (80), a conductor track structure (88) on the first encapsulation material (85) and the first component die (80), a second encapsulation (65') on the first encapsulation (92) which is bonded to the first encapsulation (92), wherein the second encapsulation (65') comprises the following: Independent-Passive-Device-Dies (20) and a second encapsulation material (48) that encapsulates the independent passive device dies (20), a power module (134) on the second encapsulation (65') which is bonded to the second encapsulation (65'), a further second encapsulation (65') comprising further independent passive device dies (20) arranged above the second device die (80) and encapsulated in the second encapsulation material (48), a further power module (134) on the further second encapsulation (65') which is bonded to the further second encapsulation (65'), Through holes (130) passing through the first encapsulation (92), a screw (138) passing through one of the through holes (130), and a strut (142), on the second encapsulation (65') and the further second encapsulation (65'), wherein the cooling plate (146) is fastened by means of the screw (138) and the strut (142). [2] Encapsulation (135) according to claim 1, wherein the Independent-Passive-Device dies (20) are identical and are components of an Independent-Passive-Device module (120). [3] Encapsulation (135) according to claim 2, wherein the Independent-Passive-Device-Dies (20) are electrically connected to each other. [4] Encapsulation (135) according to any of the preceding claims, wherein each of the Independent-Passive-Device-Dies (20) comprises a passive component (22) and has no active and additional passive components. [5] Encapsulation (135) according to one of the preceding claims, wherein the second encapsulation (65') and the power module (134) form an encapsulation stack and the encapsulation (135) further comprises several encapsulation stacks similar to the encapsulation stack on the first encapsulation (92) bonded to the first encapsulation (92), and wherein the further second encapsulation (65') and the further power module (134) form a further encapsulation stack of the several encapsulation stacks. [6] Encapsulation (135) according to claim 5, wherein the encapsulation stack and the multiple encapsulation stacks together form an array. [7] Encapsulation (135) according to any of the preceding claims, wherein the strut is a metallic strut (142), and the encapsulation (135) further comprises: a bolt (140), wherein the bolt (140) and the screw (138) fasten the metal strut (142) to the first encapsulation (92). [8] Encapsulation (135) according to any one of the preceding claims, further comprising: several first solder areas (66) bonding the first encapsulation (92) to the second encapsulation (65'), and several second solder areas (136) that bond the second encapsulation (65') to the power module (134). [9] Encapsulation (135) according to claim 8, wherein the first component die (80) is part of a die array comprising several component dies identical to the first component die (80), and the second component die (80-2, 80-3) is located in an edge region of the die array. [10] Encapsulation (135) comprising the following: a cooling plate (146), a first independent passive device encapsulation (65') and a second independent passive device encapsulation (65'), each comprising the following: an independent passive device module (120) containing multiple independent passive device dies (20), each of which comprises a passive device (22), a first molding compound (48) that forms the Independent Passive Device module (120) therein, several first rewiring lines (52) located under the first molding compound (48), wherein the several first rewiring lines (52) connect passive components (22) in the several independent passive device dies (20) as an additional passive component, and several second rewiring lines (36) on a side of the first molding compound (48) opposite the first rewiring lines (52), wherein the several first (52) and second rewiring lines (36) are electrically connected to each other, a power module (134) on the first independent passive device encapsulation (65') bonded to the first independent passive device encapsulation (65'), a further power module (134) on the second independent passive device encapsulation (65') which is bonded to the second independent passive device encapsulation (65'), an additional encapsulation (92) beneath the first independent passive device encapsulation (65') and the second independent passive device encapsulation (65'), which is bonded to the first independent passive device encapsulation (65') and to the second independent passive device encapsulation (65'), wherein the additional encapsulation (92) comprises the following: a logic computation die (80-1), a memory die (80-2) and an input-output die (80-3) above the cooling plate (146), and a second molding compound (85) that forms the logic computation die (80-1), the memory die (80-2) and the input-output die (80-3) therein, a conductor track structure (88) on the second molding compound (85), the logic computation die (80-1), the memory die (80-2) and the input-output die (80-3), several first solder areas (66) bonding the first independent passive device encapsulation (65') and the second independent passive device encapsulation (65') to the additional encapsulation (92); Through holes (130) passing through the additional encapsulation (92), a screw (138) passing through one of the through holes (130), and a strut (142) on the first independent passive device encapsulation (65') and the second independent passive device encapsulation (65'), wherein the cooling plate (146) is fastened by means of the screw (138) and the strut (142). [11] Encapsulation (135) according to claim 10, which further comprises a through-hole (42) in the first molding compound (85), wherein the through-hole (42) electrically connects the several first (52) and second rewiring lines (36) together. [12] Method comprising the following: Forming a first encapsulation (65') and a second first encapsulation (65'), each comprising the following: Encapsulation of an independent passive device die (20) and a metal post (138) in a first molding compound (48) and Forming first rewiring leads (36, 52) on opposite sides of the first molding compound (48) for connection to the independent passive device die (20) and the metal post (138), Bonding of the first encapsulation (65') to a second encapsulation (92), Bonding of the further first encapsulation (65') to the second encapsulation (92), and Bonding of power modules (134) to the first encapsulation (65') and to the further first encapsulation (65'), wherein one of the power modules (134) and the second encapsulation (92) are located on opposite sides of the first encapsulation (65') and another of the power modules (134) and the second encapsulation (92) are located on opposite sides of the further first encapsulation (65'), the second encapsulation (92) is formed as follows: Encapsulation of a first component die (80) in a second molding compound (85), Forming a conductor track structure (88) on the second molding compound (85) and the first component die (80), the bonding of the first encapsulation (65') to the second encapsulation (92) comprises: Bonding of the first encapsulation (65') to the second encapsulation (92) by means of several first plumb areas (66); the bonding of the further first encapsulation (65') to the second encapsulation (92) comprises: Bonding of the further first encapsulation (65') to the second encapsulation (92) by means of several plumb areas (66); the procedure further includes: Forming through holes passing through the second encapsulation (92); and Arranging a strut (142) and a screw (138) such that the strut (142) is arranged on the first encapsulation (65') and the further first encapsulation (65'), such that the screw (138) passes through one of the through holes (130) and such that the cooling plate (146) is fastened by means of the screw (138) and the strut (142). [13] Method according to claim 12, wherein the encapsulation of the independent passive device die (20) comprises encapsulating a first independent passive device module (120) with several identical independent passive device dies (20), wherein the several identical independent passive device dies (20) are not sawn apart. [14] Method according to claim 13, wherein the first rewiring lines (36) connect the several identical independent passive device dies together. [15] Method according to claim 13 or 14, wherein during encapsulation a second independent passive device module (120) identical to the first independent passive device module (120) is encapsulated in the first molding compound (48) and the first independent passive device module (120) is separated from the second independent passive device module (120) by the first molding compound (48). [16] Method according to claim 15, further comprising attaching a connector (148) to the second encapsulation (92), wherein both the first and the second Independent Passive Device Module (120) are located in the same continuous molding compound area when the cooling plate (146) or the connector (148) is attached. [17] Method according to any one of the preceding claims 12 to 16, wherein the Independent-Passive-Device-Die (20) comprises a single capacitor and does not contain any active or other passive components. [18] Method according to any one of claims 12 to 17, further comprising: Encapsulation of a second and a third component die (80) in the second molding compound (85) (85), wherein the first component die (80) comprises a logic computation die (80-1), the second component die (80) comprises a memory die (80-2) and the third component die (80) comprises an input-output die (80-3).

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