4CPP SRAM CELL AND ARRAY

Abstract

Static random access memory cell, SRAM cell (400), comprising: a four-contact polysilicon pitch fin field-effect transistor architecture, 4Cpp FinFET architecture, comprising a first bit cell (410) and a second bit cell (450); a first bit line (BL) and a first complementary bit line (BLB), wherein the first bit line and the first complementary bit line are shared by the first bit cell (410) and by the second bit cell (450) of the SRAM cell (400); a first word line (WL1) connected to the first bit cell (410); a second word line (WLo) connected to the second bit cell (450), wherein the first bit line (BL) comprises a first metal line (MB21) in a second metal layer (M2), and wherein the first complementary bit line (BLB) comprises a second metal line (MB11) in a first metal layer (M1).

Description

BACKGROUND ARTA conventional type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device includes an array of memory cells, or "bit cells.". In some examples, each memory cell uses six transistors connected between an upper reference potential and a lower reference potential (typically ground), such that one of two storage nodes may be occupied by the information to be stored, with the complementary information being stored at the other storage node. Each bit in the SRAM cell is stored on four of the transistors forming two cross-coupled inverters. The other two transistors are connected to the memory cell word line to control access to the memory cell during a read and write operation by selectively connecting the cell to its bit lines. The transistors of a fin field effect transistor (FinFET SRAM) cell have an active semiconductor fin structure that has source / drain (S / D) contacts connected to the fin structure on each side of a polysilicon gate structure connected to the fin. Typically, in the fabrication of a two-contacted poly pitch (2Cpp FinFET) architecture, processing steps are necessary to add certain common contacts and cut / refine the fin structure. The first metal layer (M0) of 4Cpp FinFET (Four Contacted Poly Pitch) architectures is typically overfilled and requires additional processing steps to correctly route the metal traces.US 2019 / 0259443 A1 relates to a semiconductor device having a first cell configured to be capable of holding 1-bit information and a second cell configured to be capable of holding 1-bit information and disposed adjacent to the first cell.Myung-Hee Na Na at all., "Rapid and Holistic Technology Evaluation for Exploratory DTCO in Beyond 7 nm Technologies", pages 40-44, IEEE 29 November 2018, relates to new device architectures such as horizontal nanosheets that can be considered as substitutes for FinFETs.US 2016 / 0 064 067 A1 relates to a three-port bit cell, in particular a 3-port SRAM bit cell, with an increased width, which is compatible with self-aligned double patterning (SADP) processes and can be produced using semiconductor manufacturing methods below 14 nanometers.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a block diagram illustrating an example of a memory array, in accordance with some embodiments. FIG. 1A is a circuit diagram illustrating an example of a 6T memory cell, in accordance with some embodiments. FIG. 3 is a block diagram illustrating a cross-section of an example of a semiconductor structure, in accordance with some embodiments. FIG. 4 is a block diagram illustrating an example of an interconnect metal layer structure, in accordance with some embodiments. FIG. 5 is a block diagram illustrating a cross-section of an example of an interconnect metal layer structure, in accordance with some embodiments. FIG. 6 is a block diagram illustrating a cross-section of an example of a semiconductor structure, in accordance with some embodiments. FIG. 7 is a layout diagram illustrating an example of a 4Cpp FinFET SRAM cell unit according to some embodiments. FIG. 8 is a circuit diagram illustrating an example of a 4Cpp FinFET SRAM cell unit according to some embodiments. FIG. 9 is a block diagram illustrating an example array of an array of memory cell units, in accordance with some embodiments. FIG. 10 is a block diagram illustrating another example array of an array of memory cell units, in accordance with some embodiments. FIG. 11 is a layout diagram illustrating an example of a 4Cpp FinFET SRAM cell unit according to some embodiments. FIG. 12 is an example method of forming a 4Cpp FinFET SRAM cell unit, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments, or examples, for implementing different features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or embodiments discussed.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein to facilitate discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the FIGS.. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the FIGS.. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly.A static random access memory (SRAM) device includes an array of memory cells including transistors formed using a fin field effect transistor (FinFET) architecture. For example, a polysilicon structure may be connected to a semiconductor fin extending over an isolation material. The polysilicon structure acts as the gate of the FinFET transistor such that a voltage applied to the polysilicon structure determines the flow of electrons between source / drain (S / D) contacts connected to the fin on opposite sides of the polysilicon structure. A threshold voltage of the FinFET transistor is the minimum voltage for the transistor to be considered "on" so that appreciable current can flow between the S / D contacts. The number of polysilicon structures that contact a fin along their length used in forming an SRAM cell may be considered the "pitch", often referred to as the "Contacted Poly Pitch" or Cpp, of the SRAM cell along one dimension and is at least partially indicative of the density of the SRAM cell. For example, a 4Cpp Four Contacted Poly Pitch (SRAM) cell includes two pass gate transistors, two PMOS transistors, and two NMOS transistors, all formed using multiple fins, the fins including four polysilicon structures connected to the fin along their length, and an S / D contact connected to the fin between at least some of the polysilicon structures.In fabricating typical 2Cpp FinFET SRAM architectures, a process step that requires a cut of a portion of the fins in each cell is necessary to form a 6T SRAM cell. Additionally, after forming the first set of contacts, each of the cells in the array requires an additional processing step to form certain common contacts that connect the gates of the first pair of pull-up / pull-down transistors that form the first inverter of the memory cell to the sources / drains of the second pair of transistors that form the second inverter of the memory cell to form the 6T cross-coupled cell. The shared contacts require a subsequent processing step because they connect cell components, such as fins, poly, and contacts, in the perpendicular direction from the source / drain contacts.An alternative FinFET SRAM architecture is a 4Cpp architecture that does not require a section of the fins in each cell to be cut and does not require a shared contact that requires a subsequent processing step. However, typical 4Cpp architectures result in overfilled metal layer design, for example, the bit line and the complementary bit line run in the same track and require routing guidance solutions and additional processing steps to implement those solutions in the metal layers.In some embodiments disclosed herein, a 4Cpp FinFET SRAM architecture is provided that does not require a cut of a portion of the fins in each cell, does not require shared contact, and that simplifies metal layer routing guidance is set forth. In some embodiments, a 4Cpp cell includes two 4Cpp bit cells that share a bit line and a complementary bit line.FIG. 1 is a block diagram illustrating an example of a memory array 10 in accordance with some embodiments. FIG. 1 shows a memory array 10 having a plurality of memory cells 100, or bit cells 100. One or more peripheral circuits (not shown) may be disposed at one or more regions that are peripheral with respect to or within memory array 10. The memory cell 100 and the peripheral circuits may be coupled by complementary bit lines BL and BLB, and data may be read from and written into the memory cells 100 via the complementary bit lines BL and BLB.FIG. 2 is a circuit diagram illustrating an example of a memory cell 100, in accordance with some embodiments. The memory cell 100 has a six-transistor SRAM structure (6T SRAM structure), but is not limited thereto. In some embodiments, more or less than six transistors may be used to implement memory cell 100. For example, in other embodiments, memory cell 100 may use a 4T, 8T, or 10T SRAM structure, and in other embodiments may include a memory-type bit cell or package. The memory cell 100 includes a first inverter formed by a NMOS / PMOS transistor pair PU0 and PDo, for example, pull-up 0 and pull-down 0. The memory cell 100 also includes a second inverter formed by a NMOS / PMOS transistor pair PU1 and PD1, and access transistors / pass gates PGo and PG1. The transistors PDo, PD1, PGo and PG1 have n-channel metal oxide semiconductor transistors (NMOS), and the transistors PU0 and PU1 have p-channel metal oxide semiconductor transistors (PMOS).Power is provided to each of the inverters, for example, a first terminal of each of the transistors PU 0 and PU 1 is coupled to a supply VDD, while a first terminal of each of the transistors PD 0 and PD 1 is coupled to a reference voltage VSS, for example, ground. A bit of data is stored in the memory cell 100 as a voltage level at the node Q and can be read by a circuit via the bit line BL. Access to the node Q is controlled by the pass gate transistor PG 1. Node Qbar stores the complement of the value at Q, for example, when Q is high, Qbar is low, and access to Qbar is controlled by pass gate transistor PGo.A gate of the pass gate transistor PG 1 is coupled to a word line WL. A first source / drain (S / D) terminal of the pass gate transistor PG 1 is coupled to a bit line BL, and a second S / D terminal of the pass gate transistor PG 1 is coupled to the second terminals of the transistors PU 1 and PD 1 at the node Q.Similarly, a gate of the pass gate transistor PGo is coupled to the word line WL. A first S / D terminal of the pass gate transistor PGo is coupled to a complementary bit line BLB, and a second first S / D terminal of the pass gate transistor PGo is coupled to second terminals of the transistors PU 0 and PU 1 at the node Qbar.FIG. 3 is a block diagram illustrating a cross-section of an example semiconductor structure, in accordance with some embodiments. Structure 20 is shown in the X-axis and Z-axis directions, while the Y-axis direction is perpendicular to the plane of the cross-section shown in FIG. 3. The structure 20 includes a base layer 110 and a bonding layer 120.Generally, the base layer 110 includes a semiconductor substrate, which in turn includes polysilicon regions (also referred to as "poly", for example, in this disclosure), diffusion regions, semiconductor wells (e.g., N-wells, P-wells, deep N-wells, deep P-wells), etc., forming semiconductor devices (e.g., transistors, diodes, etc.). A connection layer 120 includes N (for example, an integer of) conductive layers (for example, metal layers M 1 to MN) used for connecting devices within layers in the connection layer 120 and forming electrical connections with external devices, etc. The interconnect layer 120 generally includes vias, interlayer dielectric materials, passivation layers, bond pads, packaging resources, etc. Each metal layer (e.g., conductive layer) M in the interconnection layer 120 is commonly referred to as a metal one, a metal two, a metal three layer (M 1, M 2, M 3, etc.). Between the various metal layers M are dielectric materials (e.g., a high-k, a low-k material, etc.) 130 used to isolate the metal layers M. The base layer 110 and the connection layer 120 are often respectively called a front-end structure and a back-end structure, because they respectively represent "front-end-of-line" (FEOL) and "back-end-of-line" (BEOL) in the semiconductor manufacturing process. In some embodiments, memory or storage elements including memory cells, latches, and flip-flops are formed using the base layer 110 and one or more of the metal layers M.FIG. 4 is a block diagram illustrating an example of an interconnect metal layer structure 200 in accordance with some embodiments. The metal layer structure 200 includes a plurality of conductive layers M (M 1, M 2, M 3, etc., for example). In the illustrated embodiment, the metal layer structure 200 shows only two layers (e.g., M2 and M3), and the embodiment shown in FIG. 5 and described below shows a cross-sectional view of the metal layer structure 200 having four layers (e.g., M1, M2, M3, and M4). The number of layers illustrated in FIGS. 4 and 5 is for illustrative purposes only, and metal layer structures 200 having other numbers of layers, for example from 1 to N layers, are within the scope of the disclosed embodiments.In the embodiment illustrated in FIG. 4, each metal layer M includes a plurality of metal rods MB, for example, metal rods MB 21, MB 22, and MB 23 in the layer M 2 and metal rods MB 31, MB 32, MB 33 in the layer M 3. In some embodiments, the shape of the metal rods is cylindrical or other shape and may be any cross-sectional shape. In the illustrated embodiment, all of the metal rods MB in a layer M are substantially parallel to each other. In the illustrated embodiment, each metal layer M 2 and M 3 includes three metal rods MB, however, configurations including different numbers of metal rods MB per metal layer M are within the scope of the disclosed embodiments. In some embodiments, a first set of metal rods MB (e.g., metal rods MB in metal layers M 1, M 3, M 5, etc.) extends in a first direction (e.g., X-axis direction), while a second set of metal rods MB (e.g., in metal layers M 2, M 4, M 6, etc.) extends in a second direction (e.g., Y-axis direction), where the X-axis direction is perpendicular to the Y-axis direction. Other configurations where all of the rods MB extend in one direction, such as an X-axis direction, a Y-axis direction, or any other convenient direction, or a combination of directions, including non-perpendicular directions, are within the scope of the disclosed embodiments. In the embodiment shown in FIG. 4, each metal rod MB has a width Wbar. In some embodiments, all widths Wbarhave the same dimension, but the disclosed embodiments are not limited to such a configuration. Depending on design decisions, the widths Wbarmay have different dimensions (e.g., one width Wbarmay be shorter / longer than the other). Two adjacent metal rods MB are spaced apart or separated by a distance, for example a distance D. In some embodiments, distances D are chosen to meet the minimum requirements of the distance between two metal rods MB for forming a capacitance between those two rods. In some embodiments, all distances D in the metal layer structure 200 have the same dimension, but the disclosed embodiments are not limited to such a configuration. That is, the distances D may have different dimensions (e.g., one distance D may be shorter / longer than the other). The thickness of a metal rod MB in a layer M is proportional to the thickness of the layer M, which may be process technology dependent, and different groups of layers M may have different thicknesses. For example, a first group of metal layers M (e.g., Mx) may have a first thickness, a second group of metal layers M (e.g., My) may have a second thickness, and a third group of metal layers (e.g., Mz) may have a third thickness, etc., where the first, second, and third thicknesses are different. In the illustrated embodiment, the metal layer structure 200 has a width W and a length L.FIG. 5 is a block diagram illustrating a cross-section of an example of an interconnect metal layer structure 200 in accordance with some embodiments. In the illustrated embodiment, the metal layer structure 200 includes metal layers M 1 and M 3 including metal rods MB, for example, metal traces, wires, conductors, etc., aligned parallel to the X axis, and metal layers M 2 and M 4 including metal rods MB aligned parallel to the Y axis and perpendicular to the metal rods M 1 and M 3. In the illustrated embodiment, the metal layers M are separated by the dielectric material 130.FIG. 6 is a block diagram illustrating a cross-section of an example semiconductor structure 300 in accordance with some embodiments. The illustrated embodiment includes an FEOL layer including semiconductor structures and a BEOL layer including interconnect metal layer structures.In the illustrated embodiment, the FEOL layer includes a pass gate FinFET transistor 310. The FinFET transistor 310 includes a semiconductor substrate, a fin, an isolation region, a polysilicon structure, such as poly, the conductive contacts S and D connected to the fin, and the conductive G contact connected to the polysilicon structure. In the illustrated embodiment, the fin represents the conduction path for the current (the fin may also be referred to as the diffusion region or oxide diffusion region). The polysilicon structure acts as a gate that allows current to flow in the fin from the S contact (e.g., source) to the D contact (e.g., drain). For example, for a voltage potential between the S and D contacts, a current may flow in the fin from S to D depending on a voltage applied to the polysilicon structure. When a voltage lower than a threshold voltage is applied to the poly, no appreciable current can flow in the fin from S to D contact and transistor 310 is "off.". When a voltage greater than or equal to the threshold voltage is applied to the poly, a substantial current flows from S to D across the fin and transistor 310 is "on.". In some embodiments, the S, D, and G contacts form connections between multiple fins and polysilicon structures in the FEOL layer, thereby connecting the sources, drains, and gates of one or more transistors. In some embodiments, the sources, drains, and gates of transistor 310 are connected to a compound metal layer structure in the BEOL layer. For example, typically the gates of transistor 310 are connected to a word line, the word line being one of the metal rods in one of the layers of the interconnect metal structure in the BEOL layer, and the S / D contacts of pass gate transistors 310 are similarly connected to complementary bit lines BL and BLB, complementary bit lines BL and BLB being the other of the metal rods in one or more of the metal layers in the BEOL layer. In some embodiments, the BEOL layer serves to connect transistor 310 to peripheral circuits, for example, for read / write operations. In the illustrated embodiment, the D and G contacts are connected to the metal rods in the BEOL layer using vias. For example, Via 1 (via 1) forms a connection between the D contact with a metal bar, for example a bit line, in the first metal layer M 1 over the FEOL layer. In the illustrated embodiment, a separate via 1 connects the G contact to a landing conductive pad in the M1 layer, and via 2 connects the landing conductive pad to a metal rod, for example the word line, in the M2 layer. In some embodiments, the conductive landing pad in the M1 layer may be formed from a metal rod cut or broken in the plane of its metal layer. For example, the conductive landing pad may be formed from a metal rod, such as metal rod MB 11 shown in FIG. 5, where MB 11 has been separated or broken along its length in the X-axis direction at positions corresponding to D on each side of the MB 22 metal rod in the metal layer above it, thereby forming a conductively isolated short metal rod, or pad.FIG. 7 is a layout diagram illustrating an example of a 4Cpp FinFET SRAM cell unit 400 according to some embodiments. The 4Cpp FinFET SRAM cell unit 400 includes a first 4Cpp memory bit cell, for example, bit cell 410 and a second bit cell 450. The embodiment shown in FIG. 7 also includes metal lines in a first metal layer, for example, M 1 as shown in FIG. 5, and metal lines in a second metal layer, for example, M 2 as shown in FIG. 5. In the illustrated embodiment, each of the first bit cell 410 and the second bit cell 450 form a 6T SRAM memory cell, for example the memory cell 100 illustrated and described above in connection with FIG. 2, which includes transistors PG 0, PU 0, PD 0, PG 1, PU 1, and PD 1.In the illustrated embodiment, the first bit cell 410 includes fins 412 and 414, polysilicon structures 422, 424, 426, and 428, and S / D contacts 432, 434, and 436. The first bit cell 410 also includes vias 441- 448 connecting components of the first bit cell 410 in the FEOL layer to conductive lines or traces, such as metal rods, in the BEOL layer. In the illustrated embodiment, the fins 412 and 414 have a longer dimension (e.g., a length) along a first direction, e.g., the X-axis direction, as shown in FIG. 7, and are separated from each other in a second direction, e.g., the Y-axis direction. The polysilicon structures 422 to 428 and the S / D contacts 432 to 436 have a longer dimension (e.g., a length) along the second direction, e.g., the Y-axis direction, as shown in FIG. 7, and are separated from each other in the first direction, e.g., the X-axis direction. In some embodiments, the lengths of the fins, the poly, and the S / D contacts have lengths that are not their longest dimensions, for example, the fins, the poly, and the S / D contacts may have a square, elliptical, circular, or any other shape.In the illustrated embodiment, power is provided on the VDD lines in the first metal layer M 1 and is connected to the S / D contact 434 of both PU 0 and PU 1 of the first bit cell 410 via the via 441. S / D contact 434 connects to fin 412 adjacent but is not in contact with polysilicon structure 424. The poly 424 is also connected to the fin 412. The S / D contact 432 is connected to the fin 412 on the opposite side of the poly 424 than the S / D contact 434, for example, in the X-axis negative direction, and is adjacent to but not in contact with the poly 424. S / D contact 434, fin 412, poly 424, and S / D contact 432 form the PUo transistor with S / D contacts 434 and 432 as the sources and drains and poly 424 as the gate. The PU1 transistor is formed by the S / D contacts 434, 436 and the poly 426, all of which are connected to the fin 412, with the S / D contact 436 adjacent to but not in contact with the poly 426 and on the opposite side of the poly 426 than the S / D contact 434.In the illustrated embodiment, the S / D contacts 432 and 436 extend from the fin 412 in the second direction, for example, in the negative Y-axis direction, and are connected to the fin 414. The polysilicon structures 424 and 426 likewise extend in the second direction and are connected to the fin 414. In the illustrated embodiment, the second direction is generally perpendicular to the first direction, and the S / D contacts 432, 436 and the polys 424 and 426 repeat their placement on the fin 414 as that of the fin 412, namely the S / D contact 432, the poly 424, the poly 426, and the S / D contact 436, in the X-axis positive direction. In the illustrated embodiment, S / D contact 404 is connected to fin 414 between poly 424 and poly 426 and is connected to VSS in the M1 metal layer via 494. S / D contact 432, fin 414, poly 424, and S / D contact 404 form the PDo transistor with S / D contacts 432 and 404 as the sources and the drains and poly 424 as the gate. Similarly, along the fin 414 in the positive X-axis direction, the PD1 transistor is formed by the S / D contact 404, the poly 426, and the S / D contact 436, all of which are connected to the fin 414. In the illustrated embodiment, the PDo and PD1 transistors share the S / D contact 404 and are thereby connected to the reference voltage VSS in the M1 layer, e.g., ground. Poly 424 represents the gate for both PU0 and PDo transistors, and as such, the gates of the PU0 and PDo transistors are connected as shown in FIG. 2. Similarly, poly 426 represents the gate for both PU1 and PD1 transistors, and as such, the gates of PU1 and PD1 transistors are connected as shown in FIG. 2.In the illustrated embodiment, a poly 422 is connected to the fin 414 between the S / D contacts 432 and 402, each of which is also connected to the fin 414, thereby forming the pass gate transistor PGo. The S / D contact 402 is connected to the bit line BL in the M1 metal layer via 492, thereby connecting a source / drain terminal of the transistor PGo to the bit line BL. Similarly, poly 428 is connected to fin 414 between S / D contacts 436 and 406, each of which is also connected to fin 414, thereby forming pass gate transistor PG 1. The S / D contact 406 is connected to the complementary bit line BLB in the M1 metal layer via 496, thereby connecting a source / drain terminal of the transistor PG 1 to the complementary bit line BLB.In the illustrated embodiment, the poly 426 is connected to the S / D contact 432 by a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting the poly 426 to the conductive line in the M1 layer via via 443 and connecting the S / D contact 432 to the conductive line in the M1 layer via via 442. As such, the gates of the PU1 and PD1 transistors are connected to an S / D terminal of each of the PU0, PD0 and PGo transistors at node Q, as shown in FIG. 2. Similarly, the poly 424 is connected to the S / D contact 436 through a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting the poly 424 to the conductive line in the M1 layer via via 447 and connecting the S / D contact 436 to the conductive line in the m1 layer via via 448. As such, the gates of the PU0 and PDo transistors are connected to an S / D terminal of each of the PU1, PD1 and PG1 transistors at the complementary node Qbar, as shown in FIG. 2.In the illustrated embodiment, the poly 422 and the poly 428, for example, the gates of the PGo and PG1 transistors, are connected by a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting the poly 422 to the conductive line in the M1 layer via via 444 and connecting the poly 428 to the conductive line in the M1 layer via via 446. The conductive line in the M1 layer is connected to a conductive line in the M2 layer, for example, the word line WLo, via 445. As such, in the illustrated embodiment, both gates of the PGo and PG1 transistors are connected to the word line WL0, as shown in FIG. 2. In the illustrated embodiment, the conductive line in the first metal layer M 1 connecting the gates of PGo and PG 1 has a length dimension that is perpendicular to that of the conductive line in the second metal layer M 2, for example, the word line WLo.In the illustrated embodiment, the second bit cell 450 includes fins 452 and 454, polysilicon structures 462, 464, 466, and 468, and S / D contacts 472, 474, and 476. The first bit cell 410 also includes vias 481-488 that connect components of the second bit cell 450 in the FEOL layer to conductive lines or conductive traces, such as metal rods, in the BEOL layer. In the illustrated embodiment, the fins 452 and 454 have a longer dimension (e.g., a length) along a first direction, e.g., the X-axis direction, as shown in FIG. 7, and are separated from each other in a second direction, e.g., the Y-axis direction. The polysilicon structures 462- 468 and the S / D contacts 472- 476 have a longer dimension (e.g., a length) along the second direction, e.g., the Y-axis direction, as shown in FIG. 7, and are separated from each other in the first direction, e.g., the X-axis direction. In some embodiments, the lengths of the fins, the poly, and the S / D contacts have lengths that are not their longest dimensions, for example, the fins, the poly, and the S / D contacts may have a square, elliptical, circular, or any other shape.In the illustrated embodiment, power is provided on the VDD lines in the first metal layer M 1 and is connected to the S / D contact 474 of both PU 0 and PU 1 of the second bit cell 450 via via 481. S / D contact 474 connects to fin 452 adjacent but is not in contact with polysilicon structure 464. The poly 464 is also connected to the fin 452. The S / D contact 472 is connected to the fin 452 on the opposite side of the poly 464 as the S / D contact 474, for example, in the X-axis negative direction, and is adjacent to but not in contact with the poly 464. S / D contact 474, fin 452, poly 464, and S / D contact 472 form the PU0 transistor with S / D contacts 474 and 472 as the sources and the drains and poly 464 as the gate. The PU1 transistor is formed by the S / D contacts 474, 476 and the poly 466, all of which are connected to the fin 452, with the S / D contact 476 being adjacent to but not in contact with the poly 466 and on the opposite side of the poly 466 than the S / D contact 474.In the illustrated embodiment, the S / D contacts 472 and 476 extend from the fin 452 in the second direction, for example, in the positive Y-axis direction, and are connected to the fin 454. The polysilicon structures 464 and 466 likewise extend in the second direction and are connected to the fin 454. In the illustrated embodiment, the second direction is generally perpendicular to the first direction, and the S / D contacts 472, 476 and the polys 464 and 466 repeat their placement on the fin 454 as those of the fin 452, namely the S / D contact 472, the poly 464, the poly 466, and the S / D contact 476 in the positive X-axis direction. In the illustrated embodiment, the S / D contact 404 extends from the fin 414 in the negative Y-axis direction and is connected to the fin 454 between the poly 464 and the poly 466 and is connected to VSS in the M1 metal layer via the via 494 as described above. As such, the first bit cell 410 and the second bit cell "share" the S / D contact 404. S / D contact 472, fin 454, poly 464, and S / D contact 404 form the PD0 transistor with S / D contacts 472 and 404 as the sources and the drains and poly 464 as the gate. Similarly, along the fin 454 in the positive X-axis direction, the PD1 transistor is formed by the S / D contact 404, the poly 466, and the S / D contact 476, all of which are connected to the fin 454. In the illustrated embodiment, the PDo and PD1 transistors share the S / D contact 404 and are thereby connected to the reference voltage VSS in the M1 layer, e.g., ground. Poly 464 represents the gate for both the PUo and PDo transistors, and as such, the gates of the PU0 and PD0 transistors are connected as shown in FIG. 2. Similarly, poly 466 represents the gate for both the PU1 and PD1 transistors, and as such, the gates of the PU1 and PD1 transistors are connected as shown in FIG. 2.In the illustrated embodiment, a poly 462 is connected to the fin 454 between the S / D contacts 472 and 402, each of which is also connected to the fin 454, thereby forming the pass gate transistor PGo. In the illustrated embodiment, the S / D contact 402 extends from the fin 414 in the negative Y-axis direction and is connected to the fin 454 and is connected to the bit line BL in the M1 metal layer via 492 as described above, thereby connecting a source / drain terminal of the transistor PGo to the bit line BL. As such, the first bit cell 410 and the second bit cell "share" the S / D contact 402 and also share the bit line BL. Similarly, poly 468 is connected to fin 454 between S / D contacts 476 and 406, each of which is also connected to fin 414, thereby forming pass gate transistor PG 1. In the illustrated embodiment, the S / D contact 406 extends from the fin 414 in the negative Y-axis direction and is connected to the fin 454 and is connected to the complementary bit line BLB in the M1 metal layer via 496 as described above, thereby connecting a source / drain terminal of the transistor PG 1 to the complementary bit line BLB. As such, the first bit cell 410 and the second bit cell "share" the S / D contact 406 and also share the complementary bit line BLB.In the illustrated embodiment, the poly 464 is connected to the S / D contact 476 through a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting the poly 464 to the conductive line in the M1 layer via via 483 and connecting the S / D contact 476 to the conductive line in the M1 layer via via 482. As such, the gates of the PU0 and PDo transistors are connected to an S / D terminal of each of the PU1, PD1 and PG1 transistors at node Qbar, as shown in FIG. 2. Similarly, the poly 466 is connected to the S / D contact 472 through a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting the poly 466 to the conductive line in the M1 layer via via 487 and connecting the S / D contact 472 to the conductive line in the M1 layer via via 488. As such, the gates of the PU1 and PD1 transistors are connected to an S / D terminal of each of the PUo, PDo and PGo transistors at the complementary node Q, as shown in FIG. 2.In the illustrated embodiment, the poly 462 and the poly 468, for example, the gates of the PGo and PG1 transistors, are connected by a conductive line in the M1 layer. This connection is accomplished in the example shown by connecting poly 462 to the conductive line in the M1 layer via via 484 and connecting poly 468 to the conductive line in the M1 layer via via 486. The conductive line in the M1 layer is connected to a conductive line in the M2 layer, for example, the word line WLo, via 485. As such, in the illustrated embodiment, both gates of the PGo and PG1 transistors are connected to the word line WL1. In the illustrated embodiment, the conductive line in the first metal layer M 1 connecting the gates of PGo and PG 1 has a length dimension that is perpendicular to that of the conductive line in the second metal layer M 2, for example, the word line WL 1.As described above, in the example illustrated in FIG. 7, the S / D contacts 402, 404, and 406 are shared between the first bit cell 420 and the second bit cell 450 of the 4Cpp FinFET SRAM cell unit 400. As such, the S / D contacts 402, 404, and 404 may be considered to be part of both the first bit cell 410 and the second bit cell 450. In some embodiments, additional or subsequent processing steps are not required to form the shared S / D contacts 402, 404, and 406.In the example illustrated in FIG. 7, the bit line BL and the complementary bit line BLB are in different "lanes", for example different lines in the same metal layer M 1, thereby reducing overfilling of the BEOL metal layers. For example, in some embodiments, in terminology of the diagrams shown in FIGS. 4 and 5, the bit line BL corresponds to the metal bar MB 11 and the complementary bit line BLB corresponds to the metal bar MB 21. In some embodiments, the 4Cpp FinFET SRAM cell unit 400 does not require a fin structure or region cut. In some embodiments, the 4Cpp FinFET SRAM cell unit 400 does not require any particular shared contacts, e.g., shared contacts, that require a subsequent processing step because they connect cell components, e.g., fins, poly, and source / drain contacts, in the perpendicular direction from the source / drain contacts.FIG. 8 is a circuit diagram illustrating an example of a 4Cpp FinFET SRAM cell unit 400 according to some embodiments. The example shown in FIG. 8 generally corresponds to two of the 6T SRAM cells shown in FIG. 2 arranged to be connected to the same bit line BL and the complementary bit line BLB in a row or column of a memory array, such as memory array 10 shown in FIG. 1. In the illustrated example, the 4Cpp FinFEZ SRAM cell unit 400 includes a first bit cell 410 and a second bit cell 450. The example illustrated in FIG. 8 represents the circuit diagram of the FinFET layout structure shown in FIG. 7. In the illustrated example, the shared junction 492 connects the first bit cell 410 and the second bit cell 450 to the bit line BL, as shown in FIG. 7. Similarly, shared junction 496 connects first bit cell 410 and second bit cell 450 to complementary bit line BLB, as shown in FIG. 7.FIG. 9 is a block diagram illustrating an example array 600 of an array of memory cell units, in accordance with some embodiments. Array 600 includes nine memory cells 400 arranged in a 3x3 lattice structure. In the illustrated example, the memory cells 400 correspond to the 4Cpp FinFET SRAM cell units 400. The example shown in FIG. 9 illustrates an example of a wordline and complementary bitline arrangement of a memory array device using a 4Cpp FinFET SRAM architecture, such as the 4Cpp FinFET SRAM cell unit 400.In the illustrated embodiment, the connection of the bit cells 410 and 450 to the bit line BL is made via the via 492 connected to the shared S / D contact 402, which is a shared S / D contact of the two pass gate PGo transistors of the two bit cells 410 and 450. Similarly, the connection of the bit cells 410 and 450 to the complementary bit line BLB is made via via 496 connected to the shared S / D contact 406, which is a shared S / D contact of the two pass gate PG1 transistors of the two bit cells 410 and 450.In the illustrated example, the word line of each of the bit cells 410 in a column is shared, and the word line of each of the bit cells 450 in the column is shared. For example, each of the gates of the PGo and PG1 transistors of bit cells 410 in column C is connected to WL1, and each of the gates of the PGo and PG1 transistors of bit cells 450 in column C is connected to WLo. Similarly, in the illustrated example, bit cells 410 in column B are connected to WL3, bit cells 450 in column are connected to WL2, bit cells 410 in column A are connected to WL5, bit cells 450 in column A are connected to WL4. In the illustrated embodiment, referring to each bit cell in the column being connected to adjacent word lines in a every-second manner, the word line arrangement is a "every-second" or "even-odd" arrangement. For example, all of the bit cells 410 in column C are connected to the "odd" word line WL1, and all of the bit cells 450 in column C are connected to the "even" word line WL0. In the illustrated embodiment, bit cells 410 in columns A and B are likewise each connected to an "odd" word line WL5 and WL3, respectively, and bit cells 450 in columns A and B are likewise all each connected to an "odd" word line WL4 and WL2, respectively.FIG. 10 is a block diagram illustrating another example array 700 of an array of memory cell units, in accordance with some embodiments. The example shown in FIG. 10 represents an alternative wordline connection arrangement shown in FIG. 9.In the illustrated embodiment, referring to the first bit cell 410 of a first 4Cpp FinFET SRAM cell unit 400 being connected to the same word line as the second bit cell 450 of an adjacent 4Cpp FinFET SRAM cell unit 400 in the same column, the word line arrangement is an "odd-odd, even-even" arrangement. For example, in the illustrated embodiment, the first bit cell 410 of the cell unit 400 in row 1 and column C is connected to the same wordline WL1 as the second bit cell 450 of the cell unit 400 in row 2 and column C. The first bit cell of the cell unit 400 in row 2 and column C is connected to the same wordline WL0 as the second bit cell 450 of the cell unit 400 in row 3 and column C, and the structure repeats, wherein the wordline connection between WL0 and WL1 alternates every two bit cells, wherein the bit cells are located in adjacent cell units 400.FIG. 11 is a layout diagram illustrating an example of a 4Cpp FinFET SRAM cell unit 800 according to some embodiments. In the illustrated example, the 4Cpp FinFET SRAM cell unit 800 includes continuous poly on oxide definition edge (CPODE) 802, 804, 806, and 808 structures.In some embodiments, when a semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) is miniaturized by various technology nodes, device packaging density and device performance encounter challenges due to device layout and isolation. To avoid leakage current between adjacent devices (cells), the standard cell layout utilizes dummy polysilicon portions formed on edges of a silicon oxide definition (OD) region, e.g., a fin in a FinFET, i.e., poly-on OD edge (PODE). The PDE helps to achieve better device performance and better control of the poly profile. The fin isolation structure includes an air gap in a semiconductor fin to separate two adjacent cells and a dielectric capping layer to cap a top surface of the air gap for subsequent processes such as metal plating. The air gap has a very low dielectric constant and is an excellent electrical insulator. Since the air gap is formed within the semiconductor fin, no additional area is required to form the fin isolation structure, and therefore the device size can be reduced.In some embodiments, the PDE structures are formed on the edge of a standard cell 100 and are used to protect the ends of the semiconductor fins during processing. That is, the PODE polysilicon structures are not electrically connected as gates for MOS devices, but instead as "dummy" structures that do not have a function in the circuit. The PODE structures cover and protect the ends of the fins in the cells, thereby providing additional reliability during processing.In some embodiments, a CPODE structure or a PODE structure is used to form a trench by removing a dummy material and a portion of a semiconductor body and even a portion of an isolation feature under the dummy material. A dielectric structure is formed by filling the trench with a dielectric material, and no additional mask is required for the CPODE structure or the PODE structure. In some embodiments, the dielectric structure is formed simultaneously with the formation of other CPODE structures in other portions of the device, such as a capacitor. Forming the dielectric structures simultaneously with forming other CPODE structures helps avoid the need for additional masks and reduces manufacturing costs. By using a CPODE or a PODE structure, inter-cell coupling effects that cause noise, signal delays, logic errors and malfunctions of an integrated circuit are reduced compared to other approaches because the noise coupling path is cut off due to a non-conductive material.In some embodiments, a dual port (DP) 4Cpp FinFET SRAM cell unit may be formed. For example, the first and second bit cells 410 and 450 of the 4Cpp FinFET SRAM cell unit 400 may include two additional pass gate transistors connected to a second bit line BL- 2 and a second complementary bit line BL- 2. In some embodiments, the second set of complementary bit lines BL- 2 and BLB- 2 may be connected to other peripheral circuits, thereby connecting at least two peripheral circuits to data lines having access to the data stored in bit cells 410 and 450, and also including read-write operations. In some embodiments, dual port access to bit cells 410 and 450 enables a faster read-write speed of memory device 10. Similar to the second set of complementary bit lines, the second set of word lines may be connected to other peripheral circuits, thereby allowing at least two peripheral circuits to access data in each of the bit cells 410 and 350, and allowing at least two peripheral circuits to access read-write operations associated with the bit cells 410 and 450. In some embodiments, the dual port bit lines and connections between the first and second bit cells 410 and 450 may be shared.FIG. 12 is an example method 1000 of forming a 4Cpp FinFET SRAM cell unit, in accordance with some embodiments. The method 1000 begins at step 1002, where polysilicon structures are formed in first and second bit cells. For example, the polys 422, 424, 426, and 428 are formed in contact with two fins 412 and 414 in the first bit cell 410 and the polys 462, 464, 466, and 468 are formed in contact with two fins 452 and 454 in the second bit cell 450, as illustrated and described above with respect to FIG. 7. In some embodiments, the poly structures form the gates of FinFET transistors in a 6T SRAM bit cell having a four-contacted poly pitch (4Cpp). At step 1004, S / D contacts are formed between the polys and in contact with the fins in the first and second bit cells. For example, the S / D contacts 432, 434, and 436 are formed across and in contact with the fins 412 and 414, and are disposed between the polys 422, 424, 426, and 428, as illustrated and described above with reference to FIG. 7. Similarly, S / D contacts 472, 474, and 476 are formed across and in contact with fins 452 and 454 and are disposed between polys 462, 464, 466, and 468, as illustrated and described above with reference to FIG. 7. At step 1006, S / D contacts are formed across and in contact with the fins of the first and second bit cells and are shared by at least the pass gate transistors of the first and second bit cells. For example, the S / D contacts 402, 404, and 406 are formed across and in contact with the fins 412 and 452, where the S / D contact 402 is shared by the PGo transistors of the first and second bit cells, and the S / D contact 406 is shared by the PG1 transistors of the first and second bit cells, as illustrated and described above with reference to FIG. 7. In some embodiments, a shared S / D contact of the first and second bit cells is connected to VDD, such as shared S / D contact 404 of FIG. 7.At step 1008, the shared S / D contacts are connected to bit lines, such as the complementary bit lines BL and BLB, in a first metal layer M 1. For example, shared S / D contact 402 shared between the PGo transistors of both the first and second bit cells is connected to bit line BL as shown in FIG. 7, and shared S / D contact 406 shared between the PG1 transistors of both the first and second bit cells is connected to complementary bit line BLB as shown in FIG. 7. In some embodiments, the S / D contacts of the pull-up transistors PU 0 and PU 1 of the first and second bit cells are connected to VDD, and the S / D contacts of the pull-down transistors PD 0 and PD 1 of the first and second bit cells are connected to VSS at this step. For example, S / D contacts 434 and 474 are connected to a VDD line in the M1 layer via vias 441 and 481, and S / D contact 404 is connected to a VSS line in the M1 layer via via 494, as previously shown in FIG. 7. In some embodiments, the bitlines BL and BLB, VDD and VSS are in the M1 layer, and in other embodiments, the bitlines BL and BLB, VDD and VSS may be in any other layer or a combination thereof, and may be connected to the respective S / D contacts using vias and landing pads in other metal layers, as illustrated and described above with reference to FIG. 6.At step 1010, the gates of the pass gate transistors of the first bit cell are connected to a first word line. For example, the gates of PGo and PG1, e.g., polys 422 and 428, respectively, are connected to WL0, as illustrated and described above with reference to FIG. 7. At step 1012, the gates of the pass gate transistors of the second bit cell are connected to a second word line. For example, the gates of PGo and PG1, e.g., polys 462 and 468, respectively, are connected to WL1 as illustrated and described above with reference to FIG. 7.In some embodiments, the word lines, for example, WL 0 and WL 1, are located in the second metal layer M 2. In other embodiments, the word lines may be in any other layer or combination thereof and are connected to the respective gates or gate contacts using vias and landing pads in other metal layers, as illustrated and described above with reference to FIG. 6.By forming a 4Cpp FinFET SRAM cell unit and a memory device 10 including 4Cpp FinFET SRAM cell units, the complexity and cost of processing and manufacturing an SRAM device is reduced. Forming a 4Cpp FinFET SRAM cell unit eliminates the need for slicing the OD into bit cells and associated processing steps, forming shared contacts and associated processing steps, and reduces overfilling in the metal layers, e.g., the metal layers of the bit lines.Thus, disclosed embodiments include a static random access memory (SRAM) cell having a 4Cpp Fin Field Effect Transistor (FinFET) architecture (Four Contacted Polysilicon Pitch) including a first bit cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell and a second word line connected to the second bit cell.According to other disclosed embodiments, a method of forming a static random access memory (SRAM) cell includes forming a 4Cpp Fin Field Effect Transistor (FinFET) architecture (Four Contacted Polysilicon Pitch) that includes a first bit cell and a second bit cell. The method includes connecting a first bit line to each of the first and second bit cells, and connecting a first complementary bit line to each of the first and second bit cells. The method further includes connecting a first word line to the first bit cell, and connecting a second word line to the second bit cell.According to still further disclosed embodiments, a memory array includes a plurality of memory cells arranged in a plurality of rows and columns, each of the plurality of memory cells including a 4Cpp field effect transistor (FinFET) architecture including a first bit cell and a second bit cell. The memory array includes a plurality of complementary bit line pairs, each of the first and second bit cells sharing a first complementary bit line pair with each of the plurality of memory cells in the first row of the memory array, and each of the first and second bit cells sharing a second complementary bit line pair with each of the plurality of memory cells in a second row of the memory array.

Claims

A static random access memory, SRAM, cell (400) comprising: a four contact polysilicon pitch fin field effect transistor, 4Cpp, FinFET, architecture comprising a first bit cell (410) and a second bit cell (450); a first bit line (BL) and a first complementary bit line (BLB), wherein the first bit line and the first complementary bit line are shared between the first bit cell (410) and the second bit cell (450) of the SRAM cell (400); a first word line (WL1) connected to the first bit cell (410); a second word line (WLo) connected to the second bit cell (450), wherein the first bit line (BL) includes a first metal line (MB21) in a second metal layer (M2), and wherein the first complementary bit line (BLB) includes a second metal line (MB11) in a first metal layer (M1).The SRAM cell of claim 1, wherein the first bit cell (410) comprises: - a first polysilicon structure (422), a second polysilicon structure (428), a third polysilicon structure (424), and a fourth polysilicon structure (426), the first word line (WL1) being connected to the first polysilicon structure (422) and the second polysilicon structure (428); - a first pass gate transistor (PGo) comprising a gate comprising the first polysilicon structure (422) and a source / drain contact (432) connected to the first bit line (BL); and a second pass gate transistor (PG1) comprising a gate comprising the second polysilicon structure (428) and an S / D contact (436) connected to the first complementary bit line (BLB), and wherein the second bit cell (450) comprises: a first polysilicon structure (462), a second polysilicon structure (468), a third polysilicon structure (464), and a fourth polysilicon structure (466), wherein the second word line (WLo) is connected to the first polysilicon structure (462) and the second polysilicon structure (468); a first pass gate transistor (PGo) having a gate formed by the first polysilicon structure (462) and a source contact (472) connected to the first bit line (BL); and a second pass gate transistor (PG1) having a gate formed by the second polysilicon structure (468) and a source contact (406) connected to the first complementary bit line (BLB).The SRAM cell of claim 2, wherein the first bit cell (410) further comprises: a first inverter comprising a first transistor (PUo) and a second transistor (PDo), each of which comprises a gate comprising the third polysilicon structure (424) and an S / D contact (432) connected to an S / D contact (432) of the first pass gate transistor (PGo); and a second inverter including a third transistor (PU1) and a fourth transistor (PD1), each of which includes a gate including the fourth polysilicon structure (426) and an S / D contact connected to an S / D contact (436) of the second pass gate transistor (PG1), and wherein the second bit cell (450) further includes: a first inverter including a first transistor (PUo) and a second transistor (PDo), each of which includes a gate including the third polysilicon structure (464) and an S / D contact (472) connected to an S / D contact of the first pass gate transistor (PGo); and a second inverter including a third transistor (PU1) and a fourth transistor (PD1), each of which includes a gate including the fourth polysilicon structure (466) and an S / D contact (476) connected to an S / D contact of the second pass gate transistor (PG1).The SRAM cell according to any one of claims 1 to 3, wherein the first word line (WL1) includes a first metal line (MB22) in the second metal layer (M2), and wherein the second word line (WLo) includes a second metal line (MB23) in the second metal layer (M2).The SRAM cell of claim 4, wherein the first bit cell (410) further comprises a first contact (444) in the first metal layer (M1), wherein the first polysilicon structure (422) and the second polysilicon structure (428) of the first bit cell are connected to the first contact (444), and the first contact (444) is connected to the first metal line (MB22) of the first word line (WL1) in the second metal layer (M2), and wherein the second bit cell (450) further comprises a second contact (484) in the first metal layer (M1), wherein the first polysilicon structure (462) and the second polysilicon structure (468) of the second bit cell (150) are connected to the second contact (484), and the second contact (484) is connected to the second metal line (MB23) of the second word line (WL0) in the second metal layer (M2).The SRAM cell of any of claims 3 to 5, wherein the respective first polysilicon structure (422, 462) and the respective second polysilicon structure (428, 468) of the first bit cell (410) and the second bit cell (450) each comprise a continuous poly on diffusion edge, CPODE, structure (802, 804, 806, 808).The SRAM cell of any one of claims 3 to 6, further comprising: a second bit line (BL[1]) and a second complementary bit line (BLb[1]), wherein the second bit line and the second complementary bit line are shared by the first and second bit cells (410, 450) of the SRAM cell; a third word line (WL:even) connected to the first bit cell (410); and a fourth word line (WL:odd) connected to the second bit cell (450).A method of forming an SRAM cell (400), comprising: forming a 4Cpp FinFET architecture having a first bit cell (410) and a second bit cell (450); connecting a first bit line (BL) to the first bit cell (410) and the second bit cell (450); connecting a first complementary bit line (BLB) to the first bit cell (410) and the second bit cell (450); connecting a first word line (WL1) to the first bit cell (410); connecting a second word line (WLo) to the second bit cell (450), and wherein the first bit line (BL) comprises a first metal line (MB21) in a second metal layer (M2), and wherein the first complementary bit line (BLB) comprises a second metal line (MB11) in a first metal layer (M1).The method of claim 8, wherein forming the first bit cell (410) comprises: forming a first polysilicon structure (422), a second polysilicon structure (428), a third polysilicon structure (424), and a fourth polysilicon structure (426) in the first bit cell (410); forming a first pass gate transistor (PGo) comprising a gate comprising the first polysilicon structure (422); and forming a second pass gate transistor (PG1) comprising a gate comprising the second polysilicon structure (428), and wherein forming the second bit cell (450) comprises: forming a first polysilicon structure (462), a second polysilicon structure (468), a third polysilicon structure (464), and a fourth polysilicon structure (466) in the first bit cell; forming a first pass gate transistor (PGo) having a gate comprising the first polysilicon structure (462); and forming a second pass gate transistor (PG1) having a gate comprising the second polysilicon structure (468).The method of claim 9, wherein connecting the first bit line (BL) to the first bit cell (410) and the second bit cell (450) further comprises connecting the respective first polysilicon structure (422, 462) of the first bit cell (410) and the second bit cell (450) to the first bit line (BL), and wherein connecting the first complementary bit line (BLB) to the first bit cell (410) and the second bit cell (450) further comprises connecting the respective second polysilicon structure (428, 468) of the first bit cell (410) and the second bit cell (450) to the first complementary bit line (BLB).The method of claim 10, wherein forming the first bit cell (410) further comprises: forming a first inverter having a first transistor (PUo) and a second transistor (PDo), each having a gate including the third polysilicon structure (424), and an S / D contact connected to an S / D contact (432) of the first pass gate transistor (PGo); and forming a second inverter having a third transistor (PU1) and a fourth transistor (PD1), each having a gate including the fourth polysilicon structure (426) and an S / D contact, which is connected to an S / D contact (436) of the second pass gate transistor (PG1), and wherein forming the second bit cell (450) further comprises: forming a first inverter comprising a first transistor (PUo) and a second transistor (PDo), each comprising a gate comprising the third polysilicon structure (464) and an S / D contact (472) connected to an S / D contact of the first pass gate transistor (PGo); and forming a second inverter comprising third and fourth transistors (PU1, PD1), each comprising a gate comprising the fourth polysilicon structure (466) and an S / D contact (476) connected to an S / D contact of the second pass gate transistor (PG1).The method of claim 11, wherein the first word line (WL1) comprises a first metal line (MB22) in a second metal layer (M2), and wherein the second word line (WLo) comprises a second metal line (MB23) in the second metal layer (M2).The method of claim 12, wherein connecting the first word line (WL1) to the first bit cell (410) further comprises: forming a first contact (444) in the first metal layer (M1); connecting the first polysilicon structure (422) and the second polysilicon structure (428) of the first bit cell (410) to the first contact; and connecting the first contact (444) to the first metal line (MB22) of the first word line (WL1) in the second metal layer (M2), wherein connecting the second word line (WLo) to the second bit cell (450) further comprises: forming a second contact in the first metal layer (M1); connecting the first polysilicon structure (462) and the second polysilicon structure (468) of the second bit cell (450) to the second contact (484); and connecting the second contact (484) to the second metal line (MB23) of the second word line (WL0) in the second metal layer (M2).The method of any of claims 10 to 13, wherein the respective first polysilicon structure (422, 462) and the respective second polysilicon structure (428, 468) of the first bit cell (410) and the second bit cell (450) each comprise a CPODE structure (802, 804, 806, 808).The method of claim 14, further comprising: connecting a second bit line (BL[1]) to the first bit cell (410) and the second bit cell (450); connecting a second complementary bit line (BLB[1]) to the first bit cell (410) and the second bit cell (450); connecting a third word line (WL:odd) to the first bit cell (410); and connecting a fourth word line (WL:even) to the second bit cell (450).A memory array (600) comprising: a plurality of memory cells (400) of any of claims 1 to 7 arranged in a plurality of rows and columns, each of the plurality of memory cells (400) having a 4Cpp FinFET architecture comprising a first bit cell (410) and a second bit cell (450), a plurality of complementary bit line pairs (BL, BLB), wherein the first bit cell (410) and the second bit cell (450) of each of the plurality of memory cells (400) in a first row of the memory array shares a first complementary bit line pair (BLB), and the first bit cell (410) and the second bit cell (450) of each of the plurality of memory cells in a second row of the memory array shares a second complementary bit line pair (BLB).The memory array of claim 16, further comprising: a plurality of word lines (WL), wherein each of the first bit cells (410) of each of the plurality of memory cells (400) in a first column of the memory array shares a first word line, and each of the second bit cells (450) of each of the plurality of memory cells (400) in the first column of the memory array shares a second word line, and wherein each of the first bit cells (410) of each of the plurality of memory cells (400) in a second column of the memory array shares a third word line, and each of the second bit cells (450) of each of the plurality of memory cells (400) in the second column of the memory array shares a fourth word line.The memory array of claim 16 or 17, further comprising: a plurality of word lines, wherein each of the first bit cells (410) of each of the plurality of memory cells (400) in a first row of the memory array shares a first word line with the second bit cells (450) of each of the plurality of memory cells in an adjacent second row, and each of the second bit cells (450) of each of the plurality of memory cells in the first row of the memory array shares a second word line with the first bit cells (410) of each of the plurality of memory cells (400) in the adjacent second row.

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