Semiconductor structure with source and drain epitaxic layers and method for their manufacture

Abstract

Semiconductor structure with: a fin (110, 210) arranged on a substrate (140), wherein the fin (110, 210) and the substrate (140) comprise a semiconductor material; a gate structure (100, 200) arranged on the fin (110, 210), wherein the gate structure (100, 200) encloses part of a side wall surface of the fin (110, 210); a recess (700) which is created in a part of the fin adjacent to the gate structure (100, 200); a source / drain epiaxial stack (230) arranged in the recess (700) and comprising the following: a lower layer (230B), and an upper layer (400) that has a higher activated dopant concentration than the lower layer (230B); and a contact (930, 950) that is arranged on the upper layer (400) of the source / drain epiaxial stack (230), wherein the contact (930, 950) is arranged adjacent to the gate structure (100, 200), where the upper layer (400) has a dopant activation rate of about 100% and the lower layer (230B) has a dopant activation rate of about 10%.

Description

background

[0001] Dopants in a semiconductor material can only act as donors or acceptors if they are part of the semiconductor's lattice structure. For this reason, dopants in a semiconductor material (e.g., silicon) must be activated. An activated dopant can act as either a donor or an acceptor of electrons; that is, it can behave like an n- or p-dopant with respect to the semiconductor material. If the dopant occupies an interstitial site in the semiconductor material, it is not considered activated and is ineffective as a dopant (i.e., it cannot act as a donor or an acceptor). Heat energy can be supplied to a doped semiconductor material to move the dopants from an interstitial site to crystal sites—a process known as "activation" or "crystal activation."

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2018 / 0 166575 A1, US 2017 / 0 213 739 A1, DE 10 2015 100 860 A1, in MO Thompson et al.: “Melting Temperature and Explosive Crystallization of Amorphous Silicon during Pulsed Laser Irradiation”, Physical Review Letters, Vol. 52, No. 26, 25.06.1984 and in Wolf, S., RNTauber: “Silicon Processing in the VLSI era”, Volume I, 2nd edition, Sunset Beach: Lattice press, 2000, page 395, ISBN 0-9616721-6-1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. Brief description of the drawings

[0004] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a partial sectional view of an exemplary matrix of transistor structures fabricated on fins and having single-crystal source / drain stacks, during a laser annealing process according to some embodiments. Fig. Figure 2 is a partial sectional view of a transistor structure having source / drain epiaxial stacks with an amorphous low-melting-point upper layer and a single-crystal high-melting-point lower layer, during a laser annealing process according to some embodiments. Fig. 3 is a SIMS profile (SIMS: Secondary Ion Mass Spectroscopy) superimposed after a laser annealing process with a spreading resistance profile (SRP) for a source / drain epiaxial stack comprising an upper layer with a low melting point and a lower layer with a high melting point, according to some embodiments. Fig. Figure 4 is a sectional view of a transistor structure comprising source / drain epiaxial stacks with a laser-tempered single-crystal top layer and a single-crystal bottom layer, according to some embodiments. Fig. Figure 5 is a flowchart of a method for producing a source / drain epiaxial stack comprising a low melting point upper layer and a high melting point lower layer, according to some embodiments. Fig. Figure 6 shows partial sectional views of a transistor structure along an x- and a y-direction, according to some embodiments. Fig. Figure 7 shows partial sectional views of recessed fin parts of a transistor structure along the x and y directions, according to some embodiments. Fig. Figure 8 shows partial sectional views of a transistor structure after the fabrication of source / drain epiaxial stacks comprising a low melting point upper layer and a high melting point lower layer, on recessed portions of a fin along the x and y directions, according to some embodiments. Fig. Figure 9 shows partial sectional views of a transistor structure after the fabrication of contacts on source / drain epiaxial stacks comprising a low melting point upper layer and a high melting point lower layer, along the x and y directions, according to some embodiments. Fig. Figure 10 shows partial sectional views of a transistor structure along the x and y directions, according to some embodiments. Fig. Figure 11 shows partial sectional views of recessed fin parts of a transistor structure along the x and y directions, according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements such that the first and second elements are not in direct contact.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] The term "nominal" as used here refers to a desired or target value of a property or parameter for a component or process step, which is defined during the design phase for a product or process, along with a range of values ​​above and / or below the target value. This range of values ​​typically results from minor variations in manufacturing processes or tolerances.

[0008] In some embodiments, the terms "approximately" and "essentially" can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). In some embodiments, the terms "approximately" and "essentially" can indicate other values ​​based on features provided, for example, by a manufacturing process, a manufacturing step, or a manufacturing plant.

[0009] The term "vertical" used here nominally means perpendicular to the surface of a substrate.

[0010] Diffusion is a fundamental property that describes the movement of one material (e.g., a dopant) through another material (e.g., a semiconductor substrate). Diffusion occurs from regions with a relatively high doping concentration to regions with a low doping concentration. Different dopant species can have different diffusivity rates in a semiconductor substrate such as silicon (Si), silicon germanium (SiGe), silicon carbon (SiC), or silicon phosphorus (SiP), and the higher the diffusivity, the faster the dopant moves into the semiconductor substrate. Since the diffusion rate of dopant species in a semiconductor substrate increases with temperature, thermal diffusion is the most important mechanism used in semiconductor manufacturing to move dopant species through the semiconductor lattice.There are two basic methods for providing heat energy for the diffusion of dopants: furnace annealing and rapid thermal annealing (RTA).

[0011] Oven annealing is a process for annealing the semiconductor substrate (e.g., a semiconductor wafer) in a hot-walled oven at temperatures of approximately 800 °C to 910 °C for about 30 minutes. However, annealing cycles of this duration and temperature can lead to extensive (i.e., uncontrolled) dopant diffusion, which is unsuitable for some integrated circuit (IC) manufacturing processes (e.g., source / drain activation). Furthermore, oven annealing applies heat globally, not locally. This means that every layer and / or structure present on the semiconductor material at the time of annealing is exposed to the elevated temperatures for the duration of the process. This can pose limitations for IC manufacturing.

[0012] In an RTA process, the semiconductor material is annealed using a rapid heat rise, e.g., in the millisecond or nanosecond range, and a short residence time, e.g., in the seconds or subsecond range, at a target temperature, e.g., of approximately 910 °C or higher. Furthermore, the RTA process can be selective, providing heat locally or globally. There are two types of RTA: thermal annealing with lamps (e.g., tungsten halogen lamps) or with a laser (e.g., for laser annealing). Lamp-based RTA can be global annealing because the semiconductor surfaces (e.g., the top, the bottom, or both) are irradiated simultaneously by the lamps. In contrast, laser annealing, due to its beam size (e.g., approximately 25 mm), offers more precise control. 2 up to about 100 mm 2) and its precise energy output enable high positional accuracy and high heat transfer precision. Because of these properties, laser annealing is a preferred method for source / drain dopant activation in IC manufacturing.

[0013] As an example, and not limited to this, a pulsed laser beam scans the semiconductor surface (e.g., the surface of the semiconductor wafer) at a rate of approximately 100 mm / s during a laser annealing process. Due to the laser beam size (e.g., approximately 25 mm) 2 up to about 100 mm 2 Locally limited annealing can be achieved. The annealing depth can be controlled by process parameters such as laser energy or wavelength, number of pulses per spot, and residence time of the laser beam (i.e., the time the laser spends at each spot).

[0014] However, dopant activation for source / drain epitaxial layers can be challenging even with a laser annealing process. This is because the source / drain regions of a transistor are small compared to the size of the laser beam. This problem is further exacerbated by the decreasing size of transistors and their source / drain regions with each technology generation (e.g., with each technology node). For example, as the source / drain regions become smaller, heat from the laser beam can spread to areas outside the source / drain regions, such as the fin region located between the source and drain regions of the transistor. This can be described with reference to Fig. 1, which is a partial sectional view along the x-axis of an exemplary matrix of transistor structures 100 fabricated on fins 110, comprising single-crystal source / drain stacks 120 and channel regions 130.The fins 110 are arranged on a substrate 140. When a laser beam 150 begins to scan the surface of the substrate 140, the heat generated by the laser beam 150 creates a melt front 160 that extends outside the single-crystal source / drain stack 120 (e.g., up to the fins 110 and the channel region 130). This can cause the fin 110 to deform, which impairs the electrical properties of the transistor. To reduce fin deformation, the laser annealing conditions must be modified to decrease the heat generated by the laser beam and better control the melt front 160. However, reducing the heat generated by the laser beam can affect the dopant activation process in the single-crystal source / drain stack 120. For example, this change may result in fewer dopants being activated.

[0015] To address these problems, the embodiments described here are designed to produce source / drain stacks with a low-melting-point "upper" layer and a high-melting-point "lower" layer. In some embodiments, the low-melting-point upper layer is polycrystalline or amorphous in the deposition state, and the high-melting-point lower layer is monocrystalline in the deposition state. In other embodiments, both the low-melting-point upper layer and the high-melting-point lower layer are monocrystalline or polycrystalline in the deposition state, but they have different stoichiometries. In some embodiments, the amorphous low-melting-point upper layer recrystallizes during the laser annealing process and exhibits a higher defect density than the high-melting-point lower layer.Furthermore, the upper layer with a low melting point exhibits a higher concentration of activated dopants than the lower layer with a high melting point after the laser annealing process. In some embodiments, only the dopants in the upper layer with a low melting point are activated during the laser annealing process. In some embodiments, a laser beam with reduced power can be used for the source / drain epiaxial stacks disclosed herein. This prevents fin deformation during the laser annealing process.

[0016] Fig. Figure 2 is a sectional view of an exemplary transistor structure 200 fabricated on semiconductor fins 210, along the x-axis. It should be noted that the length of the fin is parallel to the one shown in Figure 2. Fig. The semiconductor fin 210 is arranged on a semiconductor substrate 220 and is recessed to facilitate the fabrication of source / drain epitaxial stacks 230. The semiconductor fin 210 is laterally separated from other transistor structures by an insulating layer 240. In some embodiments, each source / drain epitaxial stack 230 comprises a low-melting-point amorphous upper layer 230A and a high-melting-point monocrystalline lower layer 230B. Here, an “upper” layer refers to a layer located farther away from a semiconductor substrate 220 along the z-axis, and a “lower” layer refers to a layer located closer to the semiconductor substrate 220 along the z-axis. Furthermore, the term “amorphous” as used here also includes a polycrystalline microstructure (e.g., a microstructure with a short-range lattice periodicity).

[0017] In some embodiments, the dopants and the semiconductor substrate material contained in the source / drain epitaxial stack 230 can be selected based on the type of transistor structure 200, for example, depending on whether the transistor structure 200 is an n-type field-effect transistor (nFET) or a p-type field-effect transistor (pFET). In some embodiments, the source / drain epitaxial stack of an nFET (i.e., an n-source / drain epitaxial stack) comprises strained silicon-carbon (SiC) or strained silicon-phosphorus (SiP) layers, each doped with phosphorus, and a source / drain epitaxial stack of a pFET (i.e., a p-source / drain epitaxial stack) comprises strained silicon-germanium (SiGe) layers doped with boron (B). In some embodiments, the amount of P introduced into an n-source / drain epiaxial stack can be up to about 1 × 10 21 atoms / cm² -3the amount of B introduced into a p-source / drain epiaxial stack can also be up to about 1 × 10 21 atoms / cm² -3 The concentrations of phosphorus and boron dopants can be varied. By way of example, and without limitation, phosphorus and boron dopants can be introduced into the source / drain epiaxial stacks 230 during growth using suitable precursors. Furthermore, the upper layer 230A with a low melting point and the lower layer 230B with a high melting point can be grown such that they have a substantially equal phosphorus or boron concentration.

[0018] In some embodiments, the amorphous upper layer 230A, which has a low melting point in the deposition state, has a melting point of about 1420 K (about 1147 °C), and the single-crystal lower layer 230B, which has a high melting point in the deposition state, has a melting point higher than about 1687 K (about 1414 °C). Both layers, however, consist of the same material and have substantially the same stoichiometry, e.g., a substantially equal Si / Ge ratio for a SiGe source / drain epitaxial stack, a substantially equal Si / C ratio for a SiC source / drain epitaxial stack, or a substantially equal Si / P ratio for a SiP source / drain epitaxial stack. In some embodiments, the melting point difference between the upper and lower layers in the source / drain epitaxial stacks 230 is due to their microstructure (e.g. amorphous as opposed to single-crystal).In this example, the high-melting-point, single-crystal lower layer 230B has a higher melting point (e.g., a difference of approximately 267 K or 267 °C) than the low-melting-point, amorphous upper layer 230A. However, this is not a limiting factor, and a smaller melting point difference, e.g., greater than approximately 200 K, between the low-melting-point and high-melting-point layers can be used. A melting point difference greater than the threshold of approximately 200 K (e.g., 267 K) ensures that a melt front is selectively generated in and contained within the low-melting-point, amorphous upper layer 230A by the laser beam during a laser annealing process, while the high-melting-point, single-crystal lower layer 230B remains a solid.If the melting point difference between the aforementioned layers is equal to or less than approximately 200 K, the melt front generated by the laser beam can extend beyond the boundaries of the low-melting-point amorphous lower layer 230A, for example, into the high-melting-point lower layer 230B and the fin region. As explained above, this is undesirable. Therefore, the aforementioned selectivity can be achieved as long as the heat generated by the laser beam during the laser annealing process raises the temperature of the source / drain epitaxial stack 230 above the melting point of the low-melting-point amorphous upper layer 230A and below the melting point of the high-melting-point single-crystal lower layer 230B.In some embodiments, the temperature of the source / drain epiaxial stack 230 during the laser annealing process is equal to or higher than the melting point of the low-melting-point amorphous upper layer 230A and equal to or lower than the melting point of the high-melting-point single-crystal lower layer 230B (e.g., melting point temperature of the low-melting-point amorphous upper layer ≤ temperature of the laser annealing process ≤ melting point temperature of the high-melting-point single-crystal lower layer). Within this process window, a molten region such as the one shown in [reference missing] can be formed. Fig. The melt front 160 shown in Figure 1 is formed within the boundaries of the low-melting-point amorphous upper layer 230A. In some embodiments, the melting point of the low-melting-point amorphous upper layer 230A is also lower than the melting point of surrounding materials such as the semiconductor fin 210, which in the case of crystalline silicon can be approximately 1687 K (e.g., closer to the melting point of the high-melting-point single-crystal lower layer 230B). Therefore, deformation of the semiconductor fin 210 during the laser annealing process can be minimized or avoided.

[0019] Since the formation of a melt front in the low-melting-point amorphous upper layer 230A requires less heat, e.g., due to the amorphous layer's low melting point, the laser beam power can be reduced. For example, if a source / drain epitaxial stack contains only single-crystal layers such as the high-melting-point single-crystal lower layer 230B, the laser beam would need to operate at approximately 910 J to generate a melt front and activate the dopants (e.g., B or P). At this power level, the laser beam would also generate enough heat to deform the semiconductor fin 210, which has a substantially comparable melting point to the single-crystal layers of the source / drain epitaxial stack.In contrast, in a source / drain epitaxial stack 230 comprising a low-melting-point amorphous upper layer 230A in the deposition state and a single-crystal lower layer 230B, the laser beam would need to generate less heat and consequently operate at a lower power setting, e.g. 500 J, which in some embodiments represents a reduction of about 50%.

[0020] In some embodiments, the low-melting-point amorphous upper layer 230A is grown to constitute approximately 30% to approximately 75% of the total thickness of the source / drain epitaxial stack 230. In other words, a thickness T1 of the deposited low-melting-point amorphous upper layer 230A can be approximately 30% to approximately 75% of the total thickness T of the source / drain epitaxial stack 230 (i.e., 30% T ≤ T1 ≤ 75% T or 0.30 ≤ T1 / T ≤ 0.75), as shown in Fig. Figure 2 shows that in some embodiments, the high-melting-point, single-crystal lower layer 230B acts as a diffusion barrier for the dopants of the low-melting-point, amorphous upper layer 230A during a laser annealing process. This is because no melt front is generated in the high-melting-point, single-crystal lower layer 230B, and therefore the dopants diffusing from the low-melting-point, amorphous upper layer 230A into the high-melting-point, single-crystal lower layer 230B are slowed down (i.e., blocked). If the thickness T1 of the low-melting-point amorphous upper layer 230A is greater than about 75% of the total thickness T of the source / drain epiaxial stack 230 (i.e., T1 / T > 0.75), the high-melting-point single-crystal lower layer 230B is not thick enough to block the diffusion of dopants from the low-melting-point amorphous upper layer 230A.This results in fewer dopants being activated in the low-melting-point amorphous top layer 230A, which in turn can increase the resistance of the source / drain epiaxial stack 230. Furthermore, dopant diffusion can create undesirable creepage paths between the source / drain epiaxial stack 230 and doped regions of the semiconductor fin 210 and / or the semiconductor substrate 220. Additionally, a thicker low-melting-point amorphous top layer 230A may require a longer residence time and / or a higher power setting for the laser beam during a laser annealing process, both of which can negatively impact processing time and costs. Conversely, if the thickness T1 of the low-melting-point amorphous top layer 230A is less than approximately 30% of the total thickness T (i.e.,If , T1 / T > 30%), the amount of dopants activated in the upper layer may be insufficient to provide an acceptable resistance for the source / drain epiaxial stack 230.

[0021] In some embodiments, the microstructure, and consequently the melting point, of the amorphous upper layer 230A with a low melting point and the single-crystal lower layer 230B with a high melting point in the deposition state can be adapted via their respective growth conditions, such as growth temperature and pressure. For example, in some embodiments, the single-crystal lower layer 230B with a high melting point can be grown at a temperature of about 650 °C to about 800 °C and a pressure of about 2.666 to about 39.997 kPascal. In contrast, the amorphous upper layer 230A with a low melting point can be grown at a temperature of about 450 °C to about 600 °C and a pressure of about 39.997 to about 53.329 kPascal.In other words, a single-crystal layer can be grown at a "higher" temperature and a "lower" pressure than an amorphous epitaxial layer, which can be grown at a "lower" temperature and a "higher" pressure. In some embodiments, the aforementioned conditions can also be used for growing p-source / drain epitaxial layers (e.g., B-doped SiGe) and n-source / drain epitaxial layers (e.g., P-doped SiC and SiP).

[0022] In some embodiments, the high-melting-point, single-crystal lower layer 230B and the low-melting-point, amorphous upper layer 230A are grown in situ in the same processing reactor (i.e., without vacuum interruption). For example, by using heating lamps, rapid processing temperature changes (e.g., within 10 s to about 20 s) can be achieved. In some embodiments, the high-melting-point, single-crystal lower layer 230B and the low-melting-point, amorphous upper layer 230A are grown by chemical vapor deposition (CVD).

[0023] In some embodiments, the low-melting-point amorphous upper layer 230A can be produced using a PAI process (PAI: pre-amorphization implantation). For example, the source / drain epitaxial stack 230 may initially comprise only a single-crystal layer, e.g., the one described in Fig. Figure 1 shows a high-melting-point, single-crystal lower layer of 230B with a total thickness T. A PAI process, in which implantations are used, consumes a portion of the single-crystal layer and transforms it into an amorphous layer by bombardment with implantation ions. The type and extent of the implantations and the implantation energy are parameters that can be used to fine-tune the thickness of the amorphous layer.

[0024] In some embodiments, Ge or Tin (Sn) implantable materials can be used for SiGe source / drain epiaxial stacks, and Si implantable materials can be used for SiC or SiP source / drain epiaxial stacks. By way of example and without limitation, a Ge or Sn dose of approximately 1 × 10 14 cm -2 up to about 5 × 10 14 cm -2At an accelerating voltage of approximately 3 keV to approximately 20 keV, it can be used to produce an amorphous upper layer 230A with a low melting point and a thickness of T1. A silicon dose of approximately 1 × 10 15 cm -2 up to about 5 × 10 15 cm -2 At an accelerating voltage of approximately 1 keV to approximately 5 keV, a low-melting-point amorphous top layer 230A with a thickness of T1 can be used. In some embodiments, the low-melting-point amorphous top layer 230A and the high-melting-point single-crystal bottom layer 230B can have different Si / Ge and Si / C or Si / P ratios when a PAI process is used to produce the low-melting-point amorphous top layer 230A.

[0025] After the fabrication of the low-melting-point amorphous upper layer 230A, the source / drain epiaxial stacks 230 are subjected to a laser annealing process, e.g., using a scanning laser beam 250, to activate the dopants in the low-melting-point amorphous upper layer 230A. As explained above, the low-melting-point amorphous upper layer 230A has a lower melting point (e.g., lower than about 200 K) than the high-melting-point monocrystalline lower layer 230B. Furthermore, the power of the laser beam 250 can be adjusted based on the melting point difference between the two layers such that a melt front is selectively generated on the low-melting-point amorphous upper layer 230A, while the monocrystalline lower layer remains solid. In some embodiments, the laser beam 250 has a wavelength of approximately 308 nm to approximately 532 nm and an annealing depth (which is e.g.(measured from a top surface of the amorphous upper layer 230A with a low melting point) from about 7 nm to about 1200 nm. In some embodiments, the annealing depth corresponds to the thickness T1 of the upper amorphous layer 230A. As explained above, the laser beam 250 covers an area of ​​about 25 mm². 2 up to about 100 mm 2 (e.g. an area of ​​approximately 25 mm) 2 up to about 30 mm 2 ), and it has a scanning speed of approximately 100 mm / s. Furthermore, the laser beam is emitted in 250 pulses approximately 1 to 10 times per location, with each pulse having a duration of approximately 20 ns to 150 ns. By way of example, and without limitation, the annealing process can be carried out in a nitrogen or other inert gas environment (e.g., argon, helium, xenon, etc.).

[0026] The aforementioned laser beam properties are not intended to be limiting, and values ​​outside these ranges may be used depending on the following conditions: (I) the thicknesses of the low-melting-point amorphous upper layer 230A and the high-melting-point single-crystal lower layer 230B; and (II) the melting point difference between the low-melting-point amorphous upper layer 230A and the high-melting-point single-crystal lower layer 230B. By way of example, and not as a limitation, for a thicker amorphous top layer 230A with a low melting point (e.g., when T1 / T is closer to about 0.75), a longer pulse duration (e.g., about 150 ns) in combination with a higher number of pulses (e.g., 10) can be used to achieve a greater annealing depth (e.g., about 1200 nm), while for a smaller annealing depth (e.g., about 7 nm), fewer or shorter pulses can be used.

[0027] The beam wavelength can also be adjusted to achieve a desired heat dissipation based on other laser beam conditions (e.g., number of pulses, pulse duration, scanning speed, etc.) and layer properties (e.g., thickness and melting point of the low-melting-point amorphous top layer 230A). For example, assuming all other laser beam properties are equal, a laser beam with a short wavelength (e.g., about 300 nm) and a shallower absorption depth can be used for a thin, low-melting-point amorphous top layer 230A (e.g., about 10 nm thick), and a laser beam with a long wavelength (e.g., about 500 nm) and a greater absorption depth can be used for a thick, low-melting-point amorphous top layer 230A (e.g., about 100 nm thick).Under both conditions, the laser power can be essentially the same and can be, for example, about 200 J to 400 J.

[0028] In some embodiments, the laser annealing process described above activates the dopants (e.g., B or P) in the low-melting-point amorphous upper layer 230A. The concentration of the activated carriers in the upper layer of the source / drain epiaxial stack 230 can be approximately 1 × 10 20 cm -3 up to about 1 × 10 21 cm -3for p- and n-stacks (e.g., SiGe, SiC, or SiP). In some embodiments, the dopant activation process occurs primarily in the low-melting-point upper layer (e.g., the low-melting-point amorphous upper layer 230A) and only partially in the high-melting-point single-crystal lower layer (e.g., the high-melting-point single-crystal lower layer 230B). In some embodiments, the low-melting-point upper layer can develop an activated-support concentration that is essentially equal to its chemical dopant concentration (i.e., an activation rate of about 100%), and the high-melting-point lower layer can develop an activated-support concentration that is lower than its chemical dopant concentration (i.e., an activation rate of less than 100%).For example, in the above case, the upper layer 230A with a low melting point can have an activated carrier concentration of up to about 1 × 10. 21 cm -3 develop, while the lower layer 230B with high melting point reaches an activated carrier concentration of up to about 1 × 10 20 cm -3 may be limited. Therefore, in some embodiments, the upper layer 230A with a low melting point develops a higher concentration of activated dopants (e.g., by about an order of magnitude higher) than the lower layer 230B with a high melting point, even though dopant activation occurs throughout the entire source / drain epiaxial stack 230.

[0029] In some embodiments, dopant diffusion outside the source / drain epiaxial stack can be avoided, as in Fig. Figure 3 shows a SIMS profile (SIMS: secondary ion mass spectrometry), represented by curve 300, superimposed with a propagation resistance profile (SRP), represented by curve 310. The y-axis of Fig. 3 is logarithmic and represents the concentration of dopants and activated dopants (e.g., carriers). The x-axis represents a depth in the source / drain epiaxial stack 230. For example, the origin of the xy-diagram corresponds to Fig. 3 of a top surface of the source / drain epiaxial stack 230. In some embodiments, profiles 300 and 310 represent the dopant and carrier concentrations, respectively, after a tempering process along a Fig. 2 shows line A - B. In particular, the SIMS curve 300 corresponds to a total dopant concentration (e.g., B or P) across the source / drain epiaxial stack 230, and the SRP curve 310 corresponds to an activated dopant concentration across the source / drain epiaxial stack 230. As shown in Fig. As shown in Figure 3, both profiles 300 and 310 exhibit a significant reduction in the dopant and carrier concentration near the interface with the semiconductor fin 210. In some embodiments, the slope 320 is approximately 2.6 nm / decade, indicating that the carriers and dopants in the source / drain epiaxial stack 230 do not diffuse into the semiconductor fin 210.

[0030] In some embodiments, the amorphous upper layer 230A with a low melting point recrystallizes when it cools after the laser annealing process. For example, the amorphous upper layer 230A with a low melting point can transform into a single-crystal layer. Fig. Figure 4 shows the source / drain epiaxial stack 230 after the at Fig. 2 described laser annealing process, in which the amorphous upper layer 230A with a low melting point in the deposition state is transformed into a laser-annealed single-crystal upper layer 400. In some embodiments, the single-crystal upper layer 400 has a substantially the same thickness T1 as the amorphous upper layer 230A with a low melting point in the deposition state, which in Fig. Figure 2 is shown. Furthermore, the thickness T of the source / drain epiaxial stack 230 is essentially the same before and after the laser annealing process.

[0031] In some embodiments, an interface 410 (e.g., the interface between the upper and lower single-crystal layers 400 and 230B of the laser-annealed source / drain epitaxial stack) may have a rough (i.e., coarse) surface topography, which is detectable by TEM imaging (TEM: transmission electron microscopy). In some embodiments, the interface 410 also appears rougher (i.e., coarser) than a top surface 420 of the upper single-crystal layer 400, which is also detectable by TEM imaging. In some embodiments, the surface roughness of the upper low-melting-point layer 230A is about 6 times lower after the laser annealing process. For example, the RMS (root mean square) surface roughness of the upper low-melting-point layer 230A may be about 3 nm, and the RMS surface roughness of the single-crystal upper layer 400 (i.e.,The diameter of the annealed top layer (230A) can be approximately 0.5 nm. Furthermore, the laser-annealed single-crystal top layer 400 can have a higher defect density (i.e., number of dislocations per unit area) than the high-melting-point single-crystal bottom layer 230B. This is due to the recrystallization process that the laser-annealed single-crystal top layer 400 undergoes when it is transformed from an amorphous or polycrystalline layer into a single-crystal layer. For example, the single-crystal top layer 400 can have a defect density of approximately 1 × 10⁻⁵. 18 Displacements / cm 2 have, while the single-crystal lower layer 230B with a high melting point is approximately 1 × 10 16 Displacements / cm 2(i.e., approximately two orders of magnitude fewer dislocations per unit area). In some embodiments, due to the defect density difference between the two layers in the source / drain epiaxial stack 230, the laser-annealed single-crystal upper layer 400 develops compressive stress, while the high-melting-point single-crystal lower layer 230B develops tensile stress or a lower compressive stress than the laser-annealed single-crystal upper layer 400. In other words, the type or magnitude of stress can differ between the laser-annealed single-crystal upper layer 400 and the high-melting-point single-crystal lower layer 230B.

[0032] In some embodiments, the upper, low-melting-point layer can be made of a different material than the lower, high-melting-point layer, or it can be made of the same material but with a different stoichiometry. Furthermore, the upper, low-melting-point layer and the lower, high-melting-point layer can be single-crystal layers. By way of example, and not as a limitation, in a p-source / drain epitaxial stack, the upper, low-melting-point layer can be single-crystal SiGe with a Ge concentration of about 20% to about 40%, while the lower, high-melting-point layer can be single-crystal Si with no significant amount of Ge. In some embodiments, the incorporation of Ge into Si lowers the melting point of the resulting SiGe layer.For example, a SiGe layer with about 40% Ge has a lower melting point than a SiGe layer with about 20% Ge, and a SiGe layer with about 20% Ge has a lower melting point than Si that contains no significant amount of Ge.

[0033] In an n-source / drain epitaxial stack, the upper low-melting-point layer can be a single-crystal SiC layer with a low carbon concentration, while the lower high-melting-point layer can be a single-crystal SiC layer with a high carbon concentration, with the difference between the low and high carbon concentrations being about 2% in some embodiments.

[0034] In some embodiments, the aforementioned layers are grown by CVD at a temperature of approximately 650 °C to approximately 800 °C and a pressure of approximately 2.666 to approximately 39.997 kPascal. In some embodiments, a process temperature greater than approximately 650 °C and a process pressure less than approximately 39.997 kPascal are required to grow the single-crystal high- and low-melting-point layers. The laser annealing process allows the upper low-melting-point layer and the lower high-melting-point layer to develop the same type of stress (i.e., compressive or tensile stress), and the activated dopant concentration in the single-crystal upper layer is greater than that in the single-crystal lower layer. In some embodiments, the increase in compressive stress after annealing is approximately 0.8 GPa.

[0035] In other embodiments, the upper, low-melting-point layer can be made of a different material than the lower, high-melting-point layer, or they can be made of the same material but with a different stoichiometry. Furthermore, the upper, low-melting-point layer and the lower, high-melting-point layer can be polycrystalline or amorphous layers with appropriately adjusted melting points (e.g., with a melting point difference of at least 200 K). By way of example, and not as a limitation, in a p-source / drain epitaxial stack, the upper, low-melting-point layer can be made of polycrystalline or amorphous SiGe with a Ge concentration of about 20% to about 40%, while the lower, high-melting-point layer can be made of polycrystalline or amorphous Si without a significant amount of Ge.In some embodiments, the incorporation of Ge into Si lowers the melting point of the resulting SiGe layer, as explained above. For example, the melting point of an amorphous Si layer is about 1420 K, while the melting point of an amorphous Ge layer is about 965 K to about 1024 K. Thus, by incorporating Ge into an amorphous Si layer and controlling the Ge concentration, the melting point of the resulting layer can be adjusted to be higher than about 965 K and lower than about 1420 K. Consequently, the concentration of Ge in the Si layer can be adjusted to achieve the desired melting point difference of more than about 200 K discussed above.

[0036] In an n-source / drain epitaxial stack, the upper, low-melting-point layer can consist of polycrystalline or amorphous SiC with a low carbon concentration, while the lower, high-melting-point layer can consist of polycrystalline or amorphous SiC with a high carbon concentration, with the difference between the low and high carbon concentrations being approximately 2% in some embodiments. In some embodiments, a carbon concentration difference of approximately 2% is sufficient to achieve a melting point difference of more than approximately 200 K.

[0037] In some embodiments, the aforementioned layers are grown by CVD at a temperature of approximately 450 °C to approximately 600 °C and a pressure of approximately 39.997 to approximately 53.329 kPascal. In some embodiments, a process temperature of less than approximately 600 °C and a process pressure greater than approximately 39.997 kPascal are required for the growth of the polycrystalline or amorphous high- and low-melting-point layers. Through the laser annealing process, the upper low-melting-point layer and the lower high-melting-point layer can develop the same type of stress (e.g., compressive stress), and the activated dopant concentration is higher in the upper layer than in the lower layer. In some embodiments, the upper low-melting-point layer exhibits an activation rate of approximately 100%, i.e., all dopants in the upper layer are activated (e.g., approximately 1 × 10⁻⁶). 21 cm -3In contrast, the lower layer with a high melting point can show an activation rate of about 10%.

[0038] In some embodiments, permutations of polycrystalline or amorphous and single-crystal layers can be used for the upper and lower layers of the source / drain epitaxial stack, which are within the basic concept and scope of protection of the present invention, provided that the upper layer has a lower melting point than the lower layer, for example, provided that the melting point difference between the lower and upper layers is greater than about 200 K. Furthermore, the upper layer with the lower melting point has a thickness of about 30% to about 75% of the total thickness of the source / drain epitaxial stack.

[0039] Fig. Figure 5 is a flowchart of an exemplary process 500 for producing a source / drain epiaxial stack with a low-melting-point upper layer and a high-melting-point lower layer, according to some embodiments. Other manufacturing steps may be performed between the various steps of process 500 and may not be shown for clarity. Furthermore, the manufacturing steps of process 500 are not specific, and alternative steps may be performed instead of the steps of process 500. Embodiments of the present invention are not limited to process 500. The exemplary process 500 is described with reference to the Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. 11 described.

[0040] The process 500 begins with a step 510 in which a gate structure is produced on a fin that is arranged on a substrate. Fig. Figure 6 shows sectional views of the resulting structure along the x-axis (x-section) and along the y-axis (y-section). The direction along the x-axis corresponds to the direction of the fin's length, and the direction along the y-axis corresponds to the direction of the fin's width. For example, the y-section view is obtained by viewing the structure along line A-B of the x-section in the y-direction, and the x-section view is obtained by viewing the structure along line C-D of the y-section in the x-direction. In step 510, a fin 600 is fabricated on a substrate 610. In some embodiments, the fin 600 and the substrate 610 comprise one or more semiconductor materials. For example, the fin 600 and the substrate 610 may comprise an elemental semiconductor material, such as Si or Ge, or a semiconductor composite material, such as SiGe.Furthermore, the fin 600 and the substrate 610 can have doped areas that are in . Fig. Figure 6 is not shown. A dielectric layer 620, such as silicon oxide, insulates the fin 600 from neighboring fins. In some embodiments, the dielectric layer 620 can be an insulating structure, such as an STI structure (STI: shallow trench insulation).

[0041] A gate structure 630 is fabricated on and around the fin 600 such that it encloses a portion of the fin 600 that is not covered by the dielectric layer 620, as shown in the x- and y-sectional views of Fig. Figure 6 is shown. In some embodiments, the gate structure 630 comprises a sacrificial gate electrode 630A, a sacrificial gate dielectric 630B, and one or more spacer layers 630C. In some embodiments, the sacrificial gate electrode 630A comprises polysilicon, and the sacrificial gate dielectric 630B comprises silicon oxide. Furthermore, the one or more spacer layers 630C may comprise a nitride, such as silicon nitride. In some embodiments, the sacrificial gate electrode 630A and the sacrificial gate dielectric 630B form a sacrificial gate stack, which can be replaced by a metal gate stack in a subsequent step.

[0042] In Fig. In Figure 5, the process 500 continues with a step 520 in which a portion of the fin 600 is omitted. In some embodiments, omitting the fin 600 facilitates the fabrication of the source / drain epiaxial stack in a later step (e.g., in a step 530 of the process 500). The x-section of [reference missing] is shown as an example and is not limited to this. Fig. 7 the resulting structure after the recession process of step 520. In some embodiments, portions of the fin 600 are recessed to produce recessed fin portions 700. The recessed fin portions 700 are arranged adjacent to the spacer layers 630C of the gate structure 630. By way of example, and without limitation, the recessed fin portions 700 can be produced by masking portions of the fin 600 to be protected and etching the remaining portions (e.g., the exposed portions) of the fin 600. The masking can be achieved with a hard mask layer, such as an oxide layer or a nitride layer, with a photoresist layer, or combinations thereof. For the etching process, an etchant such as chlorine (Cl₂), hydrogen bromide (HBr), tetrafluoromethane (CF₄), or combinations thereof can be used.In some embodiments, all parts of the fin 600 that are not covered by the gate structure 630 are recessed during step 520, as in an x-section of . Fig. Figure 11 is shown. The y-intercept of Fig. Figure 7 shows the resulting structure along a line E - F of the x-section in the y-direction. In the y-section view, the recessed parts (e.g., 700) and the non-recessed parts (e.g., 600) of the fin are visible.

[0043] In Fig. In section 5, the process 500 continues with a step 530 in which a source / drain epiaxial stack with a low-melting-point upper layer and a high-melting-point lower layer is produced on the recessed fin portion 700. As explained above, in some embodiments, the low-melting-point upper layer and the high-melting-point lower layer have materials with substantially similar stoichiometry but different microstructures, for example, the low-melting-point upper layer being amorphous and the high-melting-point lower layer being monocrystalline. In this case, the melting point difference between the two layers is due to the different microstructures of the two layers.In some embodiments, the upper low-melting-point layer and the lower high-melting-point layer are made of materials with different stoichiometries but substantially similar microstructures, where, for example, the upper low-melting-point layer and the lower high-melting-point layer are single-crystal, polycrystalline, or amorphous layers. In this case, the melting point difference between the two layers is due to their different stoichiometries. In some embodiments, the melting point difference between the lower high-melting-point layer and the upper low-melting-point layer is greater than approximately 200 K. In some embodiments, the upper low-melting-point layer has a lower melting point than the surrounding structures, such as the Fin 600.In some embodiments, the fin 600 and the lower high-melting-point layer have essentially similar melting points.

[0044] This is an example, and not a limiting one. Fig. Eight x- and y-sectional views of the resulting structure after fabrication of a source / drain epiaxial stack 800. The y-sectional view of Fig. Figure 8 shows the resulting structure along the line E - F of the x-section in the y-direction, and the x-section view of Fig. Figure 8 shows the resulting structure along the line C-D of the y-section in the x-direction. In some embodiments, the source / drain epiaxial stack 800 is diamond-shaped, as shown in the y-section of Fig. Figure 8 shows the source / drain epitaxial stack 800 comprising a low-melting-point upper layer 810 and a high-melting-point lower layer 820. In some embodiments, the high-melting-point lower layer 820 may comprise further epitaxial layers, which are shown for simplicity in the sectional views of Figure 8. Fig. Figure 8 is not shown. By way of example and without limitation, the upper layer 810 with a low melting point and the lower layer 820 with a high melting point are grown using a CVD process at a temperature of 450 °C to 800 °C and a process pressure of approximately 2.666 to approximately 53.329 kPascal. In some embodiments, a combination of a low temperature (e.g., from approximately 450 °C to approximately 600 °C) and a high pressure (e.g., from approximately 39.997 to approximately 53.329 kPascal) produces an amorphous or polycrystalline layer, while a combination of a high temperature (e.g., from approximately 600 °C to approximately 800 °C) and a low pressure (e.g., from approximately 2.666 to approximately 39.997 kPascal) produces a single-crystal layer. In some embodiments, the thickness ratio between the upper layer 810 with low melting point and the source / drain epiaxial stack 800 is about 0.3 to about 0.75 (i.e., 0.30 ≤ T1 / T ≤ 0.75).In some embodiments, the laser annealing process does not change the thickness of the upper layer 810 with low melting point and the lower layer 820 with high melting point.

[0045] In some embodiments, the source / drain epiaxial stack 800 can be a B-doped SiGe stack with a Ge concentration of about 20% to about 40%, a P-doped SiC stack, or a P-doped SiP stack. In some embodiments, the doping concentration of the upper, low-melting-point layer 810 is essentially similar to the doping concentration of the lower, high-melting-point layer 820 (e.g., about 1 × 10⁻⁶). 21 cm -3 ).

[0046] In the Fig. 5 and Fig. In step 8, the process 500 continues with a step 540 in which the source / drain epiaxial stack 800 is annealed using a laser annealing process to activate the dopants. In some embodiments, a melt front is selectively generated in the upper, low-melting-point layer 810 by a passing laser beam 830. This process allows the upper, low-melting-point layer 810 to achieve an activated dopant concentration of approximately 1 × 10⁻⁶. 21 cm -3 (i.e., achieve an activation rate of approximately 100%). In some embodiments, the lower, high-melting-point layer 820 has a lower activated dopant concentration than the upper, low-melting-point layer 810 due to the laser annealing process (e.g., an activation rate of approximately 10%), where the activated dopant concentration of the lower, high-melting-point layer 820 is, for example, approximately 3 × 10 18 cm -3 up to about 1 × 10 20 cm-3 This may amount to a certain amount. In some embodiments, diffusion of dopants outside the source / drain epiaxial stack is prevented, as described above with reference to Fig. 3 has been explained.

[0047] In some embodiments, the upper, low-melting-point layer 810 recrystallizes during the laser annealing process if it was an amorphous layer in the deposition state. Furthermore, the recrystallized upper, low-melting-point layer 810 has a higher defect density than the lower, high-melting-point layer 820 (e.g., by about two orders of magnitude). In some embodiments, the interface between the upper, low-melting-point layer 810 and the lower, high-melting-point layer 820 has a rough (i.e., non-planar or coarse) surface topography, which is detectable by TEM imaging. In some embodiments, the recrystallized upper, low-melting-point layer 810 develops compressive stress, while the lower, high-melting-point layer 820 has tensile stress or a lower compressive stress than the recrystallized upper, low-melting-point layer 810.

[0048] In Fig. The process 500 ends with a step 550 in which contacts are made on the source / drain epiaxial stacks 800. By way of example and without limitation, the contacts can be made as follows. Fig. In step 9, a dielectric layer 900 is deposited on the dielectric layer 620 and subsequently polished so that a top surface of the dielectric layer 900 is substantially coplanar with a top surface of the gate structure 630. In some embodiments, the sacrificial gate electrode 630A and the sacrificial gate dielectric 630B are replaced by a metal gate electrode stack 910 and a gate dielectric stack 920, respectively. In some embodiments, the gate electrode stack 910 comprises metallic layers, such as exit-work layers (e.g., one or more titanium nitride layers), barrier layers (e.g., tantalum nitride layers), and metal filler layers (e.g., a tungsten metal filler layer), which, for the sake of simplicity, are referred to as Fig. 9 are not shown. In some embodiments, the gate dielectric stack 920 comprises a dielectric interface layer (e.g., of silicon oxide) and a dielectric high-k layer (e.g., of hafnium oxide) with a dielectric constant greater than about 3.9, both of which are shown for simplicity in Fig. 9 are not shown.

[0049] In some embodiments, contact openings are created in the dielectric layer 900 to expose the laser-tempered, low-melting-point top layer 810. Once the laser-tempered, low-melting-point top layer 810 has been exposed, a silicide 930 can be produced on the top surface of the laser-tempered, low-melting-point top layer 810. In some embodiments, the silicide 930 comprises titanium, platinum, nickel, or another suitable metal, or combinations thereof. In some embodiments, a portion of the laser-tempered, low-melting-point top layer 810 is consumed to form the silicide 930. Subsequently, the contact opening is coated with a cover layer, such as titanium niride. For simplicity, the cover layer is Fig. 9 not shown. The top layer acts as an adhesive and barrier layer for a metallic filler layer 940. In some embodiments, the metallic filler layer 940 and the top layer (in Fig. 10 (not shown) planarized to remove deposited material from the top of the dielectric layer 900 and to create contacts 950.

[0050] In some embodiments, method 500 can be used for a transistor structure that differs from the one described in the Fig. 6, Fig. 7, Fig. 8 to Fig. The transistor structure shown in 9 is different. For example, in Fig. 6 the dielectric layer 620 is grown such that its top surface is coplanar with a top surface of the gate structure 630, as shown in an x-section of Fig. Figure 10 is shown. In some embodiments, the [details] can be [details]. Fig. The transistor structure shown in 10 is a variant of the one in Fig. The transistor structure shown in section 6 should be used. Fig. 10. The dielectric layer 620 can cover the side wall and the top surfaces of the fin 600 and the spacer layers 630C of the gate structure 630. In this exemplary transistor structure, the fin 600 is covered according to step 520 of Fig. 5 between the gate structure 630 and the dielectric layer 620 is recessed, as shown in the x-section of Fig. Figure 11 shows this. For example, openings can be created in the dielectric layer 620 on both sides of the gate stack 630 to expose parts of the fin 600 that are not covered by the gate stack 630. The y-section of Fig. Figure 11 shows a representation of the structure along the line E - F of the x-section of Fig. 11. By way of example, and without limitation, this can be achieved using photolithographic and etching processes. The fin 600 can then be recessed, as in Fig.As set out in section 7. Other steps of procedure 500 (e.g., 530 to 550) are carried out unchanged.

[0051] The embodiments described here are aimed at the fabrication of source / drain epiaxial stacks comprising a low-melting-point upper layer and a high-melting-point lower layer. In some embodiments, the low-melting-point upper layer and the high-melting-point lower layer consist of materials with substantially similar stoichiometry but different microstructures, where, for example, the low-melting-point upper layer and the high-melting-point lower layer may be single-crystal. In this case, the melting point difference between the two layers is due to their differing microstructures.In other embodiments, the upper low-melting-point layer and the lower high-melting-point layer consist of materials with different stoichiometries but substantially similar microstructures, where the upper low-melting-point layer and the lower high-melting-point layer can be, for example, single-crystal, polycrystalline, or amorphous layers. In this case, the melting point difference between the two layers is due to their different stoichiometries. In some embodiments, the melting point difference between the lower high-melting-point layer and the upper low-melting-point layer is greater than 200 K, regardless of its origin (e.g., microstructure or stoichiometry).In some embodiments, after the laser annealing process, the upper layer with a low melting point and the lower layer with a high melting point can have different types and / or magnitudes of stress. In some embodiments, a combination of a low growth temperature (e.g., from about 450 °C to about 600 °C) and a high growth pressure (e.g., from about 39,997 to about 53,329 kPascal) produces an amorphous or polycrystalline layer, while a combination of a high growth temperature (e.g., from about 600 °C to about 800 °C) and a low growth pressure (e.g., from about 2,666 to about 39,997 kPascal) produces a single-crystal layer. In some embodiments, the thickness ratio between the upper low-melting-point layer and the source / drain epiaxial stack is approximately 0.3 to approximately 0.75 (i.e., 0.30 ≤ thickness ratio ≤ 0.75).In some embodiments, the laser annealing process does not significantly change the thickness of the upper low-melting-point layer and the lower high-melting-point layer. In some embodiments, the upper low-melting-point layer has a lower melting point than the surrounding structures, such as a semiconductor fin or substrate, thus preventing fin deformation during the laser annealing process. In some embodiments, the amorphous upper low-melting-point layer recrystallizes during the laser annealing process and develops a higher defect density than the lower high-melting-point layer. Furthermore, the upper low-melting-point layer exhibits a higher concentration of activated dopants than the lower high-melting-point layer after the laser annealing process.

Claims

[1] Semiconductor structure with: a fin (110, 210) arranged on a substrate (140), wherein the fin (110, 210) and the substrate (140) comprise a semiconductor material; a gate structure (100, 200) arranged on the fin (110, 210), wherein the gate structure (100, 200) encloses part of a side wall surface of the fin (110, 210); a recess (700) which is created in a part of the fin adjacent to the gate structure (100, 200); a source / drain epiaxial stack (230) arranged in the recess (700) and comprising the following: a lower layer (230B), and an upper layer (400) that has a higher activated dopant concentration than the lower layer (230B); and a contact (930, 950) that is arranged on the upper layer (400) of the source / drain epiaxial stack (230), wherein the contact (930, 950) is arranged adjacent to the gate structure (100, 200), where the upper layer (400) has a dopant activation rate of about 100% and the lower layer (230B) has a dopant activation rate of about 10%. [2] Semiconductor structure according to claim 1, wherein the upper layer (400) has a defect density two orders of magnitude higher than the lower layer (230B). [3] Semiconductor structure according to any of the preceding claims, wherein the thickness of the upper layer (400) is about 30% to about 75% of the thickness of the source / drain epiaxial stack. [4] Semiconductor structure according to one of the preceding claims, wherein the upper layer (400) induces a higher compressive stress in the fin than the lower layer (230B). [5] Semiconductor structure according to one of the preceding claims, wherein the upper layer (400) has an activated dopant concentration of about 1 × 10 21 cm -3 has. [6] Semiconductor structure according to any of the preceding claims, wherein the lower layer (230B) and the upper layer (400) each comprise boron-doped silicon germanium, phosphorus-doped silicon carbon or phosphorus-doped silicon phosphorus. [7] Procedure with the following steps: Forming a fin (110, 210) on a substrate (140); Constructing a sacrificial gate structure on the fin (110, 210), wherein the sacrificial gate structure encloses part of a top surface of the fin (110, 210) and part of a side wall surface of the fin (110, 210); Leaving out part of the fin (110, 210) that is not covered by the sacrificial gate structure; Creating a source / drain epiaxial stack (230) in the recessed part of the fin (110, 210), wherein creating the source / drain epiaxial stack (230) comprises the following: Growth of a lower layer (230B) with a crystalline microstructure, and Growth of an upper layer (230A) with an amorphous microstructure on the lower layer (230B), wherein the upper layer (230A) has a different melting point than the lower layer (230B); and Annealing the source / drain epiaxial stack (230) with a laser to generate a melt front in the upper layer (230A), where, after annealing the source / drain epiaxial stack (230) with the laser, the upper layer (230A, 400) has a dopant activation rate of about 100% and the lower layer (230B) has a dopant activation rate of about 10%. [8] Method according to claim 7, wherein the annealing comprises recrystallizing the upper layer (230A). [9] Method according to claim 7 or 8, wherein after tempering the upper layer (230A) has a number of defects per unit area approximately two orders of magnitude higher than the lower layer (230B). [10] Method according to any one of claims 7 to 9, wherein after tempering the upper layer (230A) has a higher compressive stress than the lower layer (230B). [11] Method according to any one of claims 7 to 10, wherein the growth of the upper layer (230A) comprises growing the upper layer (230A) with a thickness of 30% to 75% of the thickness of the source / drain epiaxial stack (230). [12] Method according to any one of claims 7 to 11, wherein the growth of the lower (230B) and upper layer (230A) comprises achieving a melting point difference of more than about 200 K between the lower (230B) and upper layer (230A). [13] Method according to any one of claims 7 to 12, wherein the annealing of the source / drain epitaxial stack (230) comprises converting the amorphous microstructure of the upper layer (230A) into a crystalline microstructure. [14] Method according to any one of claims 7 to 13, wherein the annealing of the source / drain epiaxial stack (230) comprises converting the upper layer (230A) into a crystalline layer which has a higher defect density per unit area than the lower layer (230B). [15] Method according to any one of claims 7 to 14, wherein the annealing of the source / drain epiaxial stack comprises converting the upper layer (230A) into a crystalline layer (400) which has a higher activated dopant concentration than the lower layer (230B). [16] Procedure with the following steps: Forming a fin (110, 210) on a substrate (140); Establishing a gate structure (100, 200) on the fin (110, 210); Removing parts of the fin (110, 210) that are not covered by the gate structure (100, 200); Manufacturing a source / drain epiaxial stack (230) on the recessed portions of the fin (110, 210), wherein manufacturing the source / drain epiaxial stack (230) comprises the following: Deposition of a first layer (230B) which has first dopants, and Deposition of a second layer (230A) having second dopants, wherein the second layer (230A) is deposited on the first layer (230B) and has a lower melting point than the first layer (230B); and Treating the source / drain epiaxial stack (230) with a annealing source to activate the first and second dopants in the first (230B) and second layer (230A), where, after treatment of the source / drain epiaxial stack (230) with the annealing source, the second layer (230A, 400) has a dopant activation rate of about 100% and the first layer (230B) has a dopant activation rate of about 10%. [17] Method according to claim 16, wherein the treatment of the source / drain epiaxial stack (230) with the annealing source comprises activating the second dopants in the second layer (230A) and activating a part of the first dopants in the first layer (230B). [18] Method according to claim 16 or 17, wherein the deposition of the first (230B) and the second layer (230A) comprises producing the first (230B) and the second layer (230A) with a substantially similar microstructure and a substantially different stoichiometry. [19] Method according to claim 16 or 17, wherein the deposition of the first (230B) and the second layer (230A) comprises producing the first (230B) and the second layer (230A) with a substantially different microstructure and a substantially similar stoichiometry.

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