ELECTRONIC CONTROL UNIT

Abstract

An electronic control unit comprises several microcomputers. After initiating the transmission of data elements, a transmitting and receiving unit in a transmitting microcomputer (20) of the microcomputers transmits all data elements stored in a transmitting data table (21) without intervention from a processing unit (28). The transmitting data elements include a determination data element for determining whether all data elements stored in the transmitting data table in the transmitting microcomputer have been completely received by a receiving microcomputer (30) of the microcomputer. Based on the determination data element, the receiving microcomputer determines whether all data elements have been completely received.

Description

TECHNICAL AREA

[0001] The present disclosure relates to an electronic control unit with multiple microcomputers. STATE OF THE ART

[0002] For example, JP 2012-034375A discloses an electronic control unit (ECU) that includes components such as a main microcomputer, a secondary microcomputer, and a driver IC for controlling input and output. These components perform SPI communication (SPI = Serial Peripheral Interface), i.e., clock-synchronous serial bus communication with a chip selection signal line.

[0003] As described, for example, in JP 2012-034375A, there has recently been a trend toward requiring automotive ECUs to have sophisticated and complex control functions to manage emissions and improve fuel economy. To meet such a requirement, it is conceivable that (i) multiple microcomputers are integrated into a single ECU, (ii) data communication occurs between the multiple microcomputers, and (iii) the multiple microcomputers cooperate to execute the control function. It should be noted that for the cooperation and execution of control functions by multiple microcomputers, it is desirable for a large amount of data to be communicated simultaneously between them, while minimizing the load on each microcomputer's central processing unit (CPU).

[0004] Each microcomputer can therefore have a data table capable of storing a large number of data elements. If the data elements to be transmitted are stored in the data table, it is conceivable that all data elements stored in the data table could be sent or received by a transmitting and receiving unit, such as a SIPI (Serial Inter-Processor Interface), without intervention from any CPU.

[0005] In the above case, a microcomputer sending the data elements (i.e., a sending microcomputer) can detect the completion of sending all data elements, for example, by completing the reading of all data elements stored in the data table. In contrast, a microcomputer receiving the data elements (i.e., a receiving microcomputer) cannot detect when the reception of all data elements has been completed. This failure to detect when the reception of all data elements has been completed leads to problems, such as (i) a receiving microcomputer that has received the data elements being unable to begin processing using the received data elements, or (ii) the receiving microcomputer being unable to start sending data elements, even if such data elements are present.

[0006] From JP S64 26 964 A, a memory write device for code data is also known, in which initial code data is sent via DMA from a serial interface control circuit to a memory. A specific data acquisition circuit then confirms the match between the code of the specified data and a specific code. Subsequently, the counter value of a specific data reception counter is incremented. The transmission data from a barcode reader is sent to the memory via DMA. When the final code data is transmitted via DMA, the match between the code of this data and the specific code is confirmed. Then, the counter value is incremented. A flip-flop is set with the second increment of the counter value. Finally, the end of the DMA transmission is reported to a CPU, and the next processing step is initiated.

[0007] JP H05 - 173 935 A relates to a data transmission method using multiple central processing units (CPUs) and in particular a data transmission method for transferring data in the memory area of ​​one CPU to a section in the memory area of ​​another CPU.

[0008] US Patent 2008 / 0126662A1 further discloses a direct memory access controller comprising: a data register for transferring data from a source to a destination address, a pattern register, a data comparator coupled to the data register and the pattern register, and a control unit coupled to the comparator that can be operated to stop data transmission when the comparator detects a match between the data register and the pattern register.

[0009] The purpose of this disclosure is to provide an electronic control unit with multiple microcomputers. In such an electronic control unit, although all data elements stored in a data table are sent and received between the microcomputers without intervention from a CPU, a receiving microcomputer is enabled to detect or recognize the completion of the reception of all data elements.

[0010] The problem is solved by the subject matter of the main claim. Advantageous further developments are specified in the dependent claims.

[0011] According to the invention, several microcomputers in the electronic control unit have transmitting and receiving units that send and receive data elements between the microcomputers. After the transmission of data elements is initiated, the transmitting and receiving unit in the sending microcomputer sends all data elements stored in the data table without intervention from the processing unit. All data elements stored in the data table can thus be sent and received between the several microcomputers without intervention from the processing unit. The data elements to be transmitted include a determination data element for determining whether the receiving microcomputer has completed receiving all data elements stored in the data table of the sending microcomputer.Such a destination data element can be used by the receiving party's microcomputer to determine whether the reception of all data elements has been completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and further functions, properties and advantages of the present disclosure are more clearly evident from the following detailed description with reference to the accompanying drawings. The drawings show: Fig. 1 An illustration to demonstrate a configuration of an electronic control unit according to one embodiment; Fig. 2. A diagram illustrating a configuration relating to a data communication process between multiple microcomputers; Fig. 3. An explanatory diagram to explain data elements sent by a transmitting microcomputer; and Fig. 4 An explanatory figure to illustrate an example of a specific data transmission and reception process between a sending microcomputer and a receiving microcomputer. DETAILED DESCRIPTION

[0013] An electronic control unit according to an embodiment of the present disclosure is described below with reference to the drawings. Fig. Figure 1 shows a block diagram illustrating a configuration of an electronic control unit 10 of the present embodiment.

[0014] An electronic control unit (hereinafter referred to as ECU) 10 is, for example, mounted on a vehicle and used in an application that controls the fuel injection and ignition of an internal combustion engine. In this case, the ECU 10 acquires several data elements, such as the rotation angle of the internal combustion engine, the engine speed, the amount of accelerator pedal depressurization, the engine coolant temperature, and the vehicle speed, based on sensor signals from various sensors. The ECU 10 determines the fuel injection timing and the ignition timing based on the acquired data elements in order to execute the fuel injection and ignition at the optimal timing. Subsequently, the ECU 10 sends a control signal to the fuel injector and the ignition system based on the determined fuel injection timing and the determined ignition timing.

[0015] To implement the complex combustion engine control system as described above, as in Fig. As shown in Figure 1, to implement this appropriately, the ECU 10 incorporates multiple microcomputers 20 and 30, a first microcomputer 20 and a second microcomputer 30, to distribute the control processing load. However, the number of microcomputers is not limited to two, and the ECU 10 can have three or more microcomputers.

[0016] To cooperate and perform control processing, the multiple microcomputers 20 and 30 must perform data communication between themselves to share data elements, such as data elements required for control or data elements relating to control timing and control results. In this case, if a central processing unit (CPU) 28 of each microcomputer 20, 30 performs data communication processing in addition to the computational processing for executing the control processing, the processing power of each CPU 28 must also be allocated to data communication processing. This may, for example, necessitate the introduction of a high-performance CPU or result in a delay in the control by the CPU.

[0017] The ECU 10 of the present embodiment is thus configured to perform data communication processing between the multiple microcomputers 20 and 30 without intervention from the CPU 28. The following describes a configuration for data communication processing between the multiple microcomputers 20 and 30 with reference to the Fig. 2 to 4 are described in more detail.

[0018] It should be noted that the Fig. 2 and Fig. Figure 4 shows that a configuration of the first microcomputer 20 as a send-side (transmitting) microcomputer differs from a configuration of the second microcomputer 30 as a receive-side (receiving) microcomputer. This is done only to illustrate or explain (i) the configuration required for transmit processing and (ii) the configuration required for receive processing. In fact, the first microcomputer 20 and the second microcomputer 30 have an identical configuration. For example, consider another case in which the second microcomputer 30 becomes a send-side microcomputer for transmitting data elements and the first microcomputer 20 becomes a receive-side microcomputer for receiving data elements. In such another case, the second microcomputer 30 transmits data elements according to the configuration described in Figure 4. Fig. 2 and Fig. In the configuration of the transmitting microcomputer shown in Figure 4, the first microcomputer receives 20 data elements according to the configuration shown in the Fig. 2 and Fig. The configuration of the receiving microcomputer shown in Figure 4 is described below. The following describes the case where the first microcomputer 20 serves as a transmitting microcomputer and the second microcomputer 30 serves as a receiving microcomputer.

[0019] As in Fig. As shown in Figure 2, the first microcomputer 20 and the second microcomputer 30 are connected via a communication line 40 and perform data communication over this line. In the present embodiment, the data communication uses LVDS technology (LVDS = Low Voltage Differential Signaling), in which data elements are transmitted serially using differential signals. The communication line 40 enables bidirectional communication of differential signals by providing (i) two transmit lines for sending data elements from the first microcomputer 20 to the second microcomputer 30 and (ii) two receive lines for the first microcomputer 20 to receive data elements from the second microcomputer 30. It should be noted that the transmit and receive lines can be used interchangeably. Furthermore, a serial communication technology other than LVDS can be used for data communication.

[0020] The first microcomputer 20 includes (i) a transmit data table 21, which stores data elements to be transmitted (i.e., data elements to be sent), and (ii) a transmit destination address table 22, which stores address values ​​of transmit destinations. The transmit data table 21 is created in RAM within the first microcomputer 20. The transmit data table 21 stores data elements to be sent by multiple transmissions through a SIPI 26, which will be described later. In other words, the transmit data table 21 can store a set of data to be sent by multiple transmissions through such a SIPI 26. Storing data elements in the transmit data table 21 is performed, for example, by the CPU 28 in the first microcomputer 20. It should be noted that storing data elements in the transmit data table 21 can also be performed by a DMAC 23, which will be described later.Furthermore, the unit of a data element for sending (i.e., a data element to be sent) is . Fig. 2 and Fig. 3 4 bytes. The size of the unit of a data element for transmission is not limited to 4 bytes, but can be a different unit. In contrast, a transmission destination address table 22 is created in the RAM or ROM of the first microcomputer 20. The transmission destination address table 22 stores address values ​​that specify memory areas contained in the receive data table 32 of the second microcomputer 30, which will be described below. The address values ​​stored in the transmission destination address table 22 can be serial or non-serial from the outset.

[0021] Fig. Figure 2 illustrates a single set of tables comprising the transmit data table 21, the transmit destination address table 22, and the receive data table 32; alternatively, multiple sets of tables may be provided. In this case, the size of each table in each set may be identical or different. Consider a case in which the first microcomputer 20 acts as a receive-side microcomputer and the second microcomputer 30 acts as a transmit-side microcomputer. In such a case, the transmit data table 21 in the first microcomputer 20 can be used as a receive data table, whereas the receive data table 32 in the second microcomputer 30 can be used as a transmit data table.

[0022] The first microcomputer 20 includes a DMAC (Direct Memory Access Controller) 23. The DMAC 23 serves to transfer (i) the data elements (data element 1 to data element N) stored in the transmit data table 21 and (ii) the address values ​​(address value 1 to address value N) stored in the transmit destination address table 22 to (i) a transmit data register 24 and (ii) a transmit destination address register 25, respectively. The DMAC 23 directly accesses the transmit data table 21 and the transmit destination address table 22, which are created in RAM or ROM, and reads the stored data elements and address values. A data element read from the transmit data table 21 is transferred to the transmit data register 24, while an address value read from the transmit destination address table 22 is transferred to the transmit destination address register 25.After initiating such a transfer process, the DMAC 23 repeatedly transfers a data element and its address value to registers 24 and 25 until the transmission of all data elements stored in the transmit data table 21 is complete. When the transmission of the last data element and its address value is complete, the DMAC 23 outputs a transfer completion message to the CPU 28.

[0023] The first microcomputer 20 includes (i) a transmission data register 24 for temporarily storing data to be transmitted and (ii) a transmission destination address register 25 for temporarily storing address values, each indicating memory areas in the receiving microcomputer. Furthermore, the first microcomputer 20 includes a SIPI (Serial Inter-Processor Interface) 26. The SIPI 26 executes a transmit process to send (i) the respective data elements stored in the transmission data register 24 and (ii) the respective address values ​​stored in the transmission destination address register 25 to the second microcomputer 30. The SIPI 26 initiates a transmit process to send the respective data elements and address values ​​to the SIPI 31 in the second microcomputer 30 based on a trigger provided by the storage of an address value in the transmission destination address register 25.

[0024] The SIPI 31 in the second microcomputer 30 receives the respective data elements and address values ​​sent by the SIPI 26 in the first microcomputer 20. Although not shown, a clock signal is provided from the first microcomputer 20 to the second microcomputer 30, or vice versa. This clock signal is used by the SIPI 26 in the first microcomputer 20 and the SIPI 31 in the second microcomputer 30 to operate synchronously according to the common clock signal. This enables the SIPI 31 in the second microcomputer 30 to perform the receiving process of receiving the data elements and address values ​​sent by the SIPI 26 in the first microcomputer 20.

[0025] The second microcomputer 30 includes a receive data table 32 formed in RAM for storing received data elements. The SIPI 31 in the second microcomputer 30 stores the received data elements in a memory area of ​​the receive data table 32, the memory area being indicated by the received address value. Consider a case in which the second microcomputer 30 determines that all of the data elements stored in the transmit data table 21 in the first microcomputer 20 have been received according to a procedure described below. In this case, each data memory area of ​​the receive data table 32 is preferably cleared (i.e., the data elements are deleted) while the reading of all data elements stored in the receive data table 32 is completed.

[0026] The following are the data elements sent by the first microcomputer 20, with reference to Fig. 3 described. As in Fig. As shown in Figure 3, the first microcomputer 20, as the last data element of data elements to be sent, sends a verification key 27, which can be verified in the second microcomputer 30.

[0027] As in Fig. As shown in Figure 3, the first microcomputer 20 and the second microcomputer 30 have the verification keys 27 and 33, which can be compared or verified against each other. These verification keys 27 and 33 are stored in the RAM or ROM of the first microcomputer 20 and the second microcomputer 30, respectively. Fig. Figure 3 shows an example where the first microcomputer 20 and the second microcomputer 30 have verification keys 27 and 33, respectively, which are identical (have the same value). However, as long as the first microcomputer 20 and the second microcomputer 30 can verify each other, the verification keys 27 and 33 do not necessarily have to have identical values. For example, the first microcomputer 20 and the second microcomputer 30 could have a predetermined or fixed ratio, such that the value of one verification key is obtained by adding a specific value to the value of the other verification key. Furthermore, the verification keys 27 and 33 could also be variable values ​​rather than fixed values.The verification keys 27, 33, for example, can be changed according to an identical rule (such as increased, decreased, and the like) each time they are added as a final data element of transmit data elements in the sending microcomputer, and each time they are verified as a destination data element in the receiving microcomputer.

[0028] The following is an example of a specific data transmission and reception process between the first microcomputer 20 as a transmitting microcomputer and the second microcomputer 30 as a receiving microcomputer, with reference to Fig. 4 described. Fig. 4 is prepared by (i) omitting the transfer destination address table 22, the transfer data register 24 and the transfer destination address register 25 in the first microcomputer 20 and (ii) omitting the SIPI 31 in the second microcomputer 30 to facilitate the description.

[0029] The CPU 28 executes control software 28a to perform a predetermined control process, such that the control software 28a provides a function. As such a function, the control software 28a writes transmit data elements to the transmit data table 21 via driver software 28b. At this time, the control software 28a writes the verification key 27 described above as a final data element (data element N) of the transmit data elements (i.e., data elements to be sent). The driver software 28b, serving as the base software, performs (i) reading data elements from a storage device (ROM, RAM, and the like), (ii) writing to the storage device, and / or (iii) exchanging signals with peripheral devices, such as the DMAC 23. As described above, the DMAC 23 can write the transmit data elements to the transmit data table 21.

[0030] After all transmit data elements have been written, the control software 28a sends a data transmission start command to the SIPI 26 (S2) via the driver software 28b. Specifically, the control software 28a writes data element 1 (stored in the transmit data table 21) and address value 1 (stored in the transmit destination address table 22) to the transmit data register 24 and the transmit destination address register 25, respectively. With this write action as a trigger, the SIPI 26 sends data element 1 to the second microcomputer 30 (S3). Alternatively, after all transmit data elements have been written, the control software 28a can instruct the DMAC 23 to start the transmission; the DMAC 23 can then transfer data element 1 and address value 1 to registers 24 and 25, respectively.

[0031] The SIPI 31 in the second microcomputer 30 receives data element 1 from the SIPI 26 in the first microcomputer 20; the SIPI 31 writes the received data element 1 to the memory area designated by address value 1 in the receive data table 32 and then returns a receive notification ACK (S4). Consequently, upon receiving the receive notification ACK from the SIPI 31 in the second microcomputer 30, the SIPI 26 in the first microcomputer 20 determines that the sending and receiving of data element 1 is normal and that data element 1 has been correctly written to the receive data table 32. Therefore, the SIPI 26 in the first microcomputer 20 outputs a DMA trigger signal to the DMAC 23 to execute the sending process of the next data element 2 in response to the receive notification ACK for sending data element 1 (S5).

[0032] After receiving the DMA trigger signal from SIPI 26, DMAC 23 reads data element 2 from transmit data table 21 and performs a DMA transfer of the read data element 2 to SIPI 26 (transmit data register 24), while simultaneously reading address value 2 from transmit destination address table 22 and performing a DMA transfer of the read address value 2 to SIPI 26 (transmit destination address register 25) (S6). With the DMA transfer of address value 2 by DMAC 23 as the trigger, SIPI 26 sends data element 2 to the second microcomputer 30 (S7). When the sent data element 2 is written to receive data table 32, SIPI 21 in the second microcomputer 30 returns an ACK notification, as it did for data element 1.

[0033] The sending and receiving process of such a data element and such a received notification ACK is repeated without intervention from CPU 28. This results in all data elements (data element 2 to data element N) stored in the transmit data table 21 being DMA-transmitted to SIPI 26, and SIPI 26 can then execute the transmit processes for the DMA-transmitted data elements 2 to N. It should be noted that the control software 28a can provide DMAC 23 with advance information indicating how many data elements are stored in transmit data table 21. DMAC 23 can thus execute the DMA transmission of data elements whose number is provided in advance as described above.

[0034] After the DMA transmission of the last data element N is completed, the DMAC 23 signals the completion of the DMA transmission with an interrupt (S9). The notification of the DMA transmission completion is received by the driver software 28b. Upon receiving the notification, the driver software 28b sends a data transmission completion notification to the control software 28a (S10). The control software 28a can thus detect that the transmission of all data elements stored in the transmit data table 21 is complete. This allows the first microcomputer 20 to begin processing and storing different data elements for transmission in the transmit data table 21, if, for example, such different data elements are available for transmission.

[0035] As in Fig.As shown in Figure 4, the ACK receive notification from SIPI 31 in the second microcomputer 30 for the last data element N is ignored (S11). That is, when the ACK receive notification for the last data element N is received, no interrupt notification is sent to the driver software 28b. There is a reason to send an interrupt notification to the driver software 28b instead of when the ACK receive notification for the last data element N is received, but rather when the DMA transfer is completed as described above. One such reason is as follows.This means that if the ACK receive notification is used as a factor for the output of an interrupt notification to the driver software 28b, the interrupt notification to the driver software 28b is not only the last data element N, but also the ACK receive notification for all data elements from data element 1 to data element N; this leads to an increase in the processing load in the CPU 28.

[0036] Thus, the first microcomputer 20, as a send-side microcomputer as described above, can detect the completion of the transmission of all data elements stored in the transmit data table 21 by the DMA transmission completion notification from the DMAC 23. In contrast, the second microcomputer 30, as a receive-side microcomputer, only receives the data elements transmitted by the first microcomputer 20 and therefore cannot detect when all of the data elements have been received unless countermeasures are taken. If the second microcomputer 30, as a receive-side microcomputer, does not detect the completion of the reception of all data elements, a problem can arise such that, for example, processing using the received data elements cannot be started, or processing to send data elements cannot be initiated when such data elements are available for transmission.

[0037] For this reason, the ECU 10 of the present embodiment provides a configuration as described above. That is, a transmitting microcomputer (the first microcomputer 20) sends, as the last data element of the data elements to be transmitted, the verification key 27, which can be verified in a receiving microcomputer with a receiver unit (the second microcomputer 30). This configuration enables the second microcomputer 30 to determine whether or not the reception of all data elements is complete by using the verification key 27 as a determining data element.In other words, in responding to the determination that the verification key 27 is contained in the data elements 1 to N stored in the receive data table 32, the second microcomputer 30 can determine, based on the verification key 33 held by the second microcomputer 30, that the reception of all data elements is complete.

[0038] Furthermore, the second microcomputer 30, acting as a receiving microcomputer, can use the last data element of the data elements to be sent as the verification key 27 to confirm or determine that all data elements sent by the first microcomputer 20, acting as the sending microcomputer, have been correctly received. The reason for this is described below.

[0039] According to a configuration as described above, the SIPI 31 in the second microcomputer 30, which acts as a receive-side microcomputer, is configured (i) to receive a data element sent by the SIPI 26 in the first microcomputer 20, which acts as a receive-side microcomputer, (ii) to write the received data element to the receive data table 32, and (iii) to return a receive notification ACK. This return of the receive notification ACK from the SIPI 31 in the second microcomputer 30 indicates that (i) the second microcomputer 30 can normally receive the data element sent by the SIPI 26 in the first microcomputer 20, and (ii) the received data element is correctly written to the receive data table 32. Subsequently, the first microcomputer 20 uses the receipt of the receive notification ACK as a trigger for the transmission process of the next data element.If the data elements up to the last data element N in the receiving data table 32 are stored in the second microcomputer 30, it is ensured that the data elements of data element 1 up to data element N-1, with the exception of the last data element N, are received normally by the second microcomputer 30 and correctly written into the data table.

[0040] It should be noted that the ACK (Received) notification for the last data element N is simply ignored, instead of being used as a trigger for the transmission process of the next data element, as is the case with the ACK notification for any data element other than the last data element N. Therefore, even if the ACK notification for the last data element N is not returned, the first microcomputer 20, for example, does not perform a retransmission of the last data element N and terminates the data transmission process without further processing. This does not guarantee or determine whether or not the last data element N is correctly received by the second microcomputer 30.

[0041] In this context, however, the present embodiment provides a configuration in which the first microcomputer 20, acting as a transmitting microcomputer, sends the verification key 27 as the last data element N, which can be compared by the second microcomputer 30, acting as a receiving microcomputer. Such a configuration enables the second microcomputer 30 to confirm or determine that the last data element N has been received correctly. That is, if it is determined that the data elements stored in the receiving data table 32 contain the verification key 27, the second microcomputer 30 can determine that the last data element N has been received normally and written to the receiving data table 32.If, on the other hand, the verification key 27 is not found in the receive data table 32 despite completion of the transmission process in the first microcomputer 20, this means that the last data element N was not received correctly by the second microcomputer 30. In this case, it may be preferable for the first microcomputer 20 to be instructed by the second microcomputer 30 to retransmit data elements, or for a safety measure to be implemented to restrict the control processing in the first microcomputer 20 and the second microcomputer 30 to only a subset of functions.

[0042] Several time points at which the second microcomputer 30 checks whether the verification key 27 is stored in the receive data table 32 can be designed as follows.

[0043] As described above, for example, the first microcomputer 20 can detect the completion of the transmission process of all data elements stored in the transmission data table 21 based on the data transmission completion notification from the DMAC 23. The first microcomputer 20 then issues a notification informing the second microcomputer 30 of the completion of the transmission process by means of a so-called handshake signal or the like. Upon receiving such a notification, the second microcomputer 30 can search the reception data table 32 to confirm whether or not the data elements stored in the reception data table 32 contain the verification key 27.

[0044] Alternatively, the second microcomputer 30 can search the receive data table 32 at predetermined time intervals to confirm whether or not the data elements stored in the receive data table 32 contain the verification key 27. In this case, if it is determined that the data elements have been correctly written to the receive data table 32, the data elements in the receive data table 32 can be cleared. This allows for the following determination: For example, if the verification key 27 cannot be found in the receive data table 32 after a predetermined time has elapsed since the last data element was written to the receive data table 32, it can be determined that the data elements have not been correctly written to the receive data table 32.

[0045] Although a preferred embodiment of the present disclosure has been described above, the present disclosure is not limited to this, but can be modified in various ways, as shown by way of example below.

[0046] The embodiment described above uses, for example, a verification key as a destination data element. Such a verification key, which is sent as the last data element of the data elements to be transmitted, can be compared between a sending microcomputer and a receiving microcomputer. However, the destination data element is not limited to such a verification key. According to an embodiment that is not part of the invention but serves to illustrate it, for example, a sending microcomputer can use quantity data indicating the quantity of all data elements to be transmitted as a destination data element; such quantity data as a destination data element can be sent as the first data element of the data elements to be transmitted (i.e., the data elements to be sent).In this case, the sending and receiving microcomputers can specify a memory location in the receiving data table for a data element to be sent first. This allows the receiving microcomputer to determine or recognize the (total) set of data elements to be received from the destination data element (i.e., from the data set data). Subsequently, when the data elements corresponding to the aforementioned total set of data elements have been written to the receiving database, the receiving microcomputer can determine that all data elements to be received have been fully received.

Claims

[1] Electronic control unit with multiple microcomputers (20, 30), each of which has: - a processing unit (28); - a data table (21, 32) configured to store data elements for sending or receiving; and - a transmitting and receiving unit (23 to 26, 31) configured to transmit or receive the data elements between the microcomputers (20, 30), wherein - the data table (21, 32) is able to store multiple data elements that are sent or received multiple times by the sending and receiving unit (23 to 26, 31), - as soon as the sending of the multiple data elements stored in the data table (21) for sending is started, the sending and receiving unit (23 to 26) in a sending-side microcomputer (20) sends all of the multiple data elements stored in the data table (21) for sending without intervention from the processing unit (28), wherein - the transmitting microcomputer (20) is one of the microcomputers (20, 30) that transmits the multiple data elements, - the multiple data elements being sent contain a determination data element to determine whether or not all of the multiple data elements stored in the data table (21) for sending in the sending-side microcomputer (20) are completely received by a receiving-side microcomputer (30), wherein - the receiving microcomputer (30) is another of the microcomputers (20, 30) that receives the multiple data elements, - the receiving microcomputer (30) determines, based on the destination data element, whether all of the multiple data elements have been fully received, - the microcomputers (20, 30) hold verification keys corresponding to the microcomputers (20, 30), wherein a verification key held by one of the microcomputers (20, 30) is verified by another of the microcomputers (20, 30), - the sending microcomputer (20) uses a corresponding verification key as the destination data element and sends the corresponding verification key as one of the last data elements of the multiple data elements being sent, - the receiving microcomputer (30) determines that all of the multiple data elements have been fully received by confirming the corresponding verification key as the destination data element, - the transmitting microcomputer (20), after transmitting the last data element, sends a transmission termination signal to the receiving microcomputer (30), and - the receiving microcomputer (30), after receiving the transmission termination signal, confirms whether or not the corresponding verification key is stored in the data table (32) for reception in the receiving microcomputer (30). [2] Electronic control unit according to claim 1, wherein the verification keys held by the microcomputers (20, 30) are configured to have an identical value. [3] Electronic control unit according to claim 1 or 2, wherein the verification keys held by the microcomputers (20, 30) are configured to change according to an identical rule. [4] Electronic control unit according to one of claims 1 to 3, wherein the transmitting and receiving unit (23 to 26) in the transmitting microcomputer (20) comprises the following: - a register (24) configured to store the data elements to be sent, and - a transmission unit (23) configured to transfer the data elements stored in the data table (21) to the register (24) for sending, wherein - the transmission unit (23) each time it completes the transmission from one of the multiple data elements to the register (24), transmits a new one of the multiple data elements from the data table (21) to the register (24) for sending, which enables the transmitting and receiving unit (23 to 26) in the transmitting microcomputer (20) to send all of the multiple data elements stored in the data table (21) for sending without intervention from the processing unit (28). [5] Electronic control unit according to claim 4, wherein - the transmitting and receiving unit (31) in the receiving microcomputer (30) sends a receive notification signal to the transmitting and receiving unit (23 to 26) in the transmitting microcomputer (20) each time it receives a data element during a single reception, wherein - the reception notification signal indicates that the one data element has been received; and - the transmission unit (23) in the transmitting microcomputer (20), upon receiving the receive notification signal as a trigger, transmits a new data element from the data table (21) to the register (24). [6] Electronic control unit according to claim 4 or 5, wherein the transmission unit (23) issues a completion notification to the processing unit (28) when all of the multiple data elements stored in the data table (21) have been fully transmitted.

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