Fin structures and manufacturing processes

Abstract

Structure (10), comprehensive: a plurality of fin structures (14) formed from substrate material (12); an insulator liner (16) covering the majority of fin structures (14); a semiconductor material (18) located between selected fin structures of the majority of fin structures (14); and Isolation areas (22) within spaces between the majority of fin structures (14), wherein the isolation areas are shallow trench isolation areas (22) located above the semiconductor material (18) between the selected fin structures of the majority of fin structures (14), wherein the semiconductor material (18) is located within selected spaces between the selected fin structures of the majority of fin structures (14), wherein selected distances between the selected fin structures of the majority of fin structures (14) each have a width (x) that is smaller than distances (x') between remaining fin structures of the majority of fin structures (14), wherein the spaces between the remaining selected fin structures of the majority of fin structures (14) are free of the semiconductor material (18).

Description

AREA OF INVENTION

[0001] The present invention relates to semiconductor structures and in particular fin structures and manufacturing processes. BACKGROUND

[0002] FinFET technologies incorporate fins formed from a substrate material. However, fin bending has long been a problem with FinFET technologies. Part of the fin bending is caused by the force generated during the curing of shallow trench insulation areas, resulting in material shrinkage and outward pull of the fins. The effect of fin bending worsens with each smaller technology node, negatively impacting device performance. For example, devices may exhibit inconsistent Vt shifts or other device variations due to fin bending.

[0003] Document US 2013 / 0193500A1 discloses a semiconductor device comprising: a substrate with a plurality of Fin field-effect transistors (FinFETs) and a plurality of Fin capacitors, each of the plurality of Fin capacitors further comprising: a plurality of silicon laminations, an electrical conductor between and parallel to two adjacent silicon laminations, and a first insulating material between the silicon laminations and the electrical conductor.

[0004] Patent application US 9,589,829 B1 describes a process comprising the following steps: forming a plurality of fins on a semiconductor substrate by defining a plurality of trenches in the substrate; forming a first insulating layer comprising silicon, oxygen, and carbon in the trenches between the plurality of fins, wherein the first insulating layer has a top surface that is on a plane below a top surface of the plurality of fins; forming a non-conforming second insulating layer above and in direct contact with the first insulating layer, wherein an entire top surface of the second insulating layer has a greater height than the top surface of the plurality of fins; flattening the second insulating layer to expose the top surface of the plurality of fins; performing at least one process step on the exposed plurality of fins.and removal of the entire second insulating material layer to expose the first insulating material layer after at least one process step has been performed.

[0005] Furthermore, according to US patent 2018 / 0108770A1, a method for forming a semiconductor device is known, comprising the following: providing at least two regions with fin structures, wherein the fin structures within each of the at least two regions have a first spacing and a second spacing is present between adjacent regions; forming a gate structure over the fin structures extending over the at least two regions, wherein the gate structure provides a first filler constriction between the fin structures separated by the first spacing; forming a material stack on the gate structure consisting of a first dielectric layer, a semiconductor-containing layer, and a second dielectric layer, wherein the second dielectric layer provides a second filler constriction between fin structures separated by the second spacing.Converting an exposed region of the semiconductor-containing layer into an oxide material layer, removing the second dielectric layer providing the second filler constriction, etching an opening in a remaining semiconductor-containing layer not converted into the oxide material layer exposed by removing the second filler constriction, using the oxide material layer as the first etch mask, etching an exposed portion of the first dielectric layer using the opening in the remaining portion of the semiconductor layer as the second etch mask, and etching a gate-cut region of the gate structure using the etched first dielectric layer as the etch mask for the gate-cut region.

[0006] Patent application US 2013 / 0221443A1 discloses a fin field-effect transistor (FinFET) comprising: a substrate comprising a primary surface, a plurality of first trenches with a first width extending downward from the primary surface of the substrate to a first height, wherein a first space between adjacent first trenches defines a first fin, and a plurality of second trenches with a second width less than the first width extending downward from the primary surface of the substrate to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin. SUMMARY

[0007] In one aspect of the invention, a structure according to independent claim 1 is provided. Advantageous embodiments thereof are defined in dependent claims 2 to 5.

[0008] In another aspect of the invention, a method according to independent claim 6 is provided. Advantageous embodiments thereof are defined in dependent claims 7 to 11.

[0009] In another aspect of the invention, a method according to independent claim 12 is provided. Advantageous embodiments thereof are defined in dependent claims 13 and 14. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention is described in the following detailed description with reference to the specified plurality of drawings by means of non-limiting examples of exemplary embodiments of the present invention. Fig. Figure 1 shows several fin structures and corresponding manufacturing processes according to aspects of the present invention. Fig. Figure 2 shows a dielectric liner on the plurality of fin structures and respective manufacturing processes according to aspects of the present invention. Fig. Figure 3 shows a layer of semiconductor material on the dielectric liner and corresponding manufacturing processes according to aspects of the present invention. Fig. Figure 4 shows an etching of the semiconductor material and the respective structures according to aspects of the present invention. Fig. Figure 5 shows, among other features, an insulating material between the majority of fin structures and respective structures according to aspects of the present invention. Fig. Figure 6 shows, among other features, recessed shallow trench isolation areas between the majority of fin structures and respective structures according to aspects of the present invention. Fig. Figure 7 shows a cross-section of the fin structure view using transmission electron microscopy (TEM). DETAILED DESCRIPTION

[0011] The present invention relates to semiconductor structures, and in particular fin structures and manufacturing processes. Specifically, the present invention relates to FinFET technologies with fins exhibiting reduced bending or with fins that do not bend. Advantageously, by implementing the processes described herein, it is now possible to reduce fin bending, which in turn improves the performance of the device. The processes described herein reduce variations in a device and can be easily integrated into existing, recorded processes.

[0012] In embodiments, the method for reducing fin bending comprises forming multiple fin structures with a liner made of an insulator material (e.g., oxide). The method further comprises depositing a conformal semiconductor material onto the fin structures. In embodiments, the semiconductor material can be a silicon material. The semiconductor material is etched to a desired thickness using a non-conformal etching process to achieve a specific desired thickness between selected adjacent fin structures. To form the STI regions, an insulator material is deposited over the semiconductor material and between the multiple fin structures, followed by curing and heating processes. The insulator material is then recessed to form the STI regions.

[0013] In alternative embodiments, the method for reducing bending comprises: forming fins by etching first and second trenches into a substrate to a first depth, each of the second trenches having a width greater than the width of the first trenches; forming a conformal dielectric layer on the substrate; depositing a conformal semiconductor layer on the substrate to fill the first trenches without filling the second trenches; and forming fin insulation by depositing, baking out, and removing the dielectric material.

[0014] The fin structures and related features of the present invention can be fabricated in various ways using a variety of different tools. Generally, however, the methods and tools are used to form structures with dimensions in the micrometer and nanometer range. The methods, i.e., technologies, used to fabricate the fin structures and related features of the present invention were adopted from integrated circuit (IC) technology. For example, the structures are built up on wafers and realized in material films that are patterned on the top surface of a wafer by photolithographic processes.In particular, three basic building blocks are used in the production of fin structures and related features: (i) deposition of thin material films onto a substrate, (ii) application of a structured mask to the films by photolithographic imaging, and (iii) selective etching of the films with respect to the mask.

[0015] Fig. Figure 1 shows several fin structures and corresponding manufacturing processes according to aspects of the present invention. More precisely, structure 10 can be made of Fig. 1. A substrate 12. In embodiments, the substrate 12 may be formed from a suitable material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or IINI compound semiconductors. In embodiments, the substrate 12 may be a bulk substrate or semiconductor-on-insulator (SOI) technologies.

[0016] A plurality of fins 14 are formed from the substrate 12 using conventional lithography and etching processes, e.g., reactive ion etching. In embodiments, the multiple fins 14 can be trapezoidal; although other shapes, e.g., rectangles, are also considered here. In the fabrication process, for example, a resist formed over the substrate 12 is exposed to energy (light) to form a structure (opening). An etching process with selective chemistry, e.g., reactive ion etching (RIE), is used to form one or more grooves 15 in the substrate 12 through the openings of the resist. The resist can then be removed by a conventional oxygen ashing process or another known removal method.

[0017] In these processes, the grooves 15 are formed in the substrate 12 to a predetermined depth, e.g., 150 nm, with each groove 15 having a spacing “x”, “x'”. In embodiments, the spacing “x'” has a width greater than the width of the spaces “x”. In embodiments, the spacing “x'” between adjacent fin structures 14 allows a conformal etching process of material coating the sidewalls of the majority of grooves 15, e.g., coating the grooves 15 and fin structures 14; whereas the spacing “x” between adjacent grooves allows only a non-conformal etching process of the material filling the grooves. In more specific embodiments, the spacing “x” can be approximately 15 nm; whereas the spacing “x'” is greater than 15 nm.

[0018] In alternative embodiments, the multiple fin structures 14 can be fabricated using a sidewall image transfer (SIT) technique. In the SIT technique, for example, a mandrel is formed on the substrate 12 using conventional deposition, lithography, and etching processes. For instance, in one example of an SIT technique, a mandrel material, e.g., SiO2, is deposited on the substrate 12 using conventional CVD processes. A resist is formed on the mandrel material and exposed to create a structure (openings). Reactive ion etching is then performed through the openings to form the mandrels. In embodiments, the mandrels can have different widths and / or spacings between the fin structures 14, depending on the desired dimensions.Spacers are formed on the sidewalls of the mandrels, preferably made of a material different from the mandrels, and formed using conventional deposition methods known to those skilled in the art. The spacers can, for example, have a width corresponding to the dimensions of the fin structures 14. The mandrels are removed or stripped using a conventional etching process that is selective with respect to the mandrel material. Etching is then carried out within the spacer spacing to form the sublithographic features. The sidewall spacers can then be removed. In embodiments, the fin structures 14 can also be formed during this or other structuring processes, or by other conventional structuring processes, as provided in the present invention.

[0019] Fig. Figure 2 shows a dielectric liner 16 deposited on a plurality of fin structures 14. In embodiments, the dielectric liner 16 is a conformal layer of an oxide material grown on the plurality of fin structures 14 using conventional growth processes. For example, the dielectric liner 16 can be grown using an in-situ vapor generation process. In embodiments, the dielectric liner 16 can have a thickness of approximately 1 nm (10 Å) to approximately 2 nm (20 Å); although other dimensions are also considered here. For example, the thickness of the dielectric liner 16 is less than the distance “x” between the plurality of adjacent fin structures 14. It should also be clear to those skilled in the art that the oxide material is not conventionally used for a crystal seed layer.

[0020] Fig. Figure 3 shows a layer of semiconductor material 18 on the dielectric liner 16 and corresponding fabrication processes according to aspects of the present invention. In embodiments, the semiconductor material 18 can be a silicon material. In alternative embodiments, the semiconductor material 18 is any material that can be consumed during subsequent fabrication processes, e.g., in annealing processes of oxide material. For example, the semiconductor material 18 can be a material identical to the materials of the substrate 12.

[0021] With further reference to Fig. 3. The semiconductor material 18 is conformally deposited to a desired thickness on the dielectric liner 16, e.g., over and between the multiple fin structures 14. In embodiments, the semiconductor material 18 can be deposited, for example, by chemical vapor deposition (CVD) or another conventional deposition method to a thickness of approximately 2.5 nm (25 Å) or more over and between the plurality of fin structures 14; although other dimensions are considered herein. In a more specific example, the semiconductor material 18 substantially or completely fills the smaller spaces “x” and coats the trenches 15 with the larger spaces “x’”, e.g., not filling the spaces “x’”.In more specific embodiments, the semiconductor material 18 can be deposited with any thickness that allows a non-conforming etching process within the smaller spaces “x” between adjacent fin structures 14 (e.g., with a thickness that does not allow complete consumption of the semiconductor material 18 during subsequent bake-out processes); while conformal etching of the semiconductor material 18 is enabled in the larger spaces “x’” (e.g., to reduce the thickness of the semiconductor material 18 so that it can be consumed during subsequent bake-out processes).

[0022] As in Fig. 4. The semiconductor material 18 is etched to reduce its thickness in certain regions, e.g., in the larger spaces “x’” between adjacent fin structures 14. Specifically, the semiconductor material in the trenches 15 is conformally etched with the larger spaces “x’” and nonconformally etched within the trenches 15 with the smaller spaces “x”. In this way, the thickness of the semiconductor material 18’ in the larger spaces “x’” is reduced more than the thickness of the semiconductor material 18” in the smaller spaces “x”. For example, the thickness of the semiconductor material 18’ in the larger spaces “x’” can be about 2 nm (20 Å) to 2.5 nm (25 Å) or less, which allows for consumption of the semiconductor material 18’ during subsequent bake-out processes (e.g., wet and dry); whereas the semiconductor material 18” has a thickness that does not allow for consumption during the subsequent bake-out processes.In a non-restrictive illustrative example, the height of the semiconductor material 18" in the trenches 15 with intervals "x" can be approximately 30% to 40% of the height of the fin structures 14.

[0023] Fig. Figure 5 shows, among other features, an insulating material 20 deposited between the multiple fin structures 14. In embodiments, the insulating material 20 is an insulator material, e.g., an oxide. In more specific embodiments, the insulating material 20 is a flowable oxide material. The insulating material 20 is subjected to a curing process known to those skilled in the art, followed by a chemical-mechanical polishing process (CMP process) and a bake-out process (represented by the arrows in Figure 5). Fig. 5) During the annealing process, the majority of fin structures 14 will not bend (e.g., remain vertically straight) due to the thickness of the semiconductor material 18' within the smaller spaces "x" on the sides of the majority of fin structures 14. During the annealing process, the semiconductor material 18' is also consumed by the insulating material 20, e.g., oxide. More precisely, when the thin film of Si, e.g., about 2 nm (20 Å) to 2.5 nm (25 Å) or less, is annealed in the presence of oxygen, the Si is consumed, forming a layer of SiO2.

[0024] In Fig. 6 The oxide layer 16 is omitted to form shallow trench insulation areas 22 between the multiple fin structures. In embodiments, the oxide layer 16 can be omitted by a selective etching process, e.g., RIE. The oxide layer 16 should be located above the Si material 18" in the trenches 15 at a distance "x".

[0025] Fig. Figure 7 shows a cross-sectional view of the fin structure using transmission electron microscopy (TEM). As shown in Fig. 6 An oxide layer is omitted to form shallow trench insulation areas 22 between the multiple fin structures. In embodiments, the oxide layer can be omitted by a selective etching process, e.g., RIE. The oxide layer 16 should be located above the Si material 18" in the trenches 15 at a distance "x".

[0026] The process(s) described above are used in the manufacture of IC chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., a single wafer containing multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic substrate with leads attached to a motherboard or other parent carrier) or in a multi-chip package (e.g., a ceramic substrate with surface contacts and / or buried contacts). In each case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input device and a central processing unit.

Claims

[1] Structure (10), comprising: a plurality of fin structures (14) formed from substrate material (12); an insulator liner (16) covering the majority of fin structures (14); a semiconductor material (18) located between selected fin structures of the majority of fin structures (14); and Isolation areas (22) within spaces between the majority of fin structures (14), wherein the isolation areas are shallow trench isolation areas (22) located above the semiconductor material (18) between the selected fin structures of the majority of fin structures (14), wherein the semiconductor material (18) is located within selected spaces between the selected fin structures of the majority of fin structures (14), wherein selected distances between the selected fin structures of the majority of fin structures (14) each have a width (x) that is smaller than distances (x') between remaining fin structures of the majority of fin structures (14), wherein the spaces between the remaining selected fin structures of the majority of fin structures (14) are free of the semiconductor material (18). [2] Structure (10) according to claim 1, wherein the insulator liner (16) is an oxide. [3] Structure (10) according to claim 1, wherein the semiconductor material (18) is located at a height that is lower than the height of the plurality of fin structures (14). [4] Structure (10) according to claim 1, wherein the majority of fin structures (14) are vertically straight. [5] Structure (10) according to claim 1, wherein the semiconductor material (18) is Si. [6] Procedure, comprehensive: a formation of multiple fin structures (14); a formation of an insulator liner (16) over the majority of fin structures (14); a deposition of a conformally thick semiconductor material (18) over and between the multiple fin structures (14); an etching of the semiconductor material (18) to a predetermined thickness; a deposition of insulating material (20) over the etched semiconductor material (18', 18"); a heating of the insulating material (20); and a recess of the insulator material (20). [7] Method according to claim 6, wherein the etching of the semiconductor material (18) is a non-conforming etching process within smaller spaces between adjacent fin structures of the plurality of fin structures (14) and a conformal etching process within larger spaces between remaining adjacent fin structures of the plurality of fin structures (14). [8] Method according to claim 7, wherein the semiconductor material (18) which is subjected to the non-conforming etching process is not consumed during the baking out of the insulator material (20). [9] Method according to claim 8, wherein the semiconductor material (18) which is subjected to the conformal etching process is consumed during the baking out of the insulator material (20). [10] Method according to claim 9, wherein the semiconductor material (18) subjected to the non-conforming etching process is provided in spaces between adjacent fin structures that are smaller than the semiconductor material (18) subjected to the conforming etching process. [11] Method according to claim 10, further comprising removing the insulator material (20) to a height below the plurality of fin structures (14) and above the semiconductor material (18). [12] Procedures, including: a formation of a plurality of fin structures (14) from a substrate material (12) by etching first and second trenches (15) into the substrate material (12) to a first depth, each of the second trenches (15) having a width greater than a width of the first trenches (15); a formation of a conformal dielectric layer (16) on the substrate material (12) and on the multiple fin structures (14); a filling of the first trenches (15) and a coating of the second trenches (15) with conformal semiconductor material (18); and a formation of fin isolation areas (22) within the first trenches (15) and the second trenches (15). [13] Method according to claim 12, wherein the semiconductor material (18) does not fill the second trenches (15). [14] Method according to claim 13, wherein the formation of the fin insulation areas (22) comprises depositing, curing and removing dielectric material (20) within the first and second trenches (15).

Images