GATE STRUCTURES IN SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE

Abstract

Method comprising: Depositing a high-k gate dielectric layer (92, 92B) over and along sidewalls of a semiconductor fin (52); Depositing an n-type work function metal layer (102, 102A) over the high-k gate dielectric layer (92, 92B); Performing a passivation treatment on the high-k gate dielectric layer (92, 92B) through the n-type work function metal layer (102, 102A) such that a first fluorine concentration of a first portion of the high-k gate dielectric layer (92, 92B) on an upper surface of the semiconductor fin (52) and a second fluorine concentration of a second portion of the high-k gate dielectric layer (92, 92B) on a sidewall of the semiconductor fin (52) are each in a range from 1.0 at% to 40.0 at%, wherein the passivation treatment comprises a remote plasma process; and Depositing a fill metal (108) over the n-work function metal layer (102, 102A) to form a metal gate stack (110) over the high-k gate dielectric layer (92, 92B), the metal gate stack (110) comprising the n-work function metal layer (102, 102A) and the fill metal (108).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which makes it possible to integrate more components into a given area. However, while the minimum feature size is reduced, additional problems arise that need to be solved. US 2017 / 0 170 027 A1 describes a method for diffusing fluorine atoms into a gate stack with a high-k dielectric using a thermal treatment. US 2017 / 0 110 551 A1 describes a treatment of a work function metal with fluorine to remove an oxidized layer from an upper surface of the work function metal layer. Further reference is made to the documents US 2014 / 0 319 620 A1 and US 2017 / 0 186 853 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of the various elements may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows an example of a FinFET in a three-dimensional view according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 19E, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 22A, Fig. 22B, Fig. 23A and Fig. 23B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 18C shows a process chamber for performing processes on a wafer according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0006] Various embodiments provide a passivation treatment for one or more gate dielectric layers of a transistor (e.g., a fin field-effect transistor (FinFET)). The passivation treatment comprises introducing a passivation species (e.g., fluorine, nitrogen, or the like) into the one or more gate dielectric layers using a remote plasma process. The passivation species may be introduced in the form of radicals (e.g., fluorine radicals, nitrogen radicals, or the like). The passivation species may help repair defects (e.g., dangling bonds, oxygen vacancies, or the like) in the gate dielectric layer(s), thereby improving device performance.In some embodiments, an n-type work function metal above the gate dielectric layer(s) may facilitate the passivation treatment by attracting the passivation species into the one or more gate dielectric layers. By using a remote plasma process, improved uniformity and a desired doping concentration of the passivation species in the gate dielectric layer(s) may be achieved. Furthermore, the passivation treatment may be performed at a relatively low temperature (e.g., with a low thermal budget), reducing the risk of transistor damage as a result of the passivation treatment.

[0007] Fig. 1 shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed within the substrate 50, and the fin 52 protrudes above and between adjacent isolation regions 56. Although the isolation regions 56 are described / shown as being separate from the substrate 50, the term "substrate" may be used herein to refer only to the semiconductor substrate or to a semiconductor substrate including the isolation regions. Further, although the fin 52 is shown as a single, continuous material as the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to portions extending between the adjacent isolation regions 56.

[0008] A gate dielectric layer 92 is located along sidewalls and above a top surface of the fin 52, and a gate electrode 94 is located above the gate dielectric layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. Fig. 1 further shows reference cross-sections used in later figures. Cross-section AA runs along a longitudinal axis of the gate electrode 94 and, for example, in a direction perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA and runs along a longitudinal axis of the fin 52 and, for example, in a direction of current flow between the source / drain regions 82 of the FinFET. Cross-section CC runs parallel to cross-section AA and extends through a source / drain region of the FinFET. The subsequent figures refer to these reference cross-sections for clarity.

[0009] Some of the embodiments described herein are described in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Some embodiments also contemplate aspects used in planar devices, such as planar FETs.

[0010] The Fig. 2 to 23B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2 to 7 show the Fig. 1 shown reference cross-section AA, except that several fins / FinFETs are present. Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A and Fig. 23A are along the Fig. 1 shown reference cross-section AA, and the Fig. 8B, 9B, 10B, 11B, 12B, 13B, 14B, 14C, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B and 23B are along a similar Fig. 1 shown cross-section BB, except that several fins / FinFETs are present. Fig. 10C and Fig. 10D are along the Fig. 1 shown reference cross section CC, except that several fins / FinFETs are present

[0011] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped or undoped (e.g., with a p-type or an n-type dopant). The substrate 50 may be part of a wafer 10, which may start from a silicon wafer. Generally, an SOI substrate consists of a layer of a semiconductor material formed on an insulating layer. The insulating layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates may also be used, for example, a multilayer or a gradient substrate.In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor, for example, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0012] The substrate 50 includes a region 50N and a region 50P. The region 50N may be used to form n-type devices such as NMOS transistors, e.g., n-type FinFETs. The region 50P may be used to form p-type devices such as PMOS transistors, e.g., p-type FinFETs. The region 50N may be spatially separated from the region 50P (as shown by the divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region 50N and the region 50P.

[0013] In Fig. 3, fins 52 are formed in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 may be formed in the substrate 50 by etching trenches in the substrate 50. The etching may be any suitable etching process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), or a combination thereof. The etching may be anisotropic.

[0014] The fins can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes so that structures can be created that have, for example, center-to-center pitches smaller than those otherwise obtainable with a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0015] In Fig. 4, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based deposition of material in a remote plasma system and post-bake to convert to another material such as an oxide), the like, or a combination thereof. Other insulating materials produced by any suitable process may be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. An annealing process may be performed after the insulating material is formed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52.Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along a surface of the substrate 50 and the fins 52. A filler material similar to that described above may then be formed over the liner.

[0016] In Fig. 5, a removal process is performed on the insulating material 54 to remove excess insulating material 54 over the fins 52. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process, an etch-back process, combinations thereof, or the like may be used. The planarization process exposes the fins 52 so that top surfaces of the fins 52 and the insulating material are flat after the planarization process is complete.

[0017] In Fig. 6, the insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material is recessed such that, in region 50N and region 50P, upper portions of the fins 52 protrude between adjacent STI regions 56. Further, the upper surfaces of the STI regions 56 may have a flat surface as shown, a convex surface, a concave surface (such as a concave), or a combination thereof. The upper surfaces of the STI regions 56 may be formed flat, convex, and / or concave by a suitable etch. The STI regions 56 may be recessed using a suitable etching process, such as one that is selective to the insulating material material (e.g., that etches the insulating material material at a faster rate than the fins 52 material).For example, chemical oxide removal can be used with a suitable etching process using, for example, dilute hydrofluoric (dHF) acid.

[0018] The one relating to the Fig. The process described in Figures 2 to 6 is only one example of how the fins 52 may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer, thereby forming fins. Additionally, in some embodiments, heteroepitaxial structures may be used for the fins 52. For example, the fins 52 may Fig. 5, and a material different from that of the fins 52 may be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 include the recessed material as well as the epitaxially grown material disposed over the recessed material. In yet another embodiment, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer. Heteroepitaxial structures may then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer, thereby forming the fins 52.In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be doped in situ during growth, which may make prior and subsequent implantations unnecessary, although in situ doping and implantation doping may be used together.

[0019] Furthermore, it may be advantageous to epitaxially grow a material in the region 50N (e.g., an NMOS region) that is different from the material in the region 50P (e.g., a PMOS region). In various embodiments, the upper portions of the fins 52 may be made of silicon germanium (Si x Ge 1-x, where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming the III-V compound semiconductor include, without limitation, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0020] Furthermore, Fig. 6 Suitable wells (not shown) may be formed in fins 52 and / or substrate 50. In some embodiments, a p-well may be formed in region 50N, and an n-well may be formed in region 50P. In some embodiments, a p-well or an n-well are formed in both region 50N and region 50P.

[0021] In embodiments with different well types, the different implantation steps for region 50N and region 50P may be achieved using photoresist or other masks (not shown). For example, a photoresist may be formed over fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, for example, a PMOS region. The photoresist may be formed using a spin-coating technique and patterned using suitable photolithography techniques. After the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may serve as a mask to substantially prevent the n-type impurities from being implanted into region 50N, for example, an NMOS region.The n-impurities may be phosphorus, arsenic or the like, ranging up to a concentration of 10. 18 cm -3 or less, for example between about 10 17 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example by a suitable ashing process.

[0022] After implanting region 50P, a photoresist is formed in region 50P over fins 52 and STI regions 56. The photoresist is patterned to expose region 50N of substrate 50, for example, the NMOS region. The photoresist may be formed using a spin-coating technique and patterned using suitable photolithography techniques. After the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may serve as a mask to substantially prevent p-type impurities from being implanted into region 50P, for example, the PMOS region. The p-type impurities may be boron, BF2, or the like, which may be introduced into the region up to a concentration of 10 18 cm -3 or less, for example between about 10 17 cm -3 and about 10 18 cm -3After implantation, the photoresist can be removed, for example, by a suitable ashing process.

[0023] After implanting region 50N and region 50P, an anneal may be performed to activate the implanted p- and / or n-type impurities. In some embodiments, the epitaxial fin materials may be doped in situ during growth, which may obviate the need for implantation, although in situ and implantation doping may be used together.

[0024] In Fig. 7, a dummy dielectric layer 60 is formed on the fins 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to suitable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized, for example, by a CMP. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material and may be selected from a group including polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.In one embodiment, amorphous silicon is deposited and recrystallized to create polysilicon. Dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit conductive materials. Dummy gate layer 62 may be made of other materials that have high etch selectivity to the etching of the isolation regions. Mask layer 64 may include, for example, SiN, SiON, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed continuously over region 50N and region 50P. In some embodiments, separate dummy gate layers may be formed in region 50N and region 50P, and separate mask layers may be formed in region 50N and region 50P.It is noted that for illustrative purposes, the dummy dielectric layer 60 is shown covering only the fins 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the STI regions 56 extending between the dummy gate layer 62 and the STI regions 56.

[0025] The Fig. 8A to 16B show various additional steps in the manufacture of the devices of the embodiment. Fig. 8A to 16B show features in both the region 50N and the region 50P. For example, the features shown in the Fig. The structures shown in Figures 8A through 16B may be applicable to both region 50N and region 50P. Differences in the structures of region 50N and region 50P (if any) are described in the text accompanying each of the figures.

[0026] In the Fig. 8A and Fig. 8B, the mask layer 64 may be patterned using suitable photolithography and etching techniques to form masks 74. The pattern of the masks 74 may then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the masks 74 may also be transferred to the dummy dielectric layer 60 using a suitable etching technique to form dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The pattern of the masks 74 may be used to spatially separate each of the dummy gates 72 from adjacent dummy gates 72. The dummy gates 72 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective epitaxial fins 52.

[0027] Furthermore, in the Fig. 8A and Fig. 8B Gate seal spacers 80 may be formed on exposed surfaces of the dummy gates 72, the masks 74, and / or the fins 52. Thermal oxidation or deposition followed by an anisotropic etch may form the gate seal spacers 80.

[0028] After forming the gate seal spacers 80, implantations for lightly doped source / drain (LDD) regions (not separately shown) may be performed. In the embodiments with different device types, similar to the above in Fig. 6, a mask such as a photoresist may be formed over region 50N while region 50P is exposed, and impurities of a suitable type (e.g., n-type or p-type) may be implanted into the exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over region 50P while region 50N is exposed, and impurities of a suitable type may be implanted into the exposed fins 52 in region 50N. The mask may then be removed. The n-type impurities may be the previously described n-type impurities, and the p-type impurities may be the previously described p-type impurities. The lightly doped source / drain regions may have an impurity concentration of about 10 15 cm -3 up to about 10 16 cm -3Annealing can be used to activate the implanted impurities.

[0029] In the Fig. 9A and Fig. 9B, gate spacers 86 are formed on the gate sealing spacers 80 along sidewalls of the dummy gates 72 and the masks 74. The gate spacers 86 may be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacers 86 may be silicon nitride, SiCN, a combination thereof, or the like.

[0030] In the Fig. 10A and Fig. 10B, epitaxial source / drain regions 82 are formed in the fins 52 to exert a voltage in the respective channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is disposed between a corresponding pair of adjacent epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52. In some embodiments, the gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit subsequently formed gates of the resulting FinFETs.

[0031] The epitaxial source / drain regions 82 in region 50N, e.g., the NMOS region, may be formed by masking region 50P, e.g., the PMOS region, and etching the source / drain regions of the fins 52 in region 50N to form recesses in the fins 52. Then, the epitaxial source / drain regions 82 in region 50N are epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any suitable material, as is suitable for n-type FinFETs. For example, if the fin 52 is made of silicon, the epitaxial source / drain regions 82 in region 50N may include materials that exert tensile strain in the channel region 58, such as Si, SiC, SiCP, SiP, or the like. The epitaxial source / drain regions 82 in the region 50N may have surfaces that are raised from respective surfaces of the fins 52 and may have facets.

[0032] The epitaxial source / drain regions 82 in the region 50P, e.g., the PMOS region, may be formed by masking the region 50N, e.g., the NMOS region, and etching the source / drain regions of the fins 52 in the region 50P to form recesses in the fins 52. Then, the epitaxial source / drain regions 82 in the region 50P are epitaxially grown in the recesses. The epitaxial source / drain regions 82 may include any suitable material, such as is suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P may include materials that exert compressive stress in the channel region 58, such as SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain regions 82 in the region 50P may also have surfaces raised from respective surfaces of the fins 52 and may have facets.

[0033] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form the source / drain regions, similar to the previously described method for forming the lightly doped source / drain regions, followed by annealing. The source / drain regions may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 The n- and / or p-type impurities for the source / drain regions may be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 82 may be doped in situ during growth.

[0034] As a result of the epitaxial processes used to form the epitaxial source / drain regions 82 in region 50N and region 50P, the top surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond sidewalls of fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as shown in Fig. 10C. In further embodiments, adjacent source / drain regions 82 remain separated after the epitaxial process is completed, as shown in Fig. 10D shown.

[0035] In the Fig. 11A and Fig. 11B, a first ILD 88 will be installed over the Fig. 10A and Fig. 10B. The first ILD 88 may be formed from a dielectric and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectrics may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. The semiconductor materials may be amorphous silicon, silicon germanium (Si x Ge 1-x, where x can be between approximately 0 and 1), pure germanium, or the like. Other insulating or semiconductor materials formed by a suitable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the hard mask 74, and the gate spacers 86. The CESL 87 may include a dielectric such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with a different etch rate than the material of the overlying first ILD 88.

[0036] In the Fig. 12A and Fig. 12B, a planarization process such as CMP may be performed to level the top surface of the first ILD 88 with the top surfaces of the dummy gates 72. The planarization process may also remove the masks 74 on the dummy gates 72 and portions of the gate seal spacers 80 and the gate spacers 86 along sidewalls of the masks 74. After the planarization process, top surfaces of the dummy gates 72, the gate seal spacers 80, the gate spacers 86, and the first ILD 88 are planar. Accordingly, the top surfaces of the dummy gates 72 are exposed through the first ILD 88.

[0037] The Fig. 13A to 21D illustrate a gate replacement process in which the dummy gates 72 are removed and replaced with a metal gate. As part of the gate replacement process, one or more gate dielectric layers are formed between the metal gate and the fins 52. In various embodiments, a passivation treatment is performed to introduce a passivation species (e.g., fluorine, nitrogen, combinations thereof, or the like) into the one or more gate dielectric layers and reduce defects present therein. The passivation treatment may be a remote plasma treatment, which advantageously provides a desired concentration of the passivation species with a high degree of uniformity across the gate dielectric layers.Another advantage of remote plasma treatment is that it can be performed at a relatively low process temperature, reducing the risk of damage to the device.

[0038] In the Fig. 13A and Fig. 13B, the dummy gates 72 are removed in one or more etch steps to form recesses 90. Portions of the dielectric layer 60 in the recesses 90 may also be removed. In some embodiments, only the dummy gates 72 are removed, and the dummy dielectric layer 60 remains and is exposed through the recesses 90. In some embodiments, the dummy dielectric layer 60 is removed from recesses 90 in a first region of a die (e.g., a core logic region) and remains in recesses 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 72 are removed using an anisotropic dry etch process. For example, the etching process may include a dry etching process using one or more reactant gases that selectively etch the dummy gates 72 without etching the first ILD 88 or the gate spacers 86.Each recess 90 exposes a channel region 58 of a respective fin 52. Each channel region 58 is disposed between an adjacent pair of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may be used as an etch stop layer when the dummy gates 72 are etched. The dummy dielectric layer 60 may then be removed, if desired, after the removal of the dummy gates 72.

[0039] In the Fig. 14A and Fig. 14B, one or more gate dielectric layers 92 are deposited over the channel regions 58 and along their sidewalls. The gate dielectric layers 92 are conformally deposited in the recesses 90, for example, on top surfaces and sidewalls of the fins 52 and on sidewalls of the gate seal spacers 80 / gate spacers 86. The gate dielectric layers 92 may also be formed on a top surface of the STIs 56 and the first ILD 88. According to some embodiments, the gate dielectric layers 92 include silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers 92 are a high-k dielectric, and in these embodiments, the gate dielectric layers 92 may have a k value greater than about 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof.In some embodiments, the gate dielectric layers 92 may include a layer of high-k dielectric and an underlying silicon oxide layer, both formed after the removal of the dummy gates 72. The formation methods of the gate dielectric layers 92 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy gate dielectric 60 remain in the recesses 90, the gate dielectric layers 92 may include a material of the dummy gate dielectric 60 (e.g., SiO). Due to manufacturing limitations of the deposition process, the gate dielectric layers 92 may include defects, such as open bonds, oxygen vacancies, combinations thereof, or the like.

[0040] Next, Fig. 15A and Fig. 15B, an optional adhesion layer 94 may be deposited over the gate dielectric layers 92. The adhesion layer 94 may be a metal-containing material such as titanium silicon nitride (TSiN), titanium nitride, combinations thereof, multilayers thereof, or the like. Forming the adhesion layer 94 may include one or more steps of MBD, ALD, PECVD, PVD, combinations thereof, or the like. After the adhesion layer 94 is deposited, an optional post-metal anneal 96 may be performed to improve the adhesion properties of the adhesion layer 94 and / or the gate dielectric layers 92. In some embodiments, the post-metal anneal 96 may range from about 100°C to about 1200°C.

[0041] In the Fig. 16A and Fig. 16B, an optional capping layer 98 may be deposited on the adhesion layer 94. The capping layer 98 may be a semiconductor material such as silicon or the like. Forming the capping layer 98 may include CVD, ALD, PVD, or the like. After the capping layer 98 is deposited, an optional post-capping anneal 100 may be performed to further improve the adhesion properties of the adhesion layer 94 and / or the gate dielectric layers 92. In some embodiments, the post-capping anneal 96 may be in the range of about 100°C to about 1200°C. After the post-capping anneal 100, the capping layer 98 may be removed using a suitable etching process, such as a dry or wet etching process. Removing the capping layer 98 may further remove a portion of the underlying adhesion layer 94. The Fig. 15A, Fig. 15B, Fig. 16A and Fig. 16B are optional, and one or both of the steps may be omitted in various embodiments.

[0042] In the Fig. 17A and Fig. 17B, ​​work function metal (WFM) layers 102 are deposited over the gate dielectric layers 92. The WFM layers 102 may be a metal-containing material such as Ti, TiN, TiO, Ta, TaN, TaC, Co, Ru, Al, W, combinations thereof, multilayers thereof, or the like. In embodiments where the adhesion layer 94 is formed, the WFM layers 102 include the adhesion layer 94.

[0043] For example, Fig. 17C a detailed view of area 200 in Fig. 17A according to one embodiment. As in Fig. 17C, the gate dielectric layers 92 include a first layer 92A (e.g., a silicon oxide, an interface layer) and a second layer 92B (e.g., a high-k gate oxide). The first layer 92A may comprise a remaining portion of the dummy gate dielectric 60 (see the Fig. 12A and Fig. 12B), a silicon oxide layer formed after removing the dummy gate 72, a combination thereof, or the like.

[0044] The WFM layers 102 may include the optional adhesion layer 94, an n-WFM layer 102A, and an optional cap layer 102B. The n-WFM layer 102A may include a combination of n-metal (e.g., Al, Ti, Ta, or the like) and another metal (e.g., Ti, TiN, Ta, TaN, TaC, TiC, TiCSi, or the like). Forming the n-WFM layer 102A may include one or more deposition steps using CVD, ALD, PVD, or the like. In some embodiments, the deposition process(es) may be performed at a temperature that facilitates diffusion of the n-metal through the n-WFM layer 102A. In some embodiments, one or more annealing steps may be performed to facilitate the diffusion of the n-type metal through the n-WFM layer 102A. As described in more detail below, a concentration of the n-type metal (e.g.,Al) in the n-WFM layer 102A can be selected such that a desired concentration of passivation species in the underlying gate dielectric layers 92 is achieved in subsequent process steps.

[0045] The cap layer 102B may be a metal-containing material such as Ti, TiN, TiO, Ta, TaN, TaC, TiC, TiCSi, or the like. The cap layer 102B may contain a common element with the n-WFM layer 102A. For example, in some embodiments, the cap layer 102B contains Ti, and the n-WFM layer 102A contains TiAl or TiAlN. A concentration of the n-metal may gradually decrease in the cap layer 102B in the direction of arrow 202. In some embodiments, a top surface of the cap layer 102B may be substantially free of the n-metal. The cap layer 102B is optional and may be omitted in some embodiments.

[0046] The Fig. The embodiments of the WFM layers 102 shown in Figure 17C are only an example, and layers may be omitted or added in further embodiments. For example, although a single n-WFM layer 102A is shown, multiple n-WFM layers 102A (e.g., with different concentrations of the n-metal) may be used depending on a desired electrical property of the resulting transistor. The configuration of Fig. 17C can be used in the 50N range to form n-type devices, for example NMOS transistors such as n-FinFETs.

[0047] Fig. Figure 17D shows a detailed view of area 200 in Fig. 17A according to an alternative embodiment. The configuration of Fig. 17D can be configured by Fig. 17C, where like reference numerals indicate like elements formed using like processes.

[0048] The configuration of Fig. 17D additionally includes a p-WFM layer 102C between the n-WFM layer 102A and the gate dielectric layers 92. The p-WFM layer 102C may include a metal (e.g., Ti, TiN, Ta, TaN, TaC, WC, WCN, MoN, or the like), and the p-WFM layer 102C may be substantially free of the n-type metal in the n-WFM layer 102A. Forming the p-WFM layer 102C may include one or more deposition steps using CVD, ALD, PVD, or the like. Although a single p-WFM layer 102C is shown, multiple p-WFM layers may be used depending on a desired electrical property of the resulting transistor. The configuration of Fig. 17D can be used in the 50P region to form p-type devices, for example, PMOS transistors such as p-FinFETs.

[0049] In the Fig. 18A and Fig. 18B, a passivation treatment is applied to the WFM layers 102. The passivation treatment may include introducing passivation species 104 into exposed surfaces of the WFM layers 102. In some embodiments, the passivation species 104 include radicals, such as fluorine radicals, nitrogen radicals, combinations thereof, or the like. The passivation species 104 may interact with the n-metal (e.g., Al) in the WFM layers 102 (e.g., in the n-WFM layer 102A, see the Fig. 17C and Fig. 17D) may be highly reactive. As a result, the n-metal in the WFM layers 102 may attract the passivation species 104 and pull them into the underlying gate dielectric layers 92. The passivation species 104 passivate defects (e.g., fill oxygen vacancies, close open bonds, etc.) in the gate dielectric layers 92. As a result, a film quality of the gate dielectric layers 92 may be improved, and the reliability and performance of the device may be improved. In some embodiments, the passivation species 104 may diffuse only into a subset of the gate dielectric layers 92. For example, the passivation species 104 may contact the second layer 92B (e.g., the high-k gate oxide, see the Fig. 17C and Fig. 17D) without removing the first layer 92A (e.g., a silicon oxide, an interface layer, see the Fig. 17C and Fig. 17D) of the gate dielectric layers 92. In further embodiments, the passivation species 104 may be present throughout the gate dielectric layers 92.

[0050] Fig. Figure 18C shows a processing tool during the passivation treatment of wafer 10 according to various embodiments. Wafer 10 is placed on a chuck 220 in a region 212 of the processing tool.

[0051] The processing tool includes an inlet 202 that allows a process gas to flow into the tool, as indicated by arrow 203. The process gas may include a precursor. In embodiments where the passivation species 104 include fluorine or nitrogen, the precursor may be any fluorine- and / or nitrogen-containing precursor, such as NF3, NH3, combinations thereof, or the like. The process gas may further include a carrier gas, such as H2, N2, He, combinations thereof, or the like. In the process gas, the precursor may be diluted by the carrier gas, and a concentration of the precursor gas may range from about 1.0 atomic fraction (at. %) to about 40.0 at. %. A concentration, flow rate, and time duration at which the process gas flows may be selected according to a desired concentration of the passivation species 104 in the gate dielectric layers 92 (see the Fig. 18A and Fig. 18B).

[0052] The process gas flows into a region 204, and plasma ions are generated from the process gas. Any method for generating plasma ions from the process gas can be used. For example, in Fig. 18C plasma ions 208 are generated between two electrodes 206 and 210. The upper electrode 206 may be an inductively coupled plasma (ICP) coil. Other plasma generation methods may be used in further embodiments. Depending on the plasma generation technique, the plasma ions 208 may be generated with a power in a range of about 5 W to about 5000 W and a pressure in a range of about 1.333 Pa (10 mTorr) to 666.6 Pa (5000 mTorr). Furthermore, the passivation treatment may be performed at a relatively low temperature, for example, less than about 100°C, e.g., in the range of about 15°C to about 87°C. The relatively low heat budget of the passivation treatment advantageously reduces the risk of damage to the wafer 10.

[0053] The lower electrode 210 may form a filter that spatially separates the region 204 (where, for example, the plasma ions are generated) from the region 212 (where, for example, the wafer 10 is located). Thus, in some embodiments, the passivation treatment may be a remote plasma treatment. The lower electrode 210 may include a plurality of openings through which a plasma afterglow or relaxing plasma (which provides radicals) is generated from the plasma ions 208. Other plasma ion filtering methods (e.g., ion filter plasma tools) may be used in further embodiments. The wafer 10 is exposed to the passivation species 104 (e.g., radicals from the plasma afterglow). Excess gases may be pumped out of the process chamber through one or more exhausts 214, as shown by arrows 213.

[0054] In various embodiments, the use of radicals instead of plasma ions to perform the passivation treatment offers advantages. For example, the radicals are relatively low-energy compared to plasma ions, and thus the risk of damaging the wafer 10 can be reduced. Furthermore, the use of a plasma afterglow is isotropic compared to a plasma ion implantation, which is anisotropic (e.g., directional and dependent on the implantation angle). Thus, using an isotropic process can achieve increased uniformity of the radicals in the gate dielectric layers 92. Furthermore, the remote plasma process does not depend on the uniformity of a gap-fill deposition process to diffuse the passivation species into the gate dielectric layers 92.Thus, the remote plasma process may be useful for passivating gate dielectric layers formed on high aspect ratio fins and / or closely spaced fins. Additionally, a concentration of the passivation species may be controlled by adjusting a concentration of the n-type metal (e.g., Al) in the WFM layers 102 and / or processing parameters (e.g., precursor concentration, precursor flow rate, duration, plasma power, plasma process, combinations thereof, or the like) of the passivation treatment. Remote plasma passivation treatments of the embodiment allow a concentration of the passivation species to be easily tuned to a desired range (e.g., a range that effectively passivates the gate dielectric layers 92 without significantly damaging the WFM layers 102).

[0055] The Fig. 19A and Fig. 19B show the WFM layers 102 and the gate dielectric layers 92 after the passivation treatment. Fig. 19C and Fig. 19D show detailed views of area 200 in Fig. 19A. Fig. Figure 19C shows an embodiment that leads to Fig. 17C belongs, and Fig. 19D shows an embodiment that leads to Fig. 17D. Through the passivation treatment, the passivation species (e.g., F, N, or the like) may be present in the WFM layers 102 and the gate dielectric layers 92. As shown in the Fig. 19C and Fig. As shown in Figure 19D, the passivation species may be present only in the second layer 92B (e.g., the high-k gate oxide) without being present in the underlying first layer 92A (e.g., the interface layer). In further embodiments, the passivation species may be present in the gate dielectric layers 92.

[0056] Alternatively, if the WFM layers 102 contain a common element as a passivation species prior to the passivation treatment, a higher than stoichiometric concentration of the passivation species may be present in the WFM layers 102. For example, in embodiments where the WFM layers 102 contain nitrogen prior to the passivation treatment and the passivation species is nitrogen, the WFM layers 102 may contain a higher than stoichiometric nitrogen concentration as a result of the passivation treatment.

[0057] In some embodiments, a concentration of the passivation species in the WFM layers 102 on a top surface of the channel region 58 is in the range of 1.0 at.% to 40.0 at.%, and a concentration of the passivation species in the WFM layers 102 on sidewalls of the channel region 58 is in the range of 1.0 at.% to 40.0 at.%. In some embodiments, a concentration of the passivation species in the gate dielectric layers 92 (e.g., in the high-k gate oxide layer 92B) on a top surface of the channel region 58 is in the range of 1.0 at.% to 40.0 at.%, and a concentration of the passivation species in the gate dielectric layers 92 (e.g., in the high-k gate oxide layer 92B) on sidewalls of the channel region 58 is in the range of 1.0 at.% to 40.0 at.%.It has been observed that by having the passivation species at these concentrations, the defects of the gate dielectric layers 92 can be advantageously mitigated, improving device reliability and performance. For example, it has been observed that concentrations below the above ranges result in insufficient passivation in the high-k dielectric layers 92, resulting in lesser benefits in device performance and reliability. It has further been observed that concentrations higher than the above ranges result in reduced film quality of the WFM layers 102, resulting in degradation in device performance and reliability.

[0058] Fig. 19E shows a profile of a passivated region 250 on the channel region 58. The passivated region 250 is a region containing the passivation species on the channel regions 58. For example, the passivated region 250 may include portions of the WFM layers 102 and the gate dielectric layers 92 containing the passivation species. In some embodiments, the passivated region 250 may be formed by all of the WFM layers 102 and may further be formed by all of the gate dielectric layers 92. A profile of the passivated region 250 may be determined, for example, by performing elemental mapping of the passivation species (e.g., fluorine) of a transmission electron microscope (TEM) image or a scanning electron microscope (SEM) image of the relevant region using energy-dispersive X-ray spectroscopy analysis.

[0059] In some embodiments, a thickness T1 of the passivated region 250 on sidewalls of the channel region 58 may be in the range of about 2.0 nm to about 10.0 nm, and a thickness T2 of the passivated region 250 on a top surface of the channel region 58 may be in the range of about 2.0 nm to about 10.0 nm. Furthermore, a ratio of an average thickness of the passivated region 250 on the sidewalls of the channel region 58 to an average thickness of the passivated region 250 on the top surface of the channel region 58 may be in the range of about 0.8:1.0 to about 0.9:1.0. It has been observed that when the passivated region 250 has a thickness within the above ranges and / or maintains the above ratios, sufficient uniformity of the passivation treatment is achieved to achieve good defect treatment coverage and improved device performance.

[0060] In the Fig. 20A and Fig. 20B, a liner 106 is deposited over the WFM layers 102. The liner 106 may be a metal-containing material such as TiN, TiO, TaN, TaC, combinations thereof, multilayers thereof, or the like. Forming the liner 106 may include one or more deposition steps using CVD, ALD, PVD, or the like. In some embodiments, the liner 106 may serve as a barrier layer, adhesion layer, wetting layer, or the like. A thickness of the liner 106 may range from about 1.0 nm (10 Å) to about 10.0 nm (100 Å), for example, about 4.0 nm (40 Å). It has been observed that when the liner 106 has this range of thicknesses, improved device performance can be achieved. For example, a thinner liner 106 may provide insufficient adhesion with unacceptably high resistance.Because the liner 106 is deposited after the passivation treatment, the liner 106 may be substantially free of the passivation species. Alternatively, the liner 106 may be deposited with a stoichiometric concentration of a common element (e.g., N) of the passivation species. For example, in some embodiments, the liner 106 may be formed from stoichiometric TiN, and the passivation species may also be nitrogen.

[0061] Next, the Fig. 21A and Fig. 21B, a filler metal 108 is formed over the lining 106. The Fig. 21C and Fig. 21D show detailed views of area 200 in Fig. 21A. Fig. 21C shows an embodiment that leads to Fig. 17C belongs, and Fig. 21D shows an embodiment that leads to Fig. 17D. The filler metal 108 may be a metal-containing material such as Co, Ru, Al, W, combinations thereof, multilayers thereof, or the like. Forming the filler metal 108 may include one or more deposition steps using CVD, ALD, PVD, or the like. As shown in the Fig. 21C and Fig. 21D, the fill metal 108 may be a multi-layer structure, for example, including a first layer 108A and a second layer 108B. For example, in embodiments where the fill metal 108 contains W, the first layer 108A may be a fluorine-free tungsten (FFW) layer and the second layer 108B may be a fluorine-poor tungsten (LFW) layer. The number of layers of the fill metal 108 may be greater or lesser in further embodiments. Because the fill metal 108 is deposited after the passivation treatment, the fill metal 108 may be substantially free of the passivating radicals. Thus, gate electrodes 110 are formed that include the WFM layers 102, the liner 106, and the fill metal 108. Alternatively, the fill metal 108 may be deposited with a common element with the passivation species. For example, the filler metal may contain 108 LFW and the passivation species may be fluorine.

[0062] After filling the gate electrodes 110, a planarization process such as CMP may be performed to remove the excess portions of the gate dielectric layers 92 and the gate electrode 110 material, with the excess portions lying above the top surface of the ILD 88. The remaining portions of the gate electrode 110 material and the gate dielectric layers 92 thus form replacement gates of the resulting FinFETs. The gate electrodes 110 and the gate dielectric layers 92 may collectively be referred to as a "gate stack." The gate and the gate stacks may extend along sidewalls of a channel region 58 of the fins 52.

[0063] The formation of the gate dielectric layers 92 in the region 50N and in the region 50P may occur simultaneously, such that the gate dielectric layers 92 in both regions are made of the same materials, and the formation of the gate electrodes 110 may occur simultaneously, such that the gate electrodes 110 in both regions are made of the same materials. In some embodiments, the gate dielectric layers 92 in both regions may be formed by different processes, such that the gate dielectric layers 92 may be different materials, and / or the gate electrodes 110 may be formed by different processes in both regions, such that the gate electrodes 110 may be different materials. Different masking steps may be used to mask and expose appropriate regions if separate processes are used.

[0064] In the Fig. 22A and Fig. 22B, a second ILD 112 is deposited over the first ILD 88. In one embodiment, the second ILD 112 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 112 is formed from a dielectric such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable process, such as CVD and PECVD.

[0065] In the Fig. 23A and Fig.23B, gate contacts 114 and source / drain contacts 116 are formed by the second ILD 112 and the first ILD 88, according to some embodiments. Openings for the source / drain contacts 116 are formed by the first and second ILDs 88 and 116, and openings for the gate contact 114 are formed by the second ILD 112. The openings may be formed using suitable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a top surface of the ILD 112.Remaining liner and conductive material form the source / drain contacts 116 and the gate contacts 114 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 116. The source / drain contacts 116 are spatially and electrically connected to the epitaxial source / drain regions 82, and the gate contacts 114 are spatially and electrically connected to the gate electrodes 110. The source / drain contacts 116 and the gate contacts 114 may be formed in different processes or in the same process. Although they are shown formed in the same cross-sections, it should be noted that both the source / drain contacts 116 and the gate contacts 114 may be formed in different cross-sections, which may avoid shorting the contacts.

[0066] Various embodiments provide a passivation treatment for one or more gate dielectric layers of a transistor formed on a wafer. The passivation treatment comprises introducing a passivation species (e.g., fluorine, nitrogen, or the like) into the one or more gate dielectric layers using a remote plasma process. The passivation species may be introduced by exposing the wafer to radicals (e.g., fluorine radicals, nitrogen radicals, or the like). The passivation species may help repair defects (e.g., dangling bonds, oxygen vacancies, or the like) in the gate dielectric layer(s), thereby improving device performance.In some embodiments, an n-type work function metal above the gate dielectric layer(s) may facilitate the passivation treatment by attracting the passivation species into the one or more gate dielectric layers. By using a remote plasma process, improved uniformity and a desired doping concentration of the passivation species in the gate dielectric layer(s) may be achieved. Furthermore, the passivation treatment may be performed at a relatively low temperature (e.g., with a low thermal budget), reducing the risk of transistor damage as a result of the passivation treatment.

[0067] In one embodiment, a method comprises depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin; depositing an n-type work function metal layer over the high-k gate dielectric layer; performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer, wherein the passivation treatment comprises a remote plasma process; and depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer, wherein the metal gate stack includes the n-type work function metal layer and the fill metal. Optionally, in one embodiment, the remote plasma process comprises exposing the high-k gate dielectric layer to radicals. Optionally, in one embodiment, the radicals are fluorine radicals, nitrogen radicals, or a combination thereof.Optionally, in one embodiment, the n-type workfunction metal layer contains aluminum, and wherein the passivation treatment comprises using the aluminum to attract the radicals into a high-k gate dielectric layer. Optionally, in one embodiment, depositing the high-k gate dielectric layer may comprise depositing a high-k gate dielectric layer containing oxygen vacancies, dangling bonds, or a combination thereof. Optionally, in one embodiment, the passivation treatment provides a passivation species in the high-k gate dielectric layer to fill the oxygen vacancies, close the dangling bonds, or a combination thereof. Optionally, in one embodiment, the method further comprises depositing an adhesion layer between the high-k gate dielectric layer and the n-type workfunction metal layer; and depositing a capping layer over the n-type workfunction metal layer.Optionally, in one embodiment, the method further comprises depositing a barrier layer between the n-type work function metal layer and the fill metal. Optionally, in one embodiment, the method further comprises depositing a p-type work function metal layer between the high-k gate dielectric layer and the n-type work function metal layer. Optionally, in one embodiment, depositing the fill metal over the n-type work function metal layer comprises depositing the fill metal over the n-type work function metal layer after the passivation treatment.

[0068] According to another embodiment, a method comprises forming a semiconductor fin extending over an isolation region in a semiconductor device; depositing a high-k gate dielectric layer over and along sidewalls of the semiconductor fin, wherein the high-k gate dielectric layer includes deposition defects; depositing a first workfunction metal layer over the high-k gate dielectric layer, wherein the first workfunction metal layer includes an n-type metal; introducing a passivation species into the high-k gate dielectric layer through the first workfunction metal layer, wherein introducing the passivation species comprises: generating a plasma; filtering the plasma to provide radicals from a plasma afterglow, exposing the semiconductor device to the radicals; and depositing filler metal over the first workfunction metal layer after introducing the passivation species.Optionally, in one embodiment, generating the plasma includes generating the plasma from a precursor gas containing fluorine, nitrogen, or a combination thereof. Optionally, in one embodiment, the method further comprises forming a second work function metal layer between the high-k gate dielectric layer and the first work function metal layer, wherein the second work function metal layer is a p-type work function metal layer. Optionally, in one embodiment, introducing the passivation species into the high-k gate dielectric layer through the first work function metal layer includes using the n-type metal of the first work function metal layer to attract the radicals. Optionally, in one embodiment, introducing the passivation species is performed at a temperature of less than 100°C.Optionally, in one embodiment, the radicals are fluorine radicals, nitrogen radicals, or a combination thereof, and wherein the n-metal is aluminum.

[0069] According to another embodiment, a device includes a semiconductor fin extending over an isolation region; a high-k gate dielectric layer over and along sidewalls of the semiconductor fin, wherein the high-k gate dielectric layer includes fluorine; and a gate stack over and along sidewalls of the high-k gate dielectric layer. The gate stack includes a first workfunction metal layer including an n-type metal and fluorine; and a first fill metal layer over the first workfunction metal layer, wherein the first fill metal layer is free of fluorine. Optionally, in one embodiment, the gate stack further includes an adhesion layer under the first workfunction metal layer; a cap layer over the first workfunction metal layer; a barrier layer over the cap layer and under the first fill metal layer; and a second fill metal layer over the first fill metal layer, wherein the second fill metal layer includes fluorine.Optionally, in one embodiment, a fluorine concentration of a portion of the high-k gate dielectric layer on a top surface of the semiconductor fin is in a range of 1.0 at.% to 40.0 at.%, and wherein a fluorine concentration of a portion of the high-k gate dielectric layer on a sidewall of the semiconductor fin is in a range of 1.0 at.% to 40.0 at.%. Optionally, in one embodiment, a fluorine concentration of a portion of the first workfunction metal layer on a top surface of the semiconductor fin is in a range of 1.0 at.% to 40.0 at.%, and wherein a fluorine concentration of a portion of the first workfunction metal layer on a sidewall of the semiconductor fin is in a range of 1.0 at.% to 40.0 at.%.

Claims

[1] Method comprising: Depositing a high-k gate dielectric layer (92, 92B) over and along sidewalls of a semiconductor fin (52); Depositing an n-type work function metal layer (102, 102A) over the high-k gate dielectric layer (92, 92B); Performing a passivation treatment on the high-k gate dielectric layer (92, 92B) through the n-type work function metal layer (102, 102A) such that a first fluorine concentration of a first portion of the high-k gate dielectric layer (92, 92B) on an upper surface of the semiconductor fin (52) and a second fluorine concentration of a second portion of the high-k gate dielectric layer (92, 92B) on a sidewall of the semiconductor fin (52) are each in a range from 1.0 at% to 40.0 at%, wherein the passivation treatment comprises a remote plasma process; and Depositing a fill metal (108) over the n-work function metal layer (102, 102A) to form a metal gate stack (110) over the high-k gate dielectric layer (92, 92B), the metal gate stack (110) comprising the n-work function metal layer (102, 102A) and the fill metal (108). [2] The method of claim 1, wherein the remote plasma process comprises exposing the high-k gate dielectric layer (92, 92B) to radicals. [3] The process of claim 2, wherein the radicals are fluorine radicals, nitrogen radicals or a combination thereof. [4] The method of claim 2 or 3, wherein the n-type work function metal layer (102, 102A) includes aluminum, and wherein the passivation treatment includes using the aluminum to attract the radicals into the high-k gate dielectric layer (92, 92B). [5] The method of any preceding claim, wherein depositing the high-k gate dielectric layer (92, 92B) comprises depositing a high-k gate dielectric layer (92, 92B) containing oxygen vacancies, unsaturated bonds, or a combination thereof. [6] The method of claim 5, wherein the passivation treatment provides a passivation species (104) in the high-k gate dielectric layer (92, 92B) to fill the oxygen vacancies, saturate the unsaturated bonds, or a combination thereof. [7] Method according to one of the preceding claims, further comprising: Depositing an adhesion layer (94) between the high-k gate dielectric layer (92, 92B) and the n-type work function metal layer (102A); and Depositing a capping layer (102B) over the n-work function metal layer (102A). [8] The method of any preceding claim, further comprising depositing a barrier layer (106) between the n-type work function metal layer (102, 102A) and the fill metal (108). [9] The method of any preceding claim, further comprising depositing a p-type work function metal layer (102C) between the high-k gate dielectric layer (92, 92B) and the n-type work function metal layer (102, 102A). [10] The method of any preceding claim, wherein depositing the fill metal (108) over the n-work function metal layer (102, 102A) comprises depositing the fill metal (108) over the n-work function metal layer (102, 102A) after the passivation treatment. [11] A method comprising: Forming a semiconductor fin (52) extending over an isolation region (56) in a semiconductor device; Depositing a high-k gate dielectric layer (92, 92B) over and along sidewalls of the semiconductor fin (52), the high-k gate dielectric layer (92, 92B) containing deposition defects; depositing a first workfunction metal layer (102) over the high-k gate dielectric layer (92, 92B), the first workfunction metal layer (102) containing an n-type metal (102A); Introducing a passivation species (104) into the high-k gate dielectric layer (92, 92B) through the first work function metal layer (102) such that a first concentration of the passivation species (104) in a first portion of the high-k gate dielectric layer (92, 92B) and a second concentration of the passivation species (104) in a second portion of the high-k gate dielectric layer (92, 92B) are each in a range from 1.0 at.% to 40.0 at.%, wherein the first portion of the high-k gate dielectric layer (92, 92B) is arranged on an upper surface of the semiconductor fin (52) and the second portion of the high-k gate dielectric layer (92, 92B) is arranged on a sidewall of the semiconductor fin (52), wherein the introduction of the passivation species (104) includes: generating a plasma (208); Filtering the plasma (208) to provide radicals from an afterglow of the plasma (208), wherein the semiconductor device is exposed to the radicals; and Depositing filler metal (108) over the first work function metal layer (102) after introducing the passivation species (104). [12] The method of claim 11, wherein generating the plasma (208) comprises generating the plasma (208) from a precursor gas containing fluorine, nitrogen, or a combination thereof. [13] The method of claim 11 or 12, further comprising forming a second work function metal layer (102C) between the high-k gate dielectric layer (92, 92B) and the first work function metal layer (102), wherein the second work function metal layer (102C) is a p-type work function metal layer (102C). [14] The method of any one of claims 11 to 13, wherein introducing the passivation species (104) into the high-k gate dielectric layer (92, 92B) through the first work function metal layer (102) comprises using the n-type metal (102A) of the first work function metal layer (102) to attract the radicals. [15] The method of any one of claims 11 to 14, wherein the introduction of the passivation species (104) is carried out at a temperature of less than 100°C. [16] A method according to any one of claims 11 to 15, wherein the radicals are fluorine radicals, nitrogen radicals or a combination thereof, and wherein the n-metal (102A) is aluminum. [17] Device comprising: a semiconductor fin (52) extending over an insulating region (56); a high-k gate dielectric layer (92, 92B) over and along sidewalls of the semiconductor fin (52), wherein the high-k gate dielectric layer (92, 92B) contains fluorine, and wherein a fluorine concentration of a portion of the high-k gate dielectric layer (92, 92B) on a top surface of the semiconductor fin (52) is in a range of 1.0 at.% to 40.0 at.%, and wherein a fluorine concentration of a portion of the high-k gate dielectric layer (92, 92B) on a sidewall of the semiconductor fin (52) is in a range of 1.0 at.% to 40.0 at.%; and a gate stack over and along sidewalls of the high-k gate dielectric layer (92, 92B), the gate stack comprising: a first work function metal layer (102, 102A) containing an n-metal and fluorine, wherein the n-metal contains aluminum; and a first fill metal layer (108) over the first work function metal layer (102, 102A), wherein the first fill metal layer (108, 108A) is free of fluorine. [18] The device of claim 17, wherein the gate stack further comprises: an adhesion layer (94) under the first work function metal layer (102A); a cap layer (102B) over the first work function metal layer (102A); a barrier layer above the cover layer (102B) and below the first filler metal layer (108); and a second filler metal layer (108B) over the first filler metal layer (108A), the second filler metal layer (108B) containing fluorine [19] The device according to any one of claims 17 to 18, wherein a fluorine concentration of a part of the first work function metal layer (102, 102A) on an upper surface of the semiconductor fin (52) is in a range of 1.0 at% to 40.0 at%, and wherein a fluorine concentration of a part of the first work function metal layer (102, 102A) on a sidewall of the semiconductor fin (52) is in a range of 1.0 at% to 40.0 at%.

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