Semiconductor storage structure

Abstract

Semiconductor device (300) comprising: a first gate structure (312) formed over a first active region (304), wherein the first active region (304) has a fin structure; a first metal conductor (304-3) arranged above, and perpendicular to, the first gate structure (312), wherein the first metal conductor is electrically connected to the first gate structure using a first conductive via (356), wherein the first conductive via (356) contacts the first gate structure (312), and wherein the first conductive via is arranged above the first active region (304); and a second metal conductor (304-2) and a third metal conductor (304-4), both of which run parallel to the first metal conductor (304-3) and are arranged on opposite sides of the first metal conductor, wherein the second metal conductor is electrically connected to a source / drain region of the first active region (304) using a second conductive via (340), and wherein the third metal conductor is electrically connected to the source / drain region of the first active region using a third conductive via (342); and where the first gate structure (312) has a first program word line.

Description

BACKGROUND

[0001] Among semiconductor storage devices, non-volatile memory (NVM) devices can be used to store data even when the power supply to the storage device is turned off. In various examples, NVM devices can include read-only memory (ROM), magnetic memory, optical memory, or flash memory, among others. Different types of NVM devices can be programmed once, a few times, or many times. NVM devices that are programmed once and cannot be overwritten are called one-time programmable (OTP) NVM devices. OTP NVM devices are widely used for embedded NVM applications due to their compatibility with existing processes, scalability, reliability, and security.Depending on the target application, device requirements, or process requirements, OTP NVM devices can be implemented using floating gate, e-fuse, or antifuse technology.

[0002] Regardless of the technology used to implement an OTP-NVM device, the cell current (T cell ) plays an important role in the operation of NVM devices. For example, reduced cell current can lead to device failure (such as due to read errors). Furthermore, the voltage of a program word line (WLP) is known to correlate with cell current. In some examples, increased gate resistance can cause an undesirable parasitic voltage drop, resulting in a reduced WLP voltage for a particular memory cell, which can lead to reduced cell current and device failure.

[0003] Therefore, existing techniques have not proven entirely satisfactory in all respects.

[0004] US 2017 / 0 154 671 A1 describes an SRAM memory cell, wherein the word line comprises a first metal line in the M2 metal layer and a second metal line in the M4 metal layer, and wherein the first and second metal lines are connected via vias so that a word line resistance is reduced.

[0005] US 2004 / 0 173 836 A1 describes a dynamic random access memory device in which the capacitor of a memory cell is arranged above a transistor and below the bit line. The bit line is connected to the source / drain region of the transistor via a via, and the drain / source region of the transistor is connected to the bottom electrode of the capacitor via another via.

[0006] DE 10 2019 101 570 B4 describes an IC layout diagram of an anti-fuse cell in which a bit line runs perpendicular to a plurality of gate regions.

[0007] The article by Lienig, J., "Electromigration and its impact on physical design in future technologies." In: Proceedings of the 2013 ACM International symposium on Physical Design (ISPD '13), 2013, pp. 33-40, describes that the resistance to electromigration increases when the line width is reduced below the average grain size of the line material, so that the lines exhibit a bamboo structure. To exploit this, a network of a large number of lines exhibiting the bamboo structure is proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be exaggerated or reduced as needed for clarity of discussion. Fig. 1 is a layout view of a semiconductor memory structure; Fig. Figure 2 illustrates a circuit diagram of an equivalent circuit of a portion of the semiconductor memory structure of Fig. 1; Fig. 3 is a layout view of a semiconductor memory structure according to some embodiments; Fig. 4 is a view of a portion of the semiconductor memory structure of Fig. 3 according to some embodiments; Fig. 5 illustrates a circuit diagram of an equivalent circuit of the Fig. 4, a portion of the semiconductor memory structure according to some embodiments; Fig. 6 is a view of a portion of the semiconductor memory structure of Fig. 3, further comprising source / drain metal layers, according to some embodiments; and Fig. 7 is a cross-sectional view of the semiconductor memory structure of Fig. 6 along a plane substantially parallel to a plane passing through the section line AA' of Fig. 6 defined level according to some embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or configurations discussed.

[0010] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0011] Among semiconductor storage devices, non-volatile memory (NVM) devices can be used to store data even when the power supply to the storage device is turned off. NVM devices can include read-only memory (ROM), magnetic memory, optical memory, or flash memory. Different types of NVM devices can be programmed once, a few times, or many times. NVM devices that are programmed once and cannot be overwritten are called one-time programmable (OTP) NVM devices. OTP NVM devices are widely used for embedded NVM applications due to their compatibility with existing processes, scalability, reliability, and security.Depending on the target application, device requirements, or process requirements, OTP NVM devices can be implemented using floating-gate, e-fuse, or antifuse technology. Regardless of the technology used to implement an OTP NVM device, the cell current (T) plays a key role. cell ) plays an important role in the operation of NVM devices, as discussed in more detail below.

[0012] In various examples, electrical connections to individual NVM devices may be established during a back-end-of-line (BEOL) manufacturing process. In a BEOL process, a network of conductive metal interconnect layers (such as copper) is formed to connect various components of a semiconductor integrated circuit (IC). The network of conductive metal interconnect layers is formed within an interlayer dielectric (ILD) material, which may include a low-K dielectric material. The ILD material electrically isolates adjacent metal interconnect layers from each other—both within a given interconnect level and between adjacent levels of interconnect layers.For example, damascene processes such as single damascene and double damascene processes are routinely used to fabricate multilevel interconnect structures. In a damascene process, trenches and vias are formed within and through an ILD layer and filled with a conductive material (such as copper or a copper alloy) to create metallization lines and vertical conductive paths (vias) between adjacent interconnect layers.

[0013] We now turn to the example of Fig. 1, which illustrates a layout view of a semiconductor memory structure 100. The semiconductor memory structure 100 may include the active regions 102, 104, 106. In some cases, the active regions 102, 104, 106 may include fin structures used to form a fin field-effect transistor (FinFET). In some examples, the active regions 102, 104, 106 may also include doped regions, such as doped semiconductor regions within which source / drain regions of the transistor may be formed. In some cases, an ion implantation process may be used to incorporate a dopant species into a semiconductor substrate within the active regions 102, 104, 106. In various cases, the active regions 102, 104, 106 may all be arranged at the same height, for example, within the same substrate layer or conductive layer.In some embodiments, the active regions 102, 104, 106 have a width 'W1' of about 50-70 nm.

[0014] In some embodiments, the semiconductor memory structure 100 is formed on a semiconductor substrate, which may include a silicon substrate, and may include various layers, including conductive or insulating layers formed on the substrate. The substrate may include various doping configurations depending on the design requirements, as known in the art. The substrate may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate may also include a compound semiconductor and / or an alloy semiconductor. Furthermore, in some embodiments, the substrate may include an epitaxial (epi) layer, the substrate may be strained to enhance performance, the substrate may include a silicon-on-insulator (SOI) structure, and / or the substrate may include other suitable optimization features.

[0015] In various examples, isolation regions, such as shallow trench isolation (STI) regions, may be formed on the semiconductor substrate to isolate adjacent devices (e.g., transistors, NVM devices, etc.) from each other. Such isolation regions may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials known in the art. In one embodiment, the isolation regions are formed by etching trenches in the substrate. The trenches may then be filled with insulating material, followed by a chemical mechanical polishing (CMP) process. However, other embodiments are also possible. In some embodiments, the isolation regions may have a multi-layer structure, for example, including one or more liner layers.

[0016] The semiconductor memory structure 100 may also include gate structures 108, 110, 112, 114, 116, 118, 120, 122. As shown, at least some of the gate structures are formed over the active regions 102, 104, 106. As an example, an array of transistors may be formed at the intersections of the gate structures and the active regions 102, 104, 106 (such as transistors T1 and T2 shown in Fig. 1), where the array of transistors can form an NVM memory array. Thus, the gate structures can function as word lines of the memory array in various cases.

[0017] In some embodiments, the gate structures 108, 110, 112, 114, 116, 118, 120, 122 may include a gate dielectric and a gate electrode disposed on the gate dielectric. In some embodiments, the gate dielectric may include an interfacial layer, such as a silicon oxide (SiO2) or silicon oxynitride (SiON). In some examples, the gate dielectric includes a high-k dielectric layer, such as hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer may also contain other high-k dielectrics such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HffaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material.In further embodiments, the gate dielectric may include silicon dioxide or another suitable dielectric. In various embodiments, the gate electrode includes a conductive layer such as W, Ti, TiN, TiAl, TiAlN, Ta, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, CoSi, Ni, NiSi, combinations thereof, and / or other suitable compositions. In some embodiments, the gate electrode may alternately or additionally include a polysilicon layer. In some embodiments, sidewall spacers are formed on the sidewalls of the gate structures. Such sidewall spacers may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0018] The semiconductor memory structure 100 further includes metal lines 124, 126, 128, 130, 132, 134, 136 formed within the same conductive or interconnect layer. In some embodiments, the metal lines may be formed within a metal 0 interconnect layer (M0 interconnect layer). The metal lines may include copper, aluminum, or other suitable metals or metal alloys. As shown in Fig. 1, metal line 124 may be electrically connected to the underlying gate structure 112 through a conductive via 138 to form a first program wordline node (WLPo node), and metal line 132 may be electrically connected to the underlying gate structure 118 through a conductive via 140 to form a second program wordline node (WLP1 node). Furthermore, metal line 136 may be electrically connected to the underlying gate structure 114 through a conductive via 142 to form a first read wordline node (WLRo node), and metal line 128 may be electrically connected to the underlying gate structure 116 through a conductive via 144 to form a second read wordline node (WLR1 node). For example, the metal lines 124, 128, 132, 136 may have a width 'W2' of about 30-50 nm.In some cases, an area of ​​the conductive vias 138, 140, 142, 144 is about 50-200 nm. 2 .

[0019] In some examples, metal line 126 may be electrically connected to the underlying active region 102 (which may, for example, include an underlying source / drain region) through a conductive via 146, metal line 130 may be electrically connected to the underlying active region 104 through a conductive via 148, and metal line 134 may be electrically connected to the underlying active region 106 through a conductive via 150. Thus, metal lines 126, 130, 134 may function as bitlines of the memory array. In some embodiments, the bitlines (metal lines 126, 130, 134) have a width 'W3' of about 50-70 nm. In some cases, an area of ​​conductive vias 146, 148, 150 is about 400-700 nm. 2. Furthermore, in some embodiments, the distance 'S1' between the metal lines connected to the gate structures and adjacent bit lines (such as between metal lines 124 and 126) is about 40-75 nm.

[0020] As previously noted, the cell current (I cell ) plays an important role in the operation of NVM devices, and reduced cell current can lead to device failures (such as read errors). It is known that the voltage of a wordline program (WLP) is correlated with cell current. Furthermore, in some examples, increased gate resistance can cause an undesirable parasitic voltage drop, resulting in a reduced WLP voltage for a particular device in the memory array, which can lead to reduced cell current and device failure. Referring to the example of Fig. 1, we consider a case where a programming voltage 'V1' is applied to the WLPo node. In some examples, the applied programming voltage 'V1' may be sufficient to program a first bit in transistor T1. However, at least in part due to the up-scale dimensions of modern semiconductor technologies, a significant wordline resistance 'R1' may exist between the WLPo node and transistor T2. In some embodiments, the resistance 'R1' may be at least about 10 kiloohms (kΩ). In particular, the resistance 'R1' may result in a drop in the applied programming voltage 'V1' such that a wordline program voltage 'V2' at transistor T2 is less than 'V1', and such that the voltage 'V2' is insufficient to program a second bit at transistor T2. As a result of the failed programming of transistor T2, a subsequent read operation of transistor T2 also fails.In various cases, the above-mentioned problems may occur in conjunction with increased wordline resistance when an applied WLP voltage is used to program two or more bits (for example, two or more transistors along a given wordline).

[0021] Fig. 2 illustrates a circuit diagram 200 of an equivalent circuit of a portion of the semiconductor memory structure 100. For example, the circuit diagram 200 shows the WLPo node (to which the programming voltage 'V1' is applied), the wordline resistor 'R1', and the reduced voltage 'V2' at the gate of transistor T2. The circuit diagram 200 also shows the first wordline read node (WLRo node) at a gate of a transistor T3, a select gate input ('SEL'), and a bitline node 'BL' (e.g., a conductive via 148 connected to the metal line 130). As noted above, and due to the wordline resistor 'R1', the voltage 'V2' may not be sufficient to program the transistor T2. Therefore, in some embodiments, a subsequent read operation of transistor T2 results in a reduced cell current (I cell ) and a read error. In various embodiments, the cell current (I cell) can also be reduced due to the individual bit line (such as metal line 126) and the individual bit line contact (such as conductive via 146), which in turn have increased resistance due to their upscaled dimensions.

[0022] Embodiments of the present disclosure provide advantages over the prior art, although it should be understood that other embodiments may provide other advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, the embodiments discussed herein include a semiconductor memory structure having a design that provides a program wordline (WLP) gate connection and a read wordline (WLR) gate connection directly over an active region and having an independent wordline for each bit, thereby reducing an effective gate resistance (or effective wordline resistance).In various embodiments, the disclosed semiconductor memory structure also includes multiple bitlines and multiple bitline contacts to the underlying active region for each bit, thereby reducing the effective bitline resistance. As a result of the disclosed semiconductor memory structure design, the effective gate resistance is reduced by more than an order of magnitude, and the cell current (I) is expected to decrease. cell) by about 1.3 times. In some examples, the reduced gate resistance provides a substantially negligible parasitic voltage drop, ensuring a high-quality WLP voltage for a given device in a memory array. Furthermore, the improved cell current provides more reliable operation of NVM devices. In some embodiments, the semiconductor memory structure disclosed herein includes an OTP NVM device. However, in some cases, the semiconductor memory structure may include other types of NVM devices. Additional details of embodiments of the present disclosure are set forth below, and additional benefits and / or other advantages will become apparent to those skilled in the art having the benefit of the present disclosure.

[0023] We now turn Fig. 3, where a layout view of a semiconductor memory structure 300 is illustrated according to some embodiments. The semiconductor memory structure 300 may include active regions 302, 304, 306. The active regions 302, 304, 306 include fin structures used to form a FinFET. In some examples, the active regions 302, 304, 306 may also include doped regions, such as doped semiconductor regions within which transistor source / drain regions may be formed, as described above. In various cases, the active regions 302, 304, 306 may all be arranged at the same height, for example, within the same substrate layer or conductive layer. In some embodiments, the active regions 302, 304, 306 have a width 'W1' in a range of about 60-150 nm.

[0024] In some embodiments, semiconductor memory structure 300 is formed on a semiconductor substrate, similar to the substrate discussed above with respect to semiconductor memory structure 100. Semiconductor memory structure 300 may also include isolation regions (e.g., STI regions) formed on the semiconductor substrate to isolate adjacent devices (e.g., transistors, NVM devices, etc.) from each other.

[0025] Semiconductor memory structure 300 may also include gate structures 308, 310, 312, 314, 316, 318, 320, 322. As shown, at least some of the gate structures are formed over the active regions 302, 304, 306. For example, an array of transistors may be formed at intersections of the gate structures and the active regions 302, 304, 306, where the array of transistors may form an NVM memory array. Thus, the gate structures may function as wordlines of the memory array in various cases. In some embodiments, the gate structures 308, 310, 312, 314, 316, 318, 320, 322 may include a gate dielectric, a gate electrode disposed on the gate dielectric, and sidewall spacers, as described above.

[0026] In contrast to the semiconductor memory structure 100, which had seven metal lines (metal lines 124, 126, 128, 130, 132, 134, 136) across three different active regions 102, 104, 106, the semiconductor memory structure 300, in some embodiments, has seven metal lines for each of the active regions 302, 304, 306 to reduce the effective gate resistance and the bit line resistance, as discussed in more detail below. For example, the semiconductor memory structure 300, as shown in Fig. 3, metal lines 302-1, 302-2, 302-3, 302-4, 302-5, 302-6, 302-7 formed within the same conductive or interconnect layer (e.g., within an M0 interconnect layer), each of which is associated with the active region 302. Similarly, semiconductor memory structure 300 includes metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 formed within the same conductive or interconnect layer (each of which is associated with active region 304), and metal lines 306-1, 306-2, 306-3, 306-4, 306-5, 306-6, 306-7 formed within the same conductive or interconnect layer (each of which is associated with active region 306). The metal lines associated with each of active regions 302, 304, 306 may include copper, aluminum, or other suitable metals or metal alloys.As discussed below, the width and pitch of the metal lines have been reduced to provide multiple bitlines and bitline contacts connected to each active region 302, 304, 306 to reduce bitline resistance. Furthermore, as discussed below, each of the active regions 302, 304, 306 has its own WLP and WLR gate connections (referred to as WLPo, WLP1, WLRo, and WLR1 for each of the active regions 302, 304, 306) to reduce gate (or wordline) resistance and ensure proper operation of the NVM devices. By providing dedicated WLP and WLR gate connections for each of the active regions 302, 304, 306, the problems associated with high wordline resistance (e.g., degraded programming voltage) can be mitigated.For example, in some embodiments, the dedicated WLP gate connection may be used to program a single bit (a single transistor) along a given wordline, ensuring that the bit is programmed correctly.

[0027] As in Fig. 3, and with respect to the active region 302, the metal line 302-3 may be electrically connected to the underlying gate structure 312 through a conductive via 326 to form a first program wordline node (WLPo node), and the metal line 302-5 may be electrically connected to the underlying gate structure 318 through a conductive via 328 to form a second program wordline node (WLP1 node). Furthermore, the metal line 302-1 may be electrically connected to the underlying gate structure 314 through a conductive via 330 to form a first read wordline node (WLRo node), and the metal line 302-7 may be electrically connected to the underlying gate structure 316 through a conductive via 332 to form a second read wordline node (WLR1 node).

[0028] With respect to the active region 304, the metal line 304-3 may be electrically connected to the underlying gate structure 312 through a conductive via 356 to form a first program wordline node (WLPo node), and the metal line 304-5 may be electrically connected to the underlying gate structure 318 through a conductive via 358 to form a second program wordline node (WLP1 node). Furthermore, the metal line 304-1 may be electrically connected to the underlying gate structure 314 through a conductive via 360 to form a first read wordline node (WLRo node), and the metal line 304-7 may be electrically connected to the underlying gate structure 316 through a conductive via 362 to form a second read wordline node (WLR1 node).

[0029] With respect to the active region 306, the metal line 306-3 may be electrically connected to the underlying gate structure 312 through a conductive via 366 to form a first program wordline node (WLPo node), and the metal line 306-5 may be electrically connected to the underlying gate structure 318 through a conductive via 368 to form a second program wordline node (WLP1 node). Furthermore, the metal line 306-1 may be electrically connected to the underlying gate structure 314 through a conductive via 370 to form a first read wordline node (WLRo node), and the metal line 306-7 may be electrically connected to the underlying gate structure 316 through a conductive via 372 to form a second read wordline node (WLR1 node).

[0030] With respect to the bitlines, the metal lines 302-2, 302-4, 302-6 may be electrically connected to the underlying active region 302 (which may, for example, have an underlying source / drain region) by conductive vias 334, 336, and 338, respectively; the metal lines 304-2, 304-4, 304-6 may be electrically connected to the underlying active region 304 (which may, for example, have an underlying source / drain region) by conductive vias 340, 342, and 344, respectively; and the metal lines 306-2, 306-4, 306-6 may be electrically connected to the underlying active region 306 (which may, for example, have an underlying source / drain region) by conductive vias 346, 348, and 350, respectively. The connections of the metal lines to the underlying active regions 302, 304, 306 by means of the various conductive vias are described below with reference to Fig. 7. The metal lines 302-2, 302-4, 302-6 may thus function as bit lines of the memory device associated with the active region 302, the metal lines 304-2, 304-4, 304-6 may function as bit lines of the memory device associated with the active region 304, and the metal lines 306-2, 306-4, 306-6 may function as bit lines of the memory device associated with the active region 306. By providing multiple bit lines and bit line contacts, the bit line resistance is reduced for each of the active regions 302, 304, 306.

[0031] Fig. 4 shows an enlarged view of a portion 324 of the semiconductor memory structure 300. In some embodiments, the portion 324 may be described as a memory cell of the semiconductor memory structure 300. For example, the Fig. 3 may include a memory cell array. Section 324 illustrates the gate structures 308, 310, 312, 314, 316, 318, 320, 322, the active region 304, and the metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 formed within the same conductive or interconnect layer (such as within the M0 layer), as well as the program wordline nodes (WLPo, WLP1) and the read wordline nodes (WLRo, WLR1) associated with the active region 304. Fig. 4 also illustrates the cut metal regions 402. In some examples, the cut metal regions 402 include dielectric regions used to electrically isolate metal layers that contact source / drain regions of adjacent active regions (such as the active regions 302, 304, 306).

[0032] In some embodiments, and further with reference to Fig. 4, each of the metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 (as well as the corresponding metal lines associated with the active regions 302, 306) has a width 'W4' of approximately 10-30 nm, and a pitch 'S2' between adjacent metal lines is approximately 10-30 nm. In some cases, an area of ​​the conductive vias 356, 358, 360, 362 contacting the word lines (as well as the corresponding conductive vias associated with WLPo, WLP1 and WLRo, WLR1 of the active regions 302, 306) is approximately 50-200 nm. 2 In some cases, an area of ​​the conductive vias 340, 342, 344 (as well as the corresponding conductive vias associated with the bit lines of the active regions 302, 306) is approximately 400-700 nm 2. In contrast to the dimensions of the metal lines discussed above with respect to the semiconductor memory structure 100, the width and pitch of the metal lines associated with the semiconductor memory structure 300 have been reduced to provide multiple bit lines and bit line contacts connected to each active region 302, 304, 306 to reduce the bit line resistance.

[0033] Fig. 5 illustrates a circuit diagram 500 of an equivalent circuit of a portion of the semiconductor memory structure 300. For example, the circuit diagram 500 shows the WLPo node at a gate of a transistor T1', the WLRo node at a gate of a transistor T2', the WLP1 node at a gate of a transistor T3', the WLR1 node at a gate of a transistor T4', and a bitline node 'BL' (e.g., conductive vias 340, 342, 344 connected to the metal lines 304-2, 304-4, and 304-6, respectively). In some embodiments, the circuit of Fig. 5 can be used to reliably store two bits, 'bito', which corresponds to WLP0 and WLR0, and 'bit1', which corresponds to WLP1 and WLR1.

[0034] We now turn to the Fig. 6 and Fig. 7, which show further details regarding the configuration of the semiconductor memory structure 300. Fig. Figure 6 shows an enlarged view of section 324, similar Fig. 4, the semiconductor memory structure 300. In Fig. However, Figure 6 also illustrates the metal layers 602 used to contact source / drain regions within the active region (such as active regions 302, 304, 306). Thus, in some embodiments, the metal layers 602 may be referred to as source / drain contacts or source / drain contact metal layers. For example, the cut metal regions 402 may be used to electrically isolate the metal layers 602 contacting the source / drain contact regions of adjacent active regions (such as active regions 302, 304, 306). Fig. Figure 7 shows a cross-sectional view of the semiconductor memory structure 300 along a plane substantially parallel to a plane defined by the section line AA' of Fig. 6 defined level.

[0035] With reference to Fig. 7 shows the cross-sectional view along section line AA' of the semiconductor memory structure 300, a view of the bitline contacts to the underlying active region. In particular, section line AA' illustrates the active region 304, which may include a source / drain region. In some embodiments, isolation regions 704 (e.g., STI regions) may be formed adjacent to the active region 304 to isolate adjacent active regions or devices (e.g., transistors, NVM devices, etc.) from each other. The active region 304 includes a fin structure, and an epitaxial source / drain feature may be formed in, on, and / or around the fin structure. Fig. 7 also illustrates a first interlayer dielectric (ILD) layer 706, within which an opening may be formed (e.g., by a suitable combination of lithography and etching) for the subsequent deposition of a source / drain contact metal (e.g., metal layer 602). For example, the first ILD layer 706 may include materials such as tetraethylorthosilicate oxide (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0036] In various embodiments, the metal layer 602 may be formed within an opening of the first ILD layer 706 to make electrical contact with the active region 304 (e.g., including the source / drain region). In some examples, the metal layer 602 may include W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, TiN, TaN, WN, silicide, or another suitable conductive material. In some cases, prior to forming the metal layer 602, a silicidation process may be performed to create a silicide layer between the active region 304 and the metal layer 602 to form a low-resistance contact. In some examples, a glue or barrier layer 708 may be formed on sidewall surfaces of the opening of the first ILD layer 706 in which the metal layer 602 is formed. In some cases, the glue or barrier layer 708 may contain Ti, TiN, Ta, TaN, W or other suitable material.

[0037] In some embodiments, the metal layer 602 may have tapered sidewall profiles, as shown in Fig. 7, wherein the upper portions of the tapered sidewalls may extend laterally beyond a plane defined by a side edge 707 of the active region 304. In some examples, and because portions of the metal layer 602 may extend beyond the side edge 707 of the active region 304, conductive vias (such as conductive vias 340, 344) and the respective metal lines to which the conductive vias are connected (for example, metal lines 304-2 and 304-6) reliably establish electrical connection with the metal layer 602, even if the conductive vias and their respective metal lines themselves are partially or completely disposed outside or beyond the plane defined by the side edge 707 of the active region 304.In some cases, epitaxial source / drain features formed in, on, and / or around the fin structure (of a FinFET device) may be grown to extend laterally beyond the plane defined by a side edge 707 of the active region 304. In such cases, the metal layer 602 may optionally have tapered sidewall profiles, and the metal layer 602 may be formed over the epitaxial source / drain features, including over portions of the epitaxial source / drain features that extend beyond the plane defined by the side edge 707 of the active region 304.Since portions of the metal layer 602 may extend beyond the side edge 707 of the active region 304, conductive vias and the respective metal lines to which the conductive vias are connected reliably establish an electrical connection with the metal layer 602, even if the conductive vias and their respective metal lines are arranged partially or completely outside or beyond the plane defined by the side edge 707 of the active region 304.

[0038] As in Fig. 7, a contact etch stop layer (CESL) 710 is formed over the metal layer 602, and a second ILD layer 712 is formed over the CESL 710. For example, the CESL 710 may include Ti, TiN, TiC, TiCN, Ta, TaN, TaC, TaCN, W, WN, WC, WCN, TiAl, TiAlN, TiAlC, TiAlCN, or combinations thereof. In some embodiments, the second ILD layer 712 may be substantially the same as the first ILD layer 706 described above. Contact via openings may be formed (e.g., by a suitable combination of lithography and etching), for example, within the second ILD layer 712 and the CESL 710 to subsequently deposit a contact via metal layer (also referred to as conductive vias).For example, conductive vias 340, 342, 344 may be formed within such contact via openings to make electrical contact with the metal layer 602 (e.g., the source / drain contact). In some cases, the conductive vias 340, 342, 344 (as well as the other conductive vias discussed herein) may contain W, Cu, Co, Ru, Al, Rh, Mo, Ta, Ti, or another conductive material.

[0039] In some embodiments, a third ILD layer 714 is formed over the second ILD layer 712 and over the conductive vias 340, 342, 344. In some embodiments, the third ILD layer 714 may be substantially the same as the first ILD layer 706 described above. Furthermore, although the second ILD layer 712 and the third ILD layer 714 are illustrated as separate ILD layers, in some cases the second and third ILD layers 712, 714 may also be formed as a single layer. In various embodiments, metal line openings may be formed (e.g., by a suitable combination of lithography and etching), for example, within the third ILD layer 714 for subsequently depositing various metal interconnect lines.For example, the metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 may be formed within such metal line openings of the third ILD layer 714. . Fig.7 further illustrates that the metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 may be formed within the same conductive or interconnect layer. For example, the metal lines 304-2, 304-4, 304-6 are formed over and electrically connected to the underlying active region 304 (e.g., the source / drain region) by the conductive vias 340, 342, and 344, respectively, as well as by the metal layer 602 (e.g., the source / drain contact). In some embodiments, the metal lines 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7 may include copper, aluminum, or other suitable metals or metal alloys.It should be noted that the material used to form one or more of the first ILD layer 706, the CESL 710, the second ILD layer 712, and the third ILD layer 714 may include a low-k dielectric material that electrically isolates adjacent metal layers (e.g., metal lines, metal contacts, and conductive vias) from each other. As discussed above, the effective bitline resistance is reduced by arranging the plurality of bitlines (e.g., metal lines 304-2, 304-4, 304-6) and the plurality of bitline contacts (e.g., through the plurality of conductive vias 340, 342, 344) in the underlying active region 304 (e.g., the source / drain region).

[0040] The various embodiments described herein provide a number of advantages over the prior art. It should be understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments, and that other embodiments may provide advantages. As an example, embodiments discussed herein include a semiconductor memory structure having a design that provides a program wordline (WLP) gate connection and a read wordline (WLR) gate connection directly over an active region and having an independent wordline for each bit, thereby reducing an effective gate resistance (or effective wordline resistance).In various embodiments, the disclosed semiconductor memory structure also includes multiple bitlines and multiple bitline contacts to the underlying active region for each bit, thereby reducing the effective bitline resistance. As a result of the disclosed semiconductor memory structure design, the effective gate resistance is reduced by more than an order of magnitude, and the cell current (I) is expected to decrease. cell) by approximately 1.3 times. In some examples, the reduced gate resistance provides a substantially negligible parasitic voltage drop, ensuring a high-quality WLP voltage for a given device in a memory array. Furthermore, the improved cell current provides more reliable operation of NVM devices. The various embodiments disclosed herein thus provide higher-quality and more reliable gate connections, which in turn leads to improved device and circuit performance.

[0041] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] A semiconductor device (300) comprising: a first gate structure (312) formed over a first active region (304), the first active region (304) having a fin structure; a first metal line (304-3) disposed over, and perpendicular to, the first gate structure (312), wherein the first metal line is electrically connected to the first gate structure using a first conductive via (356), the first conductive via (356) contacting the first gate structure (312), and the first conductive via being disposed over the first active region (304); and a second metal line (304-2) and a third metal line (304-4), both running parallel to the first metal line (304-3) and arranged on opposite sides of the first metal line, wherein the second metal line is electrically connected to a source / drain region of the first active region (304) using a second conductive via (340), and wherein the third metal line is electrically connected to the source / drain region of the first active region using a third conductive via (342); and wherein the first gate structure (312) has a first program word line. [2] The semiconductor device (300) according to claim 1, wherein the first metal line (304-3), the second metal line (304-2) and the third metal line (304-4) each have a width of 10 nm to 30 nm. [3] The semiconductor device (300) according to claim 1 or 2, wherein the second metal line (304-2) and the third metal line (304-4) comprise bit lines. [4] The semiconductor device (300) of any preceding claim, wherein the first, second and third metal lines (304-3, 304-2, 304-4) are formed within the same interconnect layer. [5] The semiconductor device (300) of claim 4, wherein the same interconnect layer comprises a metal 0 interconnect layer, 푀0 interconnect layer. [6] The semiconductor device (300) of any preceding claim, further comprising a metal layer (602) formed over the source / drain region of the first active region (304), wherein the second conductive via (340) and the third conductive via (342) are both formed over and in contact with the metal layer. [7] The semiconductor device (300) of any preceding claim, wherein at least one of the second conductive via (340) and the third conductive via (342) is disposed over the first active region (304). [8] A semiconductor device (300) according to any one of the preceding claims, further comprising: a second gate structure (318) formed over the first active region (304), the second gate structure being parallel to the first gate structure (312); and a fourth metal line (304-5) disposed over and perpendicular to the second gate structure (318), the fourth metal line being electrically connected to the second gate structure using a fourth conductive via (358), and the fourth conductive via being disposed over the first active region (304). [9] The semiconductor device (300) of claim 8, wherein the second gate structure (318) comprises a second program word line. [10] The semiconductor device (300) of any preceding claim, wherein the first active region (304) is associated with a first memory cell, and wherein the first memory cell comprises a first program word line, a second program word line, a first read word line, and a second read word line. [11] A semiconductor device (300) comprising: a memory cell (324) having an active region (304), the active region (304) having a fin structure; a first word line (312) formed over the active region (304), the first word line being a program word line, wherein a connection to the first word line is provided using a first conductive via (356) disposed over the active region, and wherein the first conductive via (356) contacts the first word line (312); and a plurality of bit lines (304-2, 304-4, 304-6) electrically connected to a source / drain of the active region (304) using respective plurality of conductive vias (340, 342, 344). [12] The semiconductor device (300) of claim 11, wherein the connection to the first word line (312) comprises a first metal line (304-3) disposed over the first word line, and wherein the first metal line is connected to the first word line using the first conductive via (356). [13] The semiconductor device (300) of claim 12, wherein the first metal line (304-3) and the plurality of bit lines (304-2, 304-4, 304-6) are formed within the same interconnect layer. [14] The semiconductor device (300) of any one of claims 11 to 13, wherein the plurality of bit lines (304-2, 304-4, 304-6) comprises at least three bit lines electrically connected to the source / drain of the active region (304) using at least three respective conductive vias (340, 342, 344). [15] The semiconductor device (300) of any one of claims 11 to 14, further comprising a metal layer (602) formed over the source / drain of the active region (304), wherein the plurality of conductive vias (340, 342, 344) are formed over, and in contact with, the metal layer (602). [16] The semiconductor device (300) of any one of claims 11 to 15, wherein at least one of a plurality of conductive vias (340, 342, 344) is disposed over the active region (304). [17] A semiconductor device (300) according to any one of claims 11 to 16, further comprising: a second word line (318) formed over the active region (304), wherein a connection to the second word line is provided using a second conductive via (358) disposed over the active region. [18] A semiconductor device (300) comprising: a plurality of active regions (302, 304, 306) corresponding to a plurality of memory cells, the active regions each having a fin structure; a first program word line (312) formed over the plurality of active regions (302, 304, 306), wherein a first connection to the first program word line is provided using a first conductive via (326) arranged over a first active region (302) of the plurality of active regions, wherein a second connection to the first program word line is provided using a second conductive via (356) arranged over a second active region (304) of the plurality of active regions, wherein the first conductive via (326) contacts the first program word line (312), and wherein the second conductive via (356) contacts the first program word line (312); a first plurality of bit lines (302-2, 302-4, 302-6) electrically connected to a first source / drain region of the first active region (302) using a first plurality of conductive vias (334, 336, 338); and a second plurality of bit lines (304-2, 304-4, 304-6) electrically connected to a second source / drain region of the second active region (304) using a second plurality of conductive vias (340, 342, 344). [19] The semiconductor device (300) of claim 18, wherein a first memory cell of the plurality of memory cells has the first connection (326) to the first program word line (312) and a first connection (330) to a first read word line (314), and wherein a second memory cell of the plurality of memory cells has the second connection (356) to the first program word line and a second connection (360) to the first read word line. [20] The semiconductor device (300) of claim 18 or 19, wherein the plurality of memory cells comprises a plurality of one-time programmable, OTP, non-volatile memory cells, NVM cells.

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