LOW RESISTANCE PICK-UP CELLS FOR A SRAM

Abstract

Semiconductor device comprising: a substrate (110) having a first well (202) of a first conductivity type; a first transistor (252a, 252b) comprising: a first fin (212) extending from the first well (202) and having a first width (w1), the first fin (212) having the first conductivity type, and two first source / drain elements (222) on the first fin (212), the two first source / drain elements (222) having a second conductivity type opposite to the first conductivity type; and a memory pick-up cell (352) comprising: a second fin (312) extending from the first trough (202) and having a second width (w3) that is at least three times the first width (w1), two second source / drain elements (322) on the second fin (312), wherein the second fin (312) and the two second source / drain elements (322) have the first conductivity type, and a stack of semiconductor layers (320) over the second fin (312) connecting the two second source / drain elements (322), wherein the substrate (110) further comprises a second well (204) of the second conductivity type adjacent to the first well (202), the semiconductor device further comprising: a second memory pick-up cell (354) with: a third fin (314) extending from the second trough (204) and having a third width (w4); two third source / drain elements (324) on the third fin (314), wherein the third fin (314) and the two third source / drain elements (324) have the second conductivity type, wherein the second and third fins (312, 314) extend along one and the same direction in a longitudinal direction and are spaced apart from each other along a transverse direction by a maximum distance (S2) designed to maximize the second width (w3) of the second fin (312) and the third width (w4) of the third fin (314).

Description

BackgroundThe IC (Semiconductor Integrated Circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component or line that can be created with a fabrication process) has decreased. This process of downsizing generally provides advantages in increasing production efficiency and decreasing associated costs. However, this downsizing has also increased the complexity of processing and manufacturing ICs.For example, in memory devices (such as static random access memory or SRAM), leakage between adjacent n-wells (or N-wells) and p-wells (or P-wells) occasionally leads to latch-up problems. The latch-up problems become more serious as the transistors are further scaled down. US Patent US 10460794 B1 discloses an SRAM array having a plurality of cells comprising a plurality of transistors and a plurality of well strap cells, each of the well strap cells being arranged at an end of one of the columns in the SRAM cell array. US patent application US 2020 / 0098766 A1 discloses a first FinFET having a first fin of a first width doped with the first type dopant and a well strap region having a second fin of a second width doped with the first type dopant, the second width being greater than the first width. The invention is defined by the main claim and the subordinate claims. The dependent claims represent further embodiments of the invention.Brief Description of the DrawingsThe present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale and are for explanation purposes only. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1 is a simplified block diagram of an embedded memory integrated circuit (IC) in accordance with various aspects of the present invention. FIG. 2 shows two cross-sectional views of a portion of the memory macro of FIG. 1 along a transverse direction of active regions, according to an embodiment. FIG. 3 shows two cross-sectional views of a portion of the memory macro of FIG. 1 along a longitudinal direction of the active regions, according to an embodiment. FIG. 4 shows a top view of a portion of the memory macro of FIG. 1 with a high current SRAM cell, according to an embodiment. FIG. 5 shows two cross-sectional views of a portion of the memory macro of FIG. 4 along a transverse direction of the active regions, according to an embodiment. FIG. 6 is a top view of a portion of the memory macro of FIG. 1 with a high current SRAM cell, according to another embodiment. FIG. 7 shows two cross-sectional views of a portion of the memory macro of FIG. 6 along a transverse direction of the active regions, according to an embodiment. FIG. 8 shows a top view of the portion of the memory macro of FIG. 1 with gate stacks and source / drain contacts over the active regions, according to an embodiment.FIGS. 9 a- 1, 9 b- 1, 9 c- 1, 9 d, and 9 e show top views of various structures in a method of manufacturing the memory macro of FIG. 1, according to an embodiment. FIGS. 9 a- 2, 9 b- 2, and 9 c- 2 show cross-sectional views of the structures of FIGS. 9 a- 1, 9 b- 1, and 9 c- 1, according to an embodiment.Detailed DescriptionThe following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. For example, the formation of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly. In addition, when a number or range of numbers is described as being "about", "about", and the like, the term is intended to include numbers that are within ±10% of the stated number, unless otherwise stated. For example, the term "about 5 nm" encompasses the dimensional range of 4.5 nm to 5.5 nm.The present invention relates generally to semiconductor devices and their fabrication methods, and more particularly to structures, layout designs, and fabrication methods for memory bit cells and memory well pick-up cells (WPU cells). The well pick-up cells allow access to p- and n-wells among the transistors serve the memory bit cells. The p-wells and the n-wells (which are doped counter-wise) are arranged alternately in a memory macro (i.e., each p-well is adjacent to an n-well adjacent to another p-well) and have separate well pick-up cells. Package pins or pads may be connected to the well pick-up cells in a final IC to provide biasing voltages for the wells. Additionally, tester pins may contact the well pick-up cells to provide voltages to the wells during fabrication testing.As the transistors are further scaled down, latch-up problems in memory macros become more serious. One approach to address this problem is to increase a pick-up cell to memory bit cell ratio (i.e., to increase the density of pick-up cells in a memory macro). This increases the number of tap points to provide a bias voltage to the wells, thereby reducing the latching probability. However, this inevitably affects the density of the memory bit cells, since more areas of the memory macro are used for the pick-up cells. An object of the present invention is to alleviate the latch-up problems by providing pick-up cells with a reduced resistance. In particular, the pickup cells are in the form of a gate-all-around (GAA) device and are fabricated using the same process as the transistors in the memory cells (also referred to as memory cell transistors) fabricated on the same well as the pickup cells. However, the pick-up cells do not have a gate contact and have a much larger active area and wider source / drain features than the memory cell transistors. The larger active area and the wider source / drain features reduce the resistance of the electrical path extending from a source / drain contact to the underlying well, thereby reducing the likelihood of latch-up problems caused by leakage of the well.FIG. 1 shows a simplified block diagram of a semiconductor device 100 with embedded memory 102, in accordance with various aspects of the present invention. The semiconductor device 100 may be, for example, a microprocessor, an application specific integrated circuit (ASIC), a general purpose circuit (FPGA), or a digital signal processor (DSP). The exact functionality of the semiconductor device 100 is not a limitation of the provided subject matter. The memory macro 102 may be a single-port SRAM macro, a dual-port SRAM macro, another type of memory macro, or a combination thereof. The memory macro 102 includes a plurality of memory bits for storage. The semiconductor device 100 also includes peripheral logic circuitry (not shown) adjacent to the memory macro 102 to implement various functions, such as a write and / or read address decoder, a word / bit selector, a data driver, a memory self-test, and the like. The memory bits and logic circuits may be implemented with various PMOS and NMOS transistors, respectively, such as planar transistors, FinFETs, gate-all-around (GAA) nanosheet transistors, GAA nanowire transistors, or other types of transistors. In addition, the memory macro 102 and the logic circuits may include various contact elements (or contacts), vias, and metal lines for connecting the transistors' source, drain, and gate electrodes (or terminals) to an integrated circuit.FIG. 1 also shows a top view (layout) of a portion of the memory macro 102. The memory macro 102 includes one or more regions 200 having memory bit cells (or memory cells) and one or more regions 300 having well pick-up cells. In the present invention, the region 200 is also referred to as a memory cell region 200, and the region 300 is also referred to as a well pick-up (WPU) region 300. The WPU region 300 may be located at an edge of the memory macro 102. For example, there are no more cells to the right of region 300 in FIG. 1. Alternatively or additionally, WPU region 300 may be located in an inner region of memory macro 102. For example, memory cell regions 200 may be disposed on the left and right sides of the WPU region 300. As set forth above, the WPU regions 300 provide well pick-up structures for supplying voltages to the n- and p-wells in the memory macro 102 (or for biasing the wells). For a large memory macro, a voltage drop across the wells may be significant, which may result in insufficient biasing of the wells in a portion of the memory macro. The WPU regions 300 should be optimally placed in selected regions of the memory macro 102 to provide sufficient bias voltage for all the wells of the memory macro.In the present embodiment, the memory macro 102 includes different p-wells and different n-wells oriented longitudinally along the x-direction and arranged alternately along the y-direction. In other words, along the y-direction, each p-well is adjacent to an n-well adjacent to another p-well, and so on and so forth. In the example shown in FIG. 1, the memory macro 102 includes a p-well 202, an n-well 204, and another p-well 206. In particular, the troughs 202, 204 and 206 extend transversely over the two regions 200 and 300. The p-wells 202 and 206 are doped with a p-dopant such as boron or indium. The n-well 204 is doped with an n-dopant such as phosphorus or arsenic.In memory cell region 200, memory macro 102 further includes active regions 212 over p-well 202, active regions 214 over n-well 204, and active regions 216 over p-well 206. In the WPU region 300, the memory macro 102 further includes an active region 312 over the p-well 202, an active region 314 over the n-well 204, and an active region 316 over the p-well 206. The various active regions 212, 214, 216, 312, 314 and 316 are oriented longitudinally along the x-direction. In particular, the active regions 214 are spaced apart from one another along the x-direction by a distance S 1. In some embodiments, the distance S 1 is 30 nm to 60 nm. The lower boundary (e.g., 30 nm) of the region is designed to provide sufficient spacing between the active regions 214 and gate stacks (see, e.g., gate stack 230 in FIG. 8 ) bridging the space along the y-direction. The upper limit (e.g., 60 nm) of the range is designed to limit a size of the memory cell. The active regions 312, 314 and 316 are spaced apart from each other along the y-direction by a distance S 2. In some embodiments, the distance S 2 is 20 nm to 60 nm. The lower limit (e.g., 20 nm) of this region is designed to provide sufficient margin for a photolithography patterning process used to create the active regions 312, 314, and 316 (see, e.g., FIGS. 9a-9e). The upper limit (e.g., 60 nm) of this region is designed to maximize a width of the active regions 312, 314, and 316, thereby reducing the resistance of the pick-up cells, as will be discussed later.In FIG. 2, cross-sectional views of the memory cell region 200 and the WPU region 300 along a line Y 1-CUT and a line Y 2-CUT of FIG. 1, respectively, are shown according to an embodiment. As shown in FIG. 2, the memory macro 102 includes a substrate 110. The various wells 202, 204, and 206 are formed in or over the substrate 110.The substrate 110 is a silicon substrate in the present embodiment. For example, it is a silicon wafer or a substrate with single crystal silicon. Alternatively, the substrate 110 may include another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and Galliumindiumarsenidphosphid; or combinations thereof.In one embodiment, the various wells 202, 204, and 206 are formed by doping different portions of the substrate 110. The p-type wells (e.g., wells 202 and 206) may be formed as follows: forming a doping mask by photolithography, the doping mask covering regions of the substrate 110 corresponding to the n-type wells (e.g., well 204); doping regions of the substrate 110 not covered by the doping mask with one or more p-type dopants; and removing the doping mask. The doped regions of the substrate 110 become the p-wells. The n-wells may be similarly formed.As shown in FIGS. 1 and 2, each of the active regions 212, 214, 216, 312, 314 and 316 is in the form of a fin extending from the respective well. Thus, the active regions 212, 214, 216, 312, 314 and 316 are also referred to as fins 212, 214, 216, 312, 314 and 316, respectively. In the present embodiment, the fins 212, 214, 216, 312, 314 and 316 each comprise the same material as the substrate 110, such as single crystal silicon. In the present embodiment, all fins extending from the p-type wells in the memory cell region 200 have the same width w 1; all fins extending from the n-type wells in the memory cell region 200 have the same width w 2; all fins extending from the p-type wells in the WPU region 300 have the same width w 3; and all fins extending from the n-type wells in the WPU region 300 have the same width w 4. The above widths are dimensions measured along the y-direction.In the present embodiment, the widths w1 and w2 are designed to be as small as the manufacturing process allows, thereby increasing the memory cell density. For example, in an embodiment where patterning may be performed by extreme ultraviolet (EUV) lithography or other modern lithographic methods, the widths w 1 and w 2 are each designed to be 6 nm to 20 nm. At the same time, the widths w 3 and w 4 are designed to be as wide as possible, following the following rules: first, the widths w 3 and w 4 are not greater than the width of the respective wells 202, 204, and 206, and second, to provide a design margin (e.g., for photolithography and etching), the spacing S 2 between adjacent fins is provided in the WPU region 300 as set forth above. In one embodiment, the widths w 3 and w 4 are each designed to be equal to the width of the respective well minus the distance S 2. Because the fins 312, 314, and 316 are part of the electrical path from a pick-up source / drain (e.g., a source / drain 322) to the respective well, by keeping these fins wide, the resistance of the pick-up cells is decreased and the likelihood of latch-up problems in the respective cell is reduced. In one embodiment, the widths w 3 and w 4 are each designed to be 10 nm to 100 nm, e.g., 10 nm to 60 nm.In the present embodiment, since the fins 212 and 312 extend from the same well 202, the width of the fin 312 is designed to be a multiple of the width of the fin 212. In particular, the width w 3 of the fin 312 may be designed to be 3 to 10 times the width w 1 of the fin 212 to simplify the manufacturing process. For example, in FIG. 1, the fin 312 and the two fins 212 over the well 202 may be designed such that their respective top and bottom sides are aligned along the x-direction, i.e., the top side of the fin 312 is aligned with the top side of the very first fin 212 (counted from the top of the side of FIG. 1 ), and the bottom side of the fin 312 is aligned with the bottom side of the very last fin 212. By this configuration, when the fins 212 and 312 are patterned using a direct exposure method such as EUV lithography, optical proximity effects are reduced and the shape fidelity of the structure is increased. This configuration reduces the complexity of the patterning process when the fins 212 and 312 are patterned using a dual (or multiple) patterning process, as the fins 212 and 312 may begin with the same mandrel structure, as will be explained later with reference to FIGS. 9a-9e. When the width of the fins 212 is 6 nm to 20 nm, the distance between the fins 212 along the y-direction is designed to be approximately equal to the width w 1. As a result, for example, the fin structuring process may be optimal. Therefore, in the above configuration, the width w 3 is at least three times the width w 1. In some embodiments, more than two parallel fins 212 may be used to increase an NMOS current in the memory cells. For example, 3, 4, or 5 parallel fins 212 may extend from the well 202. In these cases, the width w 3 in the above configuration is designed to be 5, 7, and 9 times the width w 1, respectively. In other words, in the present embodiment, the width w 3 is designed to be w 1·[(number of fins 212)·2-1]. The discussion of fins 212 and 312 applies to fins 216 and 316, as well. In general, in the present invention, the width w 3 is 3 to 10 times the width w 1, regardless of whether w 3 is a multiple of w 1 or not.The above explanations regarding the configuration of the widths w 1 and w 3 also apply in a similar manner to the configuration of the widths w 2 and w 4. In short, the width w 4 in the present embodiment is designed to be a multiple of w 2. In particular, the width w 4 may be designed to be 3 to 10 times the width w 2 to simplify the manufacturing process. Additionally, the fin 314 and the two fins 214 may be designed with their respective top and bottom sides aligned along the x-direction. In embodiments where 2, 3, 4, or 5 parallel fins 214 extend from the well 204, the width w 4 is designed to provide the 3, 5, 7, and the like, respectively. 9 times the width w2. In general, in the present invention, the width w4is 3 to 10 times the width w2 regardless of whether w4is a multiple of w2or not.FIG. 2 shows partial cross-sectional views of various transistors in the memory cell region 200 and of various pick-up cells in the WPU region 300. In FIG. 2, memory cell region 200 includes NMOS transistors 252a and 252b over p-well 202, PMOS transistors 254a and 254b over n-well 204, and NMOS transistors 256a and 256b over p-well 206. The WPU region 300 includes a p-pick-up cell 352 over the p-well 202, an n-pick-up cell 354 over the n-well 204, and a p-pick-up cell 356 over the p-well 206. NMOS transistors 252a / 252b and 256a / b include n-doped epitaxial source / drain elements 222 and 226 over fins 212 and 216, respectively. PMOS transistors 254 aand 254 bhave p-doped epitaxial source / drain elements 224 over fins 214. P-pick-up cells 352 and 356 include p-doped epitaxial source / drain elements 322 and 326 over fins 312 and 316, respectively. The n-pick-up cells 354 include n-doped epitaxial source / drain elements 324 over the fin 314. The epitaxial source / drain elements 322 and 326 are wider than the epitaxial source / drain elements 222 and 226, respectively, along the y-direction. For example, epitaxial source / drain elements 322 and 326 are each 3 to 10 times as wide as epitaxial source / drain elements 222 and 226 along the y-direction. The epitaxial source / drain element 324 is wider along the y-direction than the epitaxial source / drain elements 224. For example, the epitaxial source / drain element 324 is 3 to 10 times as wide as the epitaxial source / drain element 224 along the y-direction. In one embodiment, the n-doped source / drain elements 222, 226, and 324 may each comprise silicon and may be doped with carbon, phosphorus, arsenic, another n-dopant, or combinations thereof (e.g., to form Si:C epitaxial source / drain elements, Si:P epitaxial source / drain elements, or Si:C:P epitaxial source / drain elements). In one embodiment, the p-doped source / drain elements 224, 322, and 326 may each comprise silicon germanium or germanium and may be doped with boron, another p-dopant, or combinations thereof (e.g., to form epitaxial Si:Ge:B source / drain elements). The epitaxial source / drain elements may be formed by etching trenches into the respective fins and epitaxially growing one or more semiconductor materials in the trenches using CVD deposition techniques (e.g., vapor phase epitaxy), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof.FIG. 3 shows partial cross-sectional views of transistor 252 aand pick-up cell 352 along a line X 1-CUTand a line X 2-CUT, respectively, of FIG. 1 In FIG. 3, transistor 252 ain turn includes: a plurality of semiconductor layers 220 connecting epitaxial source / drain elements 222; a gate stack 230 between epitaxial source / drain elements 222 and in contact with semiconductor layers 220; a gate spacer 238 on sidewalls of gate stack 230; an inner spacer 238 a; an etch stop layer 237; source / drain contacts 234; a dielectric layer 239; and a gate contact 240. The gate stack 230 includes a conductive gate electrode 236 and one or more gate dielectric layers 235. Portions of the gate stack 230 are vertically (along the z-direction) arranged between two adjacent semiconductor layers 220. The inner spacer 238 ais laterally (along the x-direction) disposed between two portions of the gate stack 230 and the source / drain elements 222. The pick-up cell 352 is similarly structured and includes: a plurality of semiconductor layers 320 connecting the epitaxial source / drain elements 322; a gate stack 330 between the epitaxial source / drain elements 322 and in contact with the semiconductor layers 320; a gate spacer 338 on sidewalls of the gate stack 330; an inner spacer 338 a; an etch stop layer 337; source / drain contacts 334; and a dielectric layer 339. The gate stack 330 includes a conductive gate electrode 336 and one or more gate dielectric layers 335. The pick-up cell 352 does not have a gate contact connected to the gate electrode 336. Instead, a top surface of the gate electrode 336 is completely covered by the dielectric layer 339.The semiconductor layers 220 and 330 may include silicon, germanium, silicon germanium, or one or more other suitable semiconductor materials. The semiconductor layers 220 and 330 may be formed by the same method briefly described below using the semiconductor layers 320 as an example. First, the semiconductor layers 320 are formed as part of a semiconductor layer stack comprising the semiconductor layers 320 and further semiconductor layers of a different material. The semiconductor layer stack is patterned into the shape of a fin using one or more photolithography processes including dual or mask patterning processes (e.g., using the same method used to form the fin 312). During a gate replacement process for forming the gate stacks 330, the semiconductor layer stack is selectively etched to remove the other semiconductor layers, leaving the semiconductor layers 320 floating above the substrate 110.The gate dielectric layers 235 and 335 may each include an interfacial layer and / or a high-k dielectric layer. The interface layer may include a dielectric material such as SiO 2, HfSiO, or SiON, or combinations thereof. The interface layer may be formed by thermal oxidation, chemical oxidation, ALD, CVD, other suitable method, or combinations thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO 2, HfSiO, HfSiO 4, HfSiON, HfLaO, HfTaO, HfTiO, HfNbO, HfAlO x, ZrO, ZrO 2, ZrSiO 2, AlO, AlSiO, Al 2 O 3, TiO, TiO 2, LaO, LaSiO, and the like, Ta 2 O 3, Ta 2 O 5, Y 2 O 3, SrTiO 3, BaSrO, BaTiO 3( BTO), (Ba,Sr)TiO 3( BST), Si 3 N4, a hafnium dioxide-alumina (HfO2-Al2O3) alloy, another suitable high-k dielectric material, or combinations thereof. A high-k dielectric material generally refers to a dielectric material having a dielectric constant greater than that of silicon oxide (k≈3.9), for example. The high-k dielectric layer may be formed by any of the methods mentioned herein, such as ALD, CVD, PVD, an oxidation-based deposition process, other suitable methods, or combinations thereof.The conductive gate electrodes 236 and 336 may each include a work function metal layer and a bulk metal layer. Since transistor 252a is an NMOSFET, the work function metal layer provides an n-type work function to gate electrode 236. On the other hand, the gate electrode 336 is not used in the IC 100 per se (there is no gate contact connected to the gate electrode 336), and its work function metal may be an n- or a p-work function metal. However, in order to make the process flow between the memory cell transistors and the pickup cells uniform, in the present embodiment, gate electrodes are formed in p-pickup cells (i.e., having a p-doped source / drain) having a p-type work function, and gate electrodes are formed in n-pickup cells (i.e., having an n-doped source / drain) having an n-type work function. Therefore, the gate electrode 336 is formed with a p-type work function. Although not shown in FIG. 3, a gate electrode in transistor 254 a / b provides a p-type work function for the PMOSFET, a gate electrode in transistor 256 a / b provides an n-type work function for the NMOSFET, a gate electrode in pickup cell 354 is fabricated with an n-type work function, and a gate electrode in pickup cell 356 is fabricated with a p-type work function. A p-type work function layer includes a suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi 2, MoSi 2, TaSi 2 or NiSi 2, another p-type work function material, or combinations thereof. An n-type work function layer includes a suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, or TiAlN, another n-type work function material, or combinations thereof. The work function metal layer may be formed using a suitable deposition process such as CVD, PVD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, another deposition process, or combinations thereof. The bulk metal layer of the gate electrodes 236 and 336 includes a suitable conductive material, such as Co, Al, W, and / or Cu. The solid metal layer may additionally or alternatively comprise other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In addition, the metal gate electrodes 236 and 336 may be different portions of the same metal layers. The gate dielectric layer 235 and the gate electrode layer 236 are also formed between the semiconductor layers 220 (i.e., the transistor 252 ais a nanosheet device or a gate-all-around device). The gate dielectric layer 335 and the gate electrode layer 336 are also formed between the semiconductor layers 320 (i.e., the pick-up cell 352 is a nanosheet pick-up cell or a gate-all-around pick-up cell). In an alternative embodiment, transistor 252 ais a FinFET device (i.e., there is only one semiconductor layer 220 connected to fin 212), but pick-up cell 352 is still a nanosheet pick-up cell or a gate-all-around pick-up cell.The spacers 238, 238a, 338 and 338a may be formed by any suitable method and comprise a dielectric material. The dielectric material may be silicon, oxygen, carbon, nitrogen, another suitable material, or a combination thereof, e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride (SiOCN).The etch stop layers 237 and 337 may be different parts of a same etch stop layer and may include silicon and nitrogen, such as silicon nitride or silicon oxynitride. Contacts 234, 240, and 334 include a conductive material, such as aluminum, an aluminum alloy (e.g., an aluminum-silicon-copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may be nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination thereof. The dielectric layer 339 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS oxide, phosphosilicate glass (PSG), a low-k dielectric material, another suitable dielectric material, or a combination thereof.FIG. 4 shows a top view (layout) of another part of the memory macro 102 of FIG. 1. in FIG. 4, the memory macro 102 includes another memory cell region 200 aand another WPU region 300 a. FIG. 5 is partial sectional views of the memory cell region 200 aand the WPU region 300 aalong a line Y 3- CUT, and a line Y 4- CUT, respectively, of FIG. 4. numerous structural elements of the memory cell region 200 aand the WPU region 300 aare the same or substantially the same as those of the memory cell region 200 and the WPU region 300, respectively. Therefore, some of its details are omitted, and similar structural elements are denoted by similar reference numerals.In FIGS. 4 and 5, alternating p-type wells (e.g., 202 and 206) and n-type wells (e.g., 204) extend across memory cell region 200 aand WPU region 300 a. Active regions (or fins) 212, 214, 216, 312, 314 and 316 extend from the wells and are longitudinally oriented along the x-direction. The fins (e.g., 212 and 216) over the p-wells are wider than the fins (e.g., 204) over the n-wells in the memory cell region 200 a. In one embodiment, fins 212 and 216 are each at least 2 times as wide as fin 214. In other words, the width w 1 is at least twice the width w 2. With this configuration, a high current is provided in the NFET (i.e., the memory cell region 200 aincludes high current memory cells). There are at least two fins 212 (216) over each p-well 202 (206). The number of fins 312 (316) is equal to the number of fins 212 (216). The width w 3 is approximately equal to the width w 1. This simplifies the patterning process in which fins 212 and 312 are formed. The width w4 is at least three times the width w2. In particular, the width w 4 may be designed to be 3 to 10 times w 2 to simplify the manufacturing process. In embodiments where 2, 3, 4, or 5 parallel fins 214 extend from the well 204, the width w 4 may be designed to be 3, 5, 7, or 9 times the width w 2, respectively.FIG. 6 shows a plan view (layout) of another part of the memory macro 102 of FIG. 1. in FIG. 6, the memory macro 102 includes another memory cell region 200 aand another WPU region 300 b. FIG. 7 shows partial cross-sectional views of the memory cell region 200 aand the WPU region 300 balong a line Y 5- CUTand a line Y 6-CUT, respectively, of FIG. 6. Various structural elements of the WPU region 300 bare the same as or substantially the same as those of the WPU region 300. Therefore, some of its details are omitted, and similar structural elements are denoted by similar reference numerals.In FIGS. 6 and 7, alternating p-type wells (e.g., 202 and 206) and n-type wells (e.g., 204) extend across memory cell region 200 aand WPU region 300 b. Active regions (or fins) 212, 214, 216, 312, 314 and 316 extend from the wells and are longitudinally oriented along the x-direction. The fins (e.g., 212 and 216) over the p-wells are wider than the fins (e.g., 204) over the n-wells in the memory cell region 200 a. In one embodiment, fins 212 and 216 are each at least 2 times as wide as fin 214. In memory cell region 200a, there are at least two fins 212 (216) over each p-well 202 (206). However, in the WPU region 300 b, there is only one fin 312 ( 316) above each p-well 202 ( 206). Specifically, the width w 3 is designed to be 3 to 10 times w 1 to simplify the manufacturing process. Additionally, the fin 312 and the two fins 212 may be designed with their respective top and bottom sides aligned along the x-direction, as set forth above with reference to FIG. 1. In embodiments where 2, 3, 4, or 5 parallel fins 212 extend from the well 204, the width w 3 is designed to be 3, 5, 7, and 9 times the width w 1, respectively. The width w4 is at least three times the width w2. In particular, the width w 4 may be designed to be 3 to 10 times w 2 to simplify the manufacturing process. In embodiments where 2, 3, 4, or 5 parallel fins 214 extend from the well 204, the width w 4 may be designed to be 3, 5, 7, or 9 times the width w 2, respectively.FIG. 8 shows a top view (layout) of the portion of the memory macro 102 of FIG. 1, according to an embodiment. In particular, FIG. 8 shows gate stacks 230 and 330 oriented longitudinally along the y-direction. The gate stacks 230 are in contact with (or the nanosheet channels on) the various fin active regions 212, 214, and 216 to form the transistors of the memory cells. The gate stacks 330 are disposed over the active regions 312, 314 and 316. As stated above, the gate stacks 330 do not function as a transistor gate because there is no gate contact connected to them. They are nevertheless manufactured in the memory macro 102 for structure load purposes, i.e. to increase the shape fidelity of the structure when manufacturing the gate stacks 230. FIG. 8 further shows source / drain contacts 334 disposed over the active regions 312, 314 and 316. Well bias voltages are provided to wells 202, 204, and 206 via source / drain contacts 334. In the present invention, since the active regions 312, 314 and 316 are designed to have a wide main part (e.g., 3 to 10 times as wide as that of the active regions 212, 214 and 216 in some embodiments), the resistance in the well bias path is reduced, thereby reducing the latch-up probability in the memory macro 102. Although not shown in FIG. 8, there are source / drain contacts and gate contacts in the memory cell region 200.The active regions 212, 214, 216, 312, 314 and 316 in the various embodiments of the present invention may be formed using a photolithography process and one or more etching processes. The photolithography process includes: forming a hard mask layer over the substrate 110; depositing a photoresist layer over the hard mask layer; exposing the photoresist layer to radiation (e.g., EUV or 193 nm DUV immersion); developing the exposed photoresist layer; removing certain portions of the photoresist layer to generate a patterned resist; etching the hard mask layer using the patterned resist to generate a patterned hard mask; and etching the substrate 110 using the patterned hard mask or a pattern derived therefrom. The etching process may be a dry etch, a wet etch, or a combination thereof. For the dry etching process, for example, oxygen-containing gases, fluorine-containing gases (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), chlorine-containing gases (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasmas, or combinations thereof may be used. The wet etching process may include, for example, etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO 3) and / or acetic acid (CH 3 COOH), or in another suitable wet etchant.In the present embodiment, since the active regions 212, 214, 216, 312, 314 and 316 may have different widths and some of the widths are only 20 nm or less, direct patterning using EUV lithography may be used to generate the structures. Alternatively, the layout of the present invention also enables double patterning using a less expensive lithographic apparatus, such as a 193 nm immersion lithography apparatus, to produce the patterns. An example process flow for creating patterns for the layout shown in FIG. 1 is shown in FIGS. 9a-9e. The process flow may be modified to generate structures for the layouts shown in FIGS. 4 and 6.FIG. 9 a- 1 shows a top view of the structures, while FIG. 9 a- 2 shows sectional views of the structures along lines A - A and B - B of FIG. 9 a- 1. The process flow begins with creating mandrel structures 402 over the wells 202, 204, and 206. The mandrel structures 402 include a hard mask material, e.g., silicon dioxide, silicon nitride, or another suitable material. The mandrel structures 402 are formed as regular line structures and have a width large enough to be directly generated (or resolved) by 193 nm immersion lithography. The photolithographic process has been explained above.FIG. 9 b- 1 shows a plan view of the structures, while FIG. 9 b- 2 shows sectional views of the structures along lines A - A and B - B of FIG. 9 b- 1. A spacer 404 is formed on sidewalls of the mandrel structures 402. The spacer 404 comprises a different material than the mandrel structures 402. Spacer 404 may be fabricated by conformally depositing a layer of material over a top and sidewalls of mandrel structures 402 and over substrate 110, and then anisotropically etching the layer of material. A thickness of the spacer 404 corresponds to the width of the fin active regions (e.g., w1).FIG. 9 c- 1 shows a plan view of the structures, while FIG. 9 c- 2 shows sectional views of the structures along lines A - A and B - B of FIG. 9 c- 1. The mandrel structures 402 in the memory cell region 200 are selectively removed. This may be achieved by forming a mask 405 (e.g., a patterned photoresist) to cover the WPU region 300 and performing an etching process in the memory cell region 200 that is selective to the materials of the mandrel structures 402. Then, the mask 405 is removed.As shown in FIG. 9 d, the mandrel structures 402 and the spacer 404 are partially removed with a cutting process. For example, another hard mask pattern (cut pattern) is formed over the mandrel patterns 402 and the spacer 404. The cutting structure provides openings 406 that expose portions of the mandrel structures 402 and the spacer 404 while leaving the remainder of the mandrel structures 402 and the spacer 404 covered. Then, the mandrel structures 402 and the spacer 404 are etched through the openings 406 and then the cutting structure is removed.As shown in FIG. 9 e, the substrate 110 is etched using the remaining portions of the mandrel structures 402 and the spacer 404 as a mask to form the active regions 212, 214, 216, 312, 314 and 316. In one embodiment, a width of the mandrel structure 402 is designed to be approximately equal to a thickness of the spacer 404 such that the width of the active regions 312, 314 and 316 is three times the width of the active regions 212, 214 and 216.The present invention provides well pick-up cells with a wide fin body and a low resistance, thereby effectively reducing the resistance for well pick-up structures and reducing the latch-up probability compared to designs where well pick-up cells have the same fin width as the memory cells. The disclosed layout may be patterned by direct EUV exposure or mandrel spacer double patterning or a combination thereof. Therefore, it can be easily integrated into existing semiconductor manufacturing processes.In an exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes a substrate having a first well of a first conductivity type, a first transistor, and a memory pick-up cell. The first transistor includes a first fin extending from the first well and having a first width and two first source / drain elements on the first fin. The first fin has the first conductivity type. The two first source / drain elements have a second conductivity type opposite to the first conductivity type. The memory pick-up cell includes: a second fin extending from the first well and having a second width at least three times the first width; two second source / drain elements on the second fin; and a stack of semiconductor layers over the second fin connecting the two second source / drain elements. The second fin and the two second source / drain elements have the first conductivity type.In an embodiment of the semiconductor device, the second width is not more than 10 times the first width. In an embodiment of the semiconductor device, the first transistor further includes a first gate stack disposed between the two first source / drain elements and a gate contact electrically connected to the first gate stack, and the memory pick-up cell further includes a second gate stack disposed between the two second source / drain elements, but does not include a gate contact electrically connected to the second gate stack.In an embodiment of the semiconductor device, the first conductivity type is n and the second conductivity type is p. In an alternative embodiment of the semiconductor device, the first conductivity type is p and the second conductivity type is n.In an embodiment of the semiconductor device, the first transistor and the memory pick-up cell are located in one and the same memory macro of the semiconductor device. In an embodiment, the second width is 10 nm to 100 nm.In an embodiment, the semiconductor device further includes a second transistor having a third fin extending from the first well and having the first conductivity type. The third fin has a third width. The first and third fins are arranged parallel to each other along a longitudinal direction and are spaced apart from each other along a transverse direction by a first distance. The second width is at least equal to a sum of the first width, the third width, and the first distance.In an embodiment where the substrate further includes a second well of the second conductivity type adjacent to the first well, the semiconductor device further includes a second memory pick-up cell comprising: a third fin extending from the second well; and a third source / drain element on the third fin, wherein the third fin and the third source / drain element have the second conductivity type. The second and third fins extend longitudinally along a same direction and are spaced apart from each other along a transverse direction by a distance of 20 nm to 60 nm.In another exemplary aspect, the present invention is directed to a semiconductor device including a substrate having an n-well adjacent to a p-well. The n-well and the p-well extend across a first region for memory bits and a second region for pickup cells. The semiconductor device further includes a plurality of first fin structures protruding from the p-well in the first region and a plurality of second fin structures protruding from the n-well in the first region. The first fin structures each have a first width and the second fin structures each have a second width. The semiconductor device further includes one or more third fin structures protruding from the p-well in the second region and one or more fourth fin structures protruding from the n-well in the second region. The one or more third fin structures each have a third width and the one or more fourth fin structures each have a fourth width. The fourth width is at least three times the second width.In some embodiments, two of the plurality of second fin structures are spaced apart from one another along a fin width direction by a first distance, the fourth width being at least equal to a sum of the first distance and twice the second width. In some embodiments, the first width is approximately equal to the third width and is at least twice the second width. In some embodiments, the first width is about one third of the third width. In some embodiments, the first width is approximately equal to the second width and is less than one half of the third width. In some embodiments, the first width is at least twice the second width.In yet another exemplary aspect, the present invention is directed to an integrated circuit (IC) layout. The IC layout includes: a first region for memory bits and a second region for pickup cells; an n-well extending in the first region and the second region; a p-well extending in the first region and the second region; first active regions over the p-well in the first region, the first active regions each having a first width; second active regions over the n-well in the first region, the second active regions each having a second width; third active regions over the p-well in the second region, the third active regions each having a third width; and fourth active regions over the n-well in the second region, the fourth active regions each having a fourth width. The fourth width is at least three times the second width, and the third width is at least equal to the first width.In some embodiments, the third width is at least three times the first width. In some embodiments, the first width is at least twice the second width. In some embodiments, the fourth width is no more than 10 times the second width. In some embodiments, the second width is 6 nm to 20 nm.

Claims

A semiconductor device comprising: a substrate (110) including a first well (202) of a first conductivity type; a first transistor (252a, 252b) comprising: a first fin (212) extending from the first well (202) and having a first width (w1), the first fin (212) having the first conductivity type, and two first source / drain elements (222) on the first fin (212), the two first source / drain elements (222) having a second conductivity type opposite the first conductivity type; and a memory pick-up cell (352) comprising: a second fin (312) extending from the first well (202) and having a second width (w3), said at least three times said first width (w1), two second source / drain elements (322) on said second fin (312), said second fin (312) and said two second source / drain elements (322) having said first conductivity type, and a stack of semiconductor layers (320) over said second fin (312) connecting said two second source / drain elements (322), said substrate (110) further comprising a second well (204) of said second conductivity type adjacent said first well (202), said semiconductor device further comprising: a second memory pick-up cell (354) having: a third fin (314) extending from said second well (204); and a third width (w4); two third source / drain elements (324) on the third fin (314), wherein the third fin (314) and the two third source / drain elements (324) have the second conductivity type, wherein the second and third fins (312, 314) extend in a longitudinal direction along a same direction and are spaced apart from each other along a transverse direction by a maximum distance (S 2) designed to maximize the second width (w 3) of the second fin (312) and the third width (w 4) of the third fin (314).The semiconductor device according to claim 1, wherein the second width (w3) is not more than 10 times the first width (w1).The semiconductor device of claim 1, wherein the first transistor (252a, 252b) further comprises a first gate stack (230) disposed between the two first source / drain elements (222) and a gate contact (240) electrically connected to the first gate stack (230), and the memory pick-up cell (352) further comprises a second gate stack (330) disposed between the two second source / drain elements (322) but does not comprise a gate contact electrically connected to the second gate stack (330).The semiconductor device according to claim 1 or 2, wherein the first conductivity type is n and the second conductivity type is p.The semiconductor device according to claim 1 or 2, wherein the first conductivity type is p and the second conductivity type is n.The semiconductor device of any preceding claim, wherein the first transistor (252a, 252b) and the memory pick-up cell (352) are located in one and the same memory macro (102) of the semiconductor device.The semiconductor device according to any one of the preceding claims, wherein the second width (w3) is 10 nm to 100 nm.The semiconductor device of any preceding claim, further comprising: a second transistor (252b, 252a) having a fourth fin (212) extending from the first well (202) and having the first conductivity type, the fourth fin (212) having a fourth width (w1), the first and fourth fins (212) being arranged parallel to each other along the longitudinal direction and spaced apart from each other along the transverse direction by a first distance, the second width (w3) being at least equal to a sum of the first width (w1), the fourth width (w1), and the first distance.The semiconductor device according to any one of the preceding claims, wherein the maximum distance (S2) is 60 nm.A semiconductor device comprising: a substrate (110) having an n-well (204) adjacent a p-well (202, 206), the n-well (204) and the p-well (202, 206) extending over a first region (200) for memory bits and a second region (300) for pick-up cells; a plurality of first fin structures (212, 216) protruding from the p-well (202, 206) in the first region (200), the first fin structures (212, 216) each having a first width (w1); a plurality of second fin structures (214) protruding from the n-well (204) in the first region (200), the second fin structures (214) each having a second width (w2); one or more third fin structures (312, 316) protruding from the p-well (202, 206) in the second region (300), the one or more third fin structures (312, 316) each having a third width (w3); And one or more fourth fin structures (314) protruding from the n-well (204) in the second region (300), wherein the one or more fourth fin structures (314) each have a fourth width (w4), wherein the fourth width (w4) is at least three times the second width (w2), and wherein the third fin structures (312, 316) and the fourth fin structures (314) extend in a longitudinal direction along a same direction and are spaced apart along a transverse direction by a maximum distance (S2) designed to maximize the third width (w3) of the third fin structures (312, 316) and the fourth width (w4) of the fourth fin structures (314).The semiconductor device of claim 10, wherein two of the plurality of second fin structures (214) are spaced apart from each other along a fin width direction by a first distance, wherein the fourth width (w4) is at least equal to a sum of the first distance and twice the second width (w2).The semiconductor device according to claim 10 or 11, wherein the first width (w1) is approximately equal to the third width (w3) and is at least twice the second width (w2).The semiconductor device of claim 10 or 11, wherein the first width (w1) is about one third of the third width (w3).The semiconductor device according to claim 10 or 11, wherein the first width (w1) is approximately equal to the second width (w2) and is less than a half of the third width (w3).The semiconductor device according to claim 10 or 11, wherein the first width (w1) is at least twice the second width (w2).AN IC layout (integrated circuit) comprising: a first region for memory bits (200) and a second region for pickup cells (300); an n-well (204) extending in the first region (200) and the second region (300); a p-well (202, 206) extending in the first region (200) and the second region (300); first active regions (212, 216) over the p-well (202, 206) in the first region (200), the first active regions (212, 216) each having a first width (w1); second active regions (214) over the n-well (204) in the first region (200), the second active regions (214) each having a second width (w2); third active regions (312, 316) over the p-well (202, 206) in the second region (300), the third active regions (312, 316) each having a third width (w3); and fourth active regions (314) above the n-well (204) in the second region (300), wherein the fourth active regions (314) each have a fourth width (w4), wherein the fourth width (w4) is at least three times the second width (w2) and the third width (w3) is at least equal to the first width (w1), wherein the third active regions (312, 316) and the fourth active regions (314) extend in a longitudinal direction along one and the same direction and are spaced apart from each other along a transverse direction by a maximum distance (S2) designed such that the third width (w3) of the third active regions (312, 316) and the fourth width (w4) of the fourth active regions (314) are maximized.The IC layout of claim 16, wherein the third width (w3) is at least three times the first width (w1).The IC layout according to claim 16 or 17, wherein the first width (w1) is at least twice the second width (w2).The IC layout according to any one of claims 16 to 18, wherein the fourth width (w4) is not more than 10 times the second width (w2).The IC layout according to any one of claims 16 to 19, wherein the second width (w2) is 6 nm to 20 nm.

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