SEMICONDUCTOR DEVICE AND METHOD

Abstract

Method comprising: Depositing an ILD layer (76) over an epitaxial source / drain region (70), the epitaxial source / drain region (70) comprising a main layer (70B), a semiconductor CESL (70C) on the main layer (70B), and a semiconducting dummy layer (70D) on the semiconductor CESL (70C), wherein the semiconductor CESL (70C) is formed from an undoped semiconductor material; Exposing a first part of the dummy layer (70D) through the ILD layer (76); Removing the first portion of the dummy layer (70D) with a first etching process to expose a second portion of the semiconductor CESL (70C), wherein the first etching process etches the dummy layer (70D) at a higher rate than the semiconductor CESL (70C); Removing the second portion of the semiconductor CESL (70C) to expose a third portion of the main layer (70B); and Forming a first source / drain contact (98) on the third part of the main layer (70B).

Description

BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.The semiconductor industry constantly improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size so that more components can be integrated into a particular area. However, as the minimum feature sizes are reduced, additional problems that should be addressed arise. With regard to the prior art, reference is made to U.S. Pat. No. 2016 / 0087053 A1, U.S. Pat. No. 2020 / 01 05876 A1, and U.S. Pat. No. 2020 / 0105932 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various elements are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1 illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. FIGS. 2 and 3 are three-dimensional views of intermediate stages in the fabrication of FinFETs, in accordance with some embodiments. FIGS. 4A-12B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some embodiments. FIGS. 13A-16B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments. FIGS. 17A-21B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments. FIGS. 22A-25B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below for the purpose of simplifying the present disclosure. These are of course merely examples. For example, the formation of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe a ratio of an element or feature to one or more other element(s) or feature(s) depicted in the figures. The spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (90 degrees or rotated in other orientations) and the spatially relative descriptors used herein may also be interpreted accordinglyAccording to some embodiments, a multi-layer epitaxial source / drain region is grown with an epitaxial interlayer that may serve as a semiconductor contact etch stop layer (CESL) during subsequent processing. The semiconductor CESL may be used to protect the underlying epitaxial layers and control etch losses during a subsequent source / drain contact formation process. Performance of the resulting FinFETs may thus be improved by increasing the contact area of the source / drain contacts and by reducing etch losses of the epitaxial source / drain regions.FIG. 1 illustrates an example of simplified Fin Field Effect Transistors (FinFETs) in a three-dimensional view, in accordance with some embodiments. Some other features of the FinFETs (discussed below) are omitted for clarity of illustration. The illustrated FinFETs may be electrically connected or coupled in a manner to operate as, for example, one or more transistors, such as two transistors.The FinFETs include fins 52 that extend from a substrate 50. Shallow trench isolation (STI) regions 56 are disposed over the substrate 50, and the fins 52 protrude above and between adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separate from the substrate 50, the term "substrate" as used herein may be used to refer only to the semiconductor substrate or a semiconductor substrate having isolation regions. Additionally, although the fins 52 are illustrated as a single continuous material of the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, the fins 52 refer to the portions that extend between the adjacent STI regions 56.Gate dielectrics 82 are located along sidewalls and over top surfaces of fins 52, and gate electrodes 84 are located over gate dielectrics 82. source / drain regions 70 are disposed in opposite sides of fins 52 with respect to gate dielectrics 82 and gate electrodes 84. Gate spacers 66 separate the source / drain regions 70 from the gate dielectrics 82 and gate electrodes 84. one or more interlayer dielectric (ILD) layers (not shown, discussed in greater detail below) are disposed over the source / drain regions 70 and gate electrodes 84, and contacts (not shown, discussed in greater detail below) to the source / drain regions 70 and gate electrodes 84 are formed by the ILD layer(s). In embodiments where multiple transistors are formed, different transistors may share the source / drain regions 70. In embodiments where a transistor is formed of multiple fins 52, adjacent source / drain regions 70 may be electrically connected, such as by connecting the source / drain regions 70 by epitaxial growth or by coupling the source / drain regions 70 to a same source / drain contact.FIG. 1 further illustrates a plurality of reference cross-sections. Cross-section A-A is along a longitudinal axis of a fin 52 and in a direction of, for example, current flow between the source / drain regions 70 of the FinFETs. Cross-section B-B is perpendicular to cross-section A-A and extends through the source / drain regions 70 of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity.FIGS. 2 and 3 are three-dimensional views of intermediate stages in the fabrication of FinFETs, in accordance with some embodiments. A substrate 50 is processed to form the FinFETs. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-impurity) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.The substrate 50 has a region 50N and a region 50P. Region 50N may serve to form n-type devices, such as NMOS transistors, e.g., n-type FinFETs. Region 50P may serve to form p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The region 50N may be physically separated from the region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region 50N and the region 50P.In FIG. 2, fins 52 are formed that extend from the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 may be formed in the substrate 50 by etching trenches in the substrate 50. The etch may be any suitable etching process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic.The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes that include dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligning processes that allow patterns to be created that have, for example, smaller pitches than those otherwise available using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins.STI regions 56 are formed over substrate 50 and between adjacent fins 52. As an example of forming the STI regions 56, an insulating material is formed over the intermediate structure. The insulating material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., a remote plasma system chemical vapor deposition (CVD) material deposition and post-curing to convert it to another material such as an oxide), the like, or a combination thereof. Other insulating materials formed by any suitable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. A anneal process may be performed once the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the fins 52. Some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along a surface of the substrate 50 and the fins 52. Thereafter, a fill material such as those discussed above may be formed over the liner. A removal process is applied to the insulating material to remove excess insulating material over the fins 52. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP), an etch back process, combinations thereof, or the like may be used. The planarization process exposes the fins 52 such that top surfaces of the fins 52 and the isolation material are planar after the planarization process is completed. The insulating material is then recessed, with remaining portions of the insulating material forming the STI regions 56. The isolation material is recessed such that top portions of fins 52 protrude in region 50N and region 50P between adjacent STI regions 56. After the recess, exposed portions of the fins 52 extend over top surfaces of the STI regions 56.Further, the top surfaces of the STI regions 56 may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 56 may be formed flat, convex, and / or concave by a suitable etch. The STI regions 56 may be recessed using a suitable etching process, such as that selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 52). For example, chemical oxide removal with a suitable etching process using, for example, dilute hydrofluoric acid (dHF acid) may be used.The process described above is only one example of how the fins 52 may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures may be epitaxially grown in the trenches and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures may be used for the fins 52. For example, the fins 52 may be recessed after the isolation material of the STI regions 56 is planarized with the fins 52, and a material different from the fins 52 may be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 include the recessed material as well as the epitaxially grown material disposed over the recessed material. In yet another embodiment, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer. Heteroepitaxial structures may then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 52. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may avoid previous and subsequent implantations, although in situ and implantation doping may be shared.Still further, it may be advantageous to epitaxially grow a material in region 50N (e.g., an NMOS region) that is different from the material in region 50P (e.g., a PMOS region). In various embodiments, upper portions of the fins 52 may be formed of silicon germanium (Si x Ge 1-x, where x may be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.Further, suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well are formed in both the region 50N and the region 50P.In the embodiments with different well types, the different implantation steps for region 50N and region 50P may be accomplished using a photoresist or other masks (not shown). For example, a photoresist may be formed over the fins 52 and the STI regions 56 in the region 50N. The photoresist is patterned to expose the region 50P of the substrate 50, such as a PMOS region. The photoresist may be formed using a spin-on technique and may be patterned using suitable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in region 50P and the photoresist may serve as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like, implanted in the region to a concentration of equal to or less than 10 18 cm -3, such as from about 10 17 cm -3 to about 10 18 cm -3. After the implantation, the photoresist is removed, such as by a suitable ashing process.After the implantations of region 50P, a photoresist is formed over fins 52 and STI regions 56 in region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, such as the NMOS region. The photoresist may be formed using a spin-on technique and may be patterned using suitable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in region 50N and the photoresist may serve as a mask to substantially prevent p-type impurities from being implanted in region 50P, such as a PMOS region. The p-type impurities may be boron, BF 2, indium, or the like, implanted in the region to a concentration of equal to or less than 10 18 cm -3, such as from about 10 17 cm -3 to about 10 18 cm -3. After the implantation, the photoresist may be removed, such as by a suitable ashing process.After the implantations of the region 50N and the region 50P, an anneal may be performed to activate the p- and / or n-impurities that have been implanted. In some embodiments, epitaxial fin growth materials may be in situ doped during growth, preventing the implants, although in situ and implant doping may be shared.In FIG. 3, dummy gate dielectrics 60 are formed over fins 52, and dummy gate electrodes 62 are formed over dummy gate dielectrics 60. The dummy gate dielectrics 60 and dummy gate electrodes 62 may collectively be referred to as dummy gate stacks. The dummy gate stacks extend along sidewalls and top surfaces of the fins 52.As an example of forming dummy gate dielectrics 60 and dummy gate electrodes 62, a dummy dielectric layer is formed on fins 52. The dummy dielectric layer may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to suitable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer may be deposited over the dummy dielectric layer and then planarized, such as by CMP. The mask layer may be deposited over the dummy gate layer. The dummy gate layer may be a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, metals, or the like. The dummy gate layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used for depositing conductive materials. The dummy gate layer may be made of other materials that have high etch selectivity from the etch of the STI regions 56. The mask layer may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer and a single mask layer are formed over the region 50N and the region 50P. In some embodiments, the dummy dielectric layer may be deposited such that the dummy dielectric layer covers the STI regions 56 extending between the dummy gate layer and the STI regions 56. The mask layer is then patterned using suitable photolithography and etching techniques to form masks 64. The pattern of the masks 64 is then transferred to the dummy gate layer by a suitable etching technique to form the dummy gate electrodes 62. The pattern of the masks 64 is further transferred to the dummy dielectric layer to form the dummy gate dielectrics 60. Dummy gate electrodes 62 cover respective channel regions 58 (see FIG. 4A ) of fins 52. dummy gate electrodes 62 may also have a longitudinal direction substantially perpendicular (within process constraints) to the longitudinal direction of respective fins 52.Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-load process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs.FIGS. 4A-12B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some embodiments. FIGS. 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A are cross-sectional views illustrated along reference cross-section A-A in FIG. 1, except that only one source / drain region 70 is illustrated. FIGS. 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 12C, and 12D are cross-sectional views illustrated along reference cross-section B-B in FIG. 1, except that only two fins 52 are illustrated.In FIGS. 4A and 4B, gate spacers 66 are formed on exposed surfaces of dummy gate electrodes 62, masks 64, and / or fins 52. The gate spacers 66 may be formed by conformally depositing one or more layers of insulating material and then etching the insulating material. The insulating material of the gate spacers 66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride, a combination thereof, or the like, and may be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. In some embodiments, the gate spacers 66 are formed of one or more Siliziumoxycarbonitridschicht(en), such as two silicon oxycarbonitride layers. Once the insulating material is formed, it may be etched, for example, by wet etching to form the gate spacers 66. The etching of the gate spacers 66 may be anisotropic. After etching, the gate spacers 66 may have curved sidewalls (as illustrated) or may have straight sidewalls (not illustrated).Prior to or during the formation of the gate spacers 66, implants for lightly doped source / drain (LDD) regions 68 may be performed. In embodiments with various device types, similar to the discussed implants, a mask, such as a photoresist, may be formed over the region 50N while the region 50P is exposed, and a suitable type (e.g., p) of impurities may be implanted into the exposed fins 52 in the region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region 50P during exposure of the region 50N, and a suitable type of impurity (e.g., n) may be implanted into the exposed fins 52 in the region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities discussed above, and the p-type impurities may be any of the p-type impurities discussed above. The lightly doped source / drain regions may have a impurity concentration in the range of about 10 15 cm -3 to about 10 16 cm -3. Anneal may be used to activate the implanted impurities.Epitaxial source / drain regions 70 are then formed in the fins 52. The epitaxial source / drain regions 70 are formed in the fins 52 such that each dummy gate electrode 62 is disposed between corresponding adjacent pairs of the epitaxial source / drain regions 70. The epitaxial source / drain regions 70 extend into and may also penetrate the LDD regions 68. In some embodiments, the gate spacers 66 are used to offset the epitaxial source / drain regions 70 from the dummy gate electrodes 62 by an appropriate lateral distance such that the epitaxial source / drain regions 70 do not short-circuit subsequently formed gates of the resulting FinFETs. The epitaxial source / drain regions 70 may be formed to apply stress in the respective channel regions 58, thereby improving performance.The epitaxial source / drain regions 70 in the region 50N, e.g., the NMOS region, may be formed by masking the region 50P, e.g., the PMOS region, and etching source / drain regions of the fins 52 in the region 50N to form recesses 52R in the fins 52. Then, the epitaxial source / drain regions 70 in the region 50N are epitaxially grown in the recesses 52R. The epitaxial source / drain regions 70 in the region 50N may have faceted surfaces protruding from corresponding surfaces of the fins 52 (discussed in further detail below).The epitaxial source / drain regions 70 in the region 50P, e.g., the PMOS region, may be formed by masking the region 50N, e.g., the NMOS region, and etching source / drain regions of the fins 52 in the region 50P to form recesses 52R in the fins 52. Then, the epitaxial source / drain regions 70 in the region 50P are epitaxially grown in the recesses 52R. The epitaxial source / drain regions 70 in the region 50P may also have faceted surfaces protruding from corresponding surfaces of the fins 52 (discussed in further detail below).Each epitaxial source / drain region 70 includes function layers 70A and 70B, a semiconductor CESL 70C, a dummy layer 70D, and (optionally) a termination layer 70E, each of which is a semiconductor material layer grown by a suitable epitaxial growth process. The function layers 70A and 70B are formed of materials suitable for the desired FETs and are doped. Portions of the semiconductor CESL 70C and dummy layer 70D are removed during subsequent processing such that subsequently formed source / drain contacts may extend deep into the epitaxial source / drain region 70 and contact the functional layers 70B. The termination layer 70E is a highly doped layer that protects the epitaxial source / drain region 70 from oxidation during subsequent processing. Each of these layers is discussed in more detail below.The functional layers 70A and 70B are formed of a suitable doped semiconductor material as appropriate for n- or p-type FinFETs. For example, when the fins 52 in the region 50N are silicon, the functional layers 70A and 70B in the region 50N may include materials that exert a tensile strain in the channel regions 58, such as silicon, phosphorus-doped silicon (e.g., silicon phosphide), silicon carbide, phosphorus-doped silicon carbide, or the like. Likewise, when the fins 52 in the region 50P are silicon, the functional layers 70A and 70B in the region 50P may include materials that exert compressive strain in the channel regions 58, such as silicon germanium, boron doped silicon germanium, germanium, germanium tin, or the like. The functional layers 70A and 70B are in situ doped with n- and / or p-type impurities during growth to form source / drain regions. The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed above. The functional layers 70A and 70B may be graded or non-graded, and may each include multiple sub-layers, such as 2 to 4 sub-layers.The function layers 70A are grown along sidewalls of the recesses 52R, and the function layers 70B are grown on the function layers 70A. The functional layers 70A may also be referred to as liner layers, and the functional layers 70B may also be referred to as main layers. The functional layers 70A may be grown to a low dopant concentration and thickness that may promote adhesion to the fins 52. For example, the functional layers 70A may have a dopant concentration of less than about 10 19 cm -3 and a thickness in the range of about 1 nm to about 18 nm. The functional layers 70B may be grown to a high dopant concentration and large thickness to provide sufficient main carriers for the resulting FinFETs. For example, the functional layers 70B may have a dopant concentration in the range of about 10 19 cm -3 to about 10 21 cm -3 and a thickness in the range of about 10 nm to about 70 nm. In embodiments where the functional layers 70A and 70B comprise silicon germanium, the functional layers 70A may have a lower concentration of germanium than the functional layers 70B, which may also promote adhesion to the fins 52. For example, the functional layers 70A may have a germanium concentration in the range of about 15 at % to about 30 at %, and the functional layers 70B may have a germanium concentration in the range of about 35 at % to about 70 at %.Although two functional layers 70A and 70B are illustrated in each epitaxial source / drain region 70, it should be appreciated that the epitaxial source / drain regions 70 may include any number of functional layers. For example, more than two functional layers may be included in each epitaxial source / drain region 70. Likewise, liner layers may be omitted and only one functional layer (e.g., a main layer) may be included in each epitaxial source / drain region 70.The semiconductor CESLs 70C and dummy layers 70D are partially removed in subsequent processing and may be undoped. During a subsequent contact etching process, the semiconductor CESLs 70C and dummy layers 70D are etched to form recesses in the epitaxial source / drain regions 70. The semiconductor CESLs 70C and dummy layers 70D may be formed of different materials and may be formed of materials other than the function layers 70A and 70B and termination layers 70E. The semiconductor CESLs 70C are formed of a material having high etching selectivity with the material of the dummy layers 70D and the gate spacers 66 relative to the contact etching process. The semiconductor CESLs 70C therefore protect underlying epitaxial layers during the subsequent contact etch process for removing the dummy layers 70D. The semiconductor CESLs 70C may be formed of an undoped semiconductor material such as silicon, silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon carbide. In some embodiments, the semiconductor CESLs 70C are formed of silicon and the dummy layers 70D are formed of silicon germanium, wherein the silicon is undoped and the silicon germanium has a high germanium concentration, such as a germanium concentration in the range of about 60 at % to about 65 at %. In some embodiments, the semiconductor CESLs 70C are formed of silicon and the dummy layers 70D are formed of aluminum oxide. The semiconductor CESLs 70C are sufficiently thick to provide protection for the underlying epitaxial layers. For example, the semiconductor CESLs 70C may have a thickness of at least 1 nm, such as a thickness in the range of about 1 nm to about 10 nm. the dummy layers 70D are sufficiently thick that subsequently formed source / drain contacts may extend deeply into the epitaxial source / drain regions 70 when the dummy layers 70D are etched. For example, dummy layers 70D may have a thickness in the range of about 1 nm to about 10 nm.Termination layers 70E are formed of any suitable material as appropriate for n- or p-type FinFETs. The termination layers 70E may be formed of similar materials as the underlying functional layers 70A and 70B. For example, the function layers 70A and 70B and the termination layers 70E in the region 50N may be formed of phosphorus-doped silicon, and the function layers 70A and 70B and the termination layers 70E in the region 50P may be formed of boron-doped silicon germanium. The termination layers 70E are grown to a small thickness and low dopant concentration, which may help protect the underlying epitaxial layers from oxidation during a subsequent contact etch process. For example, the termination layers 70E may have a dopant concentration of up to about 10 21 cm -3 and a thickness in the range of about 1 nm to about 20 nm. In embodiments where the termination layers 70E include silicon germanium, the termination layers 70E may have a lower concentration of germanium than the function layers 70B. For example, the termination layers 70E may have a germanium concentration of up to about 35 at %.Due to the epitaxial processes used to form the epitaxial source / drain regions 70 in the region 50N and the region 50P, top surfaces of the epitaxial source / drain regions have facets that extend laterally beyond sidewalls of the fins 52. These facets cause some of the layers of adjacent epitaxial source / drain regions 70 of a same FinFET to fuse. Specifically, adjacent functional layers 70B, semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E (when formed) fuse. In the illustrated embodiments, gate spacers 66 are formed that cover a portion of the sidewalls of fins 52 that extend over STI regions 56, thereby blocking epitaxial growth. In some other embodiments, the etch used to form the gate spacers 66 may be adjusted to remove the spacer material such that the epitaxially grown region may extend to the surface of the STI regions 56.The top faceted surfaces of the functional layers 70B define top basins 72U that are laterally disposed between the fins 52. The lower faceted surfaces of the functional layers 70B define lower reservoirs 72L that are also laterally disposed between the fins 52. The lower basins 72L face the substrate 50, and the upper basins 72U face away from the substrate 50. The semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E are formed to fill the upper basins 72U. Specifically, the semiconductor CESLs 70C and dummy layers 70D are conformally formed in the upper basins 72U, and the termination layers 70E (if present) fill remaining portions of the upper basins 72U. Some of the epitaxial layers may not be formed in the lower basin 72L. Specifically, the semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E are not formed in the lower basin 72L.As an example of forming the epitaxial source / drain regions 70 with the termination layers 70E, multiple epitaxial growth steps and a etch back step may be performed. Specifically, the function layers 70A are grown on sidewalls of the recesses 52R, the function layers 70B are grown on the function layers 70A, the semiconductor CESLs 70C are grown on the function layers 70B, and the dummy layers 70D are grown on the semiconductor CESLs 70C. An etch back process is then performed to level the top surfaces of the layers 70B, 70C, 70D. After the etch back process, the termination layers 70E are grown on the planarized surfaces of the layers 70B, 70C, 70D. The termination layers 70E may thus cover the underlying layers 70B, 70C, 70D and may fill the upper basins 72U such that the final top surfaces of the epitaxial source / drain regions 70 are flat or concave.As the epitaxial layers are grown in the recesses 52R, they have a conformal shape in the cross-section illustrated in FIG. 4A (e.g., in a plane extending parallel to the fins 52). However, since the surfaces of the epitaxial source / drain region 70 are faceted, the epitaxial layers protrude from corresponding surfaces of the fins 52 in the cross-section illustrated in FIG. 4B (e.g., in a plane extending perpendicular to the fins 52). For example, the semiconductor CESLs 70C and dummy layers 70D are grown to extend over the top surfaces of the function layers 70B in the cross section illustrated in FIG. 4B but not in the cross section illustrated in FIG. 4A. It should be appreciated that an element that does not extend through an epitaxial layer in one cross-section may still extend through that epitaxial layer in a different cross-section.A first ILD layer 76 is then deposited over the various elements. The first ILD layer 76 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include a silicate glass such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by a suitable process may be used. In some embodiments, a CESL 74 dielectric is disposed between the first ILD layer 76 and the epitaxial source / drain regions 70, the gate spacers 66, and the masks 64. The dielectric CESL 74 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or the like, with a different etch rate than the material of the overlying first ILD layer 76, and may be formed by a suitable deposition process.In FIGS. 5A and 5B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD layer 76 with the top surfaces of the dummy gate electrodes 62 or the masks 64. The planarization process may also remove the masks 64 on the dummy gate electrodes 62 and portions of the gate spacers 66 along sidewalls of the masks 64. After the planarization process, top surfaces of dummy gate electrodes 62, gate spacers 66, and first ILD layer 76 are planar. Therefore, the top surfaces of the dummy gate electrodes 62 are exposed by the first ILD layer 76. In some embodiments, the masks 64 may remain, in which case the planarization process leveles the top surface of the first ILD layer 76 with the top surfaces of the top surface of the masks 64.In FIGS. 6A and 6B, the dummy gate electrodes 62, and optionally the dummy gate dielectrics 60, are removed and replaced with replacement gates. The replacement gates include gate dielectrics 82 and gate electrodes 84. The replacement gates may also be referred to as "gate stacks" or "metal gates". The replacement gates extend along sidewalls of the channel regions 58 of the fins 52.As an example of forming the replacement gates, the dummy gate electrodes 62 and the masks 64, if present, are removed in one or more etch step(s) to form recesses. Portions of the dummy gate dielectrics 60 in the recesses may also be removed. In some embodiments (not shown), only the dummy gate electrodes 62 are removed and the dummy gate dielectrics 60 remain and are exposed by the recesses. For example, dummy gate dielectrics 60 may be removed from recesses in a first region of a die (e.g., a core logic region) and remain in recesses in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate electrodes 62 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reaction gas(s) that selectively remove the material of dummy gate electrodes 62 at a higher rate than the materials of first ILD layer 76 and gate spacers 66. The recesses expose the fins 52. Specifically, the channel regions 58 are exposed by the recesses. Each channel region 58 is disposed between adjacent pairs of the epitaxial source / drain regions 70. During removal, the dummy gate dielectrics 60 may be used as etch stop layers when the dummy gate electrodes 62 are etched. The dummy gate dielectrics 60 may then optionally be removed after the removal of the dummy gate electrodes 62. After removal, the gate dielectrics 82 are conformally deposited in the recesses, such as on the top surfaces and sidewalls of the fins 52 and sidewalls of the gate spacers 66. In some embodiments, the gate dielectrics 82 include silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectrics 82 include a high-k dielectric material, and in these embodiments, the gate dielectrics 82 may have a k value greater than about 7.0, and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of the gate dielectrics 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In embodiments where portions of the dummy gate dielectrics 60 remain in the recesses, the gate dielectrics 82 include a material of the dummy gate dielectrics 60 (e.g., silicon oxide). The gate electrodes 84 are each deposited over the gate dielectrics 82, filling the remaining portions of the recesses. The gate electrodes 84 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multilayers thereof. For example, although a single-layer gate electrode 84 is illustrated, each gate electrode 84 may include any number of liner layers, any number of work function tuning layers, and a fill material. After filling the gate electrodes 84, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectrics 82 and the material of the gate electrodes 84, the excess portions overlying the top surface of the first ILD layer 76. The remaining portions of material of the gate dielectrics 82 and gate electrodes 84 thus form replacement gates of the resulting FinFETs.Gate masks 86 are then formed over the replacement gates. The replacement gates (e.g., gate dielectrics 82 and gate electrodes 84) may be recessed and one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, may be filled into the recesses. A planarization process may be performed to remove excess portions of the dielectric material extending over the first ILD layer 76. The gate masks 86 include portions of the dielectric material remaining in the recesses.In FIGS. 7A and 7B, portions of the first ILD layer 76 and dielectric CESL 74 are removed to form contact openings 90. The contact openings 90 expose the epitaxial source / drain regions 70, e.g., the termination layers 70E. A suitable etching process that is selective to the first ILD layer 76 and does not remove the gate spacers 66 or gate masks 86 may be performed to form the contact openings 90. Another etching process may then be performed to remove the dielectric CESL 74. In some embodiments, the removal is anisotropic etching and remaining vertical portions of the dielectric CESL 74 may remain along the gate spacers 66. Such remaining horizontal portions (not shown) may have a small width, such as a width of less than 1 nm, and may protect the functional layers 70B during a subsequent etch (discussed with respect to FIGS. 8A and 8B ).The etching process(s) may be performed with an etch mask 92, such as a photoresist, having a structure of the contact openings 90. In this embodiment, the etching mask 92 has a pattern of slit openings. The slot openings are stripes that are perpendicular to and overlap the gate electrodes 84 and parallel to and overlap the fins 52. As such, the entire first ILD layer 76 in the cross-section illustrated in FIG. 7A is removed to form the contact openings 90. In other embodiments (discussed in more detail below), the etch mask 92 may include other types of openings, resulting in contact openings 90 of different dimensions. After the etch process(s) the etch mask 92 may be removed, such as by a suitable ashing process.In FIGS. 8A and 8B, exposed portions of the termination layers 70E are removed to expose portions of the dummy layers 70D. The exposed portions of the dummy layers 70D are then removed to expose portions of the semiconductor CESLs 70C. The contact openings 90 are thus enlarged. The removal can be carried out by one or more etching step(s). The etch may be any suitable etch process selective to dummy layers 70D and termination layers 70E, e.g., etch the material of dummy layers 70D and termination layers 70E at a higher rate than the material of semiconductor CESLs 70C. For example, the etch rate of the material of dummy layers 70D and termination layers 70E may be about 10 to about 2000 times greater than the etch rate of the material of semiconductor CESLs 70C of the associated etch process. The etching process may be anisotropic.In embodiments where the semiconductor CESLs 70C are formed of silicon and the dummy layers 70D are formed of silicon germanium, the etching process may be anisotropic wet etching performed with one of a plurality of etching solutions. In some embodiments, the etching solution is a mixture of HCl, H 2 O 2 and water. In some embodiments, the etching solution is a mixture of deionized water (DIW) and ozone, e.g., ozonized DIW. In some embodiments, the etching solution is a mixture of H 2 SO 4 and H 2 O 2. In such embodiments, the etching process may be performed for a duration ranging from about 5 seconds to about 300 seconds.In embodiments where the semiconductor CESLs 70C are formed of silicon and the dummy layers 70D are formed of aluminum oxide, the etching process may be anisotropic wet etching performed with ammonia (NH 3). In such embodiments, the etching process may be performed for a duration ranging from about 5 seconds to about 200 seconds.In FIGS. 9A and 9B, the exposed portions of the semiconductor CESLs 70C in the contact openings 90 are oxidized to form dielectric layers 94. In embodiments where the semiconductor CESLs 70C are silicon, the dielectric layers 94 may be silicon oxide. Unexposed portions of the semiconductor CESLs 70C, such as portions not exposed by the contact openings 90, are not oxidized. In some embodiments, the oxidation may be by natural oxidation, such as by exposing the structure to an oxygen-containing atmosphere. In some embodiments, the oxidation may be accomplished by a wet oxygen treatment process, such as by exposing the structure to ozonized deionized water or hydrogen peroxide. In some embodiments, the oxidation may be performed by a dry oxygen treatment process, such as by exposing the structure to oxygen gas at a high temperature, such as a temperature in the range of about 80° C. to about 500° C. A dry oxygen treatment process may be performed with a plasma to damage the surface of the semiconductor CESLs 70C and thus promote oxidation. For example, a plasma with argon and oxygen may be generated during the dry oxygen treatment process.In FIGS. 10A and 10B, the dielectric layers 94 are removed, such that the contact openings 90 are enlarged. After removal, portions of the functional layers 70B are exposed, and in particular, the upper basins 72U are exposed. Source / drain contacts are then formed in the upper basin 72U, whereby the source / drain contacts may come into contact with a large surface area of the functional layers 70B, which may reduce the resistance of the source / drain contacts. By exposing the upper basins 72U through the use of an additional CESL (e.g., the semiconductor CESLs 70C), the amount of etch losses of the functional layers 70B may be reduced. The functional layers 70B have a high dopant concentration and thus reducing their losses may increase the performance of the resulting FinFETs. Further, the use of timed etches may be avoided, thereby avoiding both overetch of the functional layers 70B and underetch of the dielectric CESL 74.The dielectric layers 94 may be removed by a suitable oxide removal or cleaning process. In embodiments where the dielectric layers 94 are silicon oxide, the oxide removal process is a wet or dry etch performed with nitrogen trifluoride (NF 3), ammonia (NH 3), dilute hydrofluoric acid (dNH acid), a fluorocarbon (e.g., fluoromethane (CH 3 F), tetrafluoromethane (CF 4) or the like), or a combination thereof. For example, the etching may be a wet etch performed with dHF for a duration ranging from about 10 seconds to about 30 seconds. The etching does not remove the unoxidized portions of the semiconductor CESLs 70C. The etch is selective to the dielectric layers 94, e.g., etches the material of the dielectric layers 94 at a higher rate than the material of the functional layers 70B. For example, the etch rate of the material of the dielectric layers 94 may be about 10 to about 2000 times greater than the etch rate of the material of the functional layers 70B with respect to the etch process.After the etch, upper portions of the contact openings 90 (e.g., portions extending through the CESL 74 and first ILD dielectric layer 76) have a width W 1, which may be in the range of about 8 nm to about 20 nm, and lower portions of the contact openings 90 (e.g., portions extending through the dummy layers 70D and into the epitaxial source / drain regions 70) have a width W 2, which may be in the range of about 6 nm to about 19 nm. The width W 1 is greater than the width W 2. For example, the width W 1 may be greater than the width W 2 by about 3 nm to about 4 nm, and the ratio of W 1: W 2 may be in the range of about 1 to about 1.5. The widths W 1 and W 2 are measured in the cross-section illustrated in FIG. 10A, although the first ILD layer 76 and dummy layers 70D are illustrated in the cross-section illustrated in FIG. 10B. Due to the conformal type of epitaxy, the semiconductor CESLs 70C and dummy layers 70D (see FIGS. 4A and 4B ) may have a continuously decreasing width in a direction D 1 extending from the top surfaces of the epitaxial source / drain regions 70 to the bottom surfaces of the epitaxial source / drain regions 70. In other words, the width W 2 may decrease continuously in the direction D 1.In FIGS. 11A and 11B, lower source / drain contacts 98 are formed in the contact openings 90. A liner such as a diffusion barrier layer, an adhesion layer, or the like and a conductive material are formed in the contact holes 90. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, ruthenium, aluminum, copper, silver, gold, nickel, or the like, and may be formed by deposition, plating, or the like. A planarization process, such as CMP, may be performed to remove excess material from the top surface of the first ILD layer 76. The remaining liner and conductive material form the lower source / drain contacts 98. the lower source / drain contacts 98 are physically and electrically coupled to the epitaxial source / drain regions 70. After formation, upper portions of the lower source / drain contacts 98 are surrounded by the dielectric CESL 74, middle portions of the lower source / drain contacts 98 are surrounded by the termination layers 70E, and lower portions of the lower source / drain contacts 98 are surrounded by the function layers 70B. Silicides 96 may be disposed between the epitaxial source / drain regions 70 and the lower source / drain contacts 98. The silicides 96 may be formed by depositing a conductive material in the contact openings 90 and performing an anneal. The conductive material may be cobalt, titanium, titanium nitride, nickel, the like, or combinations thereof. After annealing, the silicides 96 may comprise TiSi 2, CoSi 2 or the like. The silicides 96 may be in contact with sidewalls of the remaining portions of the termination layers 70E.In FIGS. 12A and 12B, a second ILD layer 102 is deposited over the first ILD layer 76. In some embodiments, the second ILD layer 102 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD layer 102 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. An etch stop layer 100 is deposited between the second ILD layer 102 and the bottom source / drain contacts 98, gate masks 86, gate spacers 66, and dielectric CESL 74. The etch stop layer 100 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or the like, having a different etch rate than the material of the overlying second ILD layer 102, and may be formed by a suitable deposition process.Then, upper source / drain contacts 104 and gate contacts 106 are formed. Openings for the top source / drain contacts 104 are formed through the second ILD layer 102 and etch stop layer 100, and openings for the gate contacts 106 are formed through the second ILD layer 102, etch stop layer 100, and gate masks 86. The openings may be formed using suitable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer or the like and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a top surface of the second ILD layer 102. The remaining liner and conductive material form the top source / drain contacts 104 and gate contacts 106 in the openings. The upper source / drain contacts 104 are physically and electrically coupled to the lower source / drain contacts 98, and the gate contacts 106 are physically and electrically coupled to the gate electrodes 84. The top source / drain contacts 104 and gate contacts 106 may be formed in different processes or may be formed in the same process. Although shown as formed in the same cross-sections, it should be appreciated that each of the upper source / drain contacts 104 and gate contacts 106 may be formed in different cross-sections, thereby avoiding short-circuiting of the contacts.As stated above, the termination layers 70E and / or dummy layers 70D may be formed (or not) below the epitaxial source / drain regions 70 (e.g., in the bottom basin 72L, see FIG. 4B ). In some embodiments (see FIG. 12C ), the termination layers 70E are not formed below the epitaxial source / drain regions 70, but the dummy layers 70D. In some embodiments (see FIG. 12D ), neither the termination layers 70E nor dummy layers 70D are formed below the epitaxial source / drain regions 70.FIGS. 13A-16B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments. FIGS. 13A, 14A, 15A, and 16A are cross-sectional views illustrated along reference cross-section A-A in FIG. 1, except that only one source / drain region 70 is illustrated. FIGS. 13B, 14B, 15B, and 16B are cross-sectional views illustrated along reference cross-section B-B in FIG. 1, except that only two fins 52 are illustrated.In FIGS. 13A and 13B, an intermediate structure similar to that of FIGS. 6A and 6B is obtained, except that the gate masks 86 have been omitted and the planarization process on the first ILD layer 76 (discussed with respect to FIGS. 5A and 5B ) has also been omitted. Therefore, the CESL 74 and the first ILD layer 76 have portions disposed over the gate electrodes 84. Portions of the first ILD layer 76 and dielectric CESL 74 are removed to form the contact openings 90. Removal may be accomplished by suitable photolithography and etching techniques using etch mask 92. In this embodiment, the etch mask 92 has a limited opening pattern (e.g., non-slit openings). The bounded openings are bounded on all sides by the material of the etching mask 92. As such, some of the first ILD layer 76 may remain in the cross-section illustrated in FIG. 13A after the contact openings 90 are formed. The lower source / drain contacts 98 may thus be formed to a smaller width between adjacent gate electrodes 84, thereby decreasing the parasitic capacitance between the gate electrodes 84 and lower source / drain contacts 98.In FIGS. 14A and 14B, contact spacers 112 are formed along side walls of the contact openings 90. The contact spacers 112 may be formed by conformally depositing a dielectric layer in the contact openings 90 and then etching the dielectric layer to form the contact spacers 112. The dielectric layer may be formed of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or the like, and may be formed by a deposition process such as CVD, ALD, or the like. The etch may be anisotropic.In FIGS. 15A and 15B, portions of the semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E are removed to widen the contact openings 90. The semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E may be removed using similar etching and oxidation techniques as those discussed above with respect to FIGS. 8A-10B, e.g., by etching the termination layers 70E and dummy layers 70D to expose the semiconductor CESLs 70C, oxidizing the exposed portions of the semiconductor CESLs 70C, and then etching the oxidized portions of the semiconductor CESLs 70C. After the contact openings 90 are widened, sidewalls of the contact spacers 112, the semiconductor CESLs 70C, dummy layers 70D, and termination layers 70E are exposed.After etching, the upper portions of the contact openings 90 (e.g., portions extending through the CESL 74 and first ILD dielectric layer 76) have a width W 3, which may be in the range of about 6 nm and about 25 nm, and the lower portions of the contact openings 90 (e.g., portions extending through the dummy layers 70D and into the epitaxial source / drain regions 70) have a width W 4, which may be in the range of about 5 nm and about 24 nm. The width W 4 is greater than the width W 3. For example, the width W 4 may be greater than the width W 3 by about 3 nm to about 4 nm, and the ratio of W 4: W 3 may be in the range of about 1 to about 1.5. The width W 4 may decrease continuously in the direction D 1.In FIGS. 16A and 16B, the lower source / drain contacts 98 and silicides 96 are formed in the contact openings 90. The lower source / drain contacts 98 and silicides 96 may be formed using techniques similar to those discussed above with respect to FIGS. 11A and 11B. After formation, upper portions of the lower source / drain contacts 98 are surrounded by the contact spacers 112, middle portions of the lower source / drain contacts 98 are surrounded by the termination layers 70E, and lower portions of the lower source / drain contacts 98 are surrounded by the function layers 70B. The etch stop layer 100, second ILD layer 102, top source / drain contacts 104, and gate contacts 106 are then formed using techniques similar to those discussed above with respect to FIGS. 12A and 12B, except that the gate contacts 106 also extend through the CESL 74 and first ILD dielectric layer 76.FIGS. 17A-21B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments. FIGS. 17A, 18A, 19A, 20A, and 21A are cross-sectional views illustrated along reference cross-section A-A in FIG. 1, except that only one source / drain region 70 is illustrated. FIGS. 17B, 18B, 19B, 20B, and 21B are cross-sectional views illustrated along reference cross-section B-B in FIG. 1, except that only two fins 52 are illustrated.In FIGS. 17A and 17B, an intermediate structure similar to that of FIGS. 6A and 6B is obtained. In this embodiment, the termination layers 70E in the epitaxial source / drain regions 70 are omitted. As such, the dielectric CESL 74 is formed on parts of the semiconductor CESLs 70C and dummy layers 70D (see FIG. 17A ). Portions of the first ILD layer 76 and dielectric CESL 74 are removed to form the contact openings 90. The first ILD layer 76 and dielectric CESL 74 may be removed using techniques similar to those discussed above with respect to FIGS. 7A and 7B, such as using an etch mask 92 having slot openings.As an example of forming the epitaxial source / drain regions 70 without the termination layers 70E, multiple epitaxial growth steps and etch back steps may be performed. Specifically, the function layers 70A are grown on sidewalls of the recesses 52R, and the function layers 70B are grown on the function layers 70A. Then, an etch-back process is performed to level the top surfaces of the function layers 70B. After the etch back process, the semiconductor CESLs 70C are grown on the function layers 70B and the dummy layers 70D are grown on the semiconductor CESLs 70C. The growth may be conformal. Then, another etch back process is performed to level the top surfaces of the layers 70C, 70D. If the termination layers 70E are omitted, the upper basins 72U may remain unfilled, such that the finished top surfaces of the epitaxial source / drain regions 70 are convex.In FIGS. 18A and 18B, the dummy layers 70D are removed so that the contact openings 90 are enlarged. Dummy layers 70D may be removed using similar etching techniques to those discussed above with respect to FIGS. 8A and 8B.In FIGS. 19A and 19B, the exposed portions of the semiconductor CESLs 70C in the contact openings 90 are oxidized to form dielectric layers 94. The semiconductor CESLs 70C may be oxidized using techniques similar to those discussed above with respect to FIGS. 9A and 9B. As discussed above, unexposed portions of the semiconductor CESLs 70C are not oxidized. Further, in this embodiment, some unoxidized portions of the semiconductor CESLs 70C remain between the dielectric CESL 74 and functional layers 70B.In FIGS. 20A and 20B, the dielectric layers 94 are removed, such that the contact openings 90 are enlarged. The dielectric layers 94 may be removed using techniques similar to those discussed above with respect to FIGS. 10A and 10B. As discussed above, etching does not remove the unoxidized portions of the semiconductor CESLs 70C. After the etch, the upper portions of the contact openings 90 (e.g., portions extending through the CESL 74 and first ILD dielectric layer 76) have a width W 5, which may be in the range of about 6 nm to about 30 nm, and the lower portions of the contact openings 90 (e.g., portions extending through the dummy layers 70D and into the epitaxial source / drain regions 70) have a width W 6, which may be in the range of about 5 nm to about 30 nm. The width W 5 is greater than the width W 6. For example, the width W 5 may be greater than the width W 6 by up to about 3 nm, and the ratio of W 5: W 6 may be in the range of about 1 to about 1.5. The width W 6 may decrease continuously in the direction D 1.In FIGS. 21A and 21B, the lower source / drain contacts 98 and silicides 96 are formed in the contact openings 90. The lower source / drain contacts 98 and silicides 96 may be performed using techniques similar to those discussed above with respect to FIGS. 11A and 11B. After formation, upper portions of the lower source / drain contacts 98 are surrounded by the dielectric CESL 74, middle portions of the lower source / drain contacts 98 are surrounded by the unoxidized portions of the semiconductor CESLs 70C, and lower portions of the lower source / drain contacts 98 are surrounded by the function layers 70B. The etch stop layer 100, second ILD layer 102, top source / drain contacts 104, and gate contacts 106 are then formed using techniques similar to those discussed above with respect to FIGS. 12A and 12B.FIGS. 22A-25B are cross-sectional views of intermediate stages in the fabrication of FinFETs, in accordance with some other embodiments. FIGS. 22A, 23A, 24A, and 25A are cross-sectional views illustrated along reference cross-section A-A in FIG. 1, except that only one source / drain region 70 is illustrated. FIGS. 22B, 23B, 24B, and 25B are cross-sectional views illustrated along reference cross-section B-B in FIG. 1, except that only two fins 52 are illustrated.In FIGS. 22A and 22B, an intermediate structure similar to that of FIGS. 6A and 6B is obtained, except that the gate masks 86 have been omitted and the planarization process on the first ILD layer 76 (discussed with respect to FIGS. 5A and 5B ) is also omitted. Therefore, the CESL 74 and the first ILD layer 76 have portions disposed over the gate electrodes 84. In this embodiment, the termination layers 70E are omitted from the epitaxial source / drain regions 70. Portions of the first ILD layer 76 and dielectric CESL 74 are removed to form the contact openings 90. The first ILD layer 76 and dielectric CESL 74 may be removed using techniques similar to those discussed above with respect to FIGS. 13A and 13B, such as using a bounded opening etch mask 92.In FIGS. 23A and 23B, the contact spacers 112 are formed along side walls of the contact holes 90. The contact spacers 112 may be formed using techniques similar to those discussed above with respect to FIGS. 14A and 14B.In FIGS. 24A and 24B, portions of the semiconductor CESLs 70C and dummy layers 70D are removed to expand the contact openings 90. The semiconductor CESLs 70C and dummy layers 70D may be removed using similar etching and oxidation techniques to those discussed above with respect to FIGS. 8A-10B, e.g., by etching the dummy layers 70D to expose the semiconductor CESLs 70C, oxidizing the exposed portions of the semiconductor CESLs 70C, and then etching the oxidized portions of the semiconductor CESLs 70C. After the contact holes 90 are widened, sidewalls of the contact spacers 112 and the semiconductor CESLs 70C and dummy layers 70D are exposed. Further, some unoxidized portions of the semiconductor CESLs 70C may remain between the dielectric CESL 74 and the functional layers 70B. After the etch, the upper portions of the contact openings 90 (e.g., portions extending through the CESL 74 and first ILD dielectric layer 76) have a width W 7, which may be in the range of about 6 nm to about 25 nm, and the lower portions of the contact openings 90 (e.g., portions extending through the dummy layers 70D and into the epitaxial source / drain regions 70) have a width W 8, which may be in the range of about 5 nm to about 24 nm. The width W 8 is greater than the width W 7. For example, the width W 8 may be greater than the width W 7 up to about 3 nm, and the ratio of W 8: W 7 may be in the range of about 1 to about 1.5. The width W 8 may decrease continuously in the direction D 1.In FIGS. 25A and 25B, the lower source / drain contacts 98 and silicides 96 are formed in the contact openings 90. The lower source / drain contacts 98 and silicides 96 may be formed using techniques similar to those discussed above with respect to FIGS. 11A and 11B. After formation, upper portions of the lower source / drain contacts 98 are surrounded by the contact spacers 112, middle portions of the lower source / drain contacts 98 are surrounded by the unoxidized portions of the semiconductor CESLs 70C, and lower portions of the lower source / drain contacts 98 are surrounded by the function layers 70B. The etch stop layer 100, second ILD layer 102, top source / drain contacts 104, and gate contacts 106 are then formed using techniques similar to those discussed above with respect to FIGS. 12A and 12B, except that the gate contacts 106 also extend through the CESL 74 and first ILD dielectric layer 76.Other variations are possible. For example, in some embodiments, dummy layer 70D and termination layer 70E are both omitted. The semiconductor CESLs 70C may thus fill the upper basins 72U and the dielectric CESL 74 may be formed directly on the semiconductor CESLs 70C.Embodiments may achieve advantages. Forming the epitaxial source / drain regions 70 to include the semiconductor CESLs 70C allows for the formation of the lower source / drain contacts 98 that extend into the epitaxial source / drain regions 70 to a desired depth. The contact area for the lower source / drain contacts 98 may thus be increased, thereby reducing contact resistance and increasing ION of the resulting FinFETs. Further, extending the lower source / drain contacts 98 into the epitaxial source / drain regions 70 with a semiconductor CESL instead of a timed etch allows the amount of material removed from the functional layers 70B to be reduced. Since the functional layers 70B have a high dopant concentration, reducing losses of the functional layers 70B may increase the performance of the resulting FinFETs.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A method comprising: depositing an ILD layer (76) over an epitaxial source / drain region (70), the epitaxial source / drain region (70) having a main layer (70B), a semiconductor CESL (70C) on the main layer (70B), and a semi-conductive dummy layer (70D) on the semiconductor CESL (70C), the semiconductor CESL (70C) formed of an undoped semiconductor material; exposing a first portion of the dummy layer (70D) through the ILD layer (76); Removing the first portion of the dummy layer (70D) with a first etching process to expose a second portion of the semiconductor CESL (70C), the first etching process etching the dummy layer (70D) at a higher rate than the semiconductor CESL (70C); removing the second portion of the semiconductor CESL (70C) to expose a third portion of the main layer (70B); and forming a first source / drain contact (98) on the third portion of the main layer (70B).The method of claim 1, wherein the dummy layer (70D) is formed of silicon germanium, the semiconductor CESL (70C) is formed of silicon, the main layer (70B) is formed of phosphorus-doped silicon or boron-doped silicon germanium, and the first etching process comprises: etching the silicon germanium with a mixture of H 2 SO 4 and H 2 O 2 for a duration in a range from 5 seconds to 300 seconds.The method of claim 1 or 2, wherein the dummy layer (70D) is formed of alumina, the semiconductor CESL (70C) is formed of silicon, the main layer (70B) is formed of phosphorus-doped silicon or boron-doped silicon germanium, and the first etching process comprises: etching the alumina with ammonia for a duration in a range of 5 seconds to 200 seconds.The method of any preceding claim, wherein removing the second portion of the semiconductor CESL comprises: oxidizing the second portion of the semiconductor CESL to form a dielectric layer; and removing the dielectric layer with a second etching process, wherein the second etching process etches the dielectric layer at a higher rate than the main layer.The method of claim 4, wherein the semiconductor CESL (70C) is formed of silicon, the dielectric layer (94) is formed of silicon oxide, and the second etching process comprises: etching the silicon oxide with dilute hydrofluoric acid for a duration in a range from 10 seconds to 30 seconds.The method of any preceding claim, wherein exposing the first portion of the dummy layer (70D) comprises removing a portion of the ILD layer (76) over the epitaxial source / drain region (70) to form an opening, the opening being wider than the second portion of the semiconductor CESL (70C), and further comprising: forming a silicide (96) in the opening, the silicide disposed between the first source / drain contact (98) and the epitaxial source / drain region (70).The method of any of claims 1 to 4, wherein exposing the first portion of the dummy layer (70D) comprises removing a portion of the ILD layer (76) over the epitaxial source / drain region (70) to form an opening, the opening being narrower than the second portion of the semiconductor CESL (70C), and further comprising: forming a contact spacer in the opening, the contact spacer surrounding the first source / drain contact (98); and forming a silicide (96) in the opening, the silicide disposed between the first source / drain contact (98) and the epitaxial source / drain region (70).The method of any preceding claim, wherein the epitaxial source / drain region (70) further comprises a termination layer (70E) on the dummy layer (70D), and further comprising: depositing a dielectric CESL (74) on the termination layer (70E), wherein the ILD layer (76) is deposited over the dielectric CESL (74); exposing a fourth portion of the termination layer (70E) through the dielectric CESL (74); and removing the fourth portion of the termination layer (70E) to expose the first portion of the dummy layer (70D), wherein a fifth portion of the termination layer (70E) remains between the dielectric CESL (74) and the main layer (70B) after formation of the first source / drain contact (98).The method of any preceding claim, further comprising: depositing a dielectric CESL (74) on the dummy layer (70D) and the semiconductor CESL (70C), wherein the ILD layer (76) is deposited over the dielectric CESL (74); and exposing the first portion of the dummy layer (70D) by the dielectric CESL (74), wherein after forming the first source / drain contact (98), a fourth portion of the semiconductor CESL (70C) remains between the dielectric CESL (74) and the main layer (70B).A device, comprising: a semiconductor substrate (50); a first fin (52) extending from the semiconductor substrate (50); a second fin (52) extending from the semiconductor substrate (50); an epitaxial source / drain region (70) comprising: a main layer (70B) in the first fin (52) and the second fin (52), the main layer (70B) comprising a first semiconductor material, the main layer (70B) comprising an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface protruding from respective surfaces of the first fin (52) and the second fin (52); and an undoped semiconductor CESL (70C) in contact with the top faceted surface and the bottom faceted surface of the main layer (70B), the semiconductor CESL (70C) comprising a second semiconductor material, the second semiconductor material being different than the first semiconductor material, and further comprising: a dielectric CESL (74) over the epitaxial source / drain region (70), a portion of the semiconductor CESL (70C) in contact with the main layer (70B) and the dielectric CESL (74).The device of claim 10, further comprising: an interlayer dielectric layer, hereinafter referred to as an ILD layer (76), over the epitaxial source / drain region (70); and a source / drain contact (98) having a first portion and a second portion, the first portion extending through the ILD layer (76), the second portion extending into the epitaxial source / drain region (70), the first portion having a first width, the second portion having a second width, the second width being greater than the first width.The device of claim 10, further comprising: an interlayer dielectric layer, hereinafter referred to as an ILD layer (76), over the epitaxial source / drain region (70); and a source / drain contact (98) having a first portion and a second portion, the first portion extending through the ILD layer (76), the second portion extending into the epitaxial source / drain region (70), the first portion having a first width, the second portion having a second width, the second width being less than the first width.The device of any one of claims 10 to 12, wherein the epitaxial source / drain region (70) further comprises a dummy layer (70D) in contact with the semiconductor CESL (70C), the dummy layer (70D) comprises a third semiconductor material, the third semiconductor material being different from each of the first semiconductor material and the second semiconductor material.The device of claim 13, wherein the epitaxial source / drain region (70) further comprises a termination layer (70E) in contact with the dummy layer (70D), the termination layer (70E) comprising the first semiconductor material, and further comprising: a dielectric CESL (74) over the epitaxial source / drain region (70), a portion of the termination layer (70E) in contact with the main layer (70B) and the dielectric CESL (74).The device of any of claims 10 to 14, wherein the first semiconductor material is phosphorus-doped silicon or boron-doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is silicon germanium.The device of any of claims 10 to 14, wherein the first semiconductor material is phosphorus doped silicon or boron doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is alumina.A device, comprising: a semiconductor substrate (50); a first fin (52) extending from the semiconductor substrate (50); a second fin (52) extending from the semiconductor substrate (50); an epitaxial source / drain region (70) comprising: a main layer (70B) in the first fin (52) and the second fin (52), wherein the main layer (70B) comprises a doped semiconductor material; a first CESL (70C) on the main layer (70B), wherein the first CESL (70C) comprises an undoped semiconductor material; and a termination layer (70E) on the first CESL (70C), wherein the termination layer (70E) comprises the doped semiconductor material; a second CESL (74) on the termination layer (70E), the second CESL (74) comprising a dielectric material; an interlayer dielectric layer, hereafter referred to as an ILD layer (76), on the second CESL (74); and a source / drain contact (98) extending through the ILD layer (76), the second CESL (74), the termination layer (70E), and the first CESL (70C), the source / drain contact (98) being in contact with the main layer (70B).The apparatus of claim 17, wherein a first portion of the source / drain contact (98) extends through the first CESL (70C) and a second portion of the source / drain contact (98) extends through the second CESL (74), the first portion being wider than the second portion.The device of claim 17 or 18, wherein a first portion of the source / drain contact (98) extends through the first CESL (70C) and a second portion of the source / drain contact (98) extends through the second CESL (74), the first portion being narrower than the second portion.

Images