NON-CONFORMING CAPPING LAYER AND METHOD FOR ITS MANUFACTURE

Abstract

Procedure with the following steps: Creating a protruding structure; and Producing a non-conforming layer (40) on the protruding structure using an ALD process, wherein the non-conforming layer (40) has the following: an upper part (40A) directly above the protruding structure, wherein the upper part (40A) has a first thickness, and a side wall part (40B) on a side wall of the projecting structure, wherein the side wall part (40B) has a second thickness that is smaller than the first thickness.

Description

background

[0001] Transistors are fundamental components in integrated circuits. In the early development of integrated circuits, fin field-effect transistors (FinFETs) were fabricated to replace planar transistors. FinFET fabrication involves creating semiconductor fins, and dummy gates are then fabricated on these fins. The dummy gate fabrication process can include depositing a dummy layer, such as polysilicon, and subsequently structuring the dummy layer into dummy gates. Gate spacers are fabricated on the sidewalls of the dummy gate stacks. The dummy gate stacks are then removed to create trenches between the gate spacers. Replacement gates are then fabricated in these trenches.

[0002] US 2017 / 0 358 576 A1 describes a method for fabricating vertical FinFETs. US 2008 / 0 233 699 A1 shows various FinFET devices. US 2015 / 0 270 398 A1 proposes methods for fabricating semiconductor insulation structures. US 2018 / 0 151 704 A1 discusses various fabrication methods for FinFETs. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. The Fig. Figures 1 to 3, 4A, 4B, 5A, 5B, 5C, 5D, 6A, 6B, 7A, 7B, 8 to 10, 11A, 11B, 12A, 12B, 13, 14A, 14B and 15 show perspective views and sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments. Fig. Figure 16 shows exemplary chemical intermediate structures in the production of a non-conforming capping layer according to some embodiments. Fig. Figure 17 shows diagrams of an ALD cycle (ALD: atomic layer deposition) for the production of a non-conforming capping layer according to some embodiments. The Fig. 18A and Fig. Figure 18B shows diagrams of oxidation processes for producing a non-conforming capping layer according to some embodiments. Fig. Figure 19 shows a process flow for manufacturing a FinFET according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] According to some embodiments, a non-conforming capping layer and a method for its fabrication are provided. Furthermore, intermediate steps in the fabrication of the non-conforming capping layer and its use in the fabrication of a FinFET according to some embodiments are explained. Several variations of some embodiments are discussed. The embodiments can also be used for other embodiments where non-conforming layers are to be fabricated, which may or may not be done in FinFET processes. The embodiments discussed here are intended to provide examples of the fabrication or use of the subject matter of the present invention, and a person skilled in the art should readily recognize modifications that can be made. In all the various illustrations and explanatory embodiments, similar reference numerals are used to designate similar elements.It can be demonstrated that some procedural execution forms are executed in a specific order, but other procedural execution forms can be executed in any logical order.

[0006] The Fig. Figures 1 to 3, 4A, 4B, 5A, 5B, 5C, 5D, 6A, 6B, 7A, 7B, 8 to 10, 11A, 11B, 12A, 12B, 13, 14A, 14B and 15 show sectional views and perspective representations of intermediate stages in the fabrication of a FinFET according to some embodiments of the present invention. The corresponding processes are also shown schematically in the process flow described in Fig. 19 is shown.

[0007] In Fig. 1. A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The semiconductor substrate 20 can be part of a wafer 10, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0008] Let's stay with Fig. 1, in which a trough area 22 is produced in the substrate 20. The corresponding step is specified as step 402 in the process flow 400, which is in Fig. Figure 19 shows that in some embodiments of the present invention, the well region 22 is a p-well region produced by implanting a p-doping agent, such as boron, indium, or the like, into the substrate 20. In other embodiments of the present invention, the well region 22 is an n-well region produced by implanting an n-doping agent, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. The resulting well region 22 may extend from a top surface of the substrate 20. The n- or p-doping concentration may be equal to or less than 10 18 cm -3 be and can be about 10 17 cm -3 up to about 10 18 cm -3 be.

[0009] In Fig. 2 Insulation zones 24 are produced such that they extend from the top of the substrate 20 into the substrate 20. The insulation zones 24 are subsequently referred to alternatively as STI zones (STI: shallow trench insulation). The corresponding step is specified as step 404 in process flow 400, which is described in Fig. Figure 19 shows the following. The portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To fabricate the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are produced on the semiconductor substrate 20 and subsequently patterned. The pad oxide layer 28 can be a thin layer made of silicon oxide. In some embodiments of the present invention, the pad oxide layer 28 is produced in a thermal oxidation process in which a surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesive layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also act as an etch stop layer for etching the hard mask layer 30.In some embodiments of the present invention, the hard mask layer 30 is produced from silicon nitride, for example, by low-pressure gravure chemical vapor deposition (LPCVD). In other embodiments of the present invention, the hard mask layer 30 is produced by thermal nitriding of silicon or by plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is produced on the hard mask layer 30 and subsequently patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to produce patterned hard masks 30, as shown in [reference]. Fig. 2 is shown.

[0010] The structured hard mask layer 30 is then used as an etching mask for etching the pad oxide layer 28 and the substrate 20. Subsequently, the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a mechanical grinding process, is then performed to remove excess dielectric materials, and the remaining dielectric materials are the STI regions 24. The STI regions 24 may have a dielectric coating (not shown), which may be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20.The dielectric coating can also be a deposited silicon oxide layer, silicon nitride layer, or the like, produced, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or chemical vapor deposition (CVD). The STI areas 24 can also have a dielectric material over the oxide coating, wherein the dielectric material can be deposited by flowable chemical vapor deposition (FCVD), spin coating, or the like. In some embodiments, the dielectric material over the dielectric coating can be silicon oxide.

[0011] The top surfaces of the hard masks 30 and the top surfaces of the STI regions 24 can be essentially at the same level. Semiconductor strips 26 are located between adjacent STI regions 24. In some embodiments of the present invention, the semiconductor strips 26 are parts of the original substrate 20, and therefore the material of the semiconductor strips 26 is the same as that of the substrate 20. In alternative embodiments of the present invention, the semiconductor strips 26 are substitute strips produced by etching the parts of the substrate 20 between the STI regions 24 to create recesses and performing an epitaxial process to grow further semiconductor material in the recesses. Accordingly, the semiconductor strips 26 are produced from a semiconductor material different from that of the substrate 20.In some embodiments, the semiconductor strips 26 are made of silicon germanium, silicon-carbon or a III-V compound semiconductor material.

[0012] In Fig. 3. The STI areas 24 are left out. As a result, upper parts of the semiconductor strips 26 protrude over the top surfaces 24A of the remaining parts of the STI areas 24, forming protruding fins 36. The corresponding step is specified as step 406 in the process sequence 400, which is described in Fig. Figure 19 shows that the etching can be carried out using a dry etching process, in which, for example, NF3 and NH3 are used as etching gases. A plasma can be generated during the etching process. Argon can also be used. In alternative embodiments of the present invention, the removal of the STI areas 24 can be carried out using a wet etching process. For example, HF can be used as the etching chemical.

[0013] In the embodiments described above, the fins can be structured using any suitable method. For example, the fins can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers, or thorns, can then be used to structure the fins.

[0014] The Fig. 4A, Fig. 4B, Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 6A, Fig. 6B, Fig. 7A and Fig. Figure 7B shows the production of dummy gate stacks 45 according to some embodiments. Fig. 4A a dielectric dummy layer 38 is produced. The corresponding step is specified as step 408 in the process flow 400, which is described in Fig. Figure 19 shows that in some embodiments of the present invention, the dielectric dummy layer 38 is produced by a conformal deposition process, which may be ALD, CVD, or the like. The material for the dielectric layer 38 may be silicon oxide, silicon nitride, silicon carbonitride, or the like. When the conformal deposition process is used, the horizontal thickness of the horizontal portions and the vertical thickness of the vertical portions of the dielectric layer 38 are equal or substantially equal, for example, with a difference of less than about 20% of the horizontal thickness. In some embodiments, the thickness T1 of the dielectric layer 38 is about 1 nm to about 10 nm. In alternative embodiments, the dielectric layer 38 is produced by oxidizing (for example, by a thermal oxidation process) surface portions of the projecting fins 36.The resulting dielectric layer 38 forms on the exposed surfaces of the projecting fins 36, but not on the top surfaces of the STI regions 24. Accordingly, dashed lines are used to indicate that, depending on the manufacturing process, some parts of the dielectric layer 38 may or may not be formed on the top surface of the STI regions 24. Fig. Figure 4B shows a representation of a reference cross-section 4B - 4B, which is in Fig. 4A is shown.

[0015] Fig. Figure 5A shows the production of a non-conforming capping layer 40 according to some embodiments of the present invention. The corresponding step is indicated as step 410 in the process sequence 400, which is described in Fig. 19 is shown. As in Fig. As shown in Figure 5A, the non-conforming capping layer 40 is produced on the dielectric layer 38, and it has no horizontal parts directly over the STI areas 24.

[0016] The Fig. 5B, Fig. 5C and Fig. Figure 5D shows a representation along a reference cross-section 5B / 5C / 5D - 5B / 5C / 5D, which is in Fig. 5A is shown, with the Fig. 5B, Fig. 5C and Fig. 5D sub-layers of the non-conforming capping layer 40 are located on different levels. As shown in the Fig. 5B, Fig. 5C and Fig. As shown in Figure 5D, the non-conforming capping layer 40 has an upper part 40A directly above the projecting fins 36, where the thickness of the upper part 40A is designated T2. The upper part 40A has a uniform thickness. For example, thicknesses T2A, T2B, and T2C can be equal, with a deviation of less than about 5% or even less. The non-conforming capping layer 40 may or may not have sidewall parts 40B on the sidewalls of the projecting fins 36, the sidewall parts 40B, if present, contacting the sidewall parts of the dielectric layer 38. For example, Figure 5D shows... Fig. 5B, that the side wall parts 40B extend to an underside of the projecting fins 36. Fig. Figure 5C shows that the lower ends of the non-conforming capping layer 40 are at approximately the same height as the tops of the protruding fins 36, which means that the sidewall parts 40B of the non-conforming capping layer 40 are essentially not present. Fig. Figure 5D shows that the lower ends of the non-conforming capping layer 40 extend deeper than the tops of the projecting fins 36. The lower ends of the sidewall parts 40B may be located on a plane between the tops and bottoms of the projecting fins 36. For example, the lower ends of the sidewall parts 40B may be located between the tops and half the height of the projecting fins 36.

[0017] A thickness of the side wall parts 40B of the non-conforming capping layer 40 is in Fig. 5B, designated by T3. In some embodiments of the present invention, the thickness T3 is measured at a mean height of the projecting fins 36, the mean height being located between the top and bottom surfaces of the projecting fins 36. In some embodiments of the present invention, the thickness T2 is approximately 0.5 nm to approximately 1.0 nm. The thickness T3 is 0.0 nm to approximately 0.2 nm, where a thickness of 0.0 nm means that the non-conforming capping layer 40 does not extend to the mean height. It is understood that when the thickness T3 (at the mean height of the fins 36) is 0.0 nm, the non-conforming capping layer 40 still extends to the sidewalls of the upper parts of the projecting fins 36 (as shown in Fig. 5D is shown), for example up to the upper 25% of the protruding fins 36. However, the thicknesses of the sidewall parts 40B of the non-conforming capping layer 40 decrease stepwise (and possibly continuously) from top to bottom and eventually reach 0.0 nm.

[0018] The mean thickness of the side wall parts 40B of the non-conforming capping layer 40 can be compared with T Side-Avg can be designated, and the mean thickness of the upper parts of the non-conforming capping layer 40 can be described by T Top-Avg The mean thickness can be determined as follows throughout the description: Select a plurality of equally spaced positions (e.g., 5 or more); measure the thicknesses at these positions; and then calculate an average of these thicknesses. For example, the Fig. 5B, Fig. 5C and Fig. 5D three equidistant positions as an example, the possible positions for determining T Top-AvgThey can be. Fig. 5C and Fig. 5D also shows some equidistant positions as an example of possible positions for determining T. Side-Avg may be. In some embodiments of the present invention, a ratio T may be Side-Avg / T Top-Avg smaller than about 0.2 and can be about 0.05 to about 0.2. In comparison, if the lower part of the sidewall parts of the conformal dielectric layer 38 is designated T1-B and the upper part of its sidewall parts is designated T1-T, a ratio T1-B / T1-T in some embodiments of the present invention can be about 0.9 to about 1.0.

[0019] Fig. Figure 17 schematically shows a cycle of a non-conforming ALD process for depositing the non-conforming capping layer 40 according to some embodiments. Fig. Figure 17 comprises three diagrams, A, B, and C, where diagram A shows a precursor as a function of time, diagram B shows a purge gas as a function of time, and diagram C shows a plasma as a function of time. The time axes (horizontal axes) of diagrams A, B, and C are matched. When the corresponding y-axis value in diagram A is zero, this indicates that the plasma introduction is stopped. When the corresponding y-axis value in diagram B is zero, this indicates that the purge gas introduction is stopped. When the corresponding y-axis value in diagram C is zero, this indicates that the plasma generation is stopped. A sequence of precursor introduction, purge gas introduction, and plasma generation is briefly discussed below in an example.

[0020] In Fig. At time point TP1, the purge gas (diagram B) is introduced into a reaction chamber. The reaction chamber is a vacuum chamber that can be evacuated and used for performing ALD processes. The purge gas serves to remove the precursor from the reaction chamber. Additionally, the purge gas is used to generate plasma, which provides energy for the precursor adhering to a wafer 10 that is placed in the Fig. 4A and Fig. Figure 4B shows the following. In some embodiments, the purge gas is an inert gas, which may be argon, helium, or the like, or a combination thereof. The purge gas may also be another gas (or not) that may have a high recombination rate (as discussed in more detail in later paragraphs), and the gas is referred to below as a highly recombining gas. In some embodiments of the present invention, the highly recombining gas contained in the purge gas may comprise hydrogen (H₂), nitrogen (N₂), or combinations thereof. The addition of nitrogen may also lead to an increase in the atomic fraction of nitrogen in the resulting non-conforming capping layer 40. The purge gas may be continuously introduced into and simultaneously pumped out of the reaction chamber throughout the non-conforming deposition process.In some embodiments of the present invention, the total flow rate of the purge gas is approximately 50 Ncm. 3 / min to approximately 6 slm (standard liters per minute). The pressure in the reaction chamber can range from approximately 133.3 Pa (1000 mTorr) to approximately 1066.6 Pa (8000 mTorr). The flow rate of the inert gas can be approximately 25 Ncm³. 3 / min to about 6 slm, and the throughput of the strongly recombining gas can be about 0 Ncm 3 / min to about 6 slm, specifically about 0 Ncm 3 / min up to approximately 25 Ncm 3 / min or about 25 Ncm 3 The speed is approximately 6 seconds per minute (slm). During the deposition process, the wafer temperature ranges from approximately 50 °C to approximately 500 °C.

[0021] In some embodiments, the purge gas contains argon or helium but no oxygen (O2). This differs from conventional PEALD, since conventional PEALD uses oxygen (O2) together with argon to produce oxygen-containing dielectrics, and argon splits the oxygen into oxygen radicals. In embodiments of the present invention, however, no oxygen is added, and the oxygen in the resulting non-conforming capping layer 40 is provided entirely by the precursor. The purge gas may contain no nitrogen (N2) or only a small amount of nitrogen. The addition of nitrogen serves two purposes. First, its recombination rate is higher than that of oxygen. Second, the addition of nitrogen increases its atomic fraction in the non-conforming capping layer 40.In some embodiments, the nitrogen / argon throughput ratio (N₂ / Ar) can be less than approximately 0.2. Additionally, hydrogen (H₂) can be added at a low throughput to improve the efficiency of bond breaking in the precursor. For example, the hydrogen / argon throughput ratio (H₂ / Ar) can be less than approximately 0.2. A small bias power can be used in the deposition process to improve non-conforming behavior. The bias power can range from approximately 0 W to approximately 100 W, for example.

[0022] At time TP2, the initiation of the precursor begins, as shown in diagram A of Fig. Figure 17 shows that in some embodiments of the present invention, the precursor is a silicon-containing precursor, but it can also be an amine-containing precursor and / or a precursor with a CH ligand. For example, the precursor can be bis(diethylamino)silane (BDEAS), diisopropylaminosilane (DIPAS), or the like, or a combination thereof. The throughput for the precursor can be about 500 Ncm³. 3 The time ΔTP2 for precursor introduction can be longer than approximately 0.1 s and can range from approximately 0.1 s to approximately 10 s. During precursor introduction, the precursor adheres to the surface of the material in the Fig. 4A and Fig. The precursor is introduced into wafer 10 as shown in Figure 4B, forming a monolayer, and excess precursor is pumped out of the reaction chamber. In some embodiments, the monolayer covers all exposed surfaces of wafer 10, including the protruding fins 36. It is understood that if other gases, such as N2, Ar, or H2, are used together with the precursor, the energy required to split these gases and bind them to the surface of wafer 10 is high, and therefore these gases do not adhere to the surface of wafer 10. At time TP3, the introduction of the precursor is stopped, as shown in diagram A, while the purge gas is continuously introduced. During the continuous introduction and purging of the purge gas, the excess precursor in gaseous form is removed from the reaction chamber, while the precursor adhering to wafer 10 remains.A period ΔTP3 is sufficiently long to allow for the adequate removal of the gaseous precursor. In some embodiments of the present invention, the period ΔTP3 is longer than approximately 1 s and can range from approximately 1 s to approximately 20 s or more. While a longer purge duration does not impair the result, it does lead to a reduction in performance.

[0023] After the end of period ΔTP3 and at time TP4, energy is supplied to generate a plasma from the purge gas, as shown in diagram C. The plasma causes a reaction of the adsorbed precursor, whose bonds are broken by the silicon atoms in the precursor to generate radicals (and ions), such as carbon radicals, nitrogen radicals, hydrogen radicals, etc., and the corresponding ions. The silicon atoms remain bound to the surface of wafer 10. The radicals then recombine with silicon atoms to form a monolayer of a dielectric, such as SiC, SIN, SiCN, or the like. The resulting dielectric layer is nonconforming, and the mechanism of the formation of the nonconforming dielectric layer is described with reference to Fig. 16 discussed in more detail.

[0024] The reaction is self-stopping because the amount of adsorbed precursor molecules is limited, and the reaction terminates when all adsorbed precursor molecules have been reacted. Accordingly, a period ΔTP4 is chosen to be long enough to allow for complete reaction of the adsorbed precursor molecules, but short enough to avoid compromising performance. In some embodiments, the period ΔTP4 can be longer than approximately 0.05 s and can range from approximately 0.05 s to approximately 10 s. The energy required to generate the plasma can range from approximately 10 W to approximately 500 W. The plasma can be generated using an ICP (inductively coupled plasma) mode, a CCP (capacitively coupled plasma) mode, or the like. In some examples, the RF power frequency is 13.56 MHz, but other frequencies can also be used.

[0025] After the end of period ΔTP4, the plasma is switched off at time TP5. In some embodiments of the present invention, a period ΔTP5 is provided in which the purge gas is always switched on, while the precursor (diagram A) and the plasma (diagram C) are switched off. Period ΔTP5 ends at time TP6. It is understood that time TP6 is also time TP1 of the next ALD cycle if another cycle of a non-conforming ALD process is to be carried out. This terminates a non-conforming ALD cycle. The subsequent non-conforming ALD cycles can be a repetition of the non-conforming ALD cycles discussed above. The non-conforming ALD cycles can be repeated until the desired thickness T2 ( Fig. 5B). In some embodiments of the present invention, the number of cycles can range from 1 to 1000. The total number of cycles depends on the specific application of the embodiment.

[0026] In some embodiments of the present invention, the total period (ΔTP1 + ΔTP5) is the time required to remove the unreacted radicals, ions, etc., in preparation for the next non-conforming ALD cycle. In some embodiments of the present invention, the total period (ΔTP1 + ΔTP5) is approximately 0.1 s to approximately 100 s. In other embodiments of the present invention, the period ΔTP4 can be sufficiently long so that the total period (ΔTP1 + ΔTP5) can be reduced to 0 s. This means that if the plasma is switched on long enough, for example, longer than approximately 1 s, the unreacted radicals, ions, etc., of the precursor are completely removed while the plasma is switched on. Thus, precursor initiation for the next cycle can begin immediately after the plasma is switched off.

[0027] To achieve better results without compromising performance, the time intervals ΔTP1, ΔTP2, ΔTP3, ΔTP4, and ΔTP5 can be optimized. For example, the time intervals ΔTP2 and ΔTP4 can be as short as possible, ranging from approximately 0.1 s to approximately 10 s, with the intervals being close to 0.1 s. The time intervals ΔTP2 and ΔTP4 can be close together or of equal length, with the absolute value of the difference (ΔTP2 - ΔTP4) / ΔTP2 being less than approximately 0.2. Furthermore, the time intervals ΔTP2 and ΔTP4 can be shorter than the time intervals ΔTP3 and ΔTP5, ensuring sufficient flushing occurs during the ΔTP3 and ΔTP5 intervals.

[0028] In some embodiments, an oxidation process is carried out after one or more non-conforming ALD cycles to remove the deposited non-conforming capping layer 40 ( Fig. 4A and Fig. 4B) to oxidize. Therefore, depending on the composition of the non-conforming capping layer 40, which may be made of or contain SiC, SIN, SiCN, or the like, the resulting oxidized non-conforming capping layer 40 may consist of or contain SiOC, SiON, SiOCN, or the like. In other embodiments, the oxidation process may be omitted, and the resulting non-conforming capping layer 40 may contain SiC, SIN, SiCN, or the like. It is understood that the dielectric layer 38 and the capping layer 40 may (or may not) contain the same elements from the group Si, O, C, N, and the like, although, regardless of whether they contain the same elements or not, the dielectric layer 38 and the non-conforming capping layer 40 may have different compositions (with different percentages of the elements). Fig. 18A and Fig. 18B shows diagrams for carrying out the oxidation process.

[0029] In some embodiments, if the resulting non-conforming capping layer is 40SiCN, the carbon content can be approximately 1 atomic percent to approximately 50 atomic percent, and the nitrogen content can also be approximately 1 atomic percent to approximately 50 atomic percent. If the capping layer is 40SiOCN, the oxygen content can be approximately 1 atomic percent to approximately 50 atomic percent, the carbon content can be approximately 1 atomic percent to approximately 50 atomic percent, and the nitrogen content can also be approximately 1 atomic percent to approximately 50 atomic percent.

[0030] Fig. Figure 18A shows a continuous oxidation process with a single cycle. The upper diagram of Fig. Figure 18A shows the introduction of the oxidation and purge gas as a function of time, and the lower diagram shows the plasma as a function of time. The time in the upper diagram corresponds to the time in the lower diagram. In some embodiments of the present invention, the oxidation and purge gas comprises an oxidizing gas, which may be oxygen (O2), ozone (O3), and / or the like. The oxidation and purge gas may also contain a carrier (purge) gas, which may be nitrogen (N2) and / or an inert gas such as argon, helium, or the like. In alternative embodiments, nitrogen but no oxygen is used, and the carrier gas may be added. The corresponding process in Fig. Process 18 is therefore a nitration process rather than an oxidation process. The throughput of the oxidation gas can be approximately 1 Ncm³. 3 / min up to approximately 6000 Ncm 3 / min, and the throughput of the carrier gas can also be approximately 1 Ncm 3 / min up to approximately 6000 Ncm3 The duration of oxidation can range from approximately 0.1 s to approximately 100 s.

[0031] Fig. Figure 18B shows an oxidation process according to alternative embodiments. In this process, the plasma is switched on and off in a plurality of cycles, instead of remaining switched on for the entire duration of the introduction of the oxidation and purge gas. The throughput of the oxidation and purge gas can be similar to that described with reference to Fig. 18A has been specified. In some embodiments, the on / off ratio can be approximately 0.1 to approximately 0.9. The total number of plasma on / off cycles can be approximately 5 to 10.

[0032] After the in Fig. 18A shown single-cycle oxidation process or the one shown in Fig. In the multi-cycle oxidation process shown in Figure 18B, the process can revert to the non-conforming ALD cycle or cycles, as shown in Fig. 17 is shown. The processes of Fig. 17 and the process of Fig. 18A (or 18B) can also form a compound cycle together, and this compound cycle can be repeated.

[0033] Fig. Figure 16 shows an example illustrating chemical intermediates in the fabrication of the non-conforming capping layer 40 when the non-conforming ALD cycles are performed on wafer 10. The example is shown for the use of DIPAS as a precursor. However, the described mechanism also applies to other types of precursors, such as BDEAS. Fig. The 16 intermediate structures shown are designated with the reference numbers 112, 114, 116, 118, and 120 to distinguish the intermediate structures produced at different stages. The wafer 10 has a base layer 110, which can represent the exposed structural elements, including the dielectric layer 38 and the STI regions 24, which are located in the Fig. 4A and Fig. Figure 4B shows the following: structural elements are exposed at the beginning of the non-conforming ALD deposition process. It is understood that the elements shown in the Fig. 4A and Fig. The structure shown in Figure 4B is merely an example and the embodiments can also be used for other structures.

[0034] The initial structure of Fig. 16 is referred to as structure 112. In the illustrated example, the base layer 110 is represented as a layer containing silicon, which may be in the form of crystalline silicon, amorphous silicon, polysilicon, or a silicon-containing compound comprising, among others, silicon oxide, silicon nitride, silicon oxide carbide, silicon oxide nitride, or the like. In some embodiments of the present invention, OH bonds are formed on the surface of the silicon-containing layer 110, wherein the OH bonds can form a bond with the silicon atoms on the surface of the base layer 110.

[0035] Let's stick with structure 112. The precursor will be (at that point TP2 as in Fig. 17) is initiated and is represented as a silicon atom forming a bond with two hydrogen atoms and two ligands (functional groups) designated “L”, where ligand L is a functional group with the chemical formula N(C2H5)2 if the precursor is DIPAS. Some of the precursor molecules are adsorbed onto the exposed wafer 10, as shown in structure 112. The exposed surfaces may be covered with a protective monolayer of precursor molecules. Then, the introduction of the precursor is stopped, and the purge gas is continuously introduced so that the excess precursor molecules that are not adsorbed are flushed out of the reaction chamber.

[0036] Let's move on to... Fig. 16 back. The plasma is switched on (at that time TP4 as in Fig. 17), and structure 112 is transformed into structure 114. Assuming that argon is used in the purge gas, argon ions are generated that attack the adsorbed precursor molecules and break the bonds between OH and the bond between H and Si in the precursor molecules. As a result, the silicon atoms in the precursor molecules form bonds with the oxygen atoms on wafer 10. The silicon atoms can also form bonds with functional groups L or with hydrogen atoms, as shown in the resulting structure 114.

[0037] During plasma generation, the functional groups L, as shown in Structure 114, are further degraded to generate carbon radicals and ions, nitrogen radicals and ions, and hydrogen radicals and ions, and the resulting structure is shown as Structure 116. These radicals and ions also form plasma, and the generation of plasma containing the further degraded ions and radicals is called plasma regeneration. The regenerated plasma contains carbon radicals (C*), nitrogen radicals (N*), hydrogen radicals (H*), and CN radicals (CN*), as shown in Structure 118. The radicals and ions generated by plasma regeneration then bond with silicon atoms, resulting in Structure 120. In the example shown, the resulting dielectric layer 40 contains SiCN, SiOCN, and the like.

[0038] Once structure 120 has been manufactured, the ALD cycle, which is located in the Fig. 16 and Fig. As shown in Figure 17, this process is repeated so that a plurality of monolayers are deposited to produce the dielectric layer 40, as shown in the Fig. 5A and Fig. 5B is shown. In subsequent ALD cycles, the Si-C, Si-N, and Si-O bonds formed in a previous ALD cycle can be broken, and more Si atoms are bound in the precursors initiated in later ALD cycles, resulting in more Si-C and Si-N bonds. The in Fig. The ALD cycle shown in 16 is repeated until the resulting dielectric layer 40 has a desired thickness.

[0039] In some embodiments of the present invention, a non-conforming ALD process is used, the mechanism of which is briefly explained below. Let us return to Fig. 4B back. Due to the plasma congregation on the upper surface of the fins, the plasma and the resulting radicals are concentrated near the upper surfaces of the protruding fins 36, and they are less likely to be found in the trenches between the protruding fins 36, since the upper surfaces lie in the path of the gas flow. Thus, it is more likely that the carbon radicals C* and the nitrogen radicals N* will bond to the open bonds of the silicon atoms near the upper surface of the fins. In contrast, if the precursor is introduced into the reaction chamber or remains in the reaction chamber (rather than being adsorbed), a conformal layer forms when the plasma is switched on. Depending on the precursors and the process conditions, SiC, SIN, or SiC can form as the dielectric layer 40.C* and N* radicals are more active than H* radicals, and therefore the resulting dielectric layer 40 does not contain hydrogen.

[0040] For the carbon radicals C* and the nitrogen radicals N* to bond with silicon atoms, the radicals must move (diffusion) to the corresponding positions. However, the radicals are highly reactive, their diffusion length is short, and the probability of the C* and N* radicals moving from the top of fins 36 to their center and underside is low. Furthermore, since the plasma is only switched on after the excess precursor molecules have been washed away, the source of C* and N* radicals originating from the adsorbed precursor is sparse, and the total number of C* and N* radicals is low. The C* and N* radicals are reacted locally and conveniently with silicon at the top of the fins, and they are unlikely to move to and bond with the silicon atoms in the center and underside of the protruding fins.As a result, the deposited dielectric layer 40 is non-conforming, as shown in the . Fig. 5A to 5D are shown.

[0041] In some embodiments, which refer to Fig. As discussed in section 17, highly recombining gases, such as nitrogen (N2) and / or hydrogen (H2), are provided as part of the purge gas. These gases are also split into radicals by the inert gas plasma. The highly recombining gases have high recombination rates, meaning that their N* and H* radicals are very likely to recombine, for example, to regenerate N2 and H2. For instance, the highly recombining gases have higher recombination rates (and diffuse at shorter intervals) than oxygen radicals O*. Accordingly, these gases have a short diffusion length, and their addition enhances the non-conforming behavior, such that the ratio T Side-Avg / T Top-Avg gets even smaller.

[0042] To achieve this non-conforming behavior, the process conditions are also adjusted. It has been found that a higher pressure of the purge gas (which can be N2) and the radicals from the adsorbed precursor lead to a higher recombination rate, since more radicals are available for recombination. Thus, a higher pressure leads to a more non-conforming profile for the deposited dielectric layer 40, and vice versa. Conversely, if the pressure is too high, the quality of the dielectric layer 40 can be reduced due to insufficient energy transfer from the radicals. In some embodiments of the present invention, the pressure is regulated to be approximately 133.3 Pa (1000 mTorr) to approximately 1066.6 Pa (8000 mTorr).

[0043] Furthermore, reducing the plasma power is advantageous for producing a non-conforming capping layer 40, as it makes it less likely that the radicals will reach the underside of the fin to adhere there. However, if the plasma power is too low (e.g., below 10 W), the layer quality is also reduced. In some embodiments of the present invention, the plasma power is regulated to be between approximately 10 W and approximately 500 W.

[0044] Through the ALD cycle, which occurs in Fig. As shown in Figure 16, a monolayer of the dielectric layer 40 is deposited on the top side of the protruding structures, as shown in the Fig. 5A to 5D, but it is not deposited on the sidewalls (especially on the lower parts of the sidewalls) of the projecting structure and on the top of the STI regions 24. Furthermore, the probability of the dielectric layer 40 being deposited on the lower parts of the sidewalls is lower than that of being deposited on their respective upper parts. As a result, the thicknesses of the lower parts of the sidewall parts 40B of the dielectric layer 40 become progressively smaller (as shown in the Fig. 5C and Fig. (as shown in 5D), or they become uniform but thinner than the upper parts, as in Fig. 5B is shown.

[0045] The Fig. 6A and Fig. Figure 6B shows the deposition of a dummy gate electrode layer 42. The corresponding step is indicated as step 412 in the process flow 400, which is described in Fig. 19 is shown. Fig. 6B shows the reference cross-section 6B - 6B of Fig. 6A. The dummy gate electrode layer 42 can be made of or comprise polysilicon or amorphous silicon, but other materials can also be used. The fabrication process can include a deposition process and a subsequent planarization process. Then, a hard mask layer 44 is deposited onto the dummy gate electrode layer 42. The corresponding step is specified as step 414 in the process flow 400, which is described in Fig. Figure 19 shows that the hard mask layer 44 can be made of or comprise silicon nitride, silicon oxide, silicon oxide carbonitride, or multiple layers thereof.

[0046] The Fig. 7A and Fig. Figure 7B shows the structuring process for producing dummy gate stacks 45. The corresponding step is indicated as step 416 in the process flow 400, which is described in Fig. 19 is shown. Fig. 7B shows the reference cross-section 7B - 7B of Fig. 7A. In some embodiments of the present invention, the hard mask layer 44 is first structured, for example, using a structured photoresist layer, as an etching mask. The resulting hard masks are referred to as hard masks 44'. The structured hard masks 44' are then used as an etching mask for etching the underlying dummy gate electrode layer 42 and the dummy gate dielectric 38 to produce dummy gate electrodes 42' and dummy gate dielectrics 38', respectively. The etching is carried out using an anisotropic etching process.

[0047] The etching of the dummy gate electrode layer 42, which can be made of polysilicon, can be carried out using a process gas containing C₂F₆, CF₄, or SO₂, a mixture of HBr, Cl₂, and O₂, a mixture of HBr, Cl₂, and O₂, or a mixture of HBr, Cl₂, O₂, and CF₂, and the like. In the etching process for the dummy gate electrode layer 42, the non-conforming capping layer 40 and the dielectric dummy layer 38 are used as an etch stop layer. The non-conforming capping layer 40 helps to prevent the dielectric dummy layer 38 from being etched through during the etching of the dummy gate electrode layer 42. If, on the other hand, the non-conforming capping layer 40 is not produced and the dielectric layer 38 is etched through because the protruding fins 36 are made of the same or a similar material (e.g.Since the dummy gate electrode layer 42 may be manufactured using silicon), the protruding fins 36 are severely damaged or even completely removed. The non-conforming capping layer 40, which is thicker at the top of the protruding fins 36, provides improved protection for the underlying dielectric layer 38 and the protruding fins 36.

[0048] In some embodiments, after structuring the dummy gate electrode layer 42, the exposed portions of the non-conforming capping layer 40 and the underlying portions of the dielectric layer 38 are etched, thus exposing the underlying protruding fins 36. In alternative embodiments of the present invention, the non-conforming capping layer 40 is etched, and the underlying portions of the dielectric layer 38 are left unstructured and are structured after the gate spacers have been fabricated. In further alternative embodiments of the present invention, the non-conforming capping layer 40 and the underlying portions of the dielectric layer 38 are left unstructured and are structured after the gate spacers have been fabricated.

[0049] As in Fig. As shown in Figure 8, gate spacers 46 are then manufactured on the side walls of the dummy gate stacks 45. The corresponding step is specified as step 418 in the process flow 400, which is shown in Fig. Figure 19 shows that in some embodiments of the present invention, the gate spacers 46 are made of one or more dielectric materials, such as silicon nitride, silicon carbonitride or the like, and they can have a single-layer structure or a multi-layer structure with a plurality of dielectric layers.

[0050] Then an etching process is performed to etch the exposed parts of the non-conforming capping layer 40 and the underlying parts of the dielectric layer 38 (if they have not yet been structured). The corresponding step is specified as step 420 in the process flow 400, which is described in Fig. Figure 19 shows that dashed lines are used to indicate that portions of the dielectric layer 38 and the non-conforming capping layer 40 may or may not be present directly beneath the gate spacers 46, depending on whether the exposed portions were etched in the preceding processes. The portions of the protruding fins 36 that are not covered by the dummy gate stacks 45 and the gate spacers 46 are etched, so that the Fig. The structure shown in Figure 9 is formed. The recess can be anisotropic, and therefore the portions of the fins 36 directly beneath the dummy gate stacks 45 and the gate spacers 46 are protected and are not etched. In some embodiments, the top surfaces of the recessed semiconductor strips 26 can be lower than the top surfaces 24A of the STI areas 24. This creates recesses 50. The recesses 50 include some portions located on opposite sides of the dummy gate stacks 45 and some portions between remaining portions of the projecting fins 36.

[0051] Then, epitaxial regions (source / drain regions) 54 are produced by selective growth (by epitaxy) of a semiconductor material in the recesses 50, so that the in Fig. The structure shown in Figure 10 is created. The corresponding step is indicated as step 422 in process flow 400, which is in Fig. Figure 19 shows that, depending on whether the resulting FinFET is a p-FinFET or an n-FinFET, a p-type or an n-type dopant can be grown in situ during epitaxy. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. Conversely, if the resulting FinFET is an n-FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. In alternative embodiments of the present invention, the epitaxial regions comprise 54 III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the recesses 50 have been filled with the epitaxial areas 54, the further epitaxial growth of the epitaxial areas 54 causes them to expand horizontally, and bevels may form.As the epitaxial areas 54 continue to grow, adjacent epitaxial areas 54 can also fuse together. This can create cavities (air gaps) 56. In some embodiments of the present invention, the production of the epitaxial areas 54 can be stopped when the upper surface of the epitaxial areas 54 is still wavy, or when the upper surface of the fused epitaxial areas 54 has become planar, which is achieved by further growth of the epitaxial areas 54, as shown in [reference]. Fig. 6 is shown.

[0052] Following the epitaxy process, the epitaxy regions 54 can be further doped with a p- or n-type dopant to create source and drain regions, which are also designated by the reference number 54. In alternative embodiments of the present invention, the implantation step is omitted if the epitaxy regions 54 are doped in situ with the p- or n-type dopant during epitaxy.

[0053] Fig. Figure 11A shows a perspective view of the structure after the fabrication of a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. The corresponding step is indicated as step 424 in the process flow 400, which is described in Fig. Figure 19 shows that the CESL 58 can be fabricated from silicon oxide, silicon nitride, silicon carbonitride, or the like by CVD, ALD, or the like. The ILD 60 can be a dielectric material deposited, for example, by FCVD, spin coating, CVD, or another deposition process. The ILD 60 can be fabricated from an oxygen-containing dielectric material, which may be a silicon oxide-based material such as TEOS oxide (TEOS: tetraethyl orthosilicate), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, can be performed to bring the top surfaces of the ILD 60, the dummy gate stack 45, and the gate spacer 46 to the same height. Fig. 11B shows the reference cross-section 11B - 11B of Fig. 11A.

[0054] Then the hard masks 44', the dummy gate electrodes 42', the non-conforming capping layer 40 and the dielectric dummy layers 38' are removed, so that trenches 62 are created between the gate spacers 46, as shown in the Fig. 12A and Fig. 12B is shown. Fig. 12B shows the reference cross-section 12B - 12B of Fig. 12A. In some embodiments, the dummy gate electrodes 42' are removed by an anisotropic etching process similar to that described in the Fig. 7A and Fig. The structuring process shown in Figure 7B is similar. In alternative embodiments, the dummy gate electrodes 42' are removed using a wet etching process. The non-conforming capping layer 40 can protect the protruding fins 36 against unwanted damage during the removal of the dummy gate electrodes 42' in the event that the dummy gate dielectrics 38' are damaged. After removal of the dummy gate electrodes 42', the non-conforming capping layer 40 is exposed through the grooves 62. Then, the non-conforming capping layer 40 and the dielectric layer 38 are removed, and the resulting structure is shown in Figure 7B. Fig. 13 shown.

[0055] The Fig. 14A and Fig. Figure 14B shows the manufacture of replacement gate stacks 64 and self-adjusting hard masks 80. Fig. 14B shows the reference cross-section 14B - 14B of Fig. 14A. As in the Fig. 14A and Fig. As shown in Figure 14B, replacement gate stacks 64 are manufactured. The corresponding step is indicated as step 426 in process flow 400, which is shown in Fig. Figure 19 shows a replacement gate stack 64 comprising a gate dielectric 70 and a gate electrode 72. The gate dielectric 70 can form an interface layer (IL) 66 and a dielectric high-k layer 68 ( Fig. 14B). The IL 66 is produced on the exposed surfaces of the projecting fins 36 and may comprise an oxide layer, such as a silicon oxide layer, produced by thermal oxidation of the projecting fins 36, a chemical oxidation process, or a deposition process. The dielectric high-k layer 68 comprises a dielectric high-k material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the dielectric high-k material is greater than 3.9 and may be greater than approximately 7.0. In some embodiments of the present invention, the dielectric high-k layer 68 is produced by ALD, CVD, or the like.

[0056] Let's stick with the Fig. 14A and Fig. 14B. A gate electrode 72 is fabricated on the gate dielectric 70. The gate electrode 72 can deposit stack layers 74 ( Fig. 14B), which may include a diffusion barrier (a capping layer) and one or more exit work layers above the diffusion barrier. The diffusion barrier may be made of titanium nitride, which may (or may not) be doped with silicon. When titanium nitride is doped with silicon, it may occasionally be referred to as titanium silicon nitride (Ti-Si-N or TSN). The exit work layer determines the work function of the gate electrode and comprises at least one layer or multiple layers made of different materials. The specific material for the exit work layer may be chosen depending on whether the FinFET is an n-type or a p-type FinFET. For example, if the FinFET is an n-type FinFET, the exit work layer may include a TaN layer and a titanium-aluminum (TiAl) layer above the TaN layer.If the FinFET is a p-type FinFET, the output layer can comprise a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After deposition of the capping layer and the output layer, a barrier layer can be fabricated, which can be another TiN layer. The barrier layer can be fabricated by CVD.

[0057] Then a metal filling region 76 is deposited. The production of the metal filling region 76 can be carried out by CVD, ALD, physical vapor deposition (PVD) or the like, and the metal filling region 76 can be made of or contain cobalt, tungsten, alloys thereof or another metal or other metal alloys.

[0058] Then a planarization process, such as a CMP process or a mechanical grinding process, is performed so that the top surface of the gate stack 64 is coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 64 is back-etched to create a recess between opposing gate spacers 46. Then a hard mask 80 is fabricated over the replacement gate stack 64. The corresponding step is specified as step 428 in the process flow 400, which is described in Fig. Figure 19 shows that in some embodiments of the present invention, the fabrication of the hard mask 80 comprises a deposition process for depositing a dielectric protective material and a planarization process for removing excess dielectric material over the gate spacers 46 and the ILD 60. The hard mask 80 can be made, for example, from silicon nitride or other similar dielectric materials.

[0059] In the final structure, remaining parts of the conformal dielectric layer 38' may or may not be located on the projecting fins 36, and remaining parts of the non-conformal capping layer 40 may or may not be located on the conformal dielectric layer 38', with the remaining parts being located directly beneath the gate spacers 46, as shown in Fig. Figure 14B shows that the remaining portions of the dielectric layer 38' and the non-conforming capping layer 40 directly beneath the gate spacers 46 can have the same sectional views as shown in Figure 14B. Fig. 5B, Fig. 5C and Fig. 5D is shown.

[0060] Fig. Figure 15 shows some of the structural elements that are produced in subsequent processes and may include source / drain contact pins 84, source / drain silicide areas 86, and lower parts of gate contact pins 82. The corresponding step is indicated as step 430 in process flow 400, which is described in Fig. Figure 19 shows the process details. These details are not discussed here. This is how a FinFET 90 is manufactured.

[0061] The embodiments of the present invention have several advantages. By producing a non-conforming capping layer, the underlying layers / areas can be better protected when anisotropic etching is performed. On the other hand, the non-conforming capping layer has a very small thickness, or it is not produced on the side walls of the underlying protruding structural elements and therefore has little influence on subsequent processes.

[0062] According to some embodiments of the present invention, a method comprises the following steps: fabricating a protruding structure; and fabricating a non-conforming layer on the protruding structure using an ALD process, wherein the non-conforming layer has a top part directly above the protruding structure, the top part having a first thickness, and a sidewall part on a sidewall of the protruding structure, the sidewall part having a second thickness that is less than the first thickness. In one embodiment, the ALD process comprises a plasma-assisted ALD process, wherein plasma is switched on during the ALD process. In another embodiment, the method further comprises fabricating a dummy gate electrode layer above the non-conforming layer; and structuring the dummy gate electrode layer.In one embodiment, the ALD process comprises a cycle, wherein the cycle includes: introducing a silicon-containing precursor into a reaction chamber; stopping the introduction of the silicon-containing precursor; removing the silicon-containing precursor; and, after the removal of the silicon-containing precursor, switching on the plasma. In one embodiment, the removal is carried out using a purge gas, wherein the purge gas is continuously introduced into the reaction chamber during a period in which the plasma is switched on. In another embodiment, the removal is carried out using a purge gas, wherein the purge gas is continuously introduced into the reaction chamber during a period from a first time point at which the introduction of the silicon-containing precursor is stopped until a second time point at which the plasma is switched on.In one embodiment, fabricating the protruding structure comprises fabricating a protruding semiconductor fin; and fabricating a dielectric layer on the protruding semiconductor fin, wherein the non-conforming layer is fabricated on the dielectric layer. In one embodiment, the non-conforming layer has a lower end that is higher than the mean height of the protruding semiconductor fin.

[0063] According to some embodiments of the present invention, an integrated circuit structure comprises: a semiconductor substrate; insulating regions extending into the semiconductor substrate; a semiconductor fin projecting over the tops of the insulating regions, the insulating regions being located on opposite sides of the semiconductor fin; a dielectric layer on a top and side walls of the semiconductor fin; and a capping layer having a first part directly above the semiconductor fin, the capping layer comprising: a top part above the dielectric layer, the top part having a first thickness, and a side wall part on a side wall of a top part of the semiconductor fin, the side wall part having a second thickness that is less than the first thickness.In one embodiment, the integrated circuit structure further comprises: a gate spacer with an upper portion directly above the upper portion of the capping layer and with lower portions on the sidewall portion of the capping layer; and a gate stack contacting the gate spacer. In one embodiment, the sidewall portion of the capping layer has a lower end that is higher than the mean height of the semiconductor fin. In one embodiment, the lower portions of the sidewall portion of the capping layer are thinner than the respective upper portions of the sidewall portion of the capping layer. In one embodiment, the thickness of the sidewall portion of the capping layer increases continuously from the lower portions to the respective upper portions. In one embodiment, the dielectric layer and the capping layer are made of different materials.In one embodiment, the dielectric layer and the capping layer comprise the same elements from the group Si, O, N, and C, but the dielectric layer and the capping layer have different compositions. In another embodiment, the capping layer has no horizontal parts directly above the insulating areas.

[0064] According to some embodiments of the present invention, a structure comprises: a projecting structure extending beyond structural elements on opposite sides of the projecting structure, wherein the projecting structure has a top and sidewall surfaces; a dielectric capping layer with an upper part directly above the projecting structure, wherein the upper part of the dielectric capping layer has a uniform thickness and at least lower parts of the sidewall surfaces of the projecting structure do not have a dielectric capping layer produced thereon; and a further structural element that is in contact with the upper part of the dielectric capping layer and with lower parts of the sidewall surfaces of the projecting structure.In one embodiment, the projecting structure comprises an inner part and a conformal outer part on the inner part, wherein a lower end of the dielectric capping layer is substantially at the same level as a top surface of the inner part. In one embodiment, the inner part comprises polysilicon, and the conformal outer part comprises a dielectric material. In one embodiment, the upper part of the dielectric capping layer has a thickness of about 0.5 nm to about 1.0 nm.

Claims

[1] Procedure with the following steps: Creating a protruding structure; and Producing a non-conforming layer (40) on the protruding structure using an ALD process, wherein the non-conforming layer (40) has the following: an upper part (40A) directly above the protruding structure, wherein the upper part (40A) has a first thickness, and a side wall part (40B) on a side wall of the projecting structure, wherein the side wall part (40B) has a second thickness that is smaller than the first thickness. [2] Method according to claim 1, wherein the ALD process comprises a plasma-assisted ALD process, wherein plasma is switched on during the ALD process. [3] The method of claim 1 or 2, further comprising: fabricating a dummy gate electrode layer (42) over the non-conforming layer (40); and Structuring the dummy gate electrode layer (42). [4] A method according to any of the preceding claims, wherein the ALD process comprises a cycle, the cycle comprising: Introducing a silicon-containing precursor into a reaction chamber; Stopping the introduction of the silicon-containing precursor; Removal of the silicon-containing precursor; and After the removal of the silicon-containing precursor, the plasma is switched on. [5] Method according to claim 4, wherein the removal is carried out using a purge gas, wherein during a period in which the plasma is switched on the purge gas is continuously introduced into the reaction chamber. [6] Method according to claim 4, wherein the removal is carried out using a purge gas and the purge gas is continuously introduced into the reaction chamber during a period from a first time at which the introduction of the silicon-containing precursor is stopped, until a second time at which the plasma is switched on. [7] Method according to any of the preceding claims, wherein producing the protruding structure comprises: Forming a protruding semiconductor fin (36); and Forming a dielectric layer (38) on the protruding semiconductor fin (36), wherein the non-conforming layer (40) is formed on the dielectric layer (38). [8] Method according to claim 7, wherein the non-conforming layer (40) has a lower end that is higher than a mean height of the protruding semiconductor fin (36). [9] Integrated circuit structure with: a semiconductor substrate (20); Insulation areas (24) extending into the semiconductor substrate (20); a semiconductor fin (36) that extends over the tops of the insulation regions (24), wherein the insulation regions (24) are located on opposite sides of the semiconductor fin (36); a dielectric layer (38) on a top and side walls of the semiconductor fin (36); and a capping layer (40), wherein the capping layer comprises the following: an upper part (40A) directly above the semiconductor fin (36) and above the dielectric layer (38), wherein the upper part (40A) has a first thickness, and a side wall part (40B) on a side wall of an upper part of the semiconductor fin (36), wherein the side wall part (40B) has a second thickness that is smaller than the first thickness, wherein the sidewall portion (40B) of the capping layer (40) has a lower end that is higher than the mean height of the semiconductor fin (36); and / or lower parts of the side wall part (40B) of the capping layer (40) are thinner than the respective upper parts of the side wall part (40B) of the capping layer (40). [10] Integrated circuit structure according to claim 9, further comprising: a gate spacer (46) with an upper part directly above the upper part (40A) of the capping layer (40) and with lower parts on the side wall part (40B) of the capping layer (40); and a gate stack (45) that contacts the gate spacer (46). [11] Integrated circuit structure according to claim 9, wherein the thicknesses of the side wall part (40B) of the capping layer (40) increase continuously from the lower parts to the respective upper parts. [12] Integrated circuit structure according to one of claims 9 to 11, wherein the dielectric layer (38) and the capping layer (40) are made of different materials. [13] Integrated circuit structure according to one of claims 9 to 12, wherein the dielectric layer (38) and the capping layer (40) comprise the same elements from the group Si, O, N and C and the dielectric layer (38) and the capping layer (40) have different compositions. [14] Integrated circuit structure according to any one of claims 9 to 13, wherein the capping layer (40) has no horizontal parts directly above the insulation areas (24). [15] Structure with: a projecting structure that extends beyond structural elements on opposite sides of the projecting structure, wherein the projecting structure has a top and side wall surfaces, and further comprising: a semiconductor fin (36), a dielectric layer (38) on a top and side walls of the semiconductor fin (36); a dielectric capping layer (40) on the dielectric layer (38) with an upper part (40A) directly above the semiconductor fin (36) and above the dielectric layer (38), wherein the upper part (40A) of the dielectric capping layer (40) has a uniform thickness and at least lower parts of the sidewall surfaces of the projecting structure do not have a dielectric capping layer (40) produced thereon; and a further structural element that is in contact with the upper part (40A) of the dielectric capping layer (40) and with lower parts of the side wall surfaces of the projecting structure. [16] Structure according to claim 15, wherein the projecting structure comprises: an inner part; and a conformal outer part on the inner part, wherein a bottom end of the dielectric capping layer (40) is substantially at the same level as a top of the inner part. [17] Structure according to claim 16, wherein the inner part comprises polysilicon and the conformal outer part comprises a dielectric material. [18] Structure according to one of claims 15 to 17, wherein the upper part (40A) of the dielectric capping layer (40) has a thickness of about 0.5 nm to about 1.0 nm.

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