Three-dimensional stackable ferroelectric direct access storage devices and manufacturing processes

Abstract

Method (1000) for forming a ferroelectric direct access memory device, FeRAM device (200), wherein the method (1000) comprises: Forming a first layer stack (202A, 202B, 202C and 202D) and a second layer stack (202A, 202B, 202C and 202D) successively over a substrate (50, 101), wherein the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D) each have a first dielectric layer (201) and an electrically conductive layer (203) formed over the first dielectric layer (201); Forming a second dielectric layer (201T) over the second layer stack (202A, 202B, 202C and 202D); Structuring the first layer stack (202A, 202B, 202C and 202D), the second layer stack (202A, 202B, 202C and 202D) and the second dielectric layer (201T), wherein a step-shaped region (231) is formed during structuring, wherein in the step-shaped region (231) the second layer stack (202A, 202B, 202C and 202D) extends beyond lateral dimensions of the second dielectric layer (201T) and the first layer stack (202A, 202B, 202C and 202D) extends beyond lateral dimensions of the second layer stack (202A, 202B, 202C and 202D), wherein after structuring the electrically conductive layers of the first and second layer stacks (202A, 202B, 202C and 202D) form a first word line or a second word line; Formation of a first dielectric material (205) over the second dielectric layer (201T) and over the layer stacks (202A, 202B, 202C and 202D); Performing a planarization process such that the upper surface of the first dielectric material (205) lies on a plane with the upper surface of the second dielectric layer (201T); After structuring, a trench (206, 232, 234) is formed, which extends through the first layer stack (202A, 202B, 202C and 202D), the second layer stack (202A, 202B, 202C and 202D) and the second dielectric layer (201T); Coating the side walls and bottom of the trench (206, 232, 234) with a ferroelectric material (213); Formation of a channel material (207) over the ferroelectric material (213); Filling the trench (206, 232, 234) by forming a second dielectric material (205, 208, 209) above the channel material (207); and Forming a source line and a bit line in the second dielectric material (205, 208, 209), wherein the source line and the bit line extend through the second dielectric layer (201T), the second layer stack (202A, 202B, 202C and 202D) and the first layer stack (202A, 202B, 202C and 202D).

Description

TECHNICAL SECTOR

[0001] The present invention relates generally to semiconductor memory devices and in particular to embodiments of three-dimensional (3D) ferroelectric direct access memory devices (FeRAM devices). BACKGROUND

[0002] Semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, mobile phones, and personal computers. Semiconductor memories fall into two main categories: volatile and non-volatile. Volatile memories include random-access memory (RAM), which can be further divided into two subgroups: static random-access memory (SRAM) and dynamic random-access memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when no power is supplied.

[0003] In contrast, non-volatile memory allows data stored in it to be retained without a power supply. One type of non-volatile semiconductor memory is ferroelectric random-access memory (FeRAM or FRAM). FeRAM's advantages include its high read / write speed and small size.

[0004] US 2019 / 0006376A1 discloses memory cell arrays comprising vertically alternating layers of insulating material and memory cells. US 10937809B1 discloses a three-dimensional ferroelectric storage device. WO 2019 / 139622A1 discloses a ferroelectric field-effect transistor. Further prior art is known from WO 2019 / 152226A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To better understand the present invention and its advantages, reference is now made to the following descriptions, which are related to the accompanying drawings, in which: Fig. 1 shows a cross-sectional view of a semiconductor device with integrated memory devices in one embodiment; , the Fig. Figures 2A, 2B, 3A, 3B, 4-7, 8A, 8B, 8C, 8D, 8E, 9, 10A and 10B show different views of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) at different stages of processing in one embodiment; the Fig. 11 and Fig. 12 perspective views of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) in various processing stages in a further embodiment; the Fig. 13-19 perspective views of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) in various processing stages in yet another embodiment; Fig. 20 represents an equivalent circuit diagram of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) in one embodiment; and Fig. 21 presents a flow chart of a method for manufacturing a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) in some embodiments. DETAILED DESCRIPTION OF ILLUSTRATORY EXECUTION FORMS

[0006] The invention is defined by independent claim 1, which defines a method for constructing a ferroelectric direct-access memory device, independent claim 13, which defines a method for constructing a ferroelectric direct-access memory device, and independent claim 18, which defines a ferroelectric direct-access memory device. Embodiments of the invention are defined by the dependent claims. The following disclosure provides many different embodiments or examples of the realization of different features of the invention.For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements may be formed between the first and second elements in such a way that the first and second elements cannot make direct contact.

[0007] Furthermore, spatial relational terms such as "underlying," "below," "lower," "above," "upper," and the like can be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature (other elements or features), as illustrated in the figures. These spatial relational terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or in other directions), and the spatial designations used here can be interpreted accordingly.In the description here, the same or similar reference numeral in the various figures consistently refers to the same or similar element, which was formed by means of the same or similar process using the same or similar material (same or similar materials).

[0008] In some embodiments, a method for manufacturing a ferroelectric direct access memory device (FeRAM device) comprises forming a first layer stack and a second layer stack successively over a substrate, wherein the first layer stack and the second layer stack have an identical layer structure comprising a layer of a first electrically conductive material over a layer of a first dielectric material, wherein the first layer stack extends beyond the lateral dimensions of the second layer stack.The process further comprises forming a trench extending through the first layer stack and the second layer stack, coating the side walls and bottom of the trench with a ferroelectric material, conformally forming a channel material in the trench above the ferroelectric material, filling the trench with a second dielectric material, forming a first opening and a second opening in the second dielectric material, and filling the first opening and the second opening with a second electrically conductive material.

[0009] Fig. Figure 1 shows a cross-sectional view of a semiconductor device 100 with integrated memory devices 123 (e.g., 123A and 123B) in one embodiment. The semiconductor device 100 is a fin field-effect transistor (FinFET) device with three-dimensional (3D) ferroelectric direct-access memory devices (FeRAM devices) 123, which, in the illustrated embodiment, are integrated during the back-end-of-line (BEOL) processing of semiconductor manufacturing. To avoid confusion, the following are shown in the Fig. 1 The details of the storage devices 123 are not shown, but they are illustrated in further figures below.

[0010] As in Fig. As shown in Figure 1, the semiconductor device 100 has different regions for forming different types of circuits. For example, the semiconductor device 100 can have a first region 110 for forming logic circuits and a second region 120 for forming, for example, peripheral circuits, input / output (I / O) circuits, electrostatic discharge (ESD) circuits, and / or analog circuits. Other regions for forming other types of circuits are possible, and it is fully intended to include them within the scope of this disclosure.

[0011] The semiconductor device 100 comprises a substrate 101. The substrate 101 can be a base substrate, such as a doped or undoped silicon substrate or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 101 can comprise other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.

[0012] The electrical components, such as transistors, resistors, capacitors, inductors, diodes, or the like, are formed in or on substrate 101 during the front-end-of-line (FEOL) processing of semiconductor manufacturing. In the example of Fig. Semiconductor fins 103 (also referred to as fins) are formed, projecting beyond the substrate 101. Insulation regions 105, such as shallow trench insulation regions (STI regions), are formed between or around the semiconductor fins 103. Gate electrodes 109 are formed above the semiconductor fins 103. Gate spacers 111 are formed along the side walls of the gate electrodes 109. Source / drain regions 107, such as epitaxial source / drain regions, are formed on opposite sides of the gate electrodes 109. Contacts 113, such as gate contacts and source / drain contacts, are formed above and electrically coupled to the respective underlying electrically conductive features (such as the gate electrodes 109 or the source / drain regions 107). One or more dielectric layers 117, such as e.g., are deposited above the substrate 101 and around the semiconductor fins 103 and the gate electrodes 109.An interlayer dielectric layer (ILD layer) is formed. Other electrically conductive features, such as interconnect structures, conductor tracks 115 and vias 114, can also be formed in one or more dielectric layers 117: The FinFETs in . Fig. 1 can be formed by any suitable method known or used in the prior art, so details are not repeated here. For the sake of simplicity, the substrate 101, the electrical components formed in / on the substrate 101 (e.g., FinFETs), the contacts 113, the conductive features 115 / 114, and the one or more dielectric layers 117 are collectively referred to as substrate 50.

[0013] Still with reference to Fig. 1. A dielectric layer 119, which may be an etch stop layer (ESL), is formed over one or more dielectric layers 117. In one embodiment, the dielectric layer 119 is formed from silicon nitride using plasma-enhanced chemical vapor deposition (PECVD), although other dielectric materials, such as nitride, carbide, combinations thereof, or the like, and alternative techniques for forming the dielectric layer 119, such as low-pressure chemical vapor deposition (LPCVD), photovoltaics (PVD), or the like, could alternatively be used. In some embodiments, the dielectric layer 119 is omitted. Next, a dielectric layer 121 is formed over the dielectric layer 119. The dielectric layer 121 can be any suitable dielectric material, such as silicon oxide, silicon nitride, or the like, formed by a suitable method, such as…PVD, CVD, or the like. In the dielectric layer 121, one or more storage devices 123A, each comprising several storage cells, are formed and coupled to electrically conductive features (e.g., vias 124 and conductor tracks 125) in the dielectric layer 121. Various embodiments of the storage devices 123A or 123B are described below. Fig. 1 (e.g. the 3D-FeRAM devices 200, 200A and 200B) discussed in detail.

[0014] Fig. Figure 1 further shows a second layer of storage devices 123B formed above the storage devices 123A. The storage devices 123A and 123B can have the same or a similar structure and can be collectively referred to as storage devices 123. The example of Fig. Figure 1 shows two layers of storage devices 123 as a non-limiting example. Other numbers of layers of storage devices 123, such as one layer, three layers, or more, are also possible, and it is fully intended to include them within the scope of this disclosure. The one or more layers of storage devices 123 are formed in a storage region 130 of the semiconductor device 100, and they can be formed during the back-end-of-line (BEOL) processing of the semiconductor fabrication. During BEOL processing, the storage devices 123 can be formed at any suitable location in the semiconductor device 100, such as above (e.g., directly above) the first region 110, above the second region 120, or above several regions.

[0015] In the example of Fig. 1. The memory devices 123 occupy some, but not all, areas of the memory area 130 of the semiconductor device 100, because other features, such as conductive traces 125 and vias 124, can be formed in other areas of the memory area 130 for connection to the conductive features above and below the memory area 130. In some embodiments, a mask layer, such as a structured photoresist layer, is formed to cover some areas of the memory area 130 for the formation of the memory devices 123A or 123B, while the memory devices 123A or 123B are formed in other areas of the memory area 130 that are exposed by the mask layer. After the memory devices 123 are formed, the mask layer is then removed.

[0016] Still with reference to Fig. 1. After the formation of the storage area 130, an interconnect structure 140 is formed over the storage area 130. This interconnect structure comprises the dielectric layer 121 and the electrically conductive features (e.g., the vias 124 and the conductor tracks 125) in the dielectric layer 121. The interconnect structure 140 can electrically connect the electrical components formed in / on the substrate 101 to form functional circuits. The interconnect structure 140 can also electrically couple the storage devices 123 to the components formed in / on the substrate 101 and / or couple the storage devices 123 to conductive pads formed over the interconnect structure 140 for connection to an external circuit or device. The fabrication of the interconnect structure is known from the prior art, so details are not repeated here.

[0017] In some embodiments, the storage devices 123 are electrically coupled to the electrical components (e.g., transistors) formed on the substrate 50, for example, by means of the vias 124 and conductor tracks 125. In some embodiments, they are controlled or accessed (e.g., written to or read from) by means of the functional circuits of the semiconductor device 100. Alternatively, in some embodiments, the storage devices 123 are electrically coupled to conductive pads formed above an upper metal layer of the interconnect structure 140. In this case, the control of the storage devices 123 or access to them by an external circuit (e.g., another semiconductor device) can be carried out directly without involving the functional circuits of the semiconductor device 100. Although in the example of Fig. If additional metal layers (e.g. the interconnect structure 140) are formed over the storage devices 123, the storage devices 123 can be formed in an upper (e.g. top) metal layer of the semiconductor device 100, and it is fully intended to include these and other variants within the scope of this disclosure.

[0018] The Fig. Figures 2A, 2B, 3A, 3B, 4-7, 8A, 8B, 8C, 8D, 8E, 9, 10A, and 10B represent different views (e.g., a perspective view, cross-sectional view, and / or top view) of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) 200 at various stages of processing in one embodiment. For the sake of simplicity, a 3D FeRAM device may also be referred to herein as a 3D memory device or simply as a memory device. The 3D memory device 200 is a three-dimensional memory device made of a ferroelectric material. The 3D memory device 200 may be referred to as memory device 123A and / or 123B in Fig. 1. It should be noted that, for the sake of simplicity, not all features of the 3D storage device 200 are shown in the figures.

[0019] It will now be on Fig. Reference is made to Figure 2A, which shows a perspective view of the storage device 200 at an early stage of processing. Fig. Figure 2B shows the cross-sectional view of the storage device 200. Fig. 2A along the cross-section AA. As in the Fig. 2A and Fig. As shown in Figure 2B, the layer stacks 202A, 202B, 202C, and 202D are formed sequentially on the substrate 50. The layer stacks 202A, 202B, 202C, and 202D can be collectively referred to here as layer stacks 202. In the illustrated embodiments, the layer stacks 202A, 202B, 202C, and 202D have the same layer structure. For example, each of the layer stacks 202 has a dielectric layer 201 and an electrically conductive layer 203 above the dielectric layer 201. It should be noted that the substrate 50 in the Fig. 2A and Fig. Figure 2B shows that the storage device 200 is formed above the substrate 50 and the substrate 50 cannot be considered part of the storage device 200. For the sake of simplicity, the representation of the substrate 50 can be omitted in the following figures.

[0020] In some embodiments, to produce the layer stack 202A, the dielectric layer 201 is first formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable deposition method, such as PVD, CVD, atomic layer deposition (ALD), or the like. Subsequently, the electrically conductive layer 203 is formed over the dielectric layer 201. In some embodiments, the electrically conductive layer 203 is formed from an electrically conductive material, such as a metal or a metal-containing material. Examples of materials for the electrically conductive layer 203 include Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. The electrically conductive layer 203 can be deposited, for example, by PVD, CVD, ALD, combinations thereof, or the like.

[0021] After forming the layer stack 202A, the process for forming the layer stack 202A can be repeated to successively form the layer stacks 202B, 202C, and 202D over the layer stack 202A, as shown in Fig. Figure 1 is shown. After the formation of the layer stacks 202A, 202B, 202C and 202D, a dielectric layer 201T is formed over the uppermost layer stack, which in the illustrated embodiments is layer stack 202D. In one embodiment, the dielectric layer 201T is formed from the same dielectric material as the dielectric layer 201 of the layer stacks 202; therefore, it can also be referred to as a dielectric layer 201 in the following descriptions.

[0022] The following will be described, as in the Fig. 3A and Fig. As shown in Figure 3B, several etching processes are carried out to structure the layer stacks 202 and the dielectric layer 201T such that stepped regions 231 are formed. Furthermore, after the multiple etching processes, the structured dielectric layer 201T defines the boundary of a memory field region 233. For example, the memory field region 233 is defined by side walls of the structured dielectric layer 201T. In the subsequent processing, the memory cell fields are formed within the memory field region 233. Fig. Figure 3A shows a perspective view of the storage device 200, and Fig. Figure 3B shows a cross-sectional view of the storage device 200 in Fig. 3A along the cross-section BB.

[0023] As in the Fig. 3A and Fig. As shown in Figure 3B, the layer stack 202D extends in the stepped regions 231, e.g., along the direction of cross-section BB, beyond the lateral dimensions of the dielectric layer 201T. Furthermore, for any two vertically adjacent layer stacks (e.g., 202A and 202B), the lower layer stack (e.g., 202A), which is closer to the substrate 50, extends, e.g., along the direction of cross-section BB, beyond the lateral dimensions of the upper layer stack (e.g., 202B), which is farther from the substrate 50. In other words, the width of a lower layer stack (e.g., 202A), measured along the direction of cross-section BB between opposite side walls of the lower layer stack, is greater than the width of an upper layer stack (e.g., 202B), measured along the direction of cross-section BB between opposite side walls of the upper layer stack.Furthermore, the width of the layer stack 202D is greater than the width of the dielectric layer 201T, measured along the direction of the cross-section BB. In the illustrated embodiment, the layer stacks 202 and the dielectric layer 201T have the same width W when measured along a direction perpendicular to the cross-section BB.

[0024] It should be noted that in these descriptions, a side wall of layer stack 202A, 202B, 202C, or 202D includes the corresponding side walls of all associated layers (e.g., 201 and 203) of that layer stack. For example, a side wall of layer stack 202A, which is exposed by trench 206 (see Fig. 5), the corresponding side wall of the dielectric layer 201 and the corresponding side wall of the electrically conductive layer 203. In the illustrated embodiments, the etching process(s) carried out on each of the layer stacks 202 to form the stair-shaped regions 231 is / are anisotropic, and therefore a side wall of the dielectric layer 201 and a corresponding side wall of the electrically conductive layer 203 in an identical layer stack 202 (e.g. 202A, 202B, 202C or 202D) are aligned along the same vertical plane.

[0025] Still with reference to the Fig. 3A and Fig. In the stepped areas 231, the parts of each layer stack 202 that lie laterally outwards from the storage field area 233 are removed. The higher (e.g., further away from the substrate 50) a layer stack 202 is located, the greater the width (e.g., measured along the direction of the cross-section BB) of the removed parts of the layer stack. Consequently, for each layer stack 202, the parts of the electrically conductive layer 203 that lie laterally outwards from the storage field area 233 are exposed from an overlying layer stack. Thus, the stepped area 231 provides, for example, during the subsequent processing for forming the contacts 227 (see Fig. 10B) provides easy access to the electrically conductive layer 203 of each layer stack 202.

[0026] In some embodiments, to form the stepped region 231, a structured photoresist with a first width (e.g., along the direction of the cross-section BB) is formed over the dielectric layer 201T, and a first anisotropic etching process is performed to structure the dielectric layer 201T and expose the layer stack 202D. In other words, the first anisotropic etching process is terminated when the top surface of the electrically conductive layer 203 of the layer stack 202D is exposed. Subsequently, the width of the structured photoresist is reduced (e.g., by a photoresist trimming process), and a second anisotropic etching process is performed to structure the layer stack 202D and expose the layer stack 202C. In other words, the second anisotropic etching process is terminated when the top surface of the electrically conductive layer 203 of the layer stack 202C is exposed.The second anisotropic etching process also removes exposed portions of the dielectric layer 201T, thus reducing the width of the dielectric layer 201T. The processes described above are repeated, with the width of the structured photoresist decreasing with each subsequent anisotropic etching process, until the top surface of the electrically conductive layer 203 of the layer stack 202A is exposed by the structured layer stack 202B. The structured photoresist can then be removed, for example, by an ashing or ablation process. In some embodiments, the anisotropic etching process (e.g., a dry etching process, such as plasma etching) is carried out using a gas source containing CF4, C4F8, BCl3, Cl2, CCl4, SiCl4, CH2F2, the like, or a combination thereof.

[0027] In the present disclosure, the stair-shaped regions 231 are formed early in the processing process, before the formation of the memory cells in the memory field region 233. Such a processing process is referred to as a stair-first process, which differs from a stair-last process, in which the stair-shaped region is formed after the formation of the memory cells. Because the stair-shaped regions 231 are formed early, less material (e.g., 201 and 203) needs to be etched in the anisotropic etching process to form the stair-shaped regions 231, and therefore it is easier to select the etchant (e.g., the etching gas) with which the target object etch selectivity and the target object etch profiles (e.g., the sidewall profiles after etching) can be achieved. Consequently, the problems of the stair-last process, such as…The challenges of etching multiple thin layers (e.g., because more materials, such as the ferroelectric material 213, the channel material 207, and additional dielectric materials 209 / 212, need to be etched) and the defects (such as the failure of the staircase structure caused by non-volatile byproducts of the etching process) are reduced or avoided. Therefore, the disclosed staircase-first process achieves better process control and a better etch profile, while reducing defects and improving production yield and the performance of the device.

[0028] The following will be discussed in Fig. 4. A dielectric material 205 is formed over the dielectric layer 201T and over the layer stacks 202. A planarization process, such as chemical and mechanical planarization (CMP), can be carried out such that the top surface of the dielectric material 205 lies in a plane with the top surface of the dielectric layer 201T. In some embodiments, the dielectric material 205 is formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable deposition method, such as PVD, CVD, or the like.

[0029] The following will be discussed in Fig. Five trenches 206 are formed. The trenches 206 (which can also be referred to as openings, cavities, or slots) are formed such that they extend through the dielectric layer 201T, the dielectric material 205, and the (remaining parts of the) layer stacks 202. In the example of Fig. 5 the longitudinal axes of the trenches 206 extend along the direction of the cross-section BB (see Fig. 3A). The trenches 206 extend continuously between opposite side walls of the layer stack 202A, such that the trenches 206 define the structure of Fig. 4 cut through and the structure of Fig. 4. Divide into several slices that are separated from each other (e.g., have a distance between them).

[0030] The following will be discussed in Fig. 6. A ferroelectric material 213 is formed in the trenches 206 along the side walls and bottom surfaces of the trenches 206 (e.g., conformal), and a channel material 207 (e.g., conformal) is formed above the ferroelectric material 213. Then, a dielectric material 209 is formed above the channel material 207 to fill the trenches 206. A planarization process, such as CMP, can be performed to remove excess parts of the ferroelectric material 213, excess parts of the channel material 207, and excess parts of the dielectric material 209 from the top surface of the dielectric layer 201T and from the top surface of the dielectric material 205. The remaining ferroelectric material 213 in the trenches 206 can be referred to as ferroelectric film 213, and the remaining channel material 207 in the trenches 206 can be referred to as channel layer 207.

[0031] In some embodiments, the ferroelectric material 213 BaTiO3, PbTiO3, PbZrO3, LiNbO3, NaNbO3, KNbO3, KTaO3, BiScO3, BiFeO3, Hf 1-x He x O, Hf 1-x La x O, Hf 1-x Y x O, Hf 1-x Gd x O, Hf 1-x Al x O, Hf 1-x Zr x O, Hf 1-x Ti x O, Hf 1-x Ta xThe channel material 207 is a semiconducting material such as amorphous silicon (a-Si), polysilicon (Poly-Si), a semiconducting oxide (e.g., indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide (ITO), or indium tungsten oxide (IWO)), or the like. The channel layer 207 can be formed, for example, by PVD, CVD, ALD, combinations thereof, or the like. In some embodiments, the dielectric material 209 is formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable deposition method, such as PVD, CVD, ALD, or the like.

[0032] The following will be discussed in Fig. 7. Conductive traces 216 are formed in the storage field area 233, and they extend vertically through the dielectric layer 201T and the layer stacks 202. The conductive traces 216 are conductive columns (which can also be referred to as metal columns or metal conductors) that extend vertically (e.g., perpendicular to the upper surface of the substrate 50) through the storage field area 233 and are electrically coupled to the electrically conductive layers 203 of the layer stacks 202A, 202B, 202C, and 202D. To form the conductive traces 216, openings are created in the dielectric material 209 in the storage field area 233 (e.g., by means of photolithography and etching techniques), with the openings extending from the upper surface of the dielectric layer 201T to the lower surface of the layer stack 202A, which faces the substrate 50. Next, an electrically conductive material (or materials) will be used, such as...Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt or the like, formed to fill the openings, thereby forming the conductor tracks 216.

[0033] The following will be discussed in Fig. 8A An insulating region 212 is formed in each of the conductor tracks 216 to divide each conductor track 216 into a conductor track pair 215A and 215B. For the sake of simplicity, the conductor tracks 215A and 215B can be collectively referred to as conductor tracks 215. The insulating regions 212 can be formed by performing an anisotropic etching process to create an opening in each of the conductor tracks 216 and then filling the opening with a dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable fabrication process, such as CVD, PVD, ALD, or the like.

[0034] Fig. Figure 8B shows a top view of part of the memory field area 233 of the memory device 200. Fig. 8A. The Fig. 8C, Fig. 8D and Fig. 8E shows cross-sectional views of part of the storage device 200 in Fig. 8B along the respective cross-sections CC, DD and EE. As shown in the top view of Fig. As shown in Figure 8B, each insulation region 212 extends continuously from a first side wall of the ferroelectric material 213 to a second side wall of the ferroelectric material 213, which faces the first side wall of the ferroelectric material. In other words, the width of the insulation region 212 is, along the horizontal direction of Fig. 8B measured, equal to a distance between the inner side walls of the ferroelectric material 213, which lie in a trench and face each other. Furthermore, each of the conductor tracks 215 extends continuously from a first side wall of the channel material 207 to a second side wall of the channel material 207, which faces the first side wall of the channel material. In other words, along the horizontal direction of Fig. 8B measured, the width of the conductor track 215 is equal to the distance between the inner side walls of the channel material 207, which lie in a trench and face each other.

[0035] In Fig. 8B represents a few, but not all, of the memory cells 223 (e.g., 223A, 223B, 223C) that are formed in the memory field area, marked by dashed boxes. In the Fig. 8C and Fig. In 8D, memory cells 223 are also marked by dashed boxes. As in the Fig. As shown in Figures 8A-8E, each memory cell 223 is a transistor with an embedded ferroelectric film 213. In each memory cell 223, the electrically conductive layer 203 (see, for example, the Fig. 8C and Fig. 8D) the function of the gate electrode of the transistor, the conductor tracks 215A and 215B fulfill the function of the source / drain regions of the transistor, and the channel material 207 fulfills the function of the channel layer between the source / drain regions. The dashed line 221 in Fig. 8B (see also the Fig. 8C and Fig. Figure 8D shows the channel area that is formed in the channel material 207 during the operation of the storage device 200, e.g., when a voltage is applied to the gate of the transistor and causes the transistor to switch on. The electrical polarization direction of the ferroelectric film 213 in each memory cell 223 indicates the digital information (e.g., a "0" or "1") stored in the memory cell 223 and determines the threshold voltage of the transistor of the memory cell 223, with more details being given below.

[0036] In the context of the memory devices, the electrically conductive layer 203 (e.g., the gate electrode) in each memory cell 223 is referred to as the word line (WL) of the memory cell, and the conductor tracks 215A and 215B (e.g., the source / drain regions) can be referred to as the source line (SL) and the bit line (BL) of the memory cell. The source line can also be referred to as the scan line.

[0037] As in Fig. As shown in Figure 8A, each of the electrically conductive layers 203 (e.g., WL) of the storage device 200 electrically connects several storage cells that are arranged along the same horizontal plane (e.g., at the same vertical distance from the substrate 50). As shown in the Fig. As shown in Figure 8C-8D, each SL or BL 215 electrically connects several vertically stacked memory cells 223. Therefore, with the disclosed 3D storage device 200, an efficient distribution of the WL, BL and SL among the multiple memory cells 223 is achieved, and the 3D structure of the memory cells 223 allows the multiple layers of the memory cells 223 to be easily stacked next to each other to form high-density memory arrays.

[0038] The following will be discussed in Fig. 9. The channel material 207 arranged in the stepped regions 231 is removed, and a dielectric material 208 is formed to fill the space occupied by the removed channel material 207. In some embodiments, to remove the channel material 207 in the stepped regions 231, a structured mask layer (e.g., a structured photoresist) is formed over the storage device 200 to cover the storage field region 233 and expose the stepped regions 231. Subsequently, an etching process is carried out using an etchant that is selective for the channel material 207 (e.g., exhibits a higher etch rate for it) to selectively remove the exposed channel material 207. Subsequently, the dielectric material 208 is formed to fill the space from which the portions of the channel material 207 were removed.The dielectric material 208 can be formed from the same or a similar material as the dielectric material 205, so details are not repeated here. The interface between the dielectric material 208 and the dielectric material 209 is shown in . Fig. 9 marked by dashed lines, which may but do not have to be visible in the final product.

[0039] The following will be discussed in Fig. Contacts 225 are formed above the storage field area 233 and electrically coupled to the respective SL / BL 215, and contacts 227 are formed above the stepped areas 231 and electrically coupled to the respective WL 203. The contacts 227 can be formed by creating openings in the dielectric material 205 and filling the openings with an electrically conductive material. The contacts 225 can be formed by creating a dielectric layer (not shown) over the upper surface of the dielectric material 205, creating openings in the dielectric layer, and filling the openings with an electrically conductive material. Fig. Figure 10B shows a cross-sectional view of the 3D storage device 200. Fig. 10A along the cross-section FF. As in Fig. As shown in Figure 10B, the contacts 227 are designed to extend through the dielectric material 205, and each contact 227 is electrically coupled to an associated electrically conductive layer 203 (e.g., WL 203). As shown in Fig. As shown in Figure 10B, the stepped areas allow easy access for the WL 203 to the contacts 227. The contacts 225 and 227 can be connected, for example, via the vias 124 and the conductor tracks 125 to the underlying electrical components or circuits in the substrate 50 (see Figure 10B). Fig. 1) and / or connect to the Interconnect structures 140.

[0040] With reference to the Fig. In contacts 8A-8E and 10A, a write voltage is applied across a portion of the ferroelectric material 213 in a specific memory cell 223 to execute a write operation. The write voltage can be applied, for example, by applying a first voltage to the gate electrode 203 of the memory cell 223 (via contact 227) and a second voltage to the source / drain regions 215A / 215B (via contacts 225). The voltage difference between the first and second voltages determines the polarization direction of the ferroelectric material 213. Depending on the polarization direction of the ferroelectric material 213, the threshold voltage VT of the corresponding transistor in the memory cell 223 can be switched from a low threshold voltage VL to a high threshold voltage VH, or vice versa.The value of the transistor's threshold voltage (VL or VH) can be used to indicate a "0" or "1" bit stored in the memory cell.

[0041] To perform a read operation at memory cell 223, a read voltage, which is a voltage between the low threshold voltage VL and the high threshold voltage VH, is applied to the gate electrode 203. Depending on the polarization direction of the ferroelectric material 213 (or the threshold voltage VT of the transistor), the transistor of memory cell 223 may or may not be switched on. Consequently, if, for example, a voltage is applied between the source / drain regions 215A and 215B, an electric current may or may not flow between these regions. Therefore, the electric current must be determined to ascertain the digital bit stored in the memory cell.

[0042] The Fig. 11 and Fig. Figure 12 shows perspective views of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) 200A in various processing stages in a further embodiment. The 3D FeRAM device 200A is similar to the 3D FeRAM device 200 of Fig. 10A, however, the channel material 207 and the ferroelectric material 213 were removed from the stepped areas 231. For example, the 3D FeRAM device 200A can be formed by machining as shown in the Fig. 2A, 2B, 3A, 3B, 4-7, 8A, 8B, 8C, 8D and 8E are shown. Then, in the processing step of Fig. 9. The channel material 207 and the ferroelectric material 213 are removed from the stepped regions 231, for example by using one or more selective etching processes. Then the dielectric material 208 can be formed to fill the spaces occupied by the removed portions of the channel material 207 and the removed portions of the ferroelectric material 213. The following sections describe in Fig. 12. Contacts 225 and 227 were formed, using the same or similar processing as in Fig. 10A is executed.

[0043] The Fig. Figures 13-19 show perspective views of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) 200B in various stages of processing in yet another embodiment. The 3D FeRAM device 200B is similar to the 3D FeRAM device 200 from Fig. 10A, however, the ferroelectric material 213 and the channel material 207 were only formed in the storage field area 233. In particular, the processing takes place in Fig. 13 in the processing steps of the Fig. 2A, Fig. 2B, Fig. 3A, Fig. 3B and Fig. 4. After processing in Fig. 4. Trenches 232 are formed in the storage field area 233. The trenches 232 extend through the dielectric layer 201T and the layer stacks 202. In the illustrated embodiments, the trenches are oriented along the direction of the cross-section BB (see figure). Fig. 3A) The measured length of the trenches 232 is the same as the length of the storage area 233. Therefore, in the example of Fig. 13 not into the stepped areas 231. In other embodiments, the length of the trenches 232 measured along the direction of the cross-section BB is shorter or longer than the length of the storage area 233.

[0044] The following will be discussed in Fig. 14. The ferroelectric material 213 is formed along the side walls and bottom surfaces of the trenches 232 (e.g., conformal), and the channel material 207 (e.g., conformal) is formed over the ferroelectric material 213. Then, a dielectric material 209 is formed over the channel material 207 to fill the trenches 232. A planarization process, such as CMP, can be performed to remove excess parts of the ferroelectric material 213, excess parts of the channel material 207, and excess parts of the dielectric material 209 from the top surface of the dielectric layer 201T and from the top surface of the dielectric material 205. The ferroelectric material 213 remaining in the trenches 232 can be referred to as ferroelectric films 213, and the channel material 207 remaining in the trenches 232 can be referred to as channel layers 207.

[0045] The following will be discussed in Fig. Fifteen conductive traces 216 are formed in the dielectric material 209. The following section describes... Fig. 16 in each of the conductor tracks, an insulating area 212 is formed to divide each conductor track 216 into a conductor track pair 215A and 215B. The processing is the same as or similar to that described above with reference to the Fig. 7 and 8A-8E were discussed, so details will not be repeated.

[0046] The following will be discussed in Fig. 17 trenches 234 are formed in the stepped regions 231. The trenches 234 extend through the dielectric layer 201T and the layer stacks 202. In some embodiments, the trenches 234 are formed by forming a structured photoresist over the storage device 200B, wherein the structures (e.g., openings) of the structured photoresist expose the regions of the stepped areas 231 in which the trenches 234 are to be formed. Subsequently, an anisotropic etching process is carried out, wherein the structured photoresist is used as an etching mask to remove the exposed parts of the 3D storage device 200B. As in Fig. As shown in Figure 17, the trenches 234 expose side walls 213S of the ferroelectric material 213. It should be noted that regardless of the length of the trenches 232 in Fig. 13, the dimensions of the trenches 234 are adjusted so that they correspond to the length of the trenches 232 in Fig. 13 fit so that the side walls 213S of the ferroelectric material 213 are exposed by the grooves 234. After the etching process, the structured photoresist can be removed, for example, by ashing or a erosion process.

[0047] The following will be discussed in Fig. 18 a dielectric material is formed to fill the trenches 234. In the illustrated embodiment, the dielectric material for filling the trenches 234 is the same as the dielectric material 205, thus the dielectric material 205 can be used in Fig. 17 and the dielectric material for filling the trenches 234 in Fig. 18 can be collectively referred to as dielectric material 205. A planarization process, such as CMP, can be carried out to expose the top surface of the dielectric layer 201T and to achieve a coplanar top surface between the dielectric material 205 and the dielectric layer 201T.

[0048] The following will be discussed in Fig. 19 contacts 225 are formed above the storage field area 233 and electrically coupled to the respective SL / BL 215, and contacts 227 are formed above the stair-shaped areas 231 and electrically coupled to the respective WL 203.

[0049] Fig. Figure 20 shows an equivalent circuit diagram 300 of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) in one embodiment. The circuit diagram 300 can correspond to some of the 3D memory devices disclosed herein, such as 200, 200A, or 200B.

[0050] Fig. Figure 20 shows three horizontally oriented WLs (e.g., WL0, WL1, and WL2) arranged on three vertical planes, corresponding to the three different WLs of the 3D FeRAM devices 200, 200A, or 200B. The memory cells in each vertical plane are represented as transistors. The gate electrodes of the transistors are connected to the same WL in the same vertical plane. Fig. Figure 20 further shows vertically oriented BLs (e.g., BL0, BL1, ..., BL5) and SLs (e.g., SL0, SL1, ..., SL5). The BLs and SLs correspond, for example, to the BL 215A and SL 215B of the embodiment of the 3D FeRAM devices 200 / 200A / 200B. Each of the BLs and SLs is connected to several vertically stacked memory cells.

[0051] Fig. Figure 21 presents a flowchart of a method 1000 for manufacturing a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) in some embodiments. It should be understood that the in Fig. The 21 presented procedure example is merely one of many possible procedure examples. An expert would recognize many variations, alternatives, and modifications. For example, as in Fig. As shown in 21, various steps can be added, deleted, replaced, rearranged or repeated.

[0052] With reference to Fig. 21. At block 1010, a first layer stack and a second layer stack are successively formed over a substrate, wherein the first and second layer stacks have an identical layer structure comprising a layer of a first electrically conductive material over a layer of a first dielectric material, the first layer stack extending beyond the lateral dimensions of the second layer stack. At block 1020, a trench is formed extending through the first and second layer stacks. At block 1030, the side walls and bottom of the trench are lined with a ferroelectric material. At block 1040, a channel material is conformally formed in the trench over the ferroelectric material. At block 1050, the trench is filled with a second dielectric material.At block 1060, a first opening and a second opening are formed in the second dielectric material. At block 1070, the first opening and the second opening are filled with a second electrically conductive material.

[0053] Variants and modifications of the disclosed embodiments are possible, and it is fully intended to include them within the scope of this disclosure. For example, four layer stacks 202 (e.g., 202A, 202B, 202C, and 200D) are shown as non-limiting examples in the 3D storage devices 200, 200A, and 200B. The number of layer stacks 202 in the 3D storage device can be any suitable number, such as one, two, three, or more than four, as will be readily apparent to those skilled in the art. As another example, the number of formed trenches (e.g., 206 in Fig. 5 or Fig. 232 in Fig.13) besides the three trenches shown, any suitable number. As yet another example, the number of conductor tracks 215 formed in each row of the dielectric material 209 (e.g., each row formed in a trench) can be any suitable number. As yet another example, the stepped regions 231 in the illustrated embodiments are formed on opposite sides of the storage field region 233 as non-limiting examples. The storage devices 200, 200A, and 200B can be formed by forming only one stepped region 231 adjacent to the storage field region 233.

[0054] Advantages can be achieved with these embodiments. The disclosed step-first process reduces or eliminates problems associated with the step-last process, such as the challenges of etching multiple thin layers and defects (e.g., failure of the step structure caused by non-volatile byproducts of the etching process). Consequently, the disclosed step-first process achieves better process control and an improved etch profile, while reducing defects and improving production yield and device performance. The disclosed 3D storage devices can be easily integrated into existing semiconductor devices during BEOL processing. The areas beneath the 3D storage devices can be further utilized to create various circuits, such as...Logic circuits, I / O circuits, or ESD circuits need to be formed during FEOL processing. Therefore, apart from the peripheral circuits (e.g., decoders, amplifiers) and routing circuits used for the 3D memory devices, there are few disadvantages regarding the space requirements for integrating the disclosed 3D memory devices. Furthermore, the disclosed 3D memory devices feature highly efficient structures for reducing their memory cell size. For example, each BL or SL is shared by several vertically stacked memory cells. Each WL is shared by several horizontally oriented memory cells formed at the same vertical distance from the substrate.As outlined above, the disclosed 3D memory devices exhibit structures that can be easily scaled to enable the formation of high-density memory arrays, which is important for emerging applications such as the Internet of Things (IoT) and machine learning. By integrating the 3D memory arrays on-chip during BEOL processing, problems such as power consumption bottlenecks during off-chip memory access are avoided. As a result, semiconductor devices incorporating the disclosed 3D memory devices can be manufactured smaller and less expensively, while operating at higher speeds and consuming less power.

[0055] According to one embodiment, a method for forming a ferroelectric direct-access memory device (FeRAM device) comprises the following: forming a first layer stack and a second layer stack successively over a substrate, wherein the first layer stack and the second layer stack each have a first dielectric layer and an electrically conductive layer formed over the first dielectric layer; forming a second dielectric layer over the second layer stack; structuring the first layer stack, the second layer stack, and the second dielectric layer, wherein a stepped region is formed during structuring, wherein in the stepped region the second layer stack extends beyond the lateral dimensions of the second dielectric layer and the first layer stack extends beyond the lateral dimensions of the second layer stack.wherein, after structuring, the electrically conductive layers of the first and second layer stacks form a first word line and a second word line, respectively; after structuring, forming a trench extending through the first layer stack, the second layer stack, and the second dielectric layer; coating the sidewalls and bottom of the trench with a ferroelectric material; forming a channel material over the ferroelectric material; filling the trench by forming a dielectric material over the channel material; and forming a source line and a bit line in the dielectric material, wherein the source line and the bit line extend through the second dielectric layer,extending through the second layer stack and the first layer stack. In one embodiment, in the stepped region, the second layer stack extends along a first direction beyond the lateral dimensions of the second dielectric layer, and the first layer stack extends along the first direction beyond the lateral dimensions of the second layer stack. In one embodiment, the trench is designed such that it has a longitudinal axis along the first direction. In one embodiment, after structuring, side walls of the structured second dielectric layer define a storage field region adjacent to the stepped region. In one embodiment, the trench is designed such thatthat it extends through the memory field area and the stepped area. In one embodiment, the method, after forming the source line and the bit line, further comprises removing the channel material from the stepped area. In one embodiment, the method, after forming the source line and the bit line, further comprises removing the channel material and the ferroelectric material from the stepped area. In one embodiment, the trench is formed in the memory field area. In one embodiment, the bit line and the source line are formed in the memory field area, the method further comprising,that first contacts are formed above the memory field area and electrically coupled to the bit line and the source line, and that second contacts are formed above the stepped area and electrically coupled to the first word line and the second word line. In one embodiment, the source line and the bit line are formed from an electrically conductive material, wherein the longitudinal axes of the source line and the bit line are perpendicular to an upper surface of the substrate. In one embodiment, the source line and the bit line extend continuously in a top view from a first side wall of the channel material to a second side wall of the channel material, which corresponds to the first side wall of the,The method further comprises: forming a further source conductor in the dielectric material adjacent to the bit conductor; and forming an insulating region between and in contact with the bit conductor and the further source conductor, wherein the insulating region extends continuously in plan view from a first side wall of the ferroelectric material to a second side wall of the ferroelectric material, which faces the first side wall of the ferroelectric material.

[0056] According to one embodiment, a method for forming a ferroelectric direct-access memory device (FeRAM device) comprises the following: forming a first layer stack and a second layer stack successively over a substrate, wherein the first layer stack and the second layer stack have an identical layer structure comprising a layer of a first electrically conductive material over a layer of a first dielectric material, the first layer stack extending beyond the lateral dimensions of the second layer stack; forming a trench extending through the first layer stack and the second layer stack; coating side walls and bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; and filling the trench with a second dielectric material.Forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material. In one embodiment, the first layer stack extends in a first direction beyond the lateral dimensions of the second layer stack, with a longitudinal axis of the trench extending along the first direction. In one embodiment, the trench divides the first layer stack and the second layer stack into two separate parts. In one embodiment, the method further comprises removing, after filling the first opening and the second opening, at least portions of the ferroelectric material that lie outside the boundaries of the second layer stack. In one embodiment, the trench is formed in a region bounded by the side walls of the second layer stack.

[0057] According to one embodiment, a ferroelectric direct-access memory device (FeRAM device) comprises: a first layer stack; a second layer stack above the first layer stack, wherein the first layer stack and the second layer stack have an identical layer structure comprising a layer of a first electrically conductive material over a layer of a first dielectric material, the first layer stack extending beyond the lateral dimensions of the second layer stack; a second dielectric material embedded in the first layer stack and the second layer stack, the second dielectric material extending through the first layer stack and the second layer stack; a ferroelectric material between the second dielectric material and the first layer stack and between the second dielectric material and the second layer stack;a channel material between the ferroelectric material and the second dielectric material; and electrical conductors embedded in the second dielectric material, the electrical conductors extending through the first layer stack and the second layer stack. In one embodiment, the FeRAM device further comprises: a first dielectric layer above the second layer stack, the second layer stack extending beyond the lateral dimensions of the first dielectric layer;and a second dielectric layer above the first layer stack and the second layer stack, wherein an upper surface of the second dielectric layer lies in a plane with an upper surface of the first dielectric layer. In one embodiment, the FeRAM device further comprises insulating regions embedded in the second dielectric material, wherein the insulating regions extend through the first layer stack and the second layer stack, and wherein, in a top view, the insulating regions extend continuously from a first side wall of the ferroelectric material to a second side wall of the ferroelectric material facing the first side wall.

Claims

[1] Method (1000) for forming a ferroelectric direct access memory device, FeRAM device (200), wherein the method (1000) comprises: Forming a first layer stack (202A, 202B, 202C and 202D) and a second layer stack (202A, 202B, 202C and 202D) successively over a substrate (50, 101), wherein the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D) each have a first dielectric layer (201) and an electrically conductive layer (203) formed over the first dielectric layer (201); Forming a second dielectric layer (201T) over the second layer stack (202A, 202B, 202C and 202D); Structuring the first layer stack (202A, 202B, 202C and 202D), the second layer stack (202A, 202B, 202C and 202D) and the second dielectric layer (201T), wherein a step-shaped region (231) is formed during structuring, wherein in the step-shaped region (231) the second layer stack (202A, 202B, 202C and 202D) extends beyond lateral dimensions of the second dielectric layer (201T) and the first layer stack (202A, 202B, 202C and 202D) extends beyond lateral dimensions of the second layer stack (202A, 202B, 202C and 202D), wherein after structuring the electrically conductive layers of the first and second layer stacks (202A, 202B, 202C and 202D) form a first word line or a second word line; Formation of a first dielectric material (205) over the second dielectric layer (201T) and over the layer stacks (202A, 202B, 202C and 202D); Performing a planarization process such that the upper surface of the first dielectric material (205) lies on a plane with the upper surface of the second dielectric layer (201T); After structuring, a trench (206, 232, 234) is formed, which extends through the first layer stack (202A, 202B, 202C and 202D), the second layer stack (202A, 202B, 202C and 202D) and the second dielectric layer (201T); Coating the side walls and bottom of the trench (206, 232, 234) with a ferroelectric material (213); Formation of a channel material (207) over the ferroelectric material (213); Filling the trench (206, 232, 234) by forming a second dielectric material (205, 208, 209) above the channel material (207); and Forming a source line and a bit line in the second dielectric material (205, 208, 209), wherein the source line and the bit line extend through the second dielectric layer (201T), the second layer stack (202A, 202B, 202C and 202D) and the first layer stack (202A, 202B, 202C and 202D). [2] Method (1000) according to claim 1, wherein in the stair-shaped region (231) the second layer stack (202A, 202B, 202C and 202D) extends along a first direction beyond the lateral dimensions of the second dielectric layer (201T) and the first layer stack (202A, 202B, 202C and 202D) extends along the first direction beyond the lateral dimensions of the second layer stack (202A, 202B, 202C and 202D). [3] Method (1000) according to claim 2, wherein the trench (206, 232, 234) is designed such that it has a longitudinal axis along the first direction. [4] Method (1000) according to one of the preceding claims, wherein side walls of the structured second dielectric layer (201T) define a storage field region (233) adjacent to the stair-shaped region (231) after structuring. [5] Method (1000) according to claim 4, wherein the trench (206, 232, 234) is designed such that it extends through the storage field area (233) and the stair-shaped area (231). [6] Method (1000) according to one of the preceding claims, further comprising that after forming the source line and the bit line the channel material (207) is removed from the stair-shaped area (231). [7] Method (1000) according to any one of claims 1 to 4, further comprising that after forming the source line and the bit line the channel material (207) and the ferroelectric material (213) are removed from the stair-shaped area (231). [8] Method (1000) according to claim 4 and one of the preceding claims, wherein the trench (206, 232, 234) is formed in the storage field area (233). [9] Method (1000) according to claim 4 and one of the preceding claims, wherein the bit line and the source line are formed in the memory field area (233), wherein the method (1000) further comprises: Forming first contacts (225) above the memory field area (233) and electrically coupled to the bit line and the source line; and Forming second contacts (227) above the stair-shaped area (231) and electrically coupled to the first word line and the second word line. [10] Method (1000) according to one of the preceding claims, wherein the source line and the bit line are formed from an electrically conductive material, wherein longitudinal axes of the source line and the bit line are perpendicular to an upper surface of the substrate (50, 101). [11] Method (1000) according to one of the preceding claims, wherein the source line and the bit line extend continuously in a top view from a first side wall of the channel material (207) to a second side wall of the channel material (207) which faces the first side wall of the channel material (207). [12] Method (1000) according to any one of the preceding claims, further comprising: Formation of another source line in the second dielectric material (205, 208, 209) adjacent to the bit line; and Forming an isolation zone (105, 212) between and in contact with the bit line and the further source line, wherein the isolation zone (105, 212) extends continuously in plan view from a first side wall of the ferroelectric material (213) to a second side wall of the ferroelectric material (213) which faces the first side wall of the ferroelectric material (213). [13] Method (1000) for forming a ferroelectric direct access memory device, FeRAM device (200), wherein the method (1000) comprises: Forming a first layer stack (202A, 202B, 202C and 202D), a second layer stack (202A, 202B, 202C and 202D), and a dielectric layer (201T) successively over a substrate (50, 101), wherein the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D) have an identical layer structure comprising a layer of a first electrically conductive material over a layer of a first dielectric material (205, 208, 209), wherein the first layer stack (202A, 202B, 202C and 202D) extends over lateral dimensions of the second layer stack (202A, 202B, 202C and 202D) extends beyond, and wherein the second layer stack (202A, 202B, 202C and 202D) extends beyond lateral dimensions of the dielectric layer (201T); Forming a second dielectric material (205) over the dielectric layer (201T) and over the layer stacks (202A, 202B, 202C and 202D); Performing a planarization process such that the upper surface of the second dielectric material (205) lies on a plane with the upper surface of the dielectric layer (201T); Forming a trench (206, 232, 234) extending through the first layer stack (202A, 202B, 202C and 202D), the second layer stack (202A, 202B, 202C and 202D) and the dielectric layer (201T); Coating the side walls and bottom of the trench (206, 232, 234) with a ferroelectric material (213); conformal formation of a channel material (207) in the trench (206, 232, 234) over the ferroelectric material (213); Filling the trench (206, 232, 234) with a third dielectric material (205, 208, 209); Forming a first opening and a second opening in the third dielectric material (205, 208, 209); and Filling the first opening and the second opening with a second electrically conductive material. [14] Method (1000) according to claim 13, wherein the first layer stack (202A, 202B, 202C and 202D) extends in a first direction beyond the lateral dimensions of the second layer stack (202A, 202B, 202C and 202D), wherein a longitudinal axis of the trench (206, 232, 234) is configured to extend along the first direction. [15] Method (1000) according to claim 13 or 14, wherein the trench (206, 232, 234) divides the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D) into two separate parts. [16] Method (1000) according to any one of claims 13 to 15, further comprising: After filling the first opening and the second opening, at least parts of the ferroelectric material (213) that lie outside the boundaries of the second layer stack (202A, 202B, 202C and 202D) are removed. [17] Method (1000) according to any one of claims 13 to 16, wherein the trench (206, 232, 234) is formed in an area bounded by side walls of the second layer stack (202A, 202B, 202C and 202D). [18] Ferroelectric direct access memory device, FeRAM device (200), comprising: a first layer stack (202A, 202B, 202C and 202D); a second layer stack (202A, 202B, 202C and 202D) above the first layer stack (202A, 202B, 202C and 202D), wherein the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D) have the same layer structure comprising a layer of a first electrically conductive material above a layer of a first dielectric material (205, 208, 209), wherein the first layer stack (202A, 202B, 202C and 202D) extends in a step-shaped region (231) beyond lateral dimensions of the second layer stack (202A, 202B, 202C and 202D); a second dielectric material (205, 208, 209) embedded in the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D), wherein the second dielectric material (205, 208, 209) extends through the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D); a ferroelectric material (213) between the second dielectric material (205, 208, 209) and the first layer stack (202A, 202B, 202C and 202D) and between the second dielectric material (205, 208, 209) and the second layer stack (202A, 202B, 202C and 202D); a channel material (207) between the ferroelectric material (213) and the second dielectric material (205, 208, 209); electrical conductors embedded in the second dielectric material (205, 208, 209), the electrical conductors extending through the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D); a first dielectric layer (201T) over the second layer stack (202A, 202B, 202C and 202D), wherein the second layer stack (202A, 202B, 202C and 202D) extends beyond the lateral dimensions of the first dielectric layer (201T) in the step-shaped region (231), wherein side walls of the first dielectric layer (201T) define a storage field region (233) adjacent to the stair-shaped region (231); and a second dielectric layer (205) in the step-shaped region (231) above the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D), wherein an upper surface of the second dielectric layer (205) lies in a plane with an upper surface of the first dielectric layer (201T). [19] FeRAM device (200) according to claim 18, further comprising insulating regions embedded in the second dielectric material (205, 208, 209), wherein the insulating regions (105, 212) extend through the first layer stack (202A, 202B, 202C and 202D) and the second layer stack (202A, 202B, 202C and 202D), wherein the insulating regions (105, 212) extend continuously in a top view from a first side wall of the ferroelectric material (213) to a second side wall of the ferroelectric material (213) facing the first side wall.

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