Barrier-free interface between BEOL interconnects

Abstract

Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100), which features: a first interconnect (106) that is within a dielectric Interlayer structure, ILD structure (104), is arranged over a substrate (102), wherein the first interconnect (106) is in contact with a side wall of the ILD structure (104); a barrier layer (110), wherein an upper section of the barrier layer (110) is arranged along side walls of the ILD structure (104) and the upper section of the barrier layer (110) has an inner side wall, and wherein a lower section of the barrier layer (110) defines an opening above the first interconnect (106), the opening in the barrier layer (110) being aligned with a side wall of the first interconnect (106) and / or with the side wall of the ILD structure (104); and a second interconnect (108) arranged on the barrier layer (110), wherein the second interconnect (108) extends through the opening in the barrier layer (110) and to the first interconnect (106); wherein a lowermost section of the barrier layer (110) extends laterally from the inner side wall of the upper section of the barrier layer (110) in the direction of the opening in the barrier layer (110).

Description

BACKGROUND

[0001] Modern integrated chips feature millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., a silicon substrate). The semiconductor devices are electrically connected to each other by interconnects. The interconnects include interconnect wires and interconnect vias arranged within a dielectric structure over a semiconductor substrate. By using interconnects to electrically connect the semiconductor devices, the semiconductor devices are capable of performing logical functions that enable the operation of an integrated chip.

[0002] DE 10 2011 054 908 A1, US 2020 / 0 006 127 A1, US 7 728 436 B2, US 7 335 590 B2 and US 2008 / 0 220 608 A1 describe conventional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip having back-end-of-the-line (BEOL) interconnects that meet at a junction-free interface. Fig. 2A-2B show some further embodiments of an integrated chip having interconnects that meet at a junction-free interface. Fig. Figure 3 shows a cross-sectional view of some alternative embodiments of an integrated chip having interconnects that meet at a junction-free interface. Fig. 4A-4B show cross-sectional views of some alternative embodiments of an integrated chip having interconnects that meet at a junction-free interface. Fig. Figure 5 shows a cross-sectional view of some alternative embodiments of an integrated chip having interconnects that meet at a junction-free interface. Fig. 6-21 show cross-sectional views of some embodiments of a method for forming an integrated chip having interconnects that meet at a junction-free interface. Fig. 22 shows a flow diagram of some embodiments of a method for forming an integrated chip having interconnects that meet at a junction-free interface. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, reference numbers and / or letters may be repeated throughout the various examples in the present disclosure. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, terms describing a spatial relationship, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It is intended that the terms describing a spatial relationship encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the terms for spatial relationships used herein may also be interpreted accordingly.

[0006] Integrated chips have a front-end-of-the-line (FEOL) with components arranged within a substrate, and a back-end-of-the-line (BEOL) with interconnects (e.g., interconnect wires, interconnect vias, etc.) arranged within an inter-level dielectric structure (ILD structure) above the substrate. The interconnects are electrically connected to the transistor components. Over time, the size of the transistor components and the spacing between them have decreased. To accommodate the smaller transistor components, the size of the interconnects has also decreased.

[0007] As interconnect sizes decrease, the spacing between adjacent interconnects also decreases. The smaller spacing between adjacent interconnects causes the capacitance between adjacent interconnects to increase. Furthermore, as interconnect sizes decrease, electrical current flow through the interconnects becomes more difficult, and the resistance of the interconnects increases. Since the product of resistance and capacitance (RC) is inversely proportional to the speed of an integrated chip, interconnects can become a bottleneck for the speed of integrated chips.

[0008] To provide interconnects with low electrical resistance, a low-resistance metal can be used. For example, interconnects are often formed using copper because of its low resistance and ease of processing. However, atoms of some such metals can diffuse into a surrounding ILD structure over time. Metal atoms within the ILD structure can create current paths through the ILD structure and lead to an electrical short between neighboring interconnects. To prevent diffusion of metal atoms into a surrounding ILD structure, a barrier layer can be formed around the metal. It has been found that the barrier layer can have a significantly higher resistance than the metal and can therefore negatively impact the resistance of an interconnect structure and degrade the performance of an integrated chip.

[0009] The present disclosure, in some embodiments, relates to an integrated chip having an interconnect structure that does not include a barrier layer vertically separating an interconnect from an underlying interconnect. In some embodiments, the integrated chip may include a first interconnect disposed within an interlayer dielectric (ILD) structure over the substrate and a second interconnect disposed within the ILD structure over the first interconnect. A barrier layer laterally surrounds the second interconnect and separates the second interconnect from the ILD structure. The barrier layer has sidewalls defining an opening directly above the first interconnect. The second interconnect extends vertically through the opening defined by the sidewalls of the barrier layer to contact a top surface of the first interconnect.Because the second interconnect extends through the opening in the barrier layer, the barrier layer does not separate the second interconnect from the first interconnect, and the barrier layer does not significantly increase the resistance of the interconnect structure.

[0010] Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip 100 having back-end-of-the-line (BEOL) interconnects that meet at a junction-free interface.

[0011] The integrated chip 100 includes an interlayer dielectric (ILD) structure 104 disposed over a substrate 102. The ILD structure 104 surrounds a plurality of interconnects 106-108. The plurality of interconnects 106-108 includes a first interconnect 106 and a second interconnect 108 over the first interconnect 106. In some embodiments, the plurality of interconnects 106-108 may include a middle-end-of-the-line (MOL) interconnect, a conductive contact, an interconnect wire, and / or an interconnect via. For example, in some embodiments, the first interconnect 106 may include an interconnect via, and the second interconnect 108 may include an interconnect wire.

[0012] A barrier layer 110 extends along sidewalls of the first interconnect 108 and laterally separates the second interconnect 108 from the ILD structure 104. The barrier layer 110 is configured to prevent the diffusion of atoms from the second interconnect 108 into the ILD structure 104. In some embodiments, the barrier layer 110 may further extend along a bottom surface of the second interconnect 108 and vertically separate the second interconnect 108 from the ILD structure 104. The barrier layer 110 has sidewalls defining an opening extending through the barrier layer 110.

[0013] The second interconnect 108 extends vertically through the opening in the barrier layer 110 to physically contact a top surface of the first interconnect 106. In some embodiments, the second interconnect 108 has a bottom surface 108L resting on the barrier layer 110 and a protrusion 108P extending outward from the bottom surface 108L and through the barrier layer 110. The barrier layer 110 may comprise a material having a lower conductivity (e.g., a higher resistivity) than the second conductive material of the second interconnect 108. However, because the second interconnect 108 extends vertically through the barrier layer 110, the barrier layer 110 does not separate the first interconnect 106 from the second interconnect 108.Because the barrier layer 110 does not separate the first interconnect 106 from the second interconnect 108, the resistance between the first interconnect 106 and the second interconnect 108 is reduced. For example, the resistance between the first interconnect 106 and the second interconnect 108 can be reduced by approximately 20% or more compared to interconnects separated by a barrier layer. Reducing the resistance between the first interconnect 106 and the second interconnect 108 can improve the performance of the integrated chip 100 (e.g., a ring oscillator can experience a speed improvement of approximately 1.5% or more).

[0014] Fig. 2A shows a cross-sectional view of some further embodiments of an integrated chip 200 having interconnects that meet at a junction-free interface.

[0015] The integrated chip 200 includes a plurality of interconnects 105-108 disposed within an ILD structure 104 over a substrate 102. In some embodiments, the ILD structure 104 includes a plurality of stacked inter-level dielectric layers (ILD layers) 204a-204c. The plurality of stacked ILD layers 204a-204c includes a bottom ILD layer 204a, a first ILD layer 204b over the bottom ILD layer 204a, and a second ILD layer 204c over the first ILD layer 204b. In some embodiments, the plurality of stacked ILD layers 204a-204c may include silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), and / or a porous dielectric material, or the like.In some embodiments, adjacent ones of the plurality of stacked ILD layers 204a-204c may be separated by an etch stop layer 206. In various embodiments, the etch stop layer 206 may include a carbide (e.g., silicon carbide, silicon oxycarbide, or the like), a nitride (e.g., silicon nitride, silicon oxynitride, or the like), or the like.

[0016] The plurality of stacked interlayer dielectric (ILD) layers 204a-204c surround a plurality of interconnects 105-108. In some embodiments, the plurality of interconnects 105-108 include a bottom interconnect 105, a first interconnect 106 over the bottom interconnect 105, and a second interconnect 108 over the first interconnect 106. In some embodiments, the plurality of interconnects 105-108 may include a MOL interconnect, a conductive contact, an interconnect wire, and / or an interconnect via. In some embodiments, the lower ILD layer 204a surrounds the lower interconnect 105, the first ILD layer 204b surrounds the first interconnect 106, and the second ILD layer 204c surrounds the second interconnect 108. In some embodiments, the plurality of interconnects 105-108 are coupled to a transistor device 202 disposed within the substrate 102.In some embodiments, the transistor device 202 may comprise a MOSFET (metal oxide semiconductor field-effect transistor) device, a BJT (bipolar junction transistor), a JFET (junction gate field-effect transistor), or the like.

[0017] In some embodiments, the first interconnect 106 may include and / or be a first conductive material. In some embodiments, the first conductive material may be a material that has a low diffusivity into the surrounding first ILD layer 204b (e.g., a diffusivity into the surrounding first ILD layer 204b that is less than the diffusivity of copper). In some such embodiments, the first conductive material is not separated from the ILD structure 104 by a barrier layer, such that the first interconnect 106 directly contacts the first ILD layer 204b. In some such embodiments, the first conductive material may include tungsten, ruthenium, cobalt, or the like. In other embodiments (not shown), the first conductive material may be separated from the ILD structure 104 by a barrier layer.

[0018] The second interconnect 108 is separated from the second ILD layer 204c by a barrier layer 110. The barrier layer 110 extends along sidewalls of the second interconnect 108 and has sidewalls that lie directly below the second interconnect 108. The sidewalls of the barrier layer 110 define an opening that extends through a bottom surface of the barrier layer 110 at a location directly above the first interconnect 106. The second interconnect 108 extends through the opening to directly contact a top surface of the first interconnect 106. In some embodiments, the second interconnect 108 extends continuously between the sidewalls of the barrier layer 110 such that the second interconnect completely fills the opening.In some embodiments, the sidewalls of the barrier layer 110 defining the opening may be separated by a distance substantially equal to a width of a top surface of the first interconnect 106. In some such embodiments, a bottom corner of the barrier layer 110 may be aligned with a top corner of the first interconnect 106 along an imaginary line perpendicular to a top surface of the substrate 102.

[0019] Fig. 2B shows some embodiments of a top view 216 of the integrated chip 200. As in the top view 216 of Fig. 2B (along the section line AA' of Fig. 2A), the barrier layer 110 extends in a closed loop around the second interconnect 108. In some embodiments, the barrier layer 110 has a ring shape that extends around the second interconnect 108.

[0020] In some embodiments, the barrier layer 110 includes a vertically extending segment 110v disposed along the sidewalls of the second ILD layer 204c and a horizontally extending segment 110h projecting outward from a sidewall of the vertically extending segment 110v toward the second interconnect 108. In some embodiments, the vertically extending segment 110v may extend at an angle greater than 90° with respect to a top surface of the horizontally extending segment 110h. In various embodiments, the barrier layer 110 may include tantalum, tantalum nitride, titanium, titanium nitride, or the like.

[0021] In some embodiments, the second interconnect 108 includes a first liner 208 surrounding a conductive interior 212. The first liner 208 is disposed on the barrier layer 110 and extends vertically through the barrier layer 110 to contact the top surface of the first interconnect 106. In some embodiments, the first liner 208 has a bottom surface resting on the barrier layer 110 and a protrusion extending outward from the bottom surface and through the barrier layer 110. In some embodiments, the first liner 208 completely fills the opening extending through the barrier layer 110 such that a lowermost surface of the conductive interior 212 is above the top surface of the horizontally extending segment 110h of the barrier layer 110.In some embodiments, the first liner 208 may comprise a material having a lower resistivity than the barrier layer 110. In some embodiments, the first liner 208 may include or be the same material as the first interconnect 106. For example, in some embodiments, the first liner 208 may include ruthenium, cobalt, tungsten, or the like. In some such embodiments, a seam 301 may be present between the first interconnect 106 and the first liner 208. In other embodiments, the first liner 208 may include or be a different material than the first interconnect 106. In some embodiments, the conductive interior 212 may include copper, aluminum, or the like.

[0022] In some embodiments, a second liner 210 may be disposed between the first liner 208 and the conductive interior 212. The second liner 210 laterally and vertically separates the first liner 208 from the conductive interior 212. In some embodiments, the second liner 210 may include and / or be cobalt, ruthenium, tungsten, or the like. In some embodiments, the barrier layer 110, the first liner 208, the second liner 210, and the conductive interior 212 extend vertically to a top surface of the second ILD layer 204c. In some embodiments, the second liner 210 may include or be a different material than the first liner 208.

[0023] A cap layer 214 is disposed on the second interconnect 108. In some embodiments, the thick layer 214 extends from directly above the conductive interior 212 to directly above the first liner 208 and / or the second liner 210. In some embodiments, the barrier layer 110 is located laterally outside the cap layer 214. The cap layer 214 may contain and / or be cobalt, ruthenium, tungsten, or the like. In some embodiments, the second liner 210 and the cap layer 214 may contain and / or be the same material. In other embodiments, the second liner 210 and the cap layer 214 may contain and / or be different materials. In some embodiments, the cap layer 214 may have a sidewall that extends at an angle θ relative to a bottom surface of the cap layer 214, as measured through the cap layer 214.In some embodiments, the angle θ may be greater than or equal to approximately 90°. In some embodiments, the angle θ may be greater than 90°.

[0024] Fig. 3 shows a cross-sectional view of some alternative embodiments of an integrated chip 300 having interconnects that meet at a junction-free interface.

[0025] The integrated chip 300 includes an ILD structure 104 disposed over a substrate 102. The ILD structure 104 surrounds a lower interconnect 105 disposed within a lower ILD layer 204a, a first interconnect 106 disposed within a first ILD layer 204b, and a second interconnect 108 disposed within a second ILD layer 204c.

[0026] The second interconnect 108 is separated from the second ILD layer 204c by a barrier layer 110 disposed along opposite sides of the second interconnect 108. The barrier layer 110 has one or more sidewalls disposed directly beneath the second interconnect 108. In some embodiments, the one or more sidewalls may include a sidewall extending at an angle Φ relative to a top surface of the first ILD layer 204b, as measured through the barrier layer 110. In some embodiments, the angle Φ may be greater than or equal to approximately 90°. In some embodiments, the angle Φ may be greater than 90°.

[0027] The second interconnect 108 extends through the barrier layer 110 to contact a top surface of the first interconnect 106. In some embodiments, the second interconnect 108 includes a conductive interior 212 surrounded by a first liner 208. The first liner 208 separates the conductive interior 212 from the barrier layer 110. In some embodiments, the first liner 208 may include a horizontally extending segment extending between inner sidewalls of the first liner 208. The horizontally extending segment includes a first top surface 304 located directly above the barrier layer 110. In some embodiments, the horizontally extending segment may further include a depressed region 302 laterally separated from an inner sidewall of the first liner 208 by the first top surface 304.The recessed region 302 is located directly above the first interconnect 106. In some embodiments, the recessed region 302 is defined by a second top surface 306 that is recessed below the first top surface 304. In some embodiments, the first top surface 304 is separated from the first ILD layer 204b by a first distance 308, and the second top surface 306 is separated from the first interconnect 106 by a second distance 310 that is smaller than the first distance 308. In some embodiments, the second top surface 306 may have a curved surface. In some embodiments, the conductive interior 212 is conformal to the first liner 208 such that the conductive interior 212 is closer to the first interconnect 106 along a center of a bottom surface of the conductive interior 212 than along the lower outer edges of the conductive interior 212.

[0028] Fig. 4A shows a cross-sectional view of some alternative embodiments of an integrated chip 400 having interconnects that meet at a junction-free interface.

[0029] The integrated chip 400 includes a bottom interconnect 105 disposed over a substrate 102. In some embodiments, the bottom interconnect 105 may have a bottom surface in contact with a top surface of the substrate 102. In other embodiments, the bottom interconnect 105 may be separated from the top surface of the substrate 102 by one or more additional interconnect layers. The bottom interconnect 105 includes a bottom barrier layer 402 surrounding a conductive core 404. The bottom barrier layer 402 extends continuously along sidewalls and a bottom surface of the conductive core 404. The bottom barrier layer 402 laterally separates the conductive core 404 from a surrounding bottom ILD layer 204a. In some embodiments, the bottom barrier layer 402 may include titanium, tantalum, titanium nitride, tantalum nitride, or the like.In some embodiments, the conductive core 404 may include ruthenium, tungsten, cobalt, or the like. In some embodiments, the lower ILD layer 204a may include silicon nitride, silicon dioxide, or the like.

[0030] A first ILD layer 204b is vertically separated from the lower ILD layer 204a by a first etch stop layer 206a. The first ILD layer 204b laterally surrounds a first interconnect 106 disposed above the lower interconnect 105. In some embodiments, the first interconnect 106 may laterally contact sidewalls of the first etch stop layer 206a and the first ILD layer 204b. In some embodiments, the first interconnect 106 may include the same material (e.g., ruthenium, tungsten, cobalt, or the like) as the conductive core 404. In some embodiments, the first interconnect 106 may include a single material that extends continuously between outermost sidewalls of the first interconnect 106.

[0031] A second interconnect 108 is disposed over the first interconnect 106. The second interconnect 108 is laterally surrounded by a second ILD layer 204c. In some embodiments, the second ILD layer 204c is separated from the first ILD layer 204b by a second etch stop layer 206b. The second interconnect 108 includes a first liner 208, a second liner 210 surrounded by the first liner 208, and a conductive interior 212 surrounded by the second liner 210. In some embodiments, the first liner 208 may include the same material as the first interconnect 106 and the conductive core 404. In some such embodiments, the same material extends continuously from a top surface of the second interconnect 108 to a bottom surface of the conductive core 404.

[0032] Fig. 4B shows a cross-sectional view of some alternative embodiments of an integrated chip 406 having interconnects that meet at a junction-free interface.

[0033] The integrated chip 406 includes a bottom interconnect 105 disposed over a substrate 102. In some embodiments, the bottom interconnect 105 may have a bottom surface in contact with a top surface of the substrate 102. In other embodiments, the bottom interconnect 105 may be separated from the top surface of the substrate 102 by one or more additional interconnect layers. In some embodiments, the bottom interconnect 105 may laterally contact sidewalls of a bottom ILD layer 204a. In some embodiments, the bottom interconnect 105 may include a single material extending continuously between outermost sidewalls of the bottom interconnect 105. In some embodiments, the single material may include ruthenium, tungsten, cobalt, or the like.

[0034] A first ILD layer 204b is vertically separated from the lower ILD layer 204a by a first etch stop layer 206a. The first ILD layer 204b laterally surrounds a first interconnect 106 disposed above the lower interconnect 105. In some embodiments, the first interconnect 106 may laterally contact sidewalls of the first etch stop layer 206a and the first ILD layer 204b. In some embodiments, the first interconnect 106 may include the same material (e.g., ruthenium, tungsten, cobalt, or the like) as the lower interconnect 105. In some embodiments, the first interconnect 106 may include a single material that extends continuously between outermost sidewalls of the first interconnect 106.

[0035] A second interconnect 108 is disposed over the first interconnect 106. The second interconnect 108 is laterally separated from a second ILD layer 204c by a barrier layer 110. The second interconnect 108 includes a first liner 208, a second liner 210 surrounded by the first liner 208, and a conductive interior 212 surrounded by the second liner 210. In some embodiments, the first liner 208 may include a different material than the first interconnect 106. For example, in some embodiments, the first liner may include ruthenium, and the first interconnect may include tungsten. In some such embodiments, an interface 408 between the first interconnect 106 and the first liner 208 is substantially aligned with a bottom surface of the barrier layer 110.

[0036] Fig. 5 shows a cross-sectional view of some alternative embodiments of an integrated chip 500 having interconnects that meet at a junction-free interface.

[0037] The integrated chip 500 includes a bottom interconnect 105 disposed within a bottom ILD layer 204a on a substrate 102. In some embodiments, the bottom interconnect 105 contacts a transistor device 202 disposed on and / or within a top surface of the substrate 102. A first interconnect 106 is disposed within a first ILD layer 204b, which is located above the bottom ILD layer 204a. A second interconnect 108 is disposed above the first interconnect 106. The second interconnect 108 is laterally separated from a second ILD layer 204c by a barrier layer 110. The second interconnect 108 extends vertically through a bottom surface of the barrier layer 110 to contact a top surface of the first interconnect 106. A cap layer 214 is disposed along a top surface of the second interconnect 108.

[0038] An upper ILD layer 204d is vertically separated from the second ILD layer 204c by an upper etch stop layer 502. In some embodiments, the upper etch stop layer 502 may comprise a multi-layer etch stop layer. In some embodiments, the upper etch stop layer 502 may comprise a first material 502a, a second material 502b disposed on the first material 502a, and a third material 502c disposed on the second material 502b. In some embodiments, the first material 502a may be the same material as the third material 502c and a different material than the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0039] The upper ILD layer 204d surrounds a top interconnect 504. The top interconnect 504 extends vertically from a top surface of the upper ILD layer 204d to the cap layer 214. In some embodiments, the top interconnect 504 includes a first top liner 508, a second top liner 510 surrounded by the first top liner 508, and an upper conductive interior 512 surrounded by the second top liner 510. In some embodiments, the top interconnect 504 is surrounded by a top barrier layer 506. In some embodiments, the top barrier layer 506 extends continuously along a bottom surface of the top interconnect 504 and from a first sidewall of the top interconnect 504 to an opposite second sidewall of the top interconnect 504.

[0040] Fig. 6-21 show sectional views 600-2100 of some embodiments of a method for forming an integrated chip having interconnects that meet at a junction-free interface. Although Fig. 6-21 in connection with a procedure, it is understood that the Fig. 6-21 are not limited to such a method, but rather can stand alone as structures independent of the method.

[0041] As shown in section view 600 of Fig. 6, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers connected thereto. In some embodiments, a transistor device 202 is formed on and / or within the substrate 102. In some such embodiments, the transistor device 202 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric 202d and a gate electrode 202e. The substrate 102 may then be implanted to form source / drain regions 202 sd1 -202 sd2within the substrate 102 and on opposite sides of the gate electrode 202e.

[0042] In some embodiments, a bottom interconnect 105 may be formed within a bottom ILD layer 204a formed over the substrate 102. In some embodiments, the bottom interconnect 105 may include a MOL interconnect or a conductive contact. In some embodiments, the bottom interconnect 105 may be formed by forming the bottom ILD layer 204a over the substrate 102, selectively etching the bottom ILD layer 204a to form a bottom interconnect opening 602 within the bottom ILD layer 204a, forming a first conductive material (e.g., copper, aluminum, etc.) within the bottom interconnect opening 602, and performing a first planarization process (e.g., a chemical mechanical planarization process) to remove an excess of the first conductive material located over the bottom ILD layer 204a.

[0043] As shown in section view 700 of Fig. 7, a first ILD layer 204b is formed over the bottom ILD layer 204a. A first interconnect 106 is then formed within the first ILD layer 204b and over the bottom interconnect 105. In some embodiments, the first interconnect 106 may be formed by forming the first ILD layer 204b over the bottom ILD layer 204a, selectively etching the first ILD layer 204b to form a first interconnect opening 702 within the first ILD layer 204b, forming a second conductive material (e.g., copper, aluminum, etc.) within the first interconnect opening 702, and performing a second planarization process (e.g., a chemical mechanical planarization process) to remove an excess of the second conductive material located over the first ILD layer 204b.In various embodiments, the second conductive material may include tungsten, ruthenium, cobalt, or the like.

[0044] As shown in section view 800 of Fig. As shown in Figure 8, a second ILD layer 204c is formed over the first ILD layer 204b. In some embodiments, an etch stop layer 206 may be formed over the first ILD layer 204b prior to forming the second ILD layer 204c. In various embodiments, the etch stop layer 206 and / or the second ILD layer 204c may be formed by deposition processes (e.g., ALD processes, CVD processes, PE-CVD processes, or the like).

[0045] A first masking structure 801 is formed over the second ILD layer 204c. In some embodiments, the first masking structure 801 may include a photosensitive material (e.g., a photoresist). In other embodiments, the first masking structure 801 may include a dielectric masking layer 802 and a hard mask 804 over the dielectric masking layer 802. In some embodiments, the dielectric masking layer 802 may include an oxide (e.g., silicon oxide, silicon dioxide, or the like). In some embodiments, the hard mask 804 may include a carbide (e.g., silicon carbide, silicon oxycarbide, or the like), a nitride (e.g., silicon nitride, silicon oxynitride, titanium nitride, or the like), an oxide (e.g., silicon oxide, titanium oxide, or the like), or the like.

[0046] A first etch process is performed to selectively etch the second ILD layer 204c corresponding to the first masking structure 801 and to define an inter-interconnect opening 806. The inter-interconnect opening 806 is defined by sidewalls and a horizontally extending surface of the second ILD layer 204c. In some embodiments, the second ILD layer 204c may be selectively patterned by exposing the second ILD layer 204c to a first etchant 808 in areas exposed by the first masking structure 801. In some embodiments, the first etchant 808 may include a dry etchant (e.g., having a fluorine chemistry, a chlorine chemistry, or the like). In other embodiments, the first etchant 808 may include a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, or the like).

[0047] As shown in section view 900 of Fig. 9, a portion of the first masking structure 801 is removed. In some embodiments, the hard mask (804 of Fig. 8) may be removed, while the dielectric masking layer 802 remains over the second ILD layer 204c. In various embodiments, the hard mask (804 of Fig. 8) by means of an etching process, a planarization process (e.g., a chemical mechanical polishing (CMP) process) or the like.

[0048] As shown in section view 1000 of Fig. 10, the second ILD layer 204c and the etch stop layer 206 are further etched according to a second etch process to form a second interconnect opening 1002. In some embodiments, the second interconnect opening 1002 exposes a top surface of the first interconnect 106. In some embodiments, the second interconnect opening 1002 further exposes a top surface of the first ILD layer 204b. In some embodiments, the second etch process may expose the second ILD layer 204c and the first etch stop layer 206a to a second etchant 1004 corresponding to the dielectric masking layer 802. In some embodiments, the second etch process may comprise a linear removal method (LRM).

[0049] In some alternative embodiments (not shown), the second ILD layer 204c may be etched using a single etch process. In some further embodiments, the second ILD layer 204c and the etch stop layer 206 may be etched using separate etch processes using different etchants. For example, in some embodiments, a first single etch process may etch through the second ILD layer 204c to expose the etch stop layer 206, while a second single etch process may etch through the etch stop layer 206 to expose the top surface of the first interconnect 106.

[0050] As shown in section view 1100 of Fig. As shown in Figure 11, a blocking layer 1102 is formed within the second interconnect opening 1002 and on top of the first interconnect 106. In some embodiments, the blocking layer 1102 is laterally separated from sidewalls of the etch stop layer 206 and / or the second ILD layer 204c. In some further embodiments, the blocking layer 1102 is enclosed over the top of the first interconnect 106 such that the top of the first ILD layer 204b is exposed between sidewalls of the blocking layer 1102 and sidewalls of the second ILD layer 204c.

[0051] In some embodiments, the blocking layer 1102 may comprise a self-assembled monolayer (SAM). In some embodiments, the self-assembled monolayer may include an organic material. For example, the blocking layer 1102 may include a silane (e.g., a chlorosilane, an alkoxysilane, an organosilane, or the like), a thiolate (e.g., an organothiolate), or the like. In some embodiments, the self-assembled monolayer may be formed using a spin-on process. In some embodiments, the blocking layer 1102 may be formed to a thickness in a range between approximately 1 nm (10 angstroms (Å)) and approximately 3 nm (30 Å).In other embodiments, the blocking layer 1102 may be formed to a thickness in a range between about 1.5 nm (15 Å) and about 2.5 nm (25 Å), between about 2 nm (20 Å) and about 3 nm (30 Å), or between other suitable values.

[0052] As shown in section view 1200 of Fig. 12, a barrier layer 1202 is selectively formed within the second interconnect opening 1002. In some embodiments, the blocking layer 1202 is configured to act as a mask that prevents formation of the barrier layer 1202 on top of the first interconnect 106. The barrier layer 1202 covers areas of the first ILD layer 204b, the second ILD layer 204c, and / or the first interconnect 106. The barrier layer 1202 is not formed on areas of the blocking layer 1102, such that the blocking layer 1102 has one or more areas that are exposed after formation of the barrier layer 1202. In some embodiments, the barrier layer 1202 may be formed to a thickness in a range between approximately 1 nm (10 Å) and approximately 2 nm (20 Å).In other embodiments, the barrier layer 1202 may be formed to a thickness in a range between about 1 nm (10 Å) and about 1.5 nm (15 Å), between about 1.5 nm (15 Å) and about 2 nm (20 Å), or between other suitable values.

[0053] In some embodiments, the barrier layer 1202 may be selectively formed using an atomic layer deposition (ALD) process. In such embodiments, the ALD process may be performed by performing multiple ALD cycles. The multiple ALD cycles consist of introducing a first precursor gas into a process chamber containing the substrate 102, purging the process chamber to remove the first precursor gas from the process chamber, introducing a second precursor gas into a process chamber, and then purging the process chamber to remove the second precursor gas from the process chamber. The blocking layer 1102 is inert to the first precursor, such that the first precursor does not adhere to the blocking layer 1102.Rather, the first precursor gas selectively forms on one or more surfaces of the first ILD layer 204b, the second ILD layer 204c, and / or the etch stop layer 206. The second precursor gas interacts with the first precursor gas to form a monolayer of the barrier layer 1202 on the one or more surfaces of the first ILD layer 204b, the second ILD layer 204c, and / or the etch stop layer 206. Since the first precursor gas does not form on the blocking layer 1102, the monolayer is not formed on the blocking layer 1102.

[0054] As shown in section view 1300 of Fig. 13, the blocking layer (1102 of Fig. 12) is removed. By removing the blocking layer (1102 of Fig. 12), the top side of the first interconnect 106 is exposed, leaving an opening 1302 that extends through the barrier layer 1202 to the first interconnect 106. In some embodiments, the blocking layer (1102 of Fig. 12) by removing the blocking layer (1102 of Fig. 12) is exposed to a plasma. For example, in some embodiments, the blocking layer (1102 of Fig. 12) by exposing the blocking layer to a hydrogen-based plasma (e.g., an H2 plasma). In some embodiments, since sidewalls of the barrier layer 1202 are blocked by the blocking layer (1102 of Fig. 12) and are not defined by an etching process, one or more of the sidewalls of the barrier layer 1202 defining the opening 1302 may extend at an obtuse angle with respect to a top surface of the first ILD layer 204b, as measured through the barrier layer 110. In other embodiments, one or more of the sidewalls of the barrier layer 1202 defining the opening 1302 may extend at a right angle or at an acute angle with respect to the top surface of the first ILD layer 204b, as measured through the barrier layer 110. As shown in the cross-sectional view 1400 of Fig. 14, a first liner layer 1402 is formed within the second interconnect opening 1002. The first liner layer 1402 is formed over the barrier layer 1202 and extends through the opening 1302 in the barrier layer 1202 to contact the first interconnect 106. In various embodiments, the first liner layer 1402 may include ruthenium, tungsten, cobalt, or the like. In some embodiments, the first liner layer 1402 may be formed using a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the first liner layer 1402 may be formed to a thickness in a range between about 0.5 nm (5 Å) and about 1.5 nm (15 Å), between about 1 nm (10 Å) and about 1.5 nm (15 Å), or between other suitable values.

[0055] As shown in section view 1500 of Fig. 15, a second liner layer 1502 is formed within the second interconnect opening 1002 and over the first liner layer 1402. In some embodiments, the second liner layer 1502 may include cobalt, tungsten, ruthenium, or the like. In some embodiments, the second liner layer 1502 may include a different material than the first liner layer 1402. In various embodiments, the second liner layer 1502 may be formed using a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, or the like). In some embodiments, the second liner layer 1502 may be formed to a thickness in a range between about 0.5 nm (5 Å) and about 1.5 nm (15 Å)1, between about 1 nm (10 Å) and about 1.5 nm (15 Å), or between other suitable values.

[0056] As shown in section view 1600 of Fig. 16, a third conductive material 1602 is formed within the second interconnect opening 1002 and over the second liner layer 1502. In some embodiments, the third conductive material 1602 may be formed using a deposition process and / or plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the third conductive material 1602 may include copper, aluminum, or the like.

[0057] As shown in the sectional view 1700 of Fig. 17, a planarization process is performed. The planarization process is performed along a line 1702 to form a portion of the third conductive material (1602 of Fig. 16) and define a second interconnect 108. In some embodiments, the planarization process also removes portions of the barrier layer (1202 of Fig. 16), the first lining layer (1402 by Fig. 16) and the second lining layer (1502 of Fig. 16). The second interconnect 108 includes a first liner 208 in contact with the first interconnect 106, a second liner 210 surrounded by the first liner 208, and a conductive interior 212 surrounded by the second liner 210. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the planarization process causes the top surfaces of the barrier layer 110, the first liner 208, the second liner 210, and the conductive interior 212 to be substantially coplanar (e.g., coplanar within a tolerance of a CMP process) with a top surface of the second ILD layer 204c.

[0058] As shown in the sectional view 1800 of Fig. 18, a cap layer 214 is formed over the second interconnect 108. In some embodiments, the cap layer 214 may be formed by multiple deposition cycles, each forming a sublayer of the cap layer 214. In some embodiments, the multiple deposition cycles may each be performed by depositing a metal over the second interconnect 108 followed by a plasma treatment. In some embodiments, the metal may include cobalt, ruthenium, tungsten, or the like. In some embodiments, the plasma treatment may be performed by exposing the deposited metal to a plasma containing nitrogen, hydrogen, or the like. In some embodiments, the plasma may include an ammonia (NH3)-based plasma.In some embodiments, the cap layer 214 may be formed to a thickness in a range between about 2 nm (20 Å) and about 3 nm (30 Å), between about 2 nm (20 Å) and about 2.5 nm (25 Å), or between other suitable values.

[0059] In some embodiments, the cover layer 214 may be formed to be completely enclosed over the second liner 210 and the conductive interior 212. In some such embodiments, the cover layer 214 may have a maximum width substantially equal to a maximum width of the second liner 218. In other embodiments, the cover layer 214 may be formed to be completely enclosed over the first liner 208, the second liner 210, and the conductive interior 212. In some such embodiments, the cover layer 214 may have a maximum width substantially equal to a maximum width of the first liner 208. In still other embodiments, the cover layer 214 may be formed to extend continuously past opposite outermost edges of the first liner 208.

[0060] As shown in the sectional view from 1900 by Fig. 19, an upper ILD layer 204d is formed over the second ILD layer 204c. In various embodiments, the upper ILD layer 204d may be formed using a deposition process (e.g., an ALD process, a CVD process, a PE-CVD process, or the like). In some embodiments, prior to forming the upper ILD layer 204d, an upper etch stop layer 502 may be formed on the second ILD layer 204c. In some embodiments, the upper etch stop layer 502 may include a multi-layer etch stop layer including a first material 502a, a second material 502b over the first material 502a, and a third material 502c over the second material 502b. In some embodiments, the first material 502a, the second material 502b, and the third material 502c may include an oxide, a nitride, and / or a carbide.

[0061] As shown in the sectional view 2000 of Fig. 20, the upper ILD layer 204d is patterned to define an upper interconnect opening 2002. In some embodiments, the upper ILD layer 204d may be patterned by selectively exposing the upper ILD layer 204d to a third etchant 2004 according to a second masking pattern 2006. In some embodiments, the second masking pattern 2006 may include a photoresist layer, a hard mask layer, or the like. In various embodiments, the third etchant 2004 may include a dry etchant (e.g., having a chlorine etch chemistry, a fluorine etch chemistry, or the like) or a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, or the like).

[0062] As shown in section view 2100 of Fig. 21, a top interconnect 504 is formed within the top interconnect opening 2002. The top interconnect 504 may be formed to be separated from the top ILD layer 204d by a top barrier layer 506. In some embodiments, the top barrier layer 506 is formed by depositing a top barrier layer within the top interconnect opening 2002. The top interconnect 504 is then formed by forming a first top liner layer on the top barrier layer and within the top interconnect opening 2002, by forming a second top liner layer on the first top liner layer and within the top interconnect opening 2002, and by forming a top conductive material on the second top liner layer and within the top interconnect opening 2002.After forming the upper conductive material, a planarization process (e.g., a CMP process) may be performed to remove any excess of the upper conductive material, the first upper liner, the second upper liner, and / or the upper barrier layer located above the upper ILD layer 204d. The planarization process defines the upper interconnect 504 to include a first upper liner 508 over the upper barrier layer 506, a second upper liner 510 over the first upper liner 508, and an upper conductive interior 512 over the second upper liner 510.

[0063] The upper barrier layer, the first upper liner layer, the second upper liner layer, and the upper conductive material are formed using deposition processes (e.g., CVD, PVD, PE-CVD, or the like). In various embodiments, the upper barrier layer may include tantalum, titanium, tantalum nitride, titanium nitride, or the like. In various embodiments, the first upper liner layer may include tungsten, ruthenium, cobalt, or the like. In some embodiments, the second upper liner layer may include a different material than the first upper liner layer. In various embodiments, the second upper liner layer may include tungsten, ruthenium, cobalt, or the like. In various embodiments, the upper conductive material may include copper, aluminum, or the like.

[0064] Fig. 22 shows a flowchart of some embodiments of a method 2200 for forming an integrated chip having interconnects that meet at a junction-free interface.

[0065] Although the disclosed method 2200 is described herein as a series of steps or events, it should be understood that the illustrated order of these steps or events is not to be interpreted in a limiting sense. For example, these steps may be performed in different orders and / or concurrently with other steps or events than those illustrated and / or described herein. Furthermore, not all illustrated steps may be required to implement one or more aspects or embodiments of the description provided herein. Further, one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0066] In step 2202, a first interconnect is formed within a first inter-level dielectric layer (ILD layer) over a substrate. Fig. 6-7 show sectional views 600-700 of some embodiments corresponding to step 2202.

[0067] In step 2204, a second ILD layer is formed over the first ILD layer. Fig. 8 shows a sectional view 800 of some embodiments corresponding to step 2204.

[0068] In step 2206, the second ILD layer is etched to form inner surfaces that define an interconnect opening exposing a top surface of the first interconnect. Fig. 8-10 show sectional views 800-1000 of some embodiments corresponding to step 2206.

[0069] In step 2208, a blocking layer is formed on top of the first interconnect. In some embodiments, the blocking layer may comprise a self-assembled monolayer (SAM). Fig. 11 shows a sectional view 1100 of some embodiments corresponding to step 2208.

[0070] In step 2210, a barrier layer is selectively formed within the interconnect opening. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 2210.

[0071] In step 2212, the blocking layer is removed to expose the top surface of the first interconnect. Fig. 13 shows a sectional view 1300 of some embodiments corresponding to step 2212.

[0072] In step 2214, a second interconnect is formed on the barrier layer and on top of the first interconnect. In some embodiments, the second interconnect may be formed according to steps 2216-2222.

[0073] In step 2216, a first liner is formed on the barrier layer and the top surface of the first interconnect. Fig. 14 shows a sectional view 1400 of some embodiments corresponding to step 2216.

[0074] In step 2218, a second liner is formed on the first liner. Fig. 15 shows a sectional view 1500 of some embodiments corresponding to step 2218.

[0075] In step 2220, a conductive material is formed on the second liner. Fig. 16 shows a sectional view 1600 of some embodiments corresponding to step 2220.

[0076] In step 2222, a planarization process is performed to remove excess conductive material over the second ILD layer and define a second interconnect. Fig. 17 shows a sectional view 1700 of some embodiments corresponding to step 2222.

[0077] In step 2224, a cap layer is formed on the second interconnect. Fig. 18 shows a sectional view 1800 of some embodiments corresponding to step 2224.

[0078] In step 2226, an upper interconnect is formed within an upper ILD layer above the second ILD layer. Fig. 19-21 show sectional views 1900-2100 of some embodiments corresponding to step 2226.

[0079] Accordingly, in some embodiments, the present disclosure relates to an integrated chip having an interconnect structure that does not include a barrier layer vertically separating an interconnect from an underlying interconnect.

[0080] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first interconnect disposed within an interlayer dielectric (ILD) structure over a substrate; a barrier layer disposed along sidewalls of the ILD structure and having sidewalls defining an opening over the first interconnect; and a second interconnect disposed on the barrier layer, the second interconnect extending through the opening in the barrier layer and up to the first interconnect. In some embodiments, the barrier layer is disposed on a top surface of the ILD structure, the top surface being laterally located between the sidewalls of the ILD structure and the first interconnect.In some embodiments, the second interconnect includes a first liner disposed on the barrier layer and surrounding a conductive interior. In some embodiments, the first interconnect and the first liner include the same material; and the conductive interior and the first liner include different materials. In some embodiments, the integrated chip further includes a second liner disposed on the first liner and surrounding the conductive interior. In some embodiments, the integrated chip further includes a cap layer disposed on the conductive interior and the second liner, the cap layer and the second liner including the same material. In some embodiments, the barrier layer is laterally outward from the cap layer.In some embodiments, the first liner has a bottom surface resting on the barrier layer and a protrusion extending outwardly from the bottom surface and through the barrier layer.

[0081] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first interconnect disposed within a first interlayer dielectric (ILD) layer over a substrate; a second ILD layer disposed over the first ILD layer; a barrier layer extending along a sidewall of the second ILD layer and along a top surface of the first ILD layer; and a first liner disposed on the barrier layer and surrounding a conductive interior, the first liner extending through the barrier layer and to the first interconnect. In some embodiments, the barrier layer includes a vertically extending segment disposed along the sidewall of the second ILD layer and a horizontally extending segment projecting outwardly from the vertically extending segment toward the first interconnect.In some embodiments, the first liner has a lower resistivity than the barrier layer. In some embodiments, the first interconnect and the first liner include the same material, extending continuously from a bottom surface of the first interconnect to a top surface of the second ILD layer. In some embodiments, the barrier layer has sidewalls separated by a distance substantially equal to a width of a top surface of the first interconnect. In some embodiments, the conductive interior is closer to the first interconnect along a center of a bottom surface of the conductive interior than along lower outer edges of the conductive interior.In some embodiments, the conductive interior has a bottom surface directly above the barrier layer and a protrusion extending outwardly from the bottom surface, the protrusion being located directly above the first interconnect. In some embodiments, a bottom surface of the barrier layer, viewed in a top view of the barrier layer, defines a closed loop surrounding the first liner.

[0082] In other embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate; forming a second ILD layer over the first ILD layer; patterning the second ILD layer to form sidewalls defining an interconnect opening exposing a top surface of the first interconnect; forming a blocking layer on top of the first interconnect, the blocking layer being laterally separated from the sidewalls of the second ILD layer; forming a barrier layer within the interconnect opening; removing the blocking layer to expose the top surface of the first interconnect; and forming a second interconnect within the interconnect opening.In some embodiments, the blocking layer is removed after forming the barrier layer within the interconnect opening. In some embodiments, the blocking layer comprises a self-assembled monolayer. In some embodiments, the method further comprises forming a first liner on the barrier layer and in direct contact with the top surface of the first interconnect; forming a conductive material on the first liner; and performing a planarization process to remove a portion of the conductive material located above the second ILD layer.

Claims

[1] Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100), which has: a first interconnect (106) disposed within a dielectric Interlayer structure, ILD structure (104), arranged over a substrate (102), wherein the first interconnect (106) is in contact with a sidewall of the ILD structure (104); a barrier layer (110), wherein an upper portion of the barrier layer (110) is disposed along sidewalls of the ILD structure (104), the upper portion of the barrier layer (110) having an inner sidewall, and a lower portion of the barrier layer (110) defining an opening above the first interconnect (106), the opening in the barrier layer (110) being aligned with a sidewall of the first interconnect (106) and / or with the sidewall of the ILD structure (104); and a second interconnect (108) disposed on the barrier layer (110), the second interconnect (108) extending through the opening in the barrier layer (110) and to the first interconnect (106); wherein a lowermost portion of the barrier layer (110) extends laterally from the inner sidewall of the upper portion of the barrier layer (110) toward the opening in the barrier layer (110). [2] The integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of claim 1, wherein the barrier layer (110) is disposed on a top surface of a first dielectric interlayer (204b) of the ILD structure (104), the top surface being laterally located between the sidewalls of the ILD structure (104) and the first interconnect (106). [3] The integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of claim 1 or 2, wherein the second interconnect (108) comprises a first liner (208) disposed on the barrier layer (110) and surrounding a conductive interior (212). [4] Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) according to claim 3, wherein the first interconnect (106) and the first liner (208) contain the same material; and wherein the conductive interior (212) and the first liner (208) contain different materials. [5] Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) according to claim 3 or 4, further comprising: a second liner (210) disposed on the first liner (208) and surrounding the conductive interior (212). [6] Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) according to claim 5, further comprising: a cover layer (214) disposed on the conductive interior (212) and the second liner (210), wherein the cover layer (214) and the second liner (210) contain the same material. [7] Integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) according to claim 6, wherein the barrier layer (110) is located laterally outside the cover layer (214). [8] The integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of any one of claims 3 to 7, wherein the first liner (208) has a bottom surface resting on the barrier layer (110) and a protrusion extending outwardly from the bottom surface and through the barrier layer (110). [9] Integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100), which has: a first interconnect (106) disposed within a first dielectric interlayer, ILD layer (204b), over a substrate (102); a second ILD layer (204c) disposed over the first ILD layer (204b); a barrier layer (110) extending along a sidewall of the second ILD layer (204c) and along a top surface of the first ILD layer (204b) and comprising: a vertically extending segment (110v) arranged along the sidewall of the second ILD layer (204c); and a horizontally extending segment (110h) extending from the vertically extending segment (110v) of the barrier layer (110) toward the first interconnect (106) and defining an opening above the first interconnect (106); and a first liner (208) disposed on the barrier layer (110) and surrounding a conductive interior (212), wherein the first liner (208) extends through the barrier layer (110) and to the first interconnect (106), and wherein the opening is aligned with a sidewall of the first interconnect (106) and / or with a sidewall of the first dielectric interlayer. [10] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of claim 9, wherein the first liner (208) has a lower resistivity than the barrier layer (110). [11] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of claim 9 or 10, wherein the first interconnect (106) and the first liner (208) comprise the same material extending continuously from a bottom surface of the first interconnect (106) to a top surface of the second ILD layer (204c). [12] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of any one of claims 9 to 11, wherein the barrier layer (110) has sidewalls separated by a distance substantially equal to a width of a top surface of the first interconnect (106). [13] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of any one of claims 9 to 12, wherein the conductive interior (212) is closer to the first interconnect (106) along a center of a bottom surface of the conductive interior (212) than along lower outer edges of the conductive interior (212). [14] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of any one of claims 9 to 13, wherein the conductive interior (212) has a bottom surface directly above the barrier layer (110) and a protrusion extending outwardly from the bottom surface, the protrusion being located directly above the first interconnect (106). [15] The integrated chip (200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100) of any one of claims 9 to 14, wherein a bottom surface of the barrier layer (110), viewed in a top view of the barrier layer (110), defines a closed loop surrounding the first liner (208). [16] A method of forming an integrated chip (100, 200, 300, 400, 406, 500, 1600, 1700, 1800, 1900, 2000, 2100), comprising: Forming a first interconnect (106) within a first dielectric interlayer, ILD layer (204b), over a substrate (102); Forming a second ILD layer (204c) over the first ILD layer (204b); Patterning the second ILD layer (204c) to form sidewalls defining an interconnect opening (1002) exposing a top surface of the first interconnect (106); Forming a blocking layer (1102) on top of the first interconnect (106), the blocking layer (1102) being laterally separated from the sidewalls of the second ILD layer (204c); Forming a barrier layer (110) within the interconnect opening (1002); Removing the blocking layer (1102) to expose the top surface of the first interconnect (106); and Forming a second interconnect (108) within the interconnect opening (1002); wherein the blocking layer (1102) is removed after forming the barrier layer (110) within the interconnect opening (1002). [17] The method of claim 16, wherein the blocking layer (1102) comprises a self-assembled monolayer. [18] A method according to any one of claims 16 or 17, further comprising: Forming a first liner (208) on the barrier layer (110) and in direct contact with the top of the first interconnect (106); forming a conductive material on the first liner (208); and Performing a planarization process to remove a portion of the conductive material located above the second ILD layer (204c).

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