Voltage tracing circuit and method for its operation

Abstract

Voltage tracing circuit, featuring: a first transistor (M1) in a first well (NW4, 320a), wherein the first transistor (M1) has a first gate terminal, a first drain terminal and a first source terminal, wherein the first source terminal is coupled to a first voltage supply (VDD), the first gate terminal is coupled to a pad voltage terminal (PAD) and is configured to receive a pad voltage; a second transistor (M3) having a second gate terminal, a second drain terminal and a second source terminal, wherein the second source terminal is coupled to the first drain terminal, and the second gate terminal is coupled to the first gate terminal and the pad voltage terminal (PAD); a third transistor (M4) having a third gate terminal, a third drain terminal and a third source terminal, wherein the third gate terminal is coupled to the first voltage supply (VDD); and a fourth transistor (M2) having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, wherein the fourth drain terminal is coupled to the third source terminal, the fourth gate terminal is coupled to the third gate terminal and the first voltage supply (VDD) and the fourth source terminal is coupled to the pad voltage terminal (PAD), wherein at least the third transistor (M4) is located in a second well (NW2, 320b, 420a, 520b, 620a) which is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) is separated from the first well (NW4, 320a) in a first direction, wherein the first transistor (M1) and the second transistor (M3) are located in wells separated from each other in the first direction.

Description

BACKGROUND

[0001] The recent trend in the miniaturization of integrated circuits (ICs) has led to smaller devices that consume less power yet deliver superior performance at higher speeds than before. The miniaturization process has also increased the devices' susceptibility to electrostatic discharge (ESD) events due to several factors, such as thinner dielectric thicknesses and associated lowered dielectric breakdown voltages. ESD is one of the causes of electronic circuit damage and also a consideration in advanced semiconductor technology.

[0002] The prior art relating to the subject matter of the invention can be found, for example, in US 2013 / 0 155 557 A1.

[0003] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1A is a schematic diagram of an integrated circuit according to some embodiments. Fig. 1B is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 2A is a schematic diagram of an integrated circuit according to some embodiments. Fig. 2B is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 3A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 3B is a circuit diagram of an equivalent circuit of the integrated circuit according to some embodiments. Fig. 3C is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 4A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 4B is a circuit diagram of an equivalent circuit of the integrated circuit according to some embodiments. Fig. 4C is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 5A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 5B is a circuit diagram of an equivalent circuit of the integrated circuit according to some embodiments. Fig. 5C is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 6A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 6B is a circuit diagram of an equivalent circuit of the integrated circuit according to some embodiments. Fig. 6C is a cross-sectional view of an integrated circuit according to some embodiments. Fig. 7A is a circuit diagram of an integrated circuit according to some embodiments. Fig. 7B is a circuit diagram of an integrated circuit according to some embodiments. Fig. 7C is a circuit diagram of an integrated circuit according to some embodiments. Fig. 7D is a circuit diagram of an integrated circuit according to some embodiments. Fig. 8 is a circuit diagram of a control logic circuit according to some embodiments. Fig. 9 is a flow diagram of a method of operating such a circuit, such as the integrated circuit of Fig. 1A to 1B, 2A to 2B, 3A to 3C, 4A to 4C, 5A to 5C, 6A to 6C, 7A to 7D or 8 according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides various embodiments or examples for implementing functions of the presented content. Specific examples of components, materials, values, steps, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples and are limiting. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, in the following description, forming a first element or a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which other elements may be formed between the first and second elements such that the first and second elements need not be in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations explained.

[0006] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] According to some embodiments, a voltage tracking circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. In some embodiments, the first transistor and the second transistor are coupled together in one stacked structure, and the third transistor and the fourth transistor are coupled together in another stacked structure.

[0008] In some embodiments, all of the first gate terminal of the first transistor, a third gate terminal of the third transistor, and a pad voltage terminal are coupled together and configured to receive a pad voltage. In some embodiments, all of a second gate terminal of the second transistor, a fourth gate terminal of the fourth transistor, and a first voltage supply are coupled together and configured to receive a supply voltage.

[0009] In some embodiments, the first transistor is located in a first well, and at least the third transistor is located in a second well that is different from the first well. In some embodiments, the second well is separated from the first well in a first direction.

[0010] In some embodiments, by positioning at least the first transistor and the third transistor in respective separate wells, the voltage tracking circuit has better ESD immunity and occupies a smaller area than other approaches. INTEGRATED CIRCUIT

[0011] Fig. 1A is a schematic diagram of an integrated circuit 100A according to some embodiments.

[0012] Integrated circuit 100A includes P-type metal-oxide-semiconductor (PMOS) transistors M1, M2, M3, and M4 coupled to a voltage supply VDD and a pad terminal PAD. In some embodiments, integrated circuit 100A corresponds to a pad voltage tracking circuit configured to track a voltage from pad terminal PAD. In some embodiments, pad terminal PAD corresponds to an input / output pad (IO pad), a voltage supply pad (e.g., VDD), a reference voltage supply (e.g., VSS), or the like.

[0013] Each PMOS transistor M1, M2, M3, and M4 is positioned in a corresponding well NW4, NW1, NW3, and NW2. For example, PMOS transistor M1 is positioned in well NW4, PMOS transistor M2 is positioned in well NW1, PMOS transistor M3 is positioned in well NW3, and PMOS transistor M4 is positioned in well NW2. At least one of wells NW4, NW1, NW3, or NW2 includes an n-type dopant impurity and is referred to as an N-well. In some embodiments, at least one of wells NW4, NW1, NW3, or NW2 includes a p-type dopant impurity and is referred to as a P-well.

[0014] PMOS transistor M1 is located in well NW4. PMOS transistor M1 includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M1 is coupled to at least the first voltage supply VDD. The gate terminal of PMOS transistor M1 is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labeled). The body terminal of PMOS transistor M1 is coupled to well NW4.

[0015] PMOS transistor M2 is located in well NW1. PMOS transistor M2 includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M2 is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labeled). The gate terminal of PMOS transistor M2 is coupled to at least the power supply VDD and is configured to receive the power supply voltage (not labeled). The body terminal of PMOS transistor M2 is coupled to well NW1.

[0016] PMOS transistor M3 is located in well NW4. PMOS transistor M1 includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M3 is coupled to the drain terminal of PMOS transistor M1. Each of the gate terminal of PMOS transistor M3, the gate terminal of PMOS transistor M1, and the source terminal of PMOS transistor M2 are coupled together and are also coupled to the pad terminal PAD. The gate terminal of PMOS transistor M3 and the gate terminal of PMOS transistor M1 are configured to receive the pad voltage (not labeled) from the pad terminal PAD. The body terminal of PMOS transistor M3 is coupled to well NW3.

[0017] PMOS transistor M4 is located in well NW2. PMOS transistor M4 includes a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M4 is coupled to the drain terminal of PMOS transistor M2. The drain terminal of PMOS transistor M4 and the drain terminal of PMOS transistor M3 are coupled together and electrically floating. Each of the gate terminal of PMOS transistor M2, the gate terminal of PMOS transistor M4, and the source terminal of PMOS transistor M1 are coupled together and are also coupled to the voltage supply VDD. The gate terminal of PMOS transistor M4 and the gate terminal of PMOS transistor M2 are configured to receive the pad voltage (not labeled) from the voltage supply VDD. The body terminal of PMOS transistor M4 is coupled to well NW2.

[0018] Other transistor types or other transistor numbers in at least the integrated circuit 100A to 100B ( Fig. 1B), 200A to 200B ( Fig. 2A to 2B), 300A to 300C ( Fig. 3A to 3C), 400A to 400C ( Fig. 4A to 4C), 500A to 500C ( Fig. 5A to 5C), 600A to 600C ( Fig. 6A to 6C) or 700A to 700D ( Fig. 7A to 7D) are within the scope of this disclosure.

[0019] In some embodiments, by positioning PMOS transistors M1, M2, M3, and M4 in respective separate wells NW4, NW1, NW3, and NW2, the integrated circuit 100A to 100B has better ESD immunity and occupies a smaller area than other approaches.

[0020] Fig. Figure 1B is a cross-sectional view of an integrated circuit 100B according to some embodiments. Integrated circuit 100B is one embodiment of integrated circuit 100A.

[0021] Components that are the same or similar to those in one or more of Fig. 1A to 1B and 2A to 8 (shown below) are given the same reference numerals, and their detailed description is therefore omitted.

[0022] The integrated circuit 100B includes a substrate 102. In some embodiments, the substrate 102 is a p-type substrate. In some embodiments, the substrate 102 is an n-type substrate. In some embodiments, the substrate 102 includes an elemental semiconductor comprising silicon or germanium in crystal, polycrystalline, or an amorphous structure; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; another suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate comprises a graded SiGe element in which the Si and Ge composition changes from one ratio at one location to a different ratio at another location of the graded SiGe element.In some embodiments, the SiGe alloy is formed over a silicon substrate. In some embodiments, the first substrate 102 is a strained SiGe substrate. In some embodiments, the semiconductor substrate comprises a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epi layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.

[0023] Integrated circuit 100B further includes wells NW1, NW2, NW3, and NW4 in substrate 102. In some embodiments, at least one of wells NW1, NW2, NW3, or NW4 includes a dopant impurity type opposite to the substrate type. In some embodiments, at least one of wells NW1, NW2, NW3, or NW4 includes an n-type dopant impurity, and the substrate is a p-type substrate. In some embodiments, at least one of wells NW1, NW2, NW3, or NW4 includes a p-type dopant impurity, and the substrate is an n-type substrate.

[0024] At least one of wells NW1, NW2, NW3, or NW4 extends in a first direction X. Each of wells NW1, NW2, NW3, or NW4 is separated from another of wells NW1, NW2, NW3, or NW4 in the first direction X. In some embodiments, at least one of wells NW4, NW3, NW2, or NW1 is referred to as a body of the corresponding PMOS transistor M1, M3, M4, or M2.

[0025] The integrated circuit 100B further includes regions 104a, 104b, 104c, and 104d. Region 104a, 104b, 104c, or 104d is located within the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, at least region 104a, 104b, 104c, or 104d includes an n-type dopant impurity. In some embodiments, at least region 104a, 104b, 104c, or 104d includes a p-type dopant impurity. In some embodiments, region 104a, 104b, 104c, or 104d is connected to a corresponding body terminal of the corresponding PMOS transistor M1, M3, M4, or M2.

[0026] Integrated circuit 100B further includes gates 106a, 106b, 106c, and 106d. Gate 106a, 106b, 106c, or 106d is located over the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, gate 106a, 106b, 106c, or 106d is a corresponding gate of the corresponding PMOS transistor M1, M3, M4, or M2. For ease of illustration, gates 106a and 106b are not shown as coupled to each other or to other elements, and gates 106c and 106d are not shown as coupled to each other or to other elements.

[0027] The integrated circuit 100B further comprises implant regions 108a, 108b, 108c, and 108d. Implant region 108a, 108b, 108c, or 108d is located within the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, at least the implant region 108a, 108b, 108c, or 108d comprises a dopant impurity type opposite to the dopant impurity type in the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, at least the implant region 108a, 108b, 108c, or 108d comprises a p-type dopant impurity. In some embodiments, at least one of implantation regions 108a, 108b, 108c, or 108d includes an n-type dopant impurity. In some embodiments, implantation region 108a or 108b is the corresponding source terminal of the corresponding PMOS transistor M1 or M3.In some embodiments, the implant region 108c or 108d is the corresponding drain terminal of the corresponding PMOS transistor M4 or M2.

[0028] The integrated circuit 100B further comprises implant regions 110a, 110b, 110c, and 110d. Implant region 110a, 110b, 110c, or 110d is located within the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, at least the implant region 110a, 110b, 110c, or 110d comprises a dopant impurity type that is opposite to the dopant impurity type in the corresponding well NW4, NW3, NW2, or NW1. In some embodiments, at least the implant region 110a, 110b, 110c, or 110d comprises a p-type dopant impurity. In some embodiments, at least one of implantation regions 110a, 110b, 110c, or 110d includes an n-type dopant impurity. In some embodiments, implantation region 110a or 110b is the corresponding drain terminal of the corresponding PMOS transistor M1 or M3.In some embodiments, implantation region 110c or 110d is the corresponding source terminal of the corresponding PMOS transistor M4 or M2.

[0029] The implantation region 110a is electrically coupled to the implantation region 108b and corresponds to the connection between the drain terminal of PMOS transistor M1 and the source terminal of PMOS transistor M3 of Fig. 1A. The implantation region 110b is electrically coupled to the implantation region 108c and corresponds to the connection between the drain terminal of PMOS transistor M3 and the drain terminal of PMOS transistor M4 of Fig. 1A. The implantation region 110c is electrically coupled to the implantation region 108d and corresponds to the connection between the drain terminal of PMOS transistor M2 and the source terminal of PMOS transistor M4 of Fig. 1A.

[0030] A parasitic PNP transistor 112a, 112b, 112c, or 112d is formed by the corresponding well NW4, NW3, NW2, or NW1, the corresponding implantation region 108a, 108b, 108c, or 108d, and the corresponding implantation region 110a, 110b, 110c, or 110d. For example, well NW4 forms a base of the parasitic PNP transistor 112a, the implantation region 108a forms an emitter of the parasitic PNP transistor 112a, and region 110a forms a collector of the parasitic PNP transistor 112a. Similarly, well NW3 forms a base of the parasitic pnp transistor 112b, the implant region 108b forms an emitter of the parasitic pnp transistor 112b, and region 110b forms a collector of the parasitic pnp transistor 112a.Similarly, well NW2 forms a base of parasitic PNP transistor 112c, implant region 108c forms an emitter of parasitic PNP transistor 112c, and region 110c forms an emitter of parasitic PNP transistor 112a. Similarly, well NW1 forms a base of parasitic PNP transistor 112d, implant region 108d forms a collector of parasitic PNP transistor 112d, and region 110d forms a collector of parasitic PNP transistor 112d. In some embodiments, at least one of parasitic PNP transistors 112a, 112b, 112c, or 112d is a parasitic bipolar transistor (BJT).

[0031] In some embodiments, at least the parasitic PNP transistor 112a, 112b, 112c, or 112d is configured to provide a current path for an ESD event. In some embodiments, the ESD event corresponds to the situation where a voltage of the pad terminal PAD is greater than a voltage of the supply voltage VDD. In some embodiments, at least the parasitic PNP transistor 112a, 112b, 112c, or 112d is configured to block a current path for an ESD event.

[0032] In some embodiments, by positioning PMOS transistors M1, M2, M3, and M4 in respective separate wells NW4, NW1, NW3, and NW2, integrated circuit 100B has better ESD immunity and occupies a smaller area than other approaches.

[0033] Fig. 2A is a schematic diagram of an integrated circuit 200A according to some embodiments. Integrated circuit 200A is a variation of the integrated circuit, and a similarly detailed description is therefore omitted. For example, integrated circuit 200A illustrates an example where additional PMOS transistors M5 and M6 are used in the stacked PMOS configuration of the PAD voltage tracking circuit.

[0034] Compared with the integrated circuit 100A from Fig. 1A, the integrated circuit 200A further includes PMOS transistors M5 and M6 and corresponding wells NW5 and NW6.

[0035] PMOS transistor M5 or M6 is positioned in the corresponding well NW5 or NW6. For example, PMOS transistor M5 is positioned in a well NW5, and PMOS transistor M6 is positioned in a well NW6. At least one well NW5 or NW6 includes an n-type dopant impurity. In some embodiments, at least one well NW5 or NW6 includes a p-type dopant impurity.

[0036] PMOS transistor M5 comprises a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M5 is connected to the drain terminal of PMOS transistor M3. Fig. 2A. Each of the gate terminal of PMOS transistor M5, the gate terminal of PMOS transistor M1, the gate terminal of PMOS transistor M3 and the source terminal of PMOS transistor M2 are in Fig. 2A and are also coupled to the pad terminal PAD. The gate terminal of PMOS transistor M5 is configured to receive the pad voltage (not labeled) from the pad terminal PAD. The body terminal of PMOS transistor M5 is coupled to well NW5.

[0037] PMOS transistor M6 comprises a gate terminal, a drain terminal, a source terminal, and a body terminal. The source terminal of PMOS transistor M6 is connected to the drain terminal of PMOS transistor M4. Fig. 2A. The drain terminal of PMOS transistor M6 and the drain terminal of PMOS transistor M5 are coupled together and electrically floating. Each of the gate terminal of PMOS transistor M6, the gate terminal of PMOS transistor M2, the gate terminal of PMOS transistor M4, and the source terminal of PMOS transistor M1 are in Fig. 2A and are also coupled to the VDD power supply. The gate terminal of PMOS transistor M6 is configured to receive the supply voltage (not labeled) from the VDD power supply. The body terminal of PMOS transistor M6 is coupled to well NW6.

[0038] In some embodiments, by positioning PMOS transistors M1, M2, M3, M4, M5, and M6 in respective separate wells NW4, NW1, NW3, NW2, NW5, and NW6, the integrated circuit 100A to 100B has better ESD immunity and occupies a smaller area than other approaches.

[0039] Fig. Figure 2B is a cross-sectional view of an integrated circuit 200B according to some embodiments. Integrated circuit 200B is one embodiment of integrated circuit 200A.

[0040] Integrated circuit 200B is a variation of integrated circuit 100B, and a similarly detailed description is therefore omitted. For example, integrated circuit 100B illustrates an example where additional PMOS transistors M5 and M6 are used in the stacked PMOS configuration of the PAD voltage tracking circuit (e.g., integrated circuit 100A of Fig. 1A) can be used.

[0041] Compared with the integrated circuit 100B from Fig. 1B, the integrated circuit 200B further includes PMOS transistors M5 and M6 in corresponding wells NW5 and NW6.

[0042] Compared with the integrated circuit 100B from Fig. 1B, the integrated circuit 200B further includes wells NW5 and NW6, regions 204e and 204f, gates 206e and 206f, implant regions 208e and 208f, and implant regions 210e and 210f.

[0043] Wells NW5 and NW6 are located in substrate 102. In some embodiments, at least one of wells NW5 and NW6 comprises a dopant impurity type that is opposite to the substrate type. In some embodiments, at least one of wells NW5 and NW6 comprises an n-type dopant impurity, and the substrate is a p-type substrate. In some embodiments, at least one of wells NW5 and NW6 comprises a p-type dopant impurity, and the substrate is an n-type substrate.

[0044] At least one of wells NW5 or NW6 extends in a first direction X. Each of wells NW1, NW2, NW3, NW4, NW5, or NW6 is separated from another of wells NW1, NW2, NW3, NW4, NW5, or NW6 in the first direction X. In some embodiments, at least one of wells NW5 or NW6 is referred to as a body of the corresponding PMOS transistor M5 or M6.

[0045] Region 204e or 204f is located within the corresponding well NW5 or NW6. In some embodiments, at least region 204e or 204f comprises an n-type dopant impurity. In some embodiments, at least region 204e or 204f comprises a p-type dopant impurity. In some embodiments, region 204e or 204f is connected to a corresponding body terminal of the corresponding PMOS transistor M5 or M6.

[0046] Gate 206e or 206f is located over the corresponding well NW5 or NW6. In some embodiments, gate 206e or 206f is a corresponding gate of the corresponding PMOS transistor M5 or M6. For ease of illustration, gates 106a, 106b, and 206e are not shown as coupled to each other or to other elements, and gates 106c, 106d, 206c, and 206f are not shown as coupled to each other or to other elements.

[0047] Implant region 208e or 208f is located within the corresponding well NW5 or NW6. In some embodiments, at least implant region 208e or 208f comprises a dopant impurity type that is opposite to the dopant impurity type in the corresponding well NW5 or NW6. In some embodiments, at least implant region 208e or 208f comprises a p-type dopant impurity. In some embodiments, at least implant region 208e or 208f comprises an n-type dopant impurity. In some embodiments, implant region 208e is the source terminal of PMOS transistor M5. In some embodiments, implant region 208f is the drain terminal of PMOS transistor M6.

[0048] Implant region 210e or 210f is located within the corresponding NW5 or NW6. In some embodiments, at least implant region 210e or 210f comprises a dopant impurity type that is opposite to the dopant impurity type in the corresponding well NW5 or NW6. In some embodiments, at least implant region 210e or 210f comprises a p-type dopant impurity. In some embodiments, at least implant region 210e or 210f comprises an n-type dopant impurity. In some embodiments, implant region 210e is the drain terminal of PMOS transistor M5. In some embodiments, implant region 210f is the source terminal of PMOS transistor M6.

[0049] Compared with the integrated circuit 100B from Fig. 1B is the implantation region 110b of Fig. 2B is not electrically coupled to the implantation region 108c.

[0050] The implantation region 110b from Fig. 2B is electrically coupled to the implantation region 208e and corresponds to the connection between the drain terminal of PMOS transistor M3 and the source terminal of PMOS transistor M5 of Fig. 2A. The implantation region 108c from Fig. 2B is electrically coupled to the implantation region 210f and corresponds to the connection between the drain terminal of PMOS transistor M4 and the source terminal of PMOS transistor M6 of Fig. 2A. The implantation region 210e is electrically coupled to the implantation region 208f and corresponds to the connection between the drain terminal of PMOS transistor M5 and the drain terminal of PMOS transistor M6 of Fig. 2A.

[0051] A parasitic PNP transistor 212e or 212f is formed by the corresponding well NW5 or NW6, the corresponding implantation region 208e or 208f, and the corresponding implantation region 210e or 210f. For example, well NW5 forms a base of the parasitic PNP transistor 212e, the implantation region 208e forms an emitter of the parasitic PNP transistor 212e, and region 210e forms a collector of the parasitic PNP transistor 212e. Similarly, well NW6 forms a base of the parasitic PNP transistor 212f, the implantation region 208f forms a collector of the parasitic PNP transistor 212f, and region 210f forms a collector of the parasitic PNP transistor 212f. In some embodiments, at least the parasitic PNP transistor 112a, 112b, 112c, 112d, 112e, or 212f is a parasitic BJT.

[0052] In some embodiments, at least the parasitic PNP transistor 112a, 112b, 112c, 112d, 212e, or 212f is configured to provide a current path for an ESD event. In some embodiments, at least the parasitic PNP transistor 112a, 112b, 112c, 112d, 212e, or 212f is configured to block a current path for an ESD event.

[0053] In some embodiments, by positioning PMOS transistors M1, M2, M3, M4, M5, or M6 in respective separate wells NW4, NW1, NW3, NW2, NW5, and NW6, integrated circuit 200B has better ESD immunity and occupies a smaller area than other approaches. In some embodiments, by having further PMOS transistors M1, M2, M3, M4, M5, or M6 positioned in respective further separate wells NW4, NW1, NW3, NW2, NW5, or NW6, integrated circuit 200B has better ESD immunity than other approaches with fewer transistors positioned in respective wells.

[0054] Fig. 3A is a circuit diagram of an integrated circuit 300A according to some embodiments. Fig. 3B is a circuit diagram of an equivalent circuit 300B of the integrated circuit 300A according to some embodiments. Fig. 3C is a cross-sectional view of an integrated circuit 300A according to some embodiments.

[0055] The integrated circuit 300A is an embodiment of the integrated circuit of Fig. 1A.

[0056] The integrated circuit 300A includes PMOS transistors M1, M2, M3 and M4, which are coupled to the voltage supply VDD and the pad terminal PAD.

[0057] Compared with the integrated circuit 100A from Fig. 1A is PMOS transistor M1 in a well 320a ( Fig. 3C), and PMOS transistors M2, M3 and M4 are positioned in a well 320b ( Fig. 3C), which is different from well 320a.

[0058] The body terminal of PMOS transistor M1 and the source terminal of PMOS transistor M1 are coupled together and are further coupled to the voltage supply VDD. By coupling the body terminal of PMOS transistor M1, the source terminal of PMOS transistor M1, and the voltage supply VDD, the parasitic PNP transistor 112a is formed from Fig. 1A changed to a parasitic diode D1 ( Fig. 3B).

[0059] The PMOS transistors M2, M3 and M4 are positioned in a same well (e.g., N-well 320b), and therefore the body terminal of PMOS transistor M2, the body terminal of PMOS transistor M3, and the body terminal of PMOS transistor M4 are coupled together.

[0060] Each of the body terminal of PMOS transistor M2, the body terminal of PMOS transistor M3, the body terminal of PMOS transistor M4, the drain terminal of PMOS transistor M3, and the drain terminal of PMOS transistor M4 are coupled together at a node F1. In some embodiments, node F1 is electrically floating. In some embodiments, node F1 is electrically coupled to the supply voltage VDD through PMOS transistors M1 and M3. In some embodiments, node F1 is electrically coupled to the pad terminal PAD through PMOS transistors M2 and M4.

[0061] Fig. 3B is a circuit diagram of an equivalent circuit 300B of the integrated circuit 300A according to some embodiments.

[0062] The equivalent circuit 300B is a variation of the integrated circuit 300A that includes parasitic elements 330 of the integrated circuit 300A, and a similar description is therefore omitted. For example, according to some embodiments, the corresponding circuit 300B corresponds to the integrated circuit 300A of Fig. 3A with the parasitic elements 330 (e.g. diode D1, parasitic transistors Q2 and Q3).

[0063] The equivalent circuit 300B includes the integrated circuit 300A and the parasitic elements 330. The parasitic elements 330 include a diode D1, a parasitic transistor Q2, and a parasitic transistor Q3.

[0064] Each of an anode of diode D1, the source terminal of PMOS transistor M3, the drain terminal of PMOS transistor M1, and an emitter of parasitic transistor Q3 are coupled together. Each of a cathode of diode D1, the body terminal of PMOS transistor M1, the source terminal of PMOS transistor M1, the gate of PMOS transistor M2, the gate of PMOS transistor M4, and the first voltage supply VDD are coupled together. In some embodiments, diode D1 is forward biased and is configured to allow current flow through diode D1 and a parasitic current path. In some embodiments, diode D1 is reverse biased and is configured to block current flow through diode D1 and the parasitic current path.

[0065] Each of a base of the parasitic transistor Q3, a collector of the parasitic transistor Q3, a base of the parasitic transistor Q2, a collector of the parasitic transistor Q2, the drain terminal of PMOS transistor M3, the drain terminal of PMOS transistor M4, the body terminal of PMOS transistor M2, the body terminal of PMOS transistor M3, and the body terminal of PMOS transistor M4 are coupled together at node F1.

[0066] Each of an emitter of the parasitic transistor Q2, the source terminal of PMOS transistor M2, the gate of PMOS transistor M1, the gate of PMOS transistor M3 and the pad terminal PAD are coupled together.

[0067] In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore the PMOS transistors M2 and M4 are turned on, and the PMOS transistors M1 and M3 are turned off, and the voltage of the pad terminal PAD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the pad terminal PAD, the entire voltage stress of the ESD event is placed across PMOS transistors M3 and M1, thereby turning on the parasitic transistor Q3 and diode Q3 to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes two parasitic elements (e.g.,the parasitic diode D1 and the parasitic transistor Q3) positioned in different wells (320a and 320b), increases the ESD immunity compared to other approaches.

[0068] In some embodiments, during a negative voltage ESD event from the supply voltage VDD to the pad terminal PAD, the voltage of the supply voltage VDD is greater than the voltage of the pad terminal PAD, and therefore, PMOS transistors M1 and M3 are turned on, and PMOS transistors M2 and M4 are turned off, and the voltage of the supply voltage VDD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the supply voltage VDD, the entire voltage stress of the ESD event will be placed across PMOS transistors M2 and M4, causing the parasitic transistor Q2 to turn on to conduct the discharged ESD current to the pad terminal PAD. Thus, the ESD current path includes a parasitic element (e.g., the parasitic transistor Q2).

[0069] In some embodiments, the 2-stacked PMOS structure using PMOS transistors M2 and M4 may be reduced to a single PMOS transistor (either M2 or M4) if negative stress ESD events are not a concern.

[0070] Fig. 3C is a cross-sectional view of an integrated circuit 300A according to some embodiments.

[0071] The integrated circuit 300C is an embodiment of the integrated circuit 100B of Fig. 1B and a similarly detailed description is therefore omitted.

[0072] Integrated circuit 300C illustrates an example of where PMOS transistor M1 is positioned in well 320a, and PMOS transistors M2, M3, and M4 are positioned in well 320b. In other words, wells NW2, NW3, and NW4 are made of Fig. 1B merged into well 320b.

[0073] The integrated circuit 300C includes substrate 102, wells 320a and 320b, regions 304a and 304b, gates 106a, 106b, 106c and 106d, implant regions 308a, 308b, 308c and 308d, and implant regions 310a, 310b, 310c and 310d.

[0074] Compared with the integrated circuit 100B from Fig. 1B replaces Well 320a Well NW1, and Well 320b replaces Wells NW2, NW3 and NW4 from Fig. 1B, and a similarly detailed description is therefore omitted. In other words, Wells NW2, NW3 and NW4 from Fig. 1B are merged into well 320b, and a similarly detailed description is therefore omitted. Well 320b differs from well 320a. Well 320b is separated from well 320a in the first direction X.

[0075] Gate 106a is located above well 320a, and gates 106b, 106c, and 106d are located above well 320b. For ease of illustration, gates 106a and 106b are not shown coupled to each other or to other elements, and gates 106c and 106d are not shown coupled to each other or to other elements.

[0076] Compared with the integrated circuit 100B from Fig. 1B replaces Region 304a Region 104a, and Region 304b replaces Regions 104b, 104c and 104d from Fig. 1B, and a similarly detailed description is therefore omitted. In other words, the regions 104b, 104c and 104d of Fig. 1B are merged into region 304a, and a similarly detailed description is therefore omitted. Region 304a is located within well 320a, and region 304b is located within well 320b.

[0077] Compared with the integrated circuit 100B from Fig. 1B, implantation regions 308a, 308b, 308c, and 308d replace corresponding implantation regions 108a, 108b, 108c, and 108d, and implantation regions 310a, 310b, 310c, and 310d replace corresponding implantation regions 110a, 110b, 110c, and 110d, and a similar detailed description is therefore omitted.

[0078] The implantation regions 308a and 310a are located within well 320a. The implantation regions 308b, 308c, and 308d and the implantation regions 310b, 310c, and 310d are located within well 320b.

[0079] Each of region 304a, implantation region 308a and voltage supply VDD is electrically coupled together and corresponds to the connection between the body terminal of PMOS transistor M1, the source terminal of PMOS transistor M1 and the voltage supply VDD of Fig. 3A.

[0080] The implantation region 310a is electrically coupled to the implantation region 308b and corresponds to the connection between the drain terminal of PMOS transistor M1 and the source terminal of PMOS transistor M3 of Fig. 3A.

[0081] Each of implantation region 310b, implantation region 308c, and region 304b is electrically coupled together at node F1 and corresponds to the connection between the drain terminal of PMOS transistor M3, the drain terminal of PMOS transistor M4 of Fig. 3A, the body terminal of PMOS transistor M2, the body terminal of PMOS transistor M3 and the body terminal of PMOS transistor M4 Fig. 3A.

[0082] The implantation region 310c is electrically coupled to the implantation region 308d and corresponds to the connection between the drain terminal of PMOS transistor M2 and the source terminal of PMOS transistor M4 of Fig. 3A.

[0083] The implantation region 310d is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M2 and the pad terminal PAD of Fig. 3A.

[0084] Compared with the integrated circuit 100B from Fig. 1B, the parasitic diode D1 replaces the parasitic pnp transistor 112a from Fig. 1B, the parasitic transistor Q3 replaces the parasitic pnp transistor 112b from Fig. 1B, and the parasitic transistor Q2 replaces the parasitic pnp transistors 112c and 112d from Fig. 1B, and a similarly detailed description is therefore omitted.

[0085] The parasitic diode D1 is formed by well 320a and implantation region 310a. For example, implantation region 310a corresponds to the anode of diode D1, and well 320a corresponds to the cathode of diode D1.

[0086] The parasitic transistor Q3 is formed by well 320b, implantation region 308b, and implantation region 310b. For example, well 320b forms a base of the parasitic transistor Q3, implantation region 308b forms an emitter of the parasitic transistor Q3, and region 310b forms a collector of the parasitic transistor Q3.

[0087] The parasitic transistor Q2 is formed by well 320b, implantation region 308c, and implantation region 310d. For example, well 320b forms a base of the parasitic transistor Q2, implantation region 310d forms an emitter of the parasitic transistor Q2, and region 308c forms a collector of the parasitic transistor Q2.

[0088] In some embodiments, by positioning PMOS transistor M1 in well 320a, and by positioning PMOS transistors M2, M3, and M4 in a separate well (well 320b), the parasitic current path of integrated circuit 300C includes parasitic elements (e.g., parasitic diode D1 and parasitic transistors Q2 and Q3) positioned in different wells (320a and 320b), thereby improving the ESD immunity of integrated circuit 300A to 300C compared to other approaches, and integrated circuit 300A to 300C occupies a smaller area than other approaches with similar performance.

[0089] Fig. 4A is a circuit diagram of an integrated circuit 400A according to some embodiments. Fig. 4B is a circuit diagram of an equivalent circuit 400B of the integrated circuit 400A according to some embodiments. Fig. 4C is a cross-sectional view of an integrated circuit 400A according to some embodiments.

[0090] The integrated circuit 400A is an embodiment of the integrated circuit of Fig. 1A.

[0091] The integrated circuit 400A includes PMOS transistors M1, M2, M3 and M4, which are coupled to the voltage supply VDD and the pad terminal PAD.

[0092] The 400A integrated circuit is a variation of the 300A integrated circuit from Fig. 3A. Compared with the integrated circuit 300A from Fig. 3A is the PMOS transistor M1 of the integrated circuit 400A in well 320a ( Fig. 4C), the PMOS transistors M3 and M4 of the integrated circuit 400A are positioned in well 420a ( Fig. 4C), and PMOS transistor M2 of the integrated circuit 400A is positioned in a well 420b ( Fig. 4C), and a similarly detailed description is therefore omitted. In some embodiments, all of the wells 320a, 420a, and 420b are different from each other.

[0093] Compared with the integrated circuit 300A from Fig. 3A is the PMOS transistor M2 from Fig. 4A to 4C in well 420b, and therefore the body terminal of PMOS transistor M2 is no longer coupled to the body terminal of PMOS transistor M3 and the body terminal of PMOS transistor M4. The body terminal of PMOS transistor M2 in Fig. 4A to 4C is coupled to node F2. In some embodiments, node F2 is charged from the pad terminal PAD with a parasitic body diode of PMOS transistor M4. In some embodiments, the parasitic body diode is formed between the gate and drain of PMOS transistor M4.

[0094] For example, in some embodiments, during an ESD event, the voltage of pad terminal PAD is sufficient to cause the parasitic body diode to turn on and conduct, causing node F2 to charge the voltage of pad terminal PAD. Thus, in these embodiments, node F2 can track the voltage of pad terminal PAD without being directly coupled to the body terminal of PMOS transistor M3 and the body terminal of PMOS transistor M4 nwell controller, meaning no PMOS / NMOS connected to F2. However, the node F2 voltage could be traced back to PAD through the parasitic BJT. In some embodiments, a parasitic body diode is formed by implantation 410d and well 420b. In some embodiments, a parasitic body diode is formed by implantation 408d and well 420b.

[0095] PMOS transistors M3 and M4 are positioned in the same well (e.g., well 420a), and therefore, the body terminal of PMOS transistor M3 and the body terminal of PMOS transistor M4 are coupled together. Each of the body terminal of PMOS transistor M3, the body terminal of PMOS transistor M4, the drain terminal of PMOS transistor M3, and the drain terminal of PMOS transistor M4 are coupled together at node F1. In some embodiments, node F1 is electrically floating. In some embodiments, node F1 is electrically coupled to supply voltage VDD through PMOS transistors M1 and M3. In some embodiments, node F1 is electrically coupled to pad terminal PAD through PMOS transistors M2 and M4.

[0096] Fig. 4B is a circuit diagram of an equivalent circuit 400B of the integrated circuit 400A according to some embodiments.

[0097] The equivalent circuit 400B is a variation of the integrated circuit 400A that includes parasitic elements 430 of the integrated circuit 400A, and a similar description is therefore omitted. For example, according to some embodiments, the corresponding circuit 400B corresponds to the integrated circuit 400A of Fig. 4A with the parasitic elements 430 (e.g. diode D1, parasitic transistors Q2', Q3 and Q4).

[0098] The equivalent circuit 400B includes the integrated circuit 400A and the parasitic elements 430. Parasitic elements 430 are a variation of the parasitic elements 330 of Fig. 3B and a similarly detailed description is therefore omitted. The parasitic elements 430 include diode D1 of Fig. 3B, a parasitic transistor Q2', the parasitic transistor Q3 from Fig. 3B and a parasitic transistor Q4.

[0099] In comparison with the parasitic elements 330 from Fig. 3B to 3C, the parasitic transistor Q2' and the parasitic transistor Q4 replace the parasitic transistor Q2 from Fig. 3B, and a similarly detailed description is therefore omitted.

[0100] In comparison with the parasitic elements 330 from Fig. 3B to 3C are for Fig. 4B, each of the base of the parasitic transistor Q3, the collector of the parasitic transistor Q3, a base of the parasitic transistor Q2', a collector of the parasitic transistor Q2', the drain terminal of PMOS transistor M3, the drain terminal of PMOS transistor M4, the body terminal of PMOS transistor M3, and the body terminal of PMOS transistor M4 are coupled together at node F1.

[0101] Fig. 4B, each is coupled together from an emitter of the parasitic transistor Q4, the source terminal of PMOS transistor M2, the gate of PMOS transistor M1, the gate of PMOS transistor M3, and the pad terminal PAD. The Fig. 4B, a base of the parasitic transistor Q4 is coupled to the drain terminal of PMOS transistor M2.

[0102] In Fig. 4B, each is coupled together from an emitter of the parasitic transistor Q2', a collector of the parasitic transistor Q4, the drain terminal of PMOS transistor M2, and the source of PMOS transistor M4.

[0103] In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore the PMOS transistors M2 and M4 are turned on, and the PMOS transistors M1 and M3 are turned off, and the voltage of the pad terminal PAD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the pad terminal PAD, the entire voltage stress of the ESD event is placed across PMOS transistors M3 and M1, thereby turning on the parasitic transistor Q3 and diode Q3 to conduct the discharged ESD current to the voltage supply VDD. Thus, since the parasitic current path includes two parasitic elements (e.g.,the parasitic diode D1 and the parasitic transistor Q3) positioned in different wells (320a and 420a), increases the ESD immunity compared to other approaches.

[0104] In some embodiments, during an ESD event with a negative voltage from the supply voltage VDD to the pad terminal PAD, the voltage of the supply voltage VDD is greater than the voltage of the pad terminal PAD, and therefore the PMOS transistors M1 and M3 are turned on, and the PMOS transistors M2 and M4 are turned off, and the voltage of the supply voltage VDD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the supply voltage VDD, the entire voltage load of the ESD event is placed across PMOS transistors M2 and M4, thereby turning on the parasitic transistors Q2' and Q4 to conduct the discharged ESD current to the pad terminal PAD. Thus, since the ESD current path includes two parasitic elements (e.g.,the parasitic transistor Q4 and the parasitic transistor Q2') positioned in different wells (420a and 420b), increases the ESD immunity compared to other approaches.

[0105] Fig. 4C is a cross-sectional view of an integrated circuit 400A according to some embodiments.

[0106] The integrated circuit 400C is an embodiment of the integrated circuit 100B of Fig. 1B or the integrated circuit 300B Fig. 3B, and a similarly detailed description is therefore omitted.

[0107] Integrated circuit 400C illustrates an example of this, where PMOS transistor M1 is positioned in well 320a, PMOS transistors M3 and M4 are positioned in well 420a, and PMOS transistor M2 is positioned in well 420b. In comparison with integrated circuit 100B of Fig. 1B will be Wells NW3 and NW4 from Fig. 1B fused in well 420a.

[0108] The integrated circuit 400C includes substrate 102, wells 320a, 420a and 420b, regions 304a, 304b and 404d, gates 106a, 106b, 106c and 106d, implant regions 308a, 408b, 408c and 408d, and implant regions 310a, 410b, 410c and 410d.

[0109] Compared with the integrated circuit 100B from Fig. 1B replaces Well 320a Well NW1 and Well 420a replaces Wells NW3 and NW2 from Fig. 1B, and Well 420b replaces Wells NW1 from Fig. 1B, and a similarly detailed description is therefore omitted. In other words, Wells NW2 and NW3 from Fig. 1B are merged into well 420a, and a similarly detailed description is therefore omitted. Each of wells 320a, 420a, and 420b is separated from each other in the first direction X. In some embodiments, each of wells 320a, 420a, and 420b is different from the others.

[0110] Gate 106a is located over well 320a, gates 106b and 106c are located over well 420a, and gate 106d is located over well 420b. For ease of illustration, gates 106a and 106b are not shown coupled to each other or to other elements, and gates 106c and 106d are not shown coupled to each other or to other elements.

[0111] Compared with the integrated circuit 100B from Fig. 1B replaces Region 404b Regions 104b and 104c from Fig. 1B, and region 404d replaces regions 104d from Fig. 1B, and a similarly detailed description is therefore omitted. In other words, regions 104b and 104c are Fig. 1B is merged into region 404b, and a similarly detailed description is therefore omitted. Region 304a is located within well 320a, region 404b is located within well 420a, and region 404d is located within well 420b.

[0112] The 400C integrated circuit is a variation of the 300C integrated circuit from Fig. 3C and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 300C from Fig. 3C, implantation regions 408b, 408c, and 408d replace corresponding implantation regions 308b, 308c, and 308d, and implantation regions 410b, 410c, and 410d replace corresponding implantation regions 310b, 310c, and 310d, and a similar detailed description is therefore omitted.

[0113] The implantation regions 408b and 408c and the implantation regions 410b and 410c are located within well 420a. The implantation region 408d and the implantation region 410d are located within well 420b.

[0114] The implantation region 310a is electrically coupled to the implantation region 408b and corresponds to the connection between the drain terminal of PMOS transistor M1 and the source terminal of PMOS transistor M3 of Fig. 4A.

[0115] Each of the implantation region 410b, implantation region 408c and region 404b is electrically coupled together at node F1 and corresponds to the connection between the drain terminal of PMOS transistor M3, the drain terminal of PMOS transistor M4 of Fig. 4A, the body terminal of the body terminal of PMOS transistor M3 and the body terminal of PMOS transistor M4.

[0116] Region 404d is electrically coupled to node F2 and corresponds to the connection between the body terminal of PMOS transistor M2 and node F2 in Fig. 4A.

[0117] The implantation region 410c is electrically coupled to the implantation region 408d and corresponds to the connection between the drain terminal of PMOS transistor M2 and the source terminal of PMOS transistor M4 of Fig. 4A.

[0118] The implantation region 410d is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M2 and the pad terminal PAD of Fig. 4A.

[0119] The integrated circuit 400C includes the parasitic diode D1 made of Fig. 3C, a parasitic transistor Q2', the parasitic transistor Q3 from Fig. 3C and a parasitic transistor Q4. Compared with the integrated circuit 300C from Fig. 3C, the parasitic transistor Q2' and the parasitic transistor Q4 replace the parasitic transistor Q2 from Fig. 3C, and a similarly detailed description is therefore omitted.

[0120] Compared with the integrated circuit 100B from Fig. 1B, parasitic transistor Q2' replaces parasitic PNP transistor 112c Fig. 1B, and the parasitic transistor Q4 replaces the parasitic pnp transistor 112d from Fig. 1B, and a similarly detailed description is therefore omitted.

[0121] The parasitic transistor Q2' is formed by well 420a, implantation region 408c, and implantation region 410c. For example, well 420a forms a base of the parasitic transistor Q2', implantation region 410c forms an emitter of the parasitic transistor Q2', and region 408c forms a collector of the parasitic transistor Q2'.

[0122] The parasitic transistor Q4 is formed by well 420b, implantation region 408d, and implantation region 410d. For example, well 420b forms a base of the parasitic transistor Q4, implantation region 410d forms an emitter of the parasitic transistor Q4, and region 408d forms a collector of the parasitic transistor Q4.

[0123] In some embodiments, by positioning PMOS transistor M1 in well 320a, by positioning PMOS transistors M3 and M4 in a separate well (well 420a), and by positioning PMOS transistor M2 in another separate well (well 420b), one parasitic current path of the integrated circuit 400C comprises parasitic elements (e.g., the parasitic diode D1 and the parasitic transistor Q3) positioned in different wells (320a and 420a), and another parasitic current path of the integrated circuit 400C comprises parasitic elements (e.g., the transistors Q2' and Q4) positioned in different wells (420a and 420b), thereby improving the SD immunity of the integrated circuit 400A to 400C compared to other approaches, and the integrated circuit 400A to 400C occupies a smaller area than other Approaches with similar performance.

[0124] Fig. 5A is a circuit diagram of an integrated circuit 500A according to some embodiments. Fig. 5B is a circuit diagram of an equivalent circuit 500B of the integrated circuit 500A according to some embodiments. Fig. 5C is a cross-sectional view of an integrated circuit 500A according to some embodiments.

[0125] The integrated circuit 500A is an embodiment of the integrated circuit 200A of Fig. 2A and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 200A from Fig. 2A is PMOS transistor M1 is in well 320a ( Fig. 5C), PMOS transistor M3 is positioned in a well 520a ( Fig. 5C), and PMOS transistors M2, M5 and M6 are positioned in a well 520b ( Fig. 5C). In some embodiments, each of the wells 320a, 520a, and 520b is separate from the others and therefore different.

[0126] The integrated circuit 500A includes PMOS transistors M1, M2, M3, M4, M5 and M6, which are coupled to the voltage supply VDD and the pad terminal PAD.

[0127] The 500A integrated circuit is a variation of the 400A integrated circuit from Fig. 4A and a similarly detailed description is therefore omitted.

[0128] PMOS transistors M2, M4, M5, and M6 are positioned in a same well (e.g., well 520b). Each of the body terminal of PMOS transistor M2, the body terminal of PMOS transistor M4, the body terminal of PMOS transistor M5, the body terminal of PMOS transistor M6, the drain terminal of PMOS transistor M5, and the drain terminal of PMOS transistor M6 are coupled together at node F1. In some embodiments, node F1 is electrically floating. In some embodiments, node F1 is electrically coupled to the supply voltage VDD through PMOS transistors M1, M3, and M5. In some embodiments, node F1 is electrically coupled to the pad terminal PAD through PMOS transistors M2, M4, and M6.

[0129] PMOS transistor M3 is positioned in well 520a. In Fig. 5A to 5C and 6A to 6C, a body terminal of PMOS transistor M3, the drain terminal of PMOS transistor M3, and the source terminal of PMOS transistor M5 are coupled together at node F2'. In some embodiments, by coupling the body terminal of PMOS transistor M3 to the drain terminal of PMOS transistor M3, PMOS transistor M3 is self-biased, and node F2' is not provided with a bias voltage from circuitry external to integrated circuit 500A.

[0130] Fig. 5B is a circuit diagram of an equivalent circuit 500B of the integrated circuit 500A according to some embodiments.

[0131] The equivalent circuit 500B is a variation of the integrated circuit 500A that includes parasitic elements 530 of the integrated circuit 500A, and a similar description is therefore omitted. For example, according to some embodiments, the corresponding circuit 500B corresponds to the integrated circuit 500A of Fig. 5A with the parasitic elements 530 (e.g. diode D1, parasitic transistors Q2, Q3 and Q5).

[0132] The equivalent circuit 500B is a variation of the equivalent circuit 300B of Fig. 3B or Fig. 400B from Fig. 4B, and a similarly detailed description is therefore omitted.

[0133] The equivalent circuit 500B includes the integrated circuit 500A and the parasitic elements 530. The parasitic elements 530 include diode D1, a parasitic transistor Q2, a parasitic transistor Q3, and a parasitic transistor Q5.

[0134] Each of the gate of PMOS transistor M6, the cathode of diode D1, the body terminal of PMOS transistor M1, the source terminal of PMOS transistor M1, the gate of PMOS transistor M2, the gate of PMOS transistor M4, and the first voltage supply VDD are coupled together.

[0135] For Fig. 5A to 5C & 6A to 6C are each coupled together from an emitter of the parasitic transistor Q5, the base of the parasitic transistor Q3, the collector of the parasitic transistor Q3, the drain terminal of PMOS transistor M3 and the source terminal of PMOS transistor M5.

[0136] For Fig. 5A to 5C are each composed of a collector of the parasitic transistor Q5, a base of the parasitic transistor Q5, the body terminal of PMOS transistor M5, the drain terminal of PMOS transistor M5, the drain terminal of PMOS transistor M6, the body terminal of PMOS transistor M6, the body terminal of PMOS transistor M4, the body terminal of PMOS transistor M2, a collector of the parasitic transistor Q2", and a base of the parasitic transistor Q2" coupled together at node F1.

[0137] Each of an emitter of the parasitic transistor Q2, the gate of PMOS transistor M5, the source terminal of PMOS transistor M2, the gate of PMOS transistor M1, the gate of PMOS transistor M3, and the pad terminal PAD are coupled together.

[0138] In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore the PMOS transistors M2, M4, and M6 are turned on, and the PMOS transistors M1, M3, and M5 are turned off, and the voltage of the pad terminal PAD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the pad terminal PAD, the entire voltage stress of the ESD event is placed across PMOS transistors M5, M3, and M1, turning on the parasitic transistors Q5 and Q3 and the diode Q3 to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes three parasitic elements (e.g.,the parasitic diode D1, the parasitic transistor Q3 and the parasitic transistor Q5) positioned in different wells (320a, 520a and 520b), increases the ESD immunity compared to other approaches.

[0139] In some embodiments, during an ESD event with a negative voltage from the supply voltage VDD to the pad terminal PAD, the voltage of the supply voltage VDD is greater than the voltage of the pad terminal PAD, and therefore the PMOS transistors M1, M3, and M5 are turned on, and the PMOS transistors M2, M4, and M6 are turned off, and the voltage of the supply voltage VDD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the supply voltage VDD, the entire voltage load of the ESD event is placed across PMOS transistors M2, M4, and M6, causing the parasitic transistor Q2 to turn on to conduct the discharged ESD current to the pad terminal PAD. Thus, the ESD current path includes a parasitic element (e.g., the parasitic transistor Q2).

[0140] In some embodiments, the 3-stacked PMOS structure using PMOS transistors M2, M4, and M6 may be reduced to a single PMOS transistor (one of M2, M4, or M6) or a 2-stacked PMOS structure using two PMOS transistors (two of M2, M4, or M6) if negative stress ESD events are not a concern.

[0141] Fig. 5C is a cross-sectional view of an integrated circuit 500A according to some embodiments.

[0142] The integrated circuit 500C is an embodiment of the integrated circuit 200B of Fig. 2B and a similarly detailed description is therefore omitted.

[0143] Integrated circuit 500C illustrates an example of PMOS transistor M1 positioned in well 320a, PMOS transistor M3 positioned in well 520a, and PMOS transistors M2, M4, M5, and M6 positioned in well 520b. In some embodiments, each of wells 320a, 520a, and 520b is separate from the others and therefore distinct.

[0144] The integrated circuit 500C includes substrate 102, wells 320a, 520a and 520b, regions 304a, 504b and 504c, gates 106a, 106b, 106c, 106d, 206e and 206f, implant regions 308a, 508b, 508c, 508d, 508e and 508f and implant regions 310a, 510b, 510c, 510d, 510e and 510f.

[0145] Compared with the integrated circuit 200B from Fig. 2B replaces Well 320a Well NW4, Well 520a replaces Well NW3, and Well 520b replaces Wells NW5, NW6, NW2 and NW1 from Fig. 2B, and a similarly detailed description is therefore omitted.

[0146] In other words, Wells NW5, NW6, NW2 and NW1 from Fig. 2B are merged into well 520b, and a similarly detailed description is therefore omitted. Each of wells 320a, 520a, and 520b is separated from the others in the first direction X. In some embodiments, at least one of wells 320a, 520a, or 520b is distinct from another of at least one of wells 320a, 520a, or 520b.

[0147] Gate 106a is located above well 320a, gate 106b is located above well 520a, and gates 106b, 106c, 106d, 206e, and 206f are located above well 520b. For ease of illustration, gates 106a, 106b, and 206e are not shown as coupled to each other or to other elements, and gates 106c, 106d, 206c, and 206f are not shown as coupled to each other or to other elements.

[0148] Compared with integrated circuit 200B from Fig. 2B replaces Region 304a Region 104a, Region 504b replaces Region 104b from Fig. 2B and Region 504c replaces Regions 104c, 104d, 204e and 204f from Fig. 2B, and a similarly detailed description is therefore omitted. In other words, regions 104c, 104d, 204e and 204f from Fig. 2B are merged into region 504b, and a similarly detailed description is therefore omitted. Region 304a is located within well 320a, region 504b is located within well 520a, and region 504c is located within well 520b.

[0149] The 500C integrated circuit is a variation of the 300C integrated circuit from Fig. 3C and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 300C from Fig. 3C, implantation regions 408b, 408c, and 408d replace corresponding implantation regions 308b, 308c, and 308d, and implantation regions 410b, 410c, and 410d replace corresponding implantation regions 310b, 310c, and 310d, and a similarly detailed description is therefore omitted. Implantation regions 308a and 310a are shown in Fig. 3C, and a similarly detailed description is therefore omitted.

[0150] Compared with the integrated circuit 200B from Fig. 2B, implantation regions 508b, 508c, 508d, 508e, and 508f replace corresponding implantation regions 108b, 108c, 108d, 208e, and 208f, and implantation regions 510b, 510c, 510d, 510e, and 510f replace corresponding implantation regions 110b, 110c, 110d, 210e, and 210f, and a similar detailed description is therefore omitted.

[0151] Implant regions 308a and 310a are located within well 320a. Implant regions 508b and 510b are located within well 520a. Implant regions 508c, 508d, 508e, and 508f, and implant regions 510c, 510d, 510e, and 510f are located within well 520b.

[0152] The implantation region 310a is electrically coupled to the implantation region 508b and corresponds to the connection between the drain terminal of PMOS transistor M1 and the source terminal of PMOS transistor M3 of Fig. 5A.

[0153] Each of region 504c, implant region 510e, and implant region 508f are electrically coupled together at node F1 and correspond to the connection between the body terminal of PMOS transistor M5, the drain terminal of PMOS transistor M5, the drain terminal of PMOS transistor M6, the body terminal of PMOS transistor M6, the body terminal of PMOS transistor M4, and the body terminal of PMOS transistor M2 at node F1.

[0154] Each of region 504b, implantation region 510b, and implantation region 508e is electrically coupled together at node F2' and corresponds to the connection between the body terminal of PMOS transistor M3, the drain terminal of PMOS transistor M3, and the source terminal of PMOS transistor M5 of Fig. 5A.

[0155] The implantation region 510f is electrically coupled to the implantation region 508c and corresponds to the connection between the source terminal of PMOS transistor M6 and the drain terminal of PMOS transistor M4 of Fig. 5A.

[0156] The implantation region 510c is electrically coupled to the implantation region 508d and corresponds to the connection between the source terminal of PMOS transistor M4 and the drain terminal of PMOS transistor M2 of Fig. 5A.

[0157] The implantation region 510d is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M2 and the pad terminal PAD of Fig. 5A.

[0158] The integrated circuit 500C includes the parasitic diode D1 made of Fig. 3C, a parasitic transistor Q2", the parasitic transistor Q3 from Fig. 3C and a parasitic transistor Q5. The parasitic diode D1 is in Fig. 3C and the parasitic transistor Q3 is in Fig. 3C, and a similarly detailed description is therefore omitted.

[0159] Compared with the integrated circuit 200B from Fig. 2B, parasitic transistor Q2" replaces parasitic pnp transistors 212f, 112c and 112d from Fig. 2B, and parasitic transistor Q5 replaces parasitic pnp transistor 212e from Fig. 2B, and a similarly detailed description is therefore omitted.

[0160] The parasitic transistor Q3 from Fig. 5C is formed by well 520a, implantation region 508b, and implantation region 510b. For example, well 520a forms the base of the parasitic transistor Q3 in Fig. 5C, the implantation region 508b forms the emitter of the parasitic transistor Q3 in Fig. 5C, and region 510b forms the collector of the parasitic transistor Q3 in Fig. 5C.

[0161] The parasitic transistor Q2" is formed by well 520b, implantation region 508f, and implantation region 510d. For example, well 520b forms a base of the parasitic transistor Q2", implantation region 510d forms an emitter of the parasitic transistor Q2", and region 508f forms a collector of the parasitic transistor Q2".

[0162] The parasitic transistor Q5 is formed by well 520b, implantation region 508e, and implantation region 510e. For example, well 520b forms a base of the parasitic transistor Q5, implantation region 508e forms an emitter of the parasitic transistor Q5, and region 510e forms a collector of the parasitic transistor Q5.

[0163] In some embodiments, by positioning PMOS transistor M1 in well 320a, by positioning PMOS transistor M3 in a separate well (well 520a), and by positioning PMOS transistors M5, M6, M4, and M2 in another separate well (well 520b), one parasitic current path of the integrated circuit 500C comprises parasitic elements (e.g., parasitic diode D1, parasitic transistor Q3, and parasitic transistor Q5) positioned in different wells (320a, 520a, and 520b), and another parasitic current path of the integrated circuit 500C comprises the parasitic elements (e.g., parasitic transistor Q2) positioned in the other well (520b), thus improving the ESD immunity of the integrated circuit 500A to 500C compared to other approaches, and the integrated circuit 500A to 500C occupies a smaller area than other approaches with similar performance.

[0164] Fig. 6A is a circuit diagram of an integrated circuit 600A according to some embodiments. Fig. 6B is a circuit diagram of an equivalent circuit 600B of the integrated circuit 600A according to some embodiments. Fig. 6C is a cross-sectional view of an integrated circuit 600A according to some embodiments.

[0165] The integrated circuit 600A is an embodiment of the integrated circuit 200A of Fig. 2A.

[0166] The integrated circuit 600A includes PMOS transistors M1, M2, M3, M4, M5 and M6, which are coupled to the voltage supply VDD and the pad terminal PAD.

[0167] The 600A integrated circuit is a variation of the 500A integrated circuit from Fig. 5A and the integrated circuit 400A Fig. 4A. Compared with the integrated circuit 500A from Fig. 5A or the integrated circuit 400A Fig. 4A is the PMOS transistor M1 of the integrated circuit 600A in well 320a ( Fig. 6C), the PMOS transistor M3 of the integrated circuit 600A is positioned in well 520a ( Fig. 6C), the PMOS transistor M2 of the integrated circuit 600A is positioned in well 420b ( Fig. 6C), and the PMOS transistors M4, M5 and M6 of the integrated circuit 600A are positioned in a well 620a ( Fig. 6C), and a similarly detailed description is therefore omitted.

[0168] In some embodiments, all of the wells 320a, 420a and 420b are different from each other.

[0169] Compared with the integrated circuit 500A from Fig. 5A is the PMOS transistor M2 from Fig. 6A to 6C in well 420b, and the body terminal of PMOS transistor M2 is coupled to node F2. In some embodiments, node F2 is charged by the pad terminal PAD with the parasitic body diode of PMOS transistor M4.

[0170] The configuration of PMOS transistor M1 in Fig. 6A to 6C is similar to the configurations of PMOS transistor M1 in at least Fig. 3A to 3C, and a similarly detailed description is therefore omitted. The configuration of PMOS transistor M3 in Fig. 6A to 6C is similar to the configurations of PMOS transistor M3 in at least Fig. 5A to 5C, and a similarly detailed description is therefore omitted.

[0171] PMOS transistors M4, M5, and M6 are positioned in a same well (e.g., well 620a). Each of the body terminal of PMOS transistor M4, the body terminal of PMOS transistor M5, the body terminal of PMOS transistor M6, the drain terminal of PMOS transistor M5, and the drain terminal of PMOS transistor M6 are connected to a node 6A-6C in Fig. 6A to 6C. In some embodiments, node F1 is electrically floating. In some embodiments, node F1 is electrically coupled to supply voltage VDD through PMOS transistors M1, M3, and M5. In some embodiments, node F1 is electrically coupled to pad terminal PAD through PMOS transistors M2, M4, and M6.

[0172] Fig. 6B is a circuit diagram of an equivalent circuit 600B of the integrated circuit 600A according to some embodiments.

[0173] The equivalent circuit 600B is a variation of the integrated circuit 600A that includes parasitic elements 630 of the integrated circuit 600A, and a similar description is therefore omitted. For example, according to some embodiments, the corresponding circuit 600B corresponds to the integrated circuit 600A of Fig. 6A with the parasitic elements 630 (e.g. diode D1, Q3, parasitic transistors Q2''', Q3, Q4 and Q5).

[0174] The equivalent circuit 600B is a variation of the equivalent circuit 500B of Fig. 5B or Fig. 400B from Fig. 4B, and a similarly detailed description is therefore omitted.

[0175] The equivalent circuit 600B includes the integrated circuit 600A and the parasitic elements 630. Parasitic elements 630 include diode D1, the parasitic transistor Q2''', the parasitic transistor Q3, the parasitic transistor Q4, and the parasitic transistor Q5.

[0176] The configuration of diode D1, parasitic transistor Q3 and parasitic transistor Q5 in Fig. 6A to 6C is similar to the configurations of diode D1, parasitic transistor Q3 and parasitic transistor Q5 in at least Fig. 5A to 5C, and a similarly detailed description is therefore omitted.

[0177] For Fig. 6A to 6C, each of the collector of parasitic transistor Q5, the base of parasitic transistor Q5, the body terminal of PMOS transistor M5, the drain terminal of PMOS transistor M5, the drain terminal of PMOS transistor M6, the body terminal of PMOS transistor M6, the body terminal of PMOS transistor M4, the collector of parasitic transistor Q2''', and the base of parasitic transistor Q2''' are coupled together at node F1.

[0178] For Fig. 6A to 6C are each coupled together from an emitter of the parasitic transistor Q4, the gate of PMOS transistor M5, the source terminal of PMOS transistor M2, the gate of PMOS transistor M1, the gate of PMOS transistor M3 and the pad terminal PAD.

[0179] For Fig. 6A to 6C, the body terminal of PMOS transistor M2 is coupled to the parasitic transistor Q4.

[0180] For Fig. 6A to 6C, each of the drain terminal of PMOS transistor M2, the source terminal of PMOS transistor M4, the collector of parasitic transistor Q4, and the emitter of parasitic transistor Q2''' is coupled together.

[0181] In some embodiments, during an ESD event with positive stress from the pad terminal PAD to the voltage supply VDD, the voltage of the pad terminal PAD is greater than the voltage of the voltage supply VDD, and therefore the PMOS transistors M2, M4, and M6 are turned on, and the PMOS transistors M1, M3, and M5 are turned off, and the voltage of the pad terminal PAD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the pad terminal PAD, the entire voltage stress of the ESD event is placed across PMOS transistors M5, M3, and M1, turning on the parasitic transistors Q5' and Q3 and the diode Q3 to conduct the discharged ESD current to the voltage supply VDD. Thus, since the ESD current path includes three parasitic elements (e.g.,the parasitic diode D1, the parasitic transistor Q3 and the parasitic transistor Q5') positioned in different wells (320a, 520a and 620a), increases the ESD immunity compared to other approaches.

[0182] In some embodiments, during a negative stress ESD event from the voltage supply VDD to the pad terminal PAD, the voltage of the voltage supply VDD is greater than the voltage of the pad terminal PAD, and therefore the PMOS transistors M1, M3, and M5 are turned on, and the PMOS transistors M2, M4, and M6 are turned off, and the voltage of the voltage supply VDD is placed at node F1. In these embodiments, when the voltage of node F1 is equal to the voltage of the supply voltage VDD, the entire voltage stress of the ESD event is placed across PMOS transistors M2, M4, and M6, thereby turning on the parasitic transistors Q2 and Q4 to conduct the discharged ESD current to the pad terminal PAD. Thus, since the parasitic current path includes two parasitic elements (e.g.,the parasitic transistor Q4 and the parasitic transistor Q2''') positioned in different wells (420b and 620a), increases the ESD immunity compared to other approaches.

[0183] In some embodiments, the 2-stacked PMOS structure in a same well (well 620a) using PMOS transistors M2 and M6 may be reduced to a single PMOS transistor (one of M2 or M6) if negative stress ESD events are not a concern.

[0184] Fig. 6C is a cross-sectional view of an integrated circuit 600A according to some embodiments.

[0185] The integrated circuit 600C is an embodiment of the integrated circuit 200B of Fig. 2B and a similarly detailed description is therefore omitted.

[0186] Integrated circuit 600C illustrates an example of PMOS transistor M1 positioned in well 320a, PMOS transistor M3 positioned in well 520a, PMOS transistor M2 positioned in well 420b, and PMOS transistors M4, M5, and M6 positioned in a well 620a, and a similarly detailed description is therefore omitted. In some embodiments, each of wells 320a, 420b, 520a, and 620a is separated from the others in the first direction X and is therefore distinct.

[0187] The integrated circuit 600C includes substrate 102, wells 320a, 420b, 520a and 620a, regions 304b, 404d, 504b and 604c, gates 106a, 106b, 106c, 106d, 206e and 206f, implant regions 308a, 408d, 508b, 608c, 608e and 608f and implant regions 310a, 410d, 510b, 610c, 610e and 610f.

[0188] Compared with the integrated circuit 200B from Fig. 2B, replaces Well 320a Well NW4, Well 420b replaces Well NW1, Well 520a replaces Well NW3 and Well 620a replaces Wells NW5, NW6 and NW2 from Fig. 2B, and a similarly detailed description is therefore omitted.

[0189] In other words, Wells NW5, NW6 and NW2 are Fig. 2B merges into well 620a, and a similarly detailed description is therefore omitted. Each of wells 320a, 420b, 520a, and 620a is separated from the others in the first direction X. In some embodiments, at least one of wells 320a, 420b, 520a, or 620a is distinct from another of at least one of wells 320a, 420b, 520a, or 620a.

[0190] Gate 106a is located over well 320a, gate 106b is located over well 520a, gates 106c, 206e, and 206f are located over well 620a, and gate 106d is located over well 420b. For ease of illustration, gates 106a, 106b, and 206e are not shown coupled to each other or to other elements, and gates 106c, 106d, 206c, and 206f are not shown coupled to each other or to other elements.

[0191] Compared with the integrated circuit 200B from Fig. 2B replaces Region 304a Region 104a, Region 504b replaces Region 104b from Fig. 2B, Region 604c replaces Regions 104c, 204e and 204f from Fig. 2B, and region 404d replaces region 104d from Fig. 2B, and a similarly detailed description is therefore omitted.

[0192] In other words, regions 104c, 204e and 204f from Fig. 2B are merged into region 604c, and a similarly detailed description is therefore omitted. Region 304a is located within well 320a, region 504b is located within well 520a, region 404d is located within well 420b, and region 604c is located within well 620a.

[0193] The integrated circuit 600C is an embodiment of the integrated circuit 500C of Fig. 5C of the integrated circuit 400C Fig. 4C, and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 500C from Fig. 5C, implantation regions 608e, 608f, and 608c replace corresponding implantation regions 508e, 508f, and 508c, and implantation regions 610e, 610f, and 610c replace corresponding implantation regions 510e, 510f, and 510c, and a similar detailed description is therefore omitted.

[0194] Implant regions 308a and 310a are in Fig. 3C, and a similarly detailed description is therefore omitted. Implant regions 508b and 510b are shown in Fig. 5C, and a similarly detailed description is therefore omitted.

[0195] The 600C integrated circuit is a variation of the 400C integrated circuit from Fig. 4C and a similarly detailed description is therefore omitted. For example, implantation regions 408d and 410d are shown in Fig. 4C, and a similarly detailed description is therefore omitted.

[0196] Compared with the integrated circuit 200B from Fig. 2B, implantation regions 608e, 608f, and 608c replace corresponding implantation regions 108e, 108f, and 108c, and implantation regions 610e, 610f, and 610c replace corresponding implantation regions 110e, 110f, and 110c, and a similar detailed description is therefore omitted.

[0197] Implant regions 308a and 310a are located within well 320a. Implant regions 508b and 510b are located within well 520a. Implant regions 408d and 410d are located within well 420b. Implant regions 608c, 608e, and 608f, and implant regions 610c, 610e, and 610f are located within well 520b.

[0198] Each of region 604c, implant region 610e, and implant region 608f is electrically coupled together at node F1 and corresponds to the connection between the body terminal of PMOS transistor M5, the drain terminal of PMOS transistor M5, the drain terminal of PMOS transistor M6, the body terminal of PMOS transistor M6, and the body terminal of PMOS transistor M4 at node F1.

[0199] Each of region 504b, implantation region 510b, and implantation region 608e is electrically coupled together at node F2' and corresponds to the connection between the body terminal of PMOS transistor M3, the drain terminal of PMOS transistor M3, and the source terminal of PMOS transistor M5 of Fig. 6A.

[0200] The implantation region 404d is electrically coupled to node F2 and corresponds to the connection between the body terminal of PMOS transistor M2 and node F2 in Fig. 6A.

[0201] The implantation region 610f is electrically coupled to the implantation region 608c and corresponds to the connection between the source terminal of PMOS transistor M6 and the drain terminal of PMOS transistor M4 of Fig. 6A.

[0202] The implantation region 610c is electrically coupled to the implantation region 408d and corresponds to the connection between the source terminal of PMOS transistor M4 and the drain terminal of PMOS transistor M2 of Fig. 6A.

[0203] The implantation region 410d is electrically coupled to the pad terminal PAD and corresponds to the connection between the source terminal of PMOS transistor M2 and the pad terminal PAD of Fig. 5A.

[0204] The integrated circuit 600C includes the parasitic diode D1 made of Fig. 3C, a parasitic transistor Q2''', the parasitic transistor Q3 from Fig. 3C, the parasitic transistor Q4 from Fig. 4C and a parasitic transistor Q5'.

[0205] The parasitic diode D1 is in Fig. 3C, the parasitic transistor Q3 is in Fig. 3C and Fig. 5C, the parasitic transistor Q4 is in Fig. 4C, and a similarly detailed description is therefore omitted.

[0206] Compared with the integrated circuit 200B from Fig. 2B, the parasitic transistor Q2''' replaces the parasitic pnp transistors 212f and 112c from Fig. 2B, and a similarly detailed description is therefore omitted.

[0207] Compared with the integrated circuit 500C from Fig. 5C, the parasitic transistor Q5' replaces the parasitic transistor Q5 from Fig. 5C, and a similarly detailed description is therefore omitted.

[0208] The parasitic transistor Q5' is formed by well 620a, implantation region 608e, and implantation region 610e. For example, well 620a forms a base of the parasitic transistor Q5', implantation region 608e forms an emitter of the parasitic transistor Q5, and region 610e forms a collector of the parasitic transistor Q5.

[0209] The parasitic transistor Q2''' is formed by well 620a, implantation region 608f, and implantation region 610c. For example, well 620a forms a base of the parasitic transistor Q2''', implantation region 610c forms an emitter of the parasitic transistor Q2''', and region 608f forms a collector of the parasitic transistor Q2'''.

[0210] In some embodiments, by positioning PMOS transistor M1 in well 320a, by positioning PMOS transistor M3 in a separate well (well 520a), by positioning PMOS transistors M5, M6 and M4 in another separate well (well 620a) and by positioning PMOS transistor M2 in yet another separate well (well 420b), one parasitic current path of the integrated circuit 600C comprises the parasitic elements (e.g., parasitic diode D1, parasitic transistor Q3 and parasitic transistor Q5') positioned in different wells (320a, 520a and 620a), and another parasitic current path of the integrated circuit 600C comprises parasitic elements (e.g.,the parasitic transistor Q2''' and the parasitic transistor Q4) positioned in different wells (620a and 420b), thereby improving the ESD immunity of the integrated circuit 600A to 600C compared with other approaches, and the integrated circuit 600A to 600C occupies a smaller area than other approaches with similar performance.

[0211] Fig. 7A is a circuit diagram of an integrated circuit 700A according to some embodiments.

[0212] The integrated circuit 700A is an embodiment of the integrated circuit 100A of Fig. 1A. The 700A integrated circuit is a variation of the 300A integrated circuit from Fig. 3A and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 300A from Fig. 3A, the integrated circuit 700A further includes a control logic circuit 702a.

[0213] The control logic circuit 702a is configured to generate a control logic signal CLS. In some embodiments, the control logic signal CLS is similar to the voltage of the pad terminal PAD, and a similar detailed description is therefore omitted.

[0214] Compared with the integrated circuit 300A from Fig. 3A, each of the gate terminal of PMOS transistor M3 and the gate terminal of PMOS transistor M1 is not coupled to the source terminal of PMOS transistor M2 and the pad terminal PAD.

[0215] In Fig. 7A to 7B, the gate terminal of PMOS transistor M3 and the gate terminal of PMOS transistor M1 are coupled to control logic circuit 702a and configured to receive a control logic signal CLS from control logic circuit 702a.

[0216] In some embodiments, the control logic signal CLS is equal to a logic 0 corresponding to a reference supply voltage VSS. In some embodiments, the control logic signal CLS is equal to a logic 1 corresponding to the voltage of the pad terminal PAD (e.g., the PAD voltage).

[0217] Fig. 7B is a circuit diagram of an integrated circuit 700B according to some embodiments.

[0218] The integrated circuit 700B is an embodiment of the integrated circuit 100A of Fig. 1A. The integrated circuit 700B is a variation of the integrated circuit 400A from Fig. 4A and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 400A from Fig. 4A, the integrated circuit 700B further includes control logic circuit 702a. The control logic circuit 702a of Fig. 7B was in Fig. 7A, and a similarly detailed description is therefore omitted.

[0219] Compared with the integrated circuit 400A from Fig. 4A, each of the gate terminal of PMOS transistor M3 and the gate terminal of PMOS transistor M1 is not coupled to the source terminal of PMOS transistor M2 and the pad terminal PAD.

[0220] In Fig. 7B, the gate terminal of PMOS transistor M3 and the gate terminal of PMOS transistor M1 are coupled to control logic circuit 702a and configured to receive a control logic signal CLS from control logic circuit 702a.

[0221] Fig. 7C is a circuit diagram of an integrated circuit 700C according to some embodiments.

[0222] The integrated circuit 700C is an embodiment of the integrated circuit 200A of Fig. 2A. The 700C integrated circuit is a variation of the 500A integrated circuit from Fig. 5A and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 500A from Fig. 5A, the integrated circuit 700C further includes a control logic circuit 702b.

[0223] The control logic circuit 702b of Fig. 7C to 7D is similar to the control logic circuit 702a shown in Fig. 7A to 7B, and a similar detailed description is therefore omitted.

[0224] Compared with the integrated circuit 500A from Fig. 5A, each of the gate terminal of PMOS transistor M3, the gate terminal of PMOS transistor M1, and the gate terminal of PMOS transistor M5 is not coupled to the source terminal of PMOS transistor M2 and the pad terminal PAD.

[0225] In Fig. 7C to 7D, the gate terminal of PMOS transistor M3, the gate terminal of PMOS transistor M1, and the gate terminal of PMOS transistor M5 are coupled to control logic circuit 702b and configured to receive a control logic signal CLS from control logic circuit 702b.

[0226] Fig. 7D is a circuit diagram of an integrated circuit 700D according to some embodiments.

[0227] The integrated circuit 700D is an embodiment of the integrated circuit 200A of Fig. 2A. The 700D integrated circuit is a variation of the 600A integrated circuit from Fig. 6A and a similarly detailed description is therefore omitted. In comparison with the integrated circuit 600A from Fig. 6A, the integrated circuit 700D further includes a control logic circuit 702b.

[0228] The control logic circuit 702b of Fig. 7D is similar to the control logic circuit 702a shown in Fig. 7A to 7B, and a similar detailed description is therefore omitted.

[0229] Compared with the integrated circuit 600A from Fig. 6A, each of the gate terminal of PMOS transistor M3, the gate terminal of PMOS transistor M1, and the gate terminal of PMOS transistor M5 is not coupled to the source terminal of PMOS transistor M2 and the pad terminal PAD.

[0230] In Fig. 7D, the gate terminal of PMOS transistor M3, the gate terminal of PMOS transistor M1, and the gate terminal of PMOS transistor M5 are coupled to control logic circuit 702b and configured to receive a control logic signal CLS from control logic circuit 702b.

[0231] Fig. 8 is a circuit diagram of a control logic circuit 800 according to some embodiments.

[0232] The control logic circuit 800 is an embodiment of at least the control logic circuit 700A of Fig. 7A, the control logic circuit 700B from Fig. 7B, the control logic circuit 700C from Fig. 7C or the control logic circuit 700D Fig. 7D.

[0233] Control logic circuit 800 includes a PMOS transistor M7 and an NMOS transistor M8 coupled to the voltage supply VDD, the pad terminal PAD, the reference voltage supply VSS, and a node NA. In some embodiments, control logic circuit 800 is an inverter. Other circuits are within the scope of this disclosure.

[0234] A source terminal of PMOS transistor M7 is coupled to at least the pad terminal PAD and is configured to receive a pad voltage (not labeled). Each of a gate terminal of PMOS transistor M7 and a gate terminal of NMOS transistor M8 is coupled together. The gate terminal of PMOS transistor M7 and NMOS transistor M8 are further coupled to at least the voltage supply VDD and configured to receive the supply voltage (not labeled). A drain terminal of PMOS transistor M7 is coupled to a drain terminal of NMOS transistor M8 at node NA. A source terminal of PMOS transistor M8 is coupled to the reference voltage supply VSS.

[0235] In some embodiments, when the voltage of the pad terminal PAD is greater than a voltage of the supply voltage VDD, PMOS transistor M7 is turned on and pulls node NA to the voltage of the pad terminal PAD, whereby the voltage of node NA becomes equal to the voltage of the pad terminal PAD, and the control logic signal CLS is equal to a logic 1. In some embodiments, when the voltage of the pad terminal PAD is less than a voltage of the supply voltage VDD, NMOS transistor M8 is turned on and pulls node NA to the voltage of the reference supply voltage VSS, whereby the voltage of node NA becomes equal to the voltage of the reference supply voltage VSS, and the control logic signal CLS is equal to a logic 0. PROCEDURE

[0236] Fig. 9 is a flow diagram of a method of operating such a circuit, such as the integrated circuit of Fig. 1A to 1B, 2A to 2B, 3A to 3C, 4A to 4C, 5A to 5C, 6A to 6C, 7A to 7D, or 8 according to some embodiments. It is understood that further operations are performed before, during, and / or after the method 900 described in Fig. 9, and some other processes may only be briefly described herein. It is understood that method 900 includes integrating elements of one or more integrated elements from one or more integrated circuits 100A to 100B of Fig. 1A to 1B, 200A to 200B from Fig. 2A to 2B, 300A to 300C Fig. 3A to 3C, 400A to 400C Fig. 4A to 4C, 5004 to 500C Fig. 5A to 5C, 600A to 600C Fig. 6A to 6C, 700A to 700C Fig. 7A to 7D or 800 from Fig. 8 used.

[0237] In operation 902 of method 900, a pad voltage is received at a pad voltage terminal PAD. In some embodiments, the pad voltage is greater than a supply voltage of a power supply VDD. In some embodiments, if the pad voltage is greater than the supply voltage of the power supply VDD, method 900 proceeds to operation 904.

[0238] In some embodiments, the pad voltage is less than the supply voltage of a power supply VDD. In some embodiments, if the pad voltage is less than the supply voltage of the power supply VDD, method 900 proceeds to operation 912.

[0239] In operation 904 of method 900, at least a first set of transistors M2 coupled to the pad voltage terminal is turned on in response to the pad voltage being greater than the supply voltage of the power supply VDD, and at least a second set of transistors coupled to the first power supply is turned off in response to the pad voltage being greater than the supply voltage of the power supply VDD. In some embodiments, the first set of transistors comprises at least PMOS transistor M1, M3, or M5. In some embodiments, the second set of transistors comprises at least PMOS transistor M2, M4, or M6. In some embodiments, a first transistor of the first set of transistors is located in a first well and a second transistor of the second set of transistors is located in a second well different from the first well.In some embodiments, the first well comprises at least one well formed in . Fig. 1A to 8, the second well comprises at least one other well which is in Fig. 1A to 8.

[0240] In some embodiments, operation 904 includes one or more of operations 906, 908, or 910.

[0241] In operation 906 of method 900, a first node F1 is electrically coupled to the pad voltage terminal through the first set of transistors.

[0242] In operation 908 of method 900, the first node F1 is electrically decoupled from the first voltage supply by the second set of transistors.

[0243] In operation 910 of method 900, the pad voltage is placed across the second set of transistors.

[0244] In operation 912 of method 900, at least the first set of transistors M2 coupled to the pad voltage terminal is turned off in response to the pad voltage being less than the supply voltage of the power supply VDD, and at least the second set of transistors coupled to the first power supply is turned on in response to the pad voltage being less than the supply voltage of the power supply VDD.

[0245] In some embodiments, operation 912 includes one or more of operations 914, 916, or 918.

[0246] In operation 914 of method 900, the first node F1 is electrically decoupled from the pad voltage terminal by the first set of transistors.

[0247] In operation 916 of method 900, the first node F1 is electrically coupled to the first voltage supply through the second set of transistors.

[0248] In operation 918 of method 900, the pad voltage is placed across the first set of transistors.

[0249] In some embodiments, one or more of the operations of method 900 are not performed. While method 900 is described above with reference to Fig. 3A to 3C, it is understood that method 900 comprises the elements of one or more of Fig. 1A to 2B & 4A to 8. In these embodiments, other operations of method 900 would be consistent with the description and operation of integrated circuits 100A to 200B & 400A to 800 of Fig. 1A to 2B & 4A to 8 executed.

[0250] Furthermore, various PMOS transistors used in Fig. 1A to 8 have a particular dopant type (e.g., N- or P-type) and are for illustration purposes. Embodiments of the disclosure are not limited to a particular transistor type, and one or more of the PMOS or NMOS transistors of Fig. 1A through 8 may be replaced with a corresponding transistor of a different transistor / dopant type. Similarly, the low or high logic value of various signals used in the above description is used for illustrative purposes. Embodiments of the disclosure are not limited to a particular logic value when a signal is enabled and / or disabled. Selecting different logic values ​​is within the scope of various embodiments. Selecting different numbers of PMOS transistors in FIGS. 1A through 8 is within the scope of various embodiments.

[0251] One aspect of this description relates to a voltage tracking circuit. The voltage tracking circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. In some embodiments, the first transistor is in a first well, and the first transistor includes a first gate terminal, a first drain terminal, and a first source terminal, the first source terminal coupled to a first voltage supply, the first gate terminal coupled to a pad voltage terminal, and configured to receive a pad voltage. In some embodiments, the second transistor includes a second gate terminal, a second drain terminal, and a second source terminal, the second source terminal coupled to the first drain terminal, the second gate terminal coupled to the first gate terminal and the pad voltage terminal.In some embodiments, the third transistor comprises a third gate terminal, a third drain terminal, and a third source terminal, wherein the third gate terminal is coupled to the first voltage supply. In some embodiments, the fourth transistor comprises a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the third source terminal, the fourth gate terminal is coupled to the third gate terminal and the first voltage supply, and the fourth source terminal is coupled to the pad voltage terminal. In some embodiments, at least the third transistor is located in a second well that is different from the first well and separated from the first well in a first direction.

[0252] Another aspect of this description relates to a voltage tracking circuit. The voltage tracking circuit includes a control logic circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor. In some embodiments, the first transistor is in a first well, and the first transistor includes a first gate terminal, a first drain terminal, and a first source terminal, the first source terminal coupled to a first voltage supply, the first gate terminal coupled to the control logic circuit, and configured to receive a control logic signal.In some embodiments, the second transistor comprises a second gate terminal, a second drain terminal, and a second source terminal, the second source terminal coupled to the first drain terminal, the second gate terminal coupled to the first gate terminal and the control logic circuit, and configured to receive the control logic signal. In some embodiments, the third transistor comprises a third gate terminal, a third drain terminal, and a third source terminal, the third gate terminal coupled to the first voltage supply.In some embodiments, the fourth transistor comprises a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the third source terminal, the fourth gate terminal is coupled to the third gate terminal and the first voltage supply, and the fourth source terminal is coupled to a pad voltage terminal. In some embodiments, at least the third transistor is located in a second well that is different from the first well and separated from the first well in a first direction.

[0253] Yet another aspect of this description relates to a method of operating a pad voltage tracking circuit.The method includes receiving a pad voltage at a pad voltage terminal PAD, the pad voltage being greater than a supply voltage VDD of a first voltage supply; turning on at least a first set of transistors M2 coupled to the pad voltage terminal and turning off a second set of transistors coupled to the first voltage supply, wherein a first transistor of the first set of transistors is located in a first well and a second transistor of the second set of transistors is located in a second well different from the first well; electrically coupling a first node to the pad voltage terminal through the first set of transistors; electrically decoupling the first node from the first voltage supply through the second set of transistors; and placing the pad voltage across the second set of transistors.

[0254] A number of embodiments have been described. Nevertheless, it should be understood that various modifications are possible without departing from the spirit and scope of the disclosure. For example, various transistors depicted as a particular dopant type (e.g., N-type or P-type metal oxide semiconductor (NMOS or PMOS)) are for illustrative purposes. Embodiments of the disclosure are not limited to any particular type. Selecting different dopant types for a particular transistor is within the scope of various embodiments. The low or high logic value of various signals used in the above description is also for illustrative purposes. Various embodiments are not limited to a particular logic value when a signal is enabled and / or disabled. Selecting different logic values ​​is within the scope of various embodiments.In various embodiments, a transistor functions as a switch. A switching circuit used instead of a transistor falls within the scope of various embodiments. In various embodiments, a source of a transistor may be configured as a drain, and a drain may be configured as a source. Thus, the terms source and drain are used interchangeably. Various signals are generated by corresponding circuits but are not shown for simplicity.

[0255] Various figures depict capacitive circuits using discrete capacitors for illustrative purposes. Equivalent circuits may be used. For example, a capacitive device, circuit arrangement, or network (e.g., a combination of capacitors, capacitive elements, devices, circuit arrangements, or the like) may be used in place of the discrete capacitor. The above illustrations include exemplary steps, but the steps are not necessarily performed in the order depicted. Steps may be added, substituted, rearranged, and / or eliminated as appropriate, consistent with the spirit and scope of the disclosed embodiments.

Claims

[1] Voltage tracking circuit, comprising: a first transistor (M1) in a first well (NW4, 320a), the first transistor (M1) having a first gate terminal, a first drain terminal, and a first source terminal, the first source terminal coupled to a first voltage supply (VDD), the first gate terminal coupled to a pad voltage terminal (PAD) and configured to receive a pad voltage; a second transistor (M3) having a second gate terminal, a second drain terminal, and a second source terminal, the second source terminal being coupled to the first drain terminal, and the second gate terminal being coupled to the first gate terminal and the pad voltage terminal (PAD); a third transistor (M4) having a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply (VDD); and a fourth transistor (M2) having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the third source terminal, the fourth gate terminal is coupled to the third gate terminal and the first voltage supply (VDD), and the fourth source terminal is coupled to the pad voltage terminal (PAD), wherein at least the third transistor (M4) is located in a second well (NW2, 320b, 420a, 520b, 620a) which is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) is separated from the first well (NW4, 320a) in a first direction, wherein the first transistor (M1) and the second transistor (M3) are located in wells separated from each other in the first direction. [2] Voltage tracking circuit according to claim 1, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal; all of the second body terminal, the third body terminal, the fourth body terminal, the second drain terminal and the third drain terminal are coupled together; and the second transistor (M3), the third transistor (M4) and the fourth transistor (M2) are located in the second well (NW2, 320b, 420a, 520b, 620a). [3] Voltage tracking circuit according to claim 1, wherein the second transistor (M3) is located in the second well (NW2, 320b, 420a, 520b, 620a); and the fourth transistor (M2) is located in a third well that is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a), and the third well is separated from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) in the first direction. [4] Voltage tracking circuit according to claim 3, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal coupled to a node; all of the second body terminal, the third body terminal, the second drain terminal and the third drain terminal are coupled together. [5] The voltage tracking circuit of claim 1, further comprising: a fifth transistor (M5) having a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, the fifth source terminal being coupled to the second drain terminal, and the fifth gate terminal being coupled to the first gate terminal, the second gate terminal, and the pad voltage terminal (PAD); and a sixth transistor (M6) having a sixth gate terminal, a sixth drain terminal, and a sixth source terminal, wherein the sixth source terminal is coupled to the third drain terminal, the sixth gate terminal is coupled to the third gate terminal, the fourth gate terminal, and the first voltage supply (VDD), and the sixth drain terminal is coupled to the fifth drain terminal, wherein the fifth transistor (M5) and the sixth transistor (M6) are located in the second well (NW2, 320b, 420a, 520b, 620a); and the second transistor (M3) is located in a third well that is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) and is separated from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) in the first direction. [6] The voltage tracking circuit of claim 5, wherein the fourth transistor (M2) is located in the second well (NW2, 320b, 420a, 520b, 620a). [7] Voltage tracking circuit according to claim 6, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal coupled to a node; the fifth transistor (M5) further comprises a fifth body terminal; the sixth transistor (M6) further comprises a sixth body terminal; all of the third body terminal, the fourth body terminal, the fifth body terminal, the sixth body terminal, the fifth drain terminal and the sixth drain terminal are coupled together; and the second body terminal is coupled to a node, the second drain terminal and the fifth source terminal. [8] The voltage tracking circuit of claim 5, wherein the fourth transistor (M2) is located in a fourth well that is different from the first well (NW4, 320a), the second well (NW2, 320b, 420a, 520b, 620a) and the third well, and is separated from the first well (NW4, 320a), the second well (NW2, 320b, 420a, 520b, 620a) and the third well in the first direction. [9] Voltage tracking circuit according to claim 8, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal; the fifth transistor (M5) further comprises a fifth body terminal; the sixth transistor (M6) further comprises a sixth body terminal; all of the third body terminal, the fifth body terminal, the sixth body terminal, the fifth drain terminal and the sixth drain terminal are coupled together; and the second body terminal is coupled to a node, the second drain terminal and the fifth source terminal; and the fourth body terminal is coupled to another node. [10] Voltage tracking circuit, comprising: a control logic circuit (702); a first transistor (M1) in a first well (NW4, 320a), the first transistor (M1) having a first gate terminal, a first drain terminal and a first source terminal, the first source terminal being coupled to a first voltage supply (VDD), the first gate terminal being coupled to the control logic circuit (702) and being configured to receive a control logic signal (CLS); a second transistor (M3) having a second gate terminal, a second drain terminal, and a second source terminal, the second source terminal coupled to the first drain terminal, the second gate terminal coupled to the first gate terminal and the control logic circuit (702), and configured to receive the control logic signal (CLS); a third transistor (M4) having a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply (VDD); and a fourth transistor (M2) having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, wherein the fourth drain terminal is coupled to the third source terminal, the fourth gate terminal is coupled to the third gate terminal and the first voltage supply (VDD), and the fourth source terminal is coupled to a pad voltage terminal (PAD), wherein at least the third transistor (M4) is located in a second well (NW2, 320b, 420a, 520b, 620a) which is different from the first well (NW4, 320a) and separated from the first well (NW4, 320a) in a first direction, wherein the first transistor (M1) and the second transistor (M3) are located in wells separated from each other in the first direction. [11] The voltage tracking circuit of claim 10, wherein the control logic circuit (702) comprises an inverter configured to receive an inverted control logic signal and generate the control logic signal (CLS). [12] Voltage tracking circuit according to claim 10 or 11, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal; each of the second body terminal, the third body terminal, the fourth body terminal, the second drain terminal and the third drain terminal is coupled together; the second transistor (M3) and the fourth transistor (M2) are located in the second well (NW2, 320b, 420a, 520b, 620a); and the third drain terminal is coupled to the second drain terminal. [13] Voltage tracking circuit according to claim 10, wherein the second transistor (M3) is located in the second well (NW2, 320b, 420a, 520b, 620a); the fourth transistor (M2) is located in a third well that is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) and separated from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) in the first direction; and the third drain terminal is coupled to the second drain terminal. [14] Voltage tracking circuit according to claim 13, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal coupled to a node; and each of the second body terminal, the third body terminal, the second drain terminal and the third drain terminal is coupled together. [15] The voltage tracking circuit of claim 10, further comprising: a fifth transistor (M5) comprising a fifth gate terminal, a fifth drain terminal, and a fifth source terminal, wherein the fifth source terminal is coupled to the second drain terminal, the fifth gate terminal is coupled to the first gate terminal, the second gate terminal, and the control logic circuit (702), and is configured to receive the control logic signal (CLS); and a sixth transistor (M6) having a sixth gate terminal, a sixth drain terminal, and a sixth source terminal, wherein the sixth source terminal is coupled to the third drain terminal, the sixth gate terminal is coupled to the third gate terminal, the fourth gate terminal, and the first voltage supply (VDD), and the sixth drain terminal is coupled to the fifth drain terminal, wherein the fifth transistor (M5) and the sixth transistor (M6) are located in the second well (NW2, 320b, 420a, 520b, 620a); and the second transistor (M3) is located in a third well which is different from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) and is separated from the first well (NW4, 320a) and the second well (NW2, 320b, 420a, 520b, 620a) in the first direction. [16] The voltage tracking circuit of claim 15, wherein the fourth transistor (M2) is located in the second well (NW2, 320b, 420a, 520b, 620a). [17] Voltage tracking circuit according to claim 16, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal coupled to a node; the fifth transistor (M5) further comprises a fifth body terminal; the sixth transistor (M6) further comprises a sixth body terminal; each of the third body terminal, the fourth body terminal, the fifth body terminal, the sixth body terminal, the fifth drain terminal and the sixth drain terminal is coupled together; and the second body terminal is coupled to a node, the second drain terminal and the fifth source terminal. [18] The voltage tracking circuit of claim 15, wherein the fourth transistor (M2) is located in a fourth well that is different from the first well (NW4, 320a), the second well (NW2, 320b, 420a, 520b, 620a) and the third well, and is separated from the first well (NW4, 320a), the second well (NW2, 320b, 420a, 520b, 620a) and the third well in the first direction. [19] Voltage tracking circuit according to claim 18, wherein the first transistor (M1) further comprises a first body terminal coupled to the first voltage supply (VDD) and the first source terminal; the second transistor (M3) further comprises a second body terminal; the third transistor (M4) further comprises a third body terminal; the fourth transistor (M2) further comprises a fourth body terminal; the fifth transistor (M5) further comprises a fifth body terminal; the sixth transistor (M6) further comprises a sixth body terminal; each of the third body terminal, the fifth body terminal, the sixth body terminal, the fifth drain terminal and the sixth drain terminal is coupled together; and the second body terminal is coupled to a node, the second drain terminal and the fifth source terminal; and the fourth body terminal is coupled to another node. [20] A method of operating a pad voltage tracking circuit, comprising: Receiving a pad voltage at a pad voltage terminal (PAD), the pad voltage being greater than a supply voltage (VDD) of a first voltage supply; Turning on at least a first set of transistors (M2, M4, M6) coupled to the pad voltage terminal (PAD) and turning off a second set of transistors (M1, M3, M5) coupled to the first voltage supply, wherein a first transistor (M4) of the first set of transistors (M2, M4, M6) is located in a first well (NW2, 320b, 420a, 520b, 620a) and a second transistor (M1) of the second set of transistors (M1, M3, M5) is located in a second well (NW4, 320a) different from the first well (NW2, 320b, 420a, 520b, 620a); electrically coupling a first node (F1) to the pad voltage terminal (PAD) through the first set of transistors; electrically decoupling the first node (F1) from the first voltage supply (VDD) by the second set of transistors (M1, M3, M5); and Applying the pad voltage to the second set of transistors (M1, M3, M5), wherein the second transistor (M1) of the second set of transistors (M1, M3, M5) and a third transistor (M3) of the second set of transistors (M1, M3, M5) are located in wells separated from each other in a first direction, wherein the second transistor (M1) of the second set of transistors (M1, M3, M5) has a first gate terminal, a first drain terminal and a first source terminal, wherein the first source terminal is coupled to the first voltage supply (VDD) and the first gate terminal is coupled to the pad voltage terminal (PAD), wherein the third transistor (M3) of the second set of transistors (M1, M3, M5) has a second gate terminal, a second drain terminal and a second source terminal, the second source terminal being coupled to the first drain terminal and the second gate terminal being coupled to the first gate terminal and the pad voltage terminal (PAD), wherein the first transistor (M4) of the first set of transistors (M2, M4, M6) has a third gate terminal, a third drain terminal and a third source terminal, the third gate terminal being coupled to the first voltage supply (VDD), wherein a fourth transistor (M2) of the first set of transistors (M2, M4, M6) has a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the fourth drain terminal being coupled to the third source terminal, the fourth gate terminal being coupled to the third gate terminal and the first voltage supply (VDD), and the fourth source terminal being coupled to the pad voltage terminal (PAD).

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