METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Abstract

A method for manufacturing a semiconductor device, the method comprising: Formation of a first fin structure (20) and a second fin structure (20) over a substrate (10); Forming an insulating layer (30) over the substrate (10) such that lower sections of the first and second fin structure (20) are embedded in the insulating layer (30) and upper sections of the first and second fin structure (20) are exposed by the insulating layer (30); Formation of a gate structure (40) over channel areas of the first and second fin structures (20); Omission of source / drain areas of the first and second fin structure (20); and Forming an epitaxial source / drain structure (60) over the recessed first and second fin structures (20), wherein the epitaxial source / drain structure (60) is a united structure with a fusion point and comprises a first, second, third and fourth epitaxial layer (68) formed in that order over the recessed first and second fin structure (20), wherein a P concentration of the second epitaxial layer (64) is highest in the first to fourth epitaxial layers (62, 64, 66, 68), and wherein the height of a base of the intergrowth point, starting from an upper surface of the insulation layer (30), is 50% or more of the height of the channel areas of the first and second fin structures (20), starting from the upper surface of the insulation layer (30).

Description

BACKGROUND

[0001] This disclosure relates to an integrated semiconductor circuit, and in particular to a semiconductor device with an epitaxial source / drain (S / D) structure containing cavities, and its fabrication method. As the semiconductor industry has advanced into the nanometer process nodes in the pursuit of higher device density, higher performance, and lower costs, challenges in both fabrication and design have led to the development of three-dimensional designs, such as a fin field-effect transistor (Fin FET) and the use of a metal-gate structure with a material having a high dielectric constant (k). The metal-gate structure is often fabricated using gate-replacement technologies, and the sources and drains are formed using an epitaxial growth process.

[0002] Document US 2017 / 0256456A1 relates to a semiconductor device comprising an insulating layer arranged over a substrate, first and second fin structures, a gate structure, a source / drain structure, and a dielectric layer arranged on an upper surface of the insulating layer. Both the first and second fin structures are arranged over the substrate and extend in a first direction in plan view. The gate structure is arranged over portions of the first and second fin structures and extends in a second direction that intersects the first direction.

[0003] Publication US 2020 / 0105621A1 describes a process that includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a depression in the fin between the first gate stack and the second gate stack; forming an epitaxial source / drain region in the depression, wherein the formation includes: forming a first layer lining the sides and bottom of the depression by distributing silane, dichlorosilane, trichlorosilane, and hydrochloric acid into the depression; and after forming the first layer, forming a second layer on top of the first layer by distributing silane, dichlorosilane, trichlorosilane, and hydrochloric acid into the depression.Document US 2020 / 0135914A1 discloses a method for manufacturing a semiconductor device, comprising deepening a fin extending from a substrate, forming an epitaxial base feature on the deepened fin, forming a rod-shaped epitaxial feature on the epitaxial base feature, and forming a conformal epitaxial feature on the rod-shaped epitaxial feature.

[0004] Publication US 2020 / 0168723A1 describes a semiconductor device comprising first and second semiconductor fins extending from a substrate and a source / drain region epitaxially grown in recesses of the first and second semiconductor fins. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood from the following detailed description when read together with the accompanying figures. It is emphasized that, in accordance with common industry practice, various features are not drawn to scale and are used for illustration only. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced to clarify the description. Fig. Figure 1 shows a process flow diagram of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 2 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 3 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 4 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 5 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 6A, Fig. 6B and Fig. Figure 6C shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 7 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 8A and Fig. Figure 8B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 9A and Fig. Figure 9B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 10A and Fig. Figure 10B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 11A and Fig. Figure 11B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 12A and Fig. Figure 12B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. The Fig. 13A and Fig. Figure 13B shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 14 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 15 shows a process flow for the formation of a source / drain epitaxy layer according to an embodiment of the present disclosure. The Fig. 16A, Fig. 16B and Fig. Figure 16C shows cross-sectional views of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 17 shows a cross-sectional view of one of the various stages of a manufacturing process for a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 18 shows a result of the elementary analysis of a source / drain structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0006] It should be noted that the following disclosure provides many different embodiments or examples of the implementation of various features of the invention. Specific embodiments or examples of components and arrangements are described below for the sake of simplicity in the present disclosure. These are, of course, only examples. For instance, the dimensions of the elements are not limited to the disclosed range or values, but may depend on the process conditions and / or the desired properties of the device.Furthermore, the formation of a first feature above or on top of a second feature, as described below, can include embodiments in which the first and second features are in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, so that the first and second features are not in direct contact. For the sake of simplicity and clarity, various features may be drawn arbitrarily at different scales. In the accompanying drawings, some layers / features may be omitted for simplification.

[0007] Furthermore, to simplify the description, spatially relative terms such as "under," "below," "lower," "upper," "above," and the like may be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device in use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here may be interpreted accordingly. Additionally, the term "made of" may mean either "comprising" or "consisting of." Furthermore, the following manufacturing process may include one or more additional operations within or between the described operations, and the sequence of operations may be modified.In the present disclosure, the phrase “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C or A, B and C) and does not mean one element of A, one element of B and one element of C, unless otherwise described. Materials, configurations, dimensions, processes and / or operations that are the same or similar to those described in one embodiment may be used in the other embodiments and the detailed explanation may be omitted.

[0008] The embodiments disclosed herein relate to a semiconductor device and its manufacturing process, in particular to source / drain regions of a field-effect transistor (FET). The embodiments disclosed herein are generally applicable not only to FinFETs but also to other FETs.

[0009] Fig. Figure 1 shows a process flow diagram and Fig. Figures 2-16 show cross-sectional views of various stages for the fabrication of a semiconductor device according to the embodiments of the present disclosure. It is understood that additional processes may be carried out before, during, and after the stages described in Figures 2-16. Fig. The processes shown in Figures 1 and 2-16 can be provided for, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The sequence of operations / processes can be interchangeable.

[0010] In S101 of Fig. 1 and as in Fig. 2 and Fig. As shown in Figure 3, one or more fin structures 20 are formed over a substrate 10. Fin structures for FinFETs can be structured using any suitable method. For example, the fin structures can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography with self-aligning processes, enabling the creation of patterns with, for example, smaller spacing than is possible with a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers or spikes can be used to pattern the fin structures. Multi-patterning processes, which combine photolithography and self-aligning processes, generally result in the formation of a pair of fin structures.

[0011] In some embodiments, a mask layer 15 is formed over a substrate 10 to create fin structures. The mask layer 15 is formed, for example, by a thermal oxidation process and / or a chemical vapor deposition (CVD) process. The substrate 10 is, for example, a p-type silicon or germanium substrate with an impurity concentration in the range of approximately 1 × 10⁻⁶ 15 cm -3 up to about 1 × 10 16 cm -3 In other embodiments, the substrate is an n-type silicon or germanium substrate with an impurity concentration in the range of approximately 1 × 10 15cm -3 up to about 1 × 10 16 cm -3 .

[0012] Alternatively, the substrate 10 can comprise another elementary semiconductor such as germanium, a compound semiconductor including Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof. In one embodiment, the substrate 10 is a silicon layer of a silicon-on-insulator (SOI) substrate. When an SOI substrate is used, the fin structure can protrude from the silicon layer of the SOI substrate or it can protrude from the insulator layer of the SOI substrate. In the latter case, the silicon layer of the SOI substrate is used to form the fin structure. Amorphous substrates, such as amorphous Si or amorphous SiC, or insulating material, such as silicon dioxide, can also be used as substrate 10.The substrate 10 can have different regions that are suitably doped with impurities (e.g. p-type or n-type conductivity).

[0013] The mask layer 15 comprises, for example, a contact point oxide layer (e.g., silicon oxide) 15A and a silicon nitride mask layer 15B in some embodiments. The contact point oxide layer 15A can be formed by thermal oxidation or a CVD process. The silicon nitride mask layer 15B can be formed by physical vapor deposition (PVD), such as sputtering, CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD), atomic layer deposition (ALD), and / or other methods.

[0014] The thickness of the contact point oxide layer 15A ranges from approximately 2 nm to approximately 15 nm, and the thickness of the silicon nitride mask layer 15B ranges from approximately 2 nm to approximately 50 nm in some embodiments. A mask pattern is also formed over the mask layer. This mask pattern is, for example, a resist pattern formed by lithography.

[0015] By using the mask pattern as an etching mask, a hard mask pattern 15 is formed from the contact point oxide layer and the silicon nitride mask layer, as shown in Fig. 2 shown.

[0016] Then, as in Fig. Figure 3 shows that, using the hard mask pattern 15 as an etching mask, the substrate 10 is structured into fin structures 20 by trench etching with a dry etching process and / or a wet etching process.

[0017] In Fig. In the 3 embodiment, three fin structures 20 are arranged over the substrate 10. However, the number of fin structures is not limited to three. The number can be as small as one or more than three. In some embodiments, the number of fin structures ranges from 5 to 1000, connected by a source / drain epitaxy layer formed in subsequent operations. In other embodiments, the number of fin structures ranges from 5 to 100, connected by source / drain epitaxy layers formed in subsequent operations. In certain embodiments, the number of fin structures ranges from 5 to 20, connected by source / drain epitaxy layers formed in subsequent operations. Additionally, one or more dummy fin structures can be arranged on both sides of the fin structure 20 to improve pattern fidelity in structuring processes.

[0018] The fin structure 20 can be made of the same material as the substrate 10 and extend continuously from the substrate 10. In this embodiment, the fin structure is made of silicon. The silicon layer of the fin structure 20 can be intrinsic or doped with an n-type or p-type impurity.

[0019] The width W1 of the fin structure 20 ranges from approximately 3 nm to approximately 40 nm in some embodiments and from approximately 7 nm to approximately 12 nm in other embodiments. The distance S1 between two fin structures ranges from approximately 10 nm to approximately 50 nm in some embodiments. The height (along the Z-direction) of the fin structure 20 ranges from approximately 100 nm to approximately 300 nm in some embodiments and from approximately 50 nm to 100 nm in other embodiments.

[0020] The lower part of the fin structure 20 below the gate structure 40 (see Fig. 6A) can be referred to as the trough area, and the upper part of the fin structure 20 can be referred to as the channel area. Below the gate structure 40, the trough area merges into the insulation layer 30 (see Fig. 6A) embedded, and the channel area protrudes from the insulating layer 30. A lower part of the channel area may also be embedded in the insulating layer 30 to a depth of approximately 1 nm to approximately 5 nm.

[0021] In some embodiments, the height of the basin area is in a range of about 60 nm to 100 nm, and the height of the channel area is in a range of about 40 nm to 60 nm, and in other embodiments in a range of about 38 nm to about 55 nm.

[0022] After the fin structures 20 are formed, the substrate 10 is further etched to form a mesaform 10M in some embodiments, as shown in Fig. Figure 4 shows. In other embodiments, the mesa form 10M is formed first, and then the fin structures 20 are formed. In certain embodiments, no mesa form is formed.

[0023] After the fin structures 20 and the mesa form 10M have been formed, in S102 of Fig. 1. An insulating insulation layer 30 is formed in the spaces between the fin structures and / or in a space between a fin structure and another element formed above the substrate 10. The insulating insulation layer 30 can also be referred to as a shallow-trench insulation (STI) layer. The insulating material for the insulating insulation layer 30 can comprise one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a dielectric material with a low k-value. The insulating insulation layer is formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, flowable dielectric materials can be deposited instead of silicon oxide.Flowable dielectric materials, as their name suggests, can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to the silicon-containing precursors to enable the deposited layer to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methylsilsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ / HSQ, a perhydrosilazane (TCPS), a perhydropolysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silylamine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multi-step process. After the flowable film is deposited, it is cured and then annealed to remove unwanted elements and form silicon oxide.When the unwanted element(s) is / are removed, the flowable film densifies and shrinks. In some embodiments, several annealing processes are carried out. The flowable film is hardened and tempered more than once. The flowable film may be doped with boron and / or phosphorus.

[0024] The insulating layer 30 is first formed in a thick layer so that the fin structures are embedded in the thick layer, and the thick layer is deepened so that the upper sections of the fin structures 20 are exposed, as shown in Fig. Figure 5 shows that the height H11 of the fin structures from the upper surface of the insulating layer 30 is in some embodiments in a range of about 20 nm to about 100 nm and in other embodiments in a range of about 30 nm to about 50 nm. A thermal process, e.g., an annealing process, can be carried out before or after the embedding of the insulating layer 30 to improve its quality. In certain embodiments, the thermal process is carried out using rapid thermal annealing (RTA) at a temperature in the range of about 900 °C to about 1050 °C for about 1.5 seconds to about 10 seconds in an inert gas environment, such as an N2, Ar, or He environment.

[0025] After the insulating layer 30 has formed, S103 is used. Fig. 1 a victim-gate structure 40 formed over the fin structures 20, as in Fig. 6A-6C shown. Fig. 6A is an exemplary perspective view, Fig. 6B is an exemplary cross-sectional view along line aa of Fig. 6A and Fig. 6C is an exemplary cross-sectional view along line bb of Fig. 6A. The Fig. Figures 7, 8A, 10A and 11-20 are also cross-sectional views along line bb of Fig. 6A. Fig. 8B and Fig. 10B are cross-sectional views along line cc of Fig. 6A.

[0026] As in Fig. As shown in Figure 6A, the sacrificial gate structure 40 extends in the X direction, while the fin structures 20 extend in the Y direction. To fabricate the sacrificial gate structure 40, a dielectric layer and a polysilicon layer are formed over the insulating layer 30 and the exposed fin structures 20. Then, structuring operations are performed to capture sacrificial gate structures comprising a polysilicon sacrificial gate pattern 44 and a dielectric sacrificial layer 42. In some embodiments, the polysilicon layer is structured using a hard mask, and the hard mask remains on the gate pattern 44 as the hard mask layer 46. The hard mask layer 46 comprises one or more layers of insulating material. In some embodiments, the hard mask layer 46 comprises a silicon oxide layer 46-2 formed over a silicon nitride layer 46-1.In other embodiments, the hard mask layer 46 comprises a silicon nitride layer formed over a silicon oxide layer. The insulating material for the hard mask layer 46 can be formed by CVD, PVD, ALD, E-beam evaporation, or other suitable methods. In some embodiments, the dielectric sacrificial layer 42 can comprise one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectrics. In some embodiments, the thickness of the dielectric layer 42 is in the range of about 2 nm to about 20 nm, and in other embodiments, in the range of about 2 nm to about 10 nm. The height H12 of the sacrificial gate structures is in the range of about 50 nm to about 400 nm in some embodiments and in the range of about 100 nm to 200 nm in other embodiments.

[0027] Furthermore, in S104 of Fig. 1 Gate sidewall spacers 48 are formed on both sidewalls of the sacrificial gate pattern. The sidewall spacers 48 comprise one or more layers of insulating material, such as SiO2, SiN, SiON, SiOCN, or SiCN, formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. A dielectric material with a low k-value can be used as the sidewall spacer. The sidewall spacers 48 are formed by forming a planar layer of insulating material and subsequent anisotropic etching. In one embodiment, the sidewall spacer layers 48 consist of a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN. In some embodiments, the sidewall spacers 48 are also formed on the sidewalls of the exposed fin structures 20, as shown in Fig. 6C shown.

[0028] In some embodiments, S105 is used by Fig. 1 one or more ion implantation processes were performed to implant ions into the source / drain region of the fin structure upstream and / or downstream of the gate sidewall spacers 48 to form a lightly doped drain structure (LDD).

[0029] Then, as in Fig. 7 shown, at S106 of Fig. 1. A fin mask layer 50 (fin sidewall) is formed over the fin structures 20. The fin mask layer 50 consists of a dielectric material comprising silicon nitride-based materials such as SiN, SiON, SiOCN, or SiCN. In one embodiment, SiN is used as the fin mask layer 50. The fin mask layer 50 is produced by CVD, PVD, ALD, electron beam evaporation, or other suitable methods. The thickness of the fin mask layer 50 is in the range of approximately 3 nm to approximately 30 nm in some embodiments.

[0030] After the formation of the fin mask layer 50, at S107 from Fig. 1. The upper part of the fin structures 20 is recessed, and part of the fin mask layer 50 and the sidewall spacers 48 are removed by dry etching and / or wet etching. The upper part of the fin structures 20 is recessed (etched) to the level that is equal to or below the upper surface of the fin mask layer 50 on the upper insulating layer 30, as shown in Fig. 8A shown.

[0031] In some embodiments, the recess 22 is formed separately for an n-type FET and a p-type FET. In some embodiments, the recess 22 (and the subsequent epitaxial layer) for an n-type FET is formed first, while the area for a p-type FET is covered by a cover layer 49 (e.g., silicon nitride) (see Fig. 9B), and then the recess 22 (and the subsequent epitaxial layer) for the p-type FET is formed, while the area for the n-type FET is covered by a cover layer (see S113 and S114 in Fig. 1).

[0032] In some embodiments, the upper surface of the recessed fin structure 20 (the bottom of the recess 22) is located above the upper surface of the insulating layer 30, as shown in Fig. 8A shown. In other embodiments, the top of the recessed fin structure 20 (the bottom of the recess 22) is at the same level as the top of the insulation layer 30 or deeper than it.

[0033] In some embodiments, the etching of the fin mask layer 50 and the sidewall spacer 48 is asymmetric with respect to the fin structure depending on the distance between two adjacent fin structures and a distance between the two adjacent fin structures and another fin structure, as shown in Fig. 8B shown. Fig. Figure 8B also shows a fin structure in front of the recess (or below the sacrificial gate structure). In some embodiments, the remaining fin mask layer 50 and the side wall spacer 48 of one of the two adjacent fin structures on the side facing the other fin structure have a lower height than the remaining fin mask layer 50 and the side wall spacer 48 of one of the two adjacent fin structures on the other side. In other embodiments, the height ratio is reversed.

[0034] In some embodiments, the upper surface of the recessed fin structure 20 has a U-shape, a W-shape or a corrugated shape.

[0035] In S109 of Fig. 1. An epitaxial source / drain structure for an n-type FET is formed over the recessed fin structures 20. The epitaxial source / drain structure consists of one or more layers of semiconductor material with a different lattice constant than that of the fin structures 20 (channel regions). In Fig. Figures 9A-13B and 16A-16B show the “A” figures cross-sectional views along the X direction (gate extension direction) and the “B” figures cross-sectional views along the Y direction (fin extension direction).

[0036] In some embodiments, such as in Fig. 9A and Fig. As shown in Figure 9B, a first epitaxial layer 62 is formed over the recessed fin structure 20. In some embodiments, the first epitaxial layer 62 comprises SiAs and / or SiGeAs, which can suppress the diffusion of phosphorus (P) from the subsequently formed second epitaxial layer into the channel region of the fin structure. In some embodiments, the As concentration in the first epitaxial layer 62 is in the range of approximately 5 × 10⁻⁶ 19 atoms / cm² 3 up to about 5×10 21 atoms / cm² 3 and in other embodiments in a range of about 1×10 20 atoms / cm² 3 up to about 2×10 21 atoms / cm² 3If the As concentration is too low, the diffusion barrier effect against P is insufficient. It is difficult to contain As beyond the upper limit of the region, and a high As concentration would reduce the stress exerted on the channel and increase the resistance. In other embodiments, SiGe doped with P is used as the first epitaxial layer 62.

[0037] In some embodiments, the thickness T0 of the first epitaxial layer 62 is in the range of about 3 nm to about 20 nm, and in other embodiments in the range of about 10 nm to about 15 nm. If the thickness T0 is too small, the diffusion barrier effect against P is insufficient, and if the thickness is too large, it would reduce the stress exerted on the channel and increase the resistance. In some embodiments, the first epitaxial layer 62 is deposited to the level corresponding to or slightly below the bottom of the gate sidewall spacers 48 (less than 2 nm).

[0038] In some embodiments, the epitaxial growth of the first epitaxial layer 62 comprises one or more deposition phases and one or more etching phases to control the shape of the epitaxial layer. The deposition and etching phases can be performed alternatively. In some embodiments, the substrate 10 is a (100) Si substrate. The first SiAs epitaxial layer grows faster along the (100) face than on the (110) and (111) faces. After etching, however, the first SiAs epitaxial layer 62 forms the facet (111) on the top side and etches faster along the (110) and (111) directions than along the (100) direction. Accordingly, in some embodiments, there is a thickness difference between the bottom and the side of the first epitaxial layer.In some embodiments, the bottom thickness is greater than the side thickness, and the difference between the thickness of the bottom (along the vertical or Z direction) and along the channel side (along the Y direction) is in a range of about 5 nm to about 10 nm.

[0039] After the first epitaxial layer 62 is formed, the second epitaxial layer 64, comprising a lower layer 64-1 and an upper layer 64-2, is formed on top of the first epitaxial layer, as shown in Fig. 10A, Fig. 10B, Fig. 11A and Fig. Figure 11B shows that in some embodiments the second epitaxial layer comprises 64 SiP or SiCP.

[0040] In some embodiments, the phosphorus (P) concentration in the second epitaxial layer 64 is in a range of approximately 2×10 20 atoms / cm² 3 up to about 1×10 22 atoms / cm² 3 and in other embodiments in a range of about 5×10 20atoms / cm² 3 up to about 5×10 21 atoms / cm² 3 If the P concentration is too low, the resistance of the second epitaxial layer increases, and if the P concentration is too high, the voltage exerted on the channel is reduced.

[0041] As in Fig. 10A and Fig. As shown in Figure 10B, the lower layer 64-1 is grown substantially symmetrically with respect to the respective fin structures. In some embodiments, the epitaxial growth of the lower epitaxial layer 64-1 comprises one or more deposition phases and one or more etching phases to control the shape of the epitaxial layer, which can be performed alternatively. After the last etching phase, in some embodiments the (110) facet is formed on the top surface of the lower layer 64-1. As shown in Fig. As shown in Figure 10A, the lower layer 64-1 of the second epitaxial layer does not fuse with the lower layer 64-1 above the adjacent fin structure.

[0042] Then, as in Fig. 11A and Fig. As shown in Figure 11B, the upper layer 64-2 is formed such that the second epitaxial layers of the adjacent fin structures grow together through the upper layer 64-2. As shown in Fig. As shown in Figure 11A, the fusion point is located at a relatively high level above the surface of the insulating layer 30. If the fin height (below the sacrificial gate structure) is H2 from the upper surface of the insulating layer, the height H1 of the underside of the fusion point is in some embodiments in a range of approximately 0.5 H2 to approximately 0.8 H2, and in other embodiments in a range of approximately 0.65 H2 to 0.75 H2. The thickness H3 of the upper layer 64-2 at the fusion point is in some embodiments in a range of approximately 7 nm to approximately 30 nm. As shown in Fig. As shown in Figure 10A, a gap 65 is formed below the fusion point. After the upper layer 64-2 is formed, the upper surface of the second epitaxial layer 64 has a wave-like shape with a peak-to-valley contour in a range of about 2 nm to about 10 nm in the Z-direction in some embodiments.

[0043] In some embodiments, the phosphorus concentration in the lower layer 64-1 is the same as or different from the phosphorus concentration in the upper layer 64-2. In some embodiments, the upper layer 64-2 is formed after the etching phase of the lower layer 64-1. No etching phase is included during the formation of the upper layer 64-2. The thickness of the second epitaxial layer along the Z-direction is in a range of approximately 10 nm to approximately 50 nm in some embodiments. In some embodiments, the second epitaxial layer 64 is deposited up to the level corresponding to or slightly below (less than 2 nm) the base of the gate sidewall spacers 48. In other embodiments, the second epitaxial layer 64 is deposited slightly above (less than 2 nm) the top surface of the fin structure 20 beneath the sacrificial gate structure.In some embodiments, the thickness ratio of the upper layer 64-2 to the lower layer 64-1 along the vertical direction above the fin structure is in a range of about 0.1 to about 0.3.

[0044] Then, as in Fig. 12A and Fig. Figure 12B shows a third epitaxial layer 66 formed on the second epitaxial layer 64. In some embodiments, the third epitaxial layer 66 comprises SiP or SiCP. In some embodiments, the third epitaxial layer 66 further comprises Ge to reduce the contact resistance for a subsequently formed source / drain contact.

[0045] In some embodiments, the phosphorus (P) concentration in the third epitaxial layer 66 is equal to or less than that in the second epitaxial layer 64 and is in a range of approximately 2×10 20 atoms / cm² 3 up to about 1×10 22 atoms / cm² 3, and in other embodiments in a range of about 5×10 20 atoms / cm² 3 up to about 5×10 21 atoms / cm² 3If the phosphorus concentration is too low, the resistance of the second epitaxial layer increases, and if the phosphorus concentration is too high, it reduces the stress applied to the channel. In some embodiments, the germanium concentration in the third epitaxial layer 66 is in the range of about 0.2 atomic percent to about 10 atomic percent, and in other embodiments in the range of about 0.5 atomic percent to about 5 atomic percent. A small amount of germanium contributes to TiSi formation and reduces contact resistance, and if the amount is too small, such an effect cannot be achieved. If the germanium concentration is too high, it induces germanium agglomeration during TiSi formation, increasing contact resistance and defects, and also reducing the stress in the epitaxial layers.In some embodiments, the epitaxial growth of the third epitaxial layer 66 comprises one or more deposition phases and one or more etching phases that control the shape of the epitaxial layer, which can be carried out alternatively. The thickness of the third epitaxial layer along the Z-direction is in a range of approximately 5 nm to approximately 10 nm in some embodiments. If the thickness is too small, it would not achieve the desired shape of the epitaxial layers. If the thickness is too large, it would merge with adjacent devices, either NFETs or PFETs, and the wave-like shape would also be compromised. In some embodiments, the third epitaxial layer 66 completely covers the surface of the second epitaxial layer 64 except for the gap 65 and is in contact with the first epitaxial layer.In some embodiments, the first and third epitaxial layers, which sandwich the second epitaxial layer, suppress the diffusion of phosphorus from the second epitaxial layer into the channel region or a metal-gate electrode. Furthermore, as in . Fig. 13A and Fig. Figure 13B shows a fourth epitaxial layer 68 as a cover layer on the third epitaxial layer 66. In some embodiments, the fourth epitaxial layer 68 comprises SiP or SiCP. In some embodiments, the fourth epitaxial layer does not comprise Ge.

[0046] In some embodiments, the phosphorus (P) concentration in the fourth epitaxial layer 68 is the same as or different from that in the third epitaxial layer 66 and is in a range of about 2×10 20 atoms / cm² 3 up to about 1×10 22 atoms / cm² 3 and in other embodiments in a range of about 5×10 20 atoms / cm² 3up to about 5×10 21 atoms / cm² 3 The thickness of the fourth epitaxial layer 68 along the Z-direction is in some embodiments in a range of approximately 5 nm to approximately 10 nm. The fourth epitaxial layer 68 is grown mainly in the (100) direction, thereby preserving the (100) shape on the fin structure and the (110) shape between the fin structures. As in Fig. As shown in Figure 13A, the first to fourth epitaxial layers are collectively referred to as the source / drain epitaxial layer (structure) 60.

[0047] Fig. Figure 14 shows a line drawing of a TEM image of the source / drain structure 60. Due to the transmissive nature of TEM, a fin structure is also visible below the sacrificial gate. Fig. 14 The dimension T1 corresponds to the thickness of the first epitaxial layer 62 and in some embodiments lies in a range of about 5 nm to about 20 nm. In some embodiments, the top surface of the first epitaxial layer 62 is located at about 80% to about 100% of the height of the fin mask layer 50 and / or the sidewall spacers 48 on the fin structure from the top surface of the insulating layer 30.

[0048] Dimension T2 is the height of the underside of the fusion point from the top surface of the insulating layer 30 and, in some embodiments, lies in a range of approximately 20 nm to approximately 50 nm. In some embodiments, the fusion point is located at or above 75% of the height T6 of the top surface of the fin structure beneath the sacrificial gate structure from the upper surface of the insulating layer. The high fusion point of the second epitaxial layer can improve a short-channel effect.

[0049] Dimension T3 is the distance between the top surface of the first epitaxial layer and the underside of the fusion point. Dimension T4 is the thickness of the fusion point. The fusion point is defined at the midpoint of the adjacent fin structures. In some embodiments, the thickness T4 ranges from approximately 5 nm to approximately 20 nm, depending on the process and / or design requirements. If the thickness T4 is too small, the clearance for source / drain contact may be insufficient; if the thickness T4 is too thick, the top surface of the source / drain epitaxial layer may be flatter, which would increase the contact resistance for the source / drain contact. Dimension T5 is the thickness of the source / drain epitaxial layer above the top surface of the fin structure and, in some embodiments, ranges from approximately 2 nm to approximately 10 nm.If the thickness T5 is too small, the clearance for a source / drain contact may be insufficient, and if the thickness T5 is too thick, the upper surface of the source / drain epitaxy layer may be flatter, which would increase the contact resistance for the source / drain contact.

[0050] Dimension T6 is the height of the fins (channels) from the underside of the first epitaxial layer (or the top side of the insulation-insulation layer) to the top of the fin structure and ranges from approximately 40 nm to approximately 80 nm, depending on process and / or design requirements. Dimension T7 is the total height of the source / drain epitaxial layer from the underside of the first epitaxial layer (or the top side of the insulation-insulation layer) to the top of the source / drain epitaxial layer and ranges from approximately 50 nm to approximately 90 nm, depending on process and / or design requirements. In some embodiments, the ratio T4 / T7 ranges from approximately 0.1 to approximately 0.3, and in other embodiments, from approximately 0.15 to approximately 0.25.The dimension W is the total (maximum) width of the intergrown source / drain epitaxy layer 60 and lies in a range of approximately 40 nm to approximately 80 nm, depending on the process and / or design requirements.

[0051] Fig. Figure 15 shows a process flow for the fabrication of the source / drain epitaxy layer 60 for an n-type FET according to the embodiments of the present disclosure. After the source / drain region of the fin structure has been recessed to form a source / drain space 22, a pre-cleaning process is carried out as shown in Fig. Figure 15 shows that in some embodiments, the pre-cleaning process includes plasma treatment with Ar and / or NH3 plasma. The process temperature in some embodiments is in the range of approximately 300 °C to approximately 600 °C. A pre-etching process is then performed to control the shape of the subsequently formed epitaxial layer, as shown in Figure 15. Fig. Figure 15 shows that in some embodiments, the pre-etching process is carried out in an environment containing H₂ and HCl gas. The process temperature is higher than that of the pre-cleaning process and, in some embodiments, is in the range of approximately 550 °C to approximately 750 °C.

[0052] Then the first epitaxial layer 62 (in Fig. 15 (designated as L1) is formed using a silicon-containing gas, such as SiH4, Si2H6, or SiCl2H2, and a doping gas, such as AsH3 or organic As, with H2 as the carrier gas. The process temperature for the formation of the first epitaxial layer 62 is equal to or higher than that of the pre-etching process and, in some embodiments, is in the range of about 650 °C to about 750 °C. After the first epitaxial layer 62 has been formed, an etching process is carried out to control the shape of the epitaxial layer. In some embodiments, the etching process includes a plasma or dry treatment with N2 and HCl gas. The process temperature is higher than the growth temperature of the first epitaxial layer and, in some embodiments, is in the range of about 700 °C to about 800 °C.

[0053] After the first epitaxial layer 62 has been formed and etched, a second epitaxial layer 64 (64-1 and 64-2) (in Fig. 15 (designated as L2). The process temperature for the formation of the second epitaxial layer 64 is lower than that of the L1 etching process and that of the formation of the first epitaxial layer 62, and in some embodiments lies in the range of about 600 °C to about 700 °C. The second epitaxial layer 64 is formed using a silicon-containing gas, such as SiH4, Si2H6, or SiCl2H2, and a dopant gas, such as PH3 or organic As, with H2 or N2 as the carrier gas.

[0054] In some embodiments, a cleaning process is optionally carried out after the formation of the second epitaxial layer 64. The cleaning process comprises dry chemical cleaning (etching) using SiH4 and / or GeH4 and HCl gases. The process temperature of the cleaning process is lower than that of the formation of the first epitaxial layer 62 and higher than that of the formation of the second epitaxial layer 64, and in some embodiments is in the range of approximately 650 °C to approximately 750 °C.

[0055] After the cleaning process, a third epitaxial layer 66 (in Fig. 15 (designated as L3). The process temperature for forming the third epitaxial layer 66 is higher than that for forming the first and second epitaxial layers and, in some embodiments, is in the range of approximately 650 °C to approximately 750 °C. The third epitaxial layer 66 is formed using a silicon-containing gas, such as SiH4, Si2H6, or SiCl2H2, a germanium-containing gas, such as GeH4 or Ge2H6, and a doping gas, such as PH3 or organic arsenic, with H2 or N2 as the carrier gas. After the third epitaxial layer 66 has been formed, an etching process is carried out to control the shape of the epitaxial layer. In some embodiments, the etching process includes a plasma or dry treatment with GeH4, H2, and HCl gas. The process temperature is higher than the growth temperature of the third epitaxial layer and in some embodiments is in a range of about 750 °C to about 800 °C.L3 etching creates a V-shape between the fin structures.

[0056] Then the fourth epitaxial layer 68 (in Fig. 15 (designated as L4) is formed using a silicon-containing gas, such as SiH4, Si2H6, or SiCl2H2, and a dopant gas, such as PH3 or organic As, with H2 or N2 as the carrier gas. The process temperature for the formation of the fourth epitaxial layer 68 is lower than that of the L3 etching process and the L3 deposition and, in some embodiments, is in the range of about 650 °C to about 750 °C.

[0057] After the epitaxial layer 60 has been formed for an n-type FET, in some embodiments the fin mask layer and the side wall are removed, specifically in S110 in Fig. 1. In other embodiments, the fin mask layer and the spacers on the side wall are not removed. In some embodiments, the cover layer covering the p-type area is also removed in S110. Fig. 1 removed, followed by a cleaning process in S111 of Fig. 1.

[0058] Then, similar to S106, S112 will be affected by Fig. 1. A fin mask layer (fin sidewall) is formed for a p-type FET, and then at S113... Fig. 1. A recess was formed in the source / drain region of the fin structure for a p-type FET. The procedure for producing the recess for a p-type FET is the same or similar to the procedure for producing recess 22 for the n-type FET. In S114 of Fig. 1. A cleaning process similar to that of S108 is performed.

[0059] Then in S115 from Fig. 1. An epitaxial source / drain structure for a p-type FET is formed over the recessed fin structures 20. The epitaxial source / drain structure consists of one or more layers of semiconductor material with a different lattice constant than that of the fin structures 20 (channel regions). If the fin structures are made of Si, the epitaxial source / drain structure comprises SiGe or Ge for a p-channel FIN FET. The epitaxial source / drain structure is formed epitaxially over the upper regions of the recessed fin structures. The epitaxial source / drain layer can be grown at a temperature of about 600 to 800 °C under a pressure of about 10,665.8 to 19,998.4 Pa (about 80 to 150 Torr) using a silicon-containing gas, such as SiH₄, Si₂H₆, or SiCl₂H₂, and a germanium-containing gas, such as GeH₄, Ge₂H₆, or GeCl₂H₂. In some embodiments, the source / drain epitaxial layer further comprises boron.

[0060] Then at S117 from Fig. 1, as in Fig. 16A, Fig. 16B and Fig. Figure 16C shows an insulating layer, acting as a contact etch stop layer, formed over the metal gate structure and the source / drain structures 60, and then an intermediate dielectric layer (ILD) 90 is formed. The ILD 90 is one or more layers of insulating material. In one embodiment, the etch stop layer consists of silicon nitride formed by CVD. Materials for the ILD 90 include compounds containing Si, O, C, and / or H, such as silicon dioxide, SiCOH, and SiOC. Organic materials, such as polymers, can also be used for the ILD 90.

[0061] Then in S118 from Fig. 1. A metal gate structure is formed using a gate replacement technology. After the formation of the dielectric intermediate layer 90, a CMP process is performed to expose the dummy gate electrode 44. The dummy gate structures (dummy gate electrode 44 and the dielectric dummy gate layer 42) are then removed and replaced by a metal gate structure (metal gate electrode 86 and the dielectric gate layer 82), as shown in Fig. 16B and Fig. 16C shown.

[0062] The dummy gate electrode 44 and the dummy gate dielectric layer 42 are each removed by suitable etching processes to form a gate opening. Metal gate structures are formed in the gate openings, comprising the gate dielectric layer 82 and the metal gate electrode 86.

[0063] In some embodiments, the dielectric gate layer 82 is formed above an interface layer (not shown) arranged above the channel layer of the fin structures 20. In some embodiments, the interface layer may comprise silicon oxide or germanium oxide with a thickness of 0.2 nm to 1.5 nm. In other embodiments, the thickness of the interface layer is in the range of approximately 0.5 nm to approximately 1.0 nm.

[0064] The gate dielectric layer 82 comprises one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectrics, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer is formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or other suitable processes and / or combinations thereof. The thickness of the dielectric gate layer is in some embodiments in a range of about 1 nm to about 10 nm and in other embodiments in a range of about 2 nm to about 7 nm.

[0065] The gate dielectric layer is superimposed by the metal gate electrode 86. The metal gate electrode 86 comprises one or more layers of any suitable metallic material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0066] In certain embodiments of the present disclosure, one or more functional matching layers 84N, 84P are arranged between the gate dielectric layer and the metal gate electrode. The functional matching layer consists of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multiple layer of two or more of these materials. For the n-channel FIN-FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the functional matching layer 84N, and for the p-channel FIN-FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the functional matching layer 84P.

[0067] After the deposition of suitable materials for the metal gate structures, planarization operations such as CMP are performed.

[0068] After the metal-gate structure is formed, one or more dielectric intermediate layers are formed over the metal-gate structure and the dielectric intermediate layer 90. The dielectric intermediate layers are collectively referred to as the dielectric intermediate layer 95, as shown in Fig. 17 shown. Fig. Figure 17 shows a line drawing of a TEM image of the source / drain structure 60 and the source / drain contact.

[0069] In S119 of Fig. 1. A contact hole is formed in the dielectric intermediate layer 95 by a structuring process that includes lithography, in order to expose the epitaxial source and drain structures 60. The contact hole is then filled with a conductive material, forming a contact plug 100, as shown in Fig. Figure 17 shows the contact plug 100, which can comprise a single layer or multiple layers of any suitable metal such as Co, W, Ti, Ta, Cu, Al and / or Ni and / or nitride thereof.

[0070] After the contact connector is formed, CMOS processes are further carried out to create various features such as additional dielectric intermediate layers, contacts / vias, connecting metal layers and passivation layers, etc.

[0071] In some embodiments, S106 refers to Fig. 1. After the epitaxial source / drain structure 60 was formed, a silicide layer 70 (see Fig. 17) formed over the epitaxial source / drain structure 60. A metallic material, such as Ni, Ti, Ta, and / or W, is formed over the epitaxial source / drain structure 60, and an annealing process is carried out to form a silicide layer 70. In other embodiments, a silicide material, such as NiSi, TiSi, TaSi, and / or WSi, is formed over the epitaxial source / drain structure 60, and an annealing process may be carried out. The annealing process is carried out at a temperature of about 250 °C to about 850 °C. The metallic material or the silicide material is formed by CVD or ALD. The thickness of the silicide layer 70 is in the range of about 4 nm to about 10 nm in some embodiments. Before or after the annealing processes, the metallic material or the silicide material formed over the insulating layer 30 is selectively removed.

[0072] In other embodiments, the silicide layer 70 is formed after the contact hole is opened. In such a case, after the formation of the epitaxial source / drain structure 60, the metal gate structures, the contact etch stop layer, and the dielectric intermediate layer 95 are formed without the formation of a silicide layer. Then, a contact hole is formed in the dielectric intermediate layer 95 to expose the upper surface of the epitaxial source / drain structure 60, and a silicide layer is then formed on the upper surface of the epitaxial source / drain structure 60. After the formation of the silicide layer, the conductive material is formed in the contact hole, thereby forming a contact plug.

[0073] Fig. Figure 18 shows an elemental analysis in a depth direction Z as in Fig. 13B shown after the source / drain epitaxy layer 60 was formed. As in Fig.As shown in Figure 18, arsenic in the first epitaxial layer 62 (L1) can effectively suppress the diffusion of P from the second epitaxial layer 64 (L2) into the fin structure.

[0074] Although the preceding embodiments describe a FinFET, the technologies disclosed in the present disclosure are also applicable to other types of FETs, e.g., a planar FET and a gate all-around FET (GAA) using a nanowire or nanosheet semiconductor.

[0075] In the embodiments of the present disclosure, the formation of a SiAs layer as the first epitaxial layer makes it possible to suppress the diffusion of P from the second epitaxial layer into the canal region. Furthermore, it is possible to improve short canal effects by positioning a fusion point of the united epitaxial layer at a relatively high location.

[0076] It goes without saying that not all advantages have necessarily been discussed here, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0077] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a first fin structure and a second fin structure are formed over a substrate, an insulation layer is formed over the substrate such that lower sections of the first and second fin structures are embedded in the insulation layer and upper sections of the first and second fin structures are exposed by the insulation layer, a gate structure is formed over channel regions of the first and second fin structures, source / drain regions of the first and second fin structures are recessed, and an epitaxial source / drain structure is formed over the recessed first and second fin structures.The epitaxial source / drain structure is an intergrown structure with an intergrowth point, and the height of the base of the intergrowth point from the upper surface of the insulation layer is 50% or more of the height of the channel regions of the first and second fin structures from the upper surface of the insulation layer. In one or more of the preceding and following embodiments, the height of the base of the intergrowth point from the upper surface of the insulation layer is 75% or more of the height of the channel regions of the first and second fin structures from the upper surface of the insulation layer. In one or more of the preceding and following embodiments, the epitaxial source / drain structure comprises a first, second, third, and fourth epitaxial layer formed in that order above the recessed first and second fin structures.In one or more of the preceding and following embodiments, the first epitaxial layer above the recessed first fin structure and the first epitaxial layer above the recessed second fin structure are not fused together, and the second epitaxial layer forms the fusion point. In one or more of the preceding and following embodiments, the first epitaxial layer comprises SiAs and the second epitaxial layer comprises SiP. In one or more of the preceding and following embodiments, the third epitaxial layer comprises Ge-doped SiP, and the fourth epitaxial layer comprises SiP. In one or more of the preceding and following embodiments, the P concentration of the second epitaxial layer is highest in the first through fourth epitaxial layers. In one or more of the preceding and following embodiments, the third epitaxial layer is in contact with the first epitaxial layer.

[0078] According to a further aspect of the present disclosure, in a method for manufacturing a semiconductor device, a first fin structure and a second fin structure are formed over a substrate, an insulating layer is formed over the substrate such that lower sections of the first and second fin structures are embedded in the insulating layer and upper sections of the first and second fin structures are exposed by the insulating layer, fin sidewalls are formed on opposite side faces of source / drain regions of the first and second fin structures, source / drain regions of the first and second fin structures are recessed, a first epitaxial layer is formed over the recessed first and second fin structures, and a second epitaxial layer with a different composition than the first epitaxial layer is formed over the first epitaxial layer.to form an fused second epitaxial layer with a fusion point. The height of the base of the fusion point from the upper surface of the insulating layer is 50% or more of the height of the channel regions of the first and second fin structures from the upper surface of the insulating layer. In one or more of the preceding and following embodiments, the formation of the second epitaxial layer comprises one or more deposition phases and one or more etching phases, performed alternately. In one or more of the preceding and following embodiments, the formation of the second epitaxial layer comprises the formation of a lower layer over the first epitaxial layer, which does not form the fused second epitaxial layer, and the formation of an upper layer over the lower layer, which forms the second epitaxial layer.and the formation of the upper layer does not include an etching phase. In one or more of the preceding and following embodiments, the upper layer is formed after the etching phase of the lower layer. In one or more of the preceding and following embodiments, the first epitaxial layer comprises SiAs with an As concentration in the range of 1 × 10⁻⁶. 20 atoms / cm² 3 up to 2×10 21 atoms / cm² 3 In one or more of the preceding and following embodiments, the second epitaxial layer comprises SiP with a P concentration in the range of 5×10 20 atoms / cm² 3 up to 5×10 21 atoms / cm² 3In one or more of the preceding and following embodiments, the first epitaxial layer is configured such that it does not extend beyond the upper surface of the fin sidewalls. In one or more of the preceding and following embodiments, the fin sidewalls comprise multiple layers.

[0079] According to a further aspect of the present disclosure, in a method for manufacturing a semiconductor device, a first fin structure and a second fin structure are formed over a substrate, an insulating layer is formed over the substrate such that lower sections of the first and second fin structures are embedded in the insulating layer and upper sections of the first and second fin structures are exposed by the insulating layer, fin sidewalls lie on opposite side faces of source / drain regions of the first and second fin structures, source / drain regions of the first and second fin structures are recessed, a first epitaxial layer is formed over the recessed first and second fin structures, each at a first temperature, and an etching process is carried out on the first epitaxial layer at a second temperature.A second epitaxial layer with a different composition than the first epitaxial layer is formed over the first epitaxial layer at a third temperature; a third epitaxial layer with a different composition than the second epitaxial layer is formed over the second epitaxial layer at a fourth temperature; an etching process is carried out on the third epitaxial layer at a fifth temperature; and a fourth epitaxial layer with a different composition than the third epitaxial layer is formed over the third epitaxial layer at a sixth temperature. In one or more of the preceding and following embodiments, the second epitaxial layer forms an fused second epitaxial layer with a fusion point.and the height of the base of the fusion point from an upper surface of the insulating layer is 50% or more of the height of the channel regions of the first and second fin structures from the upper surface of the insulating layer. In one or more of the preceding and following embodiments, the formation of the second epitaxial layer comprises one or more deposition phases and one or more etching phases, which are carried out alternately. In one or more of the preceding and following embodiments, the formation of the second epitaxial layer comprises the formation of a lower layer over the first epitaxial layer, which does not form the fused second epitaxial layer, and the formation of an upper layer over the lower layer, which forms the second epitaxial layer, and the formation of the upper layer does not include an etching phase. In one or more of the preceding and following embodiments,where the second temperature is higher than the first temperature. In one or more of the preceding and following embodiments, the third temperature is lower than the second temperature. In one or more of the preceding and following embodiments, the fourth temperature is higher than the third temperature. In one or more of the preceding and following embodiments, the fifth temperature is higher than the fourth temperature.

[0080] According to another aspect of the present disclosure, a semiconductor device comprises an insulating layer arranged over a substrate, a first fin structure and a second fin structure arranged over the substrate, a gate structure arranged over channel regions of the first and second fin structures, and a source / drain epitaxy layer over source / drain regions of the first and second fin structures. The source / drain epitaxy layer has a fused structure with a fusion point, and the height of the base of the fusion point from the upper surface of the insulating layer is 65% or more of the height of the channel regions of the first and second fin structures from the upper surface of the insulating layer.In one or more of the preceding and following embodiments, the vertical thickness of the fusion point lies within a range of 10% to 30% of the height of the source / drain epitaxy layer from an upper surface of the insulation layer. In one or more of the preceding and following embodiments, the source / drain epitaxy layer comprises a first, second, third, and fourth epitaxy layer formed in that order over the recessed first and second fin structures. In one or more of the preceding and following embodiments, the first epitaxy layer comprises SiAs and the second epitaxy layer comprises SiP. A fin structure is formed over a substrate.

[0081] The foregoing outlines the features of several embodiments or examples, thereby enabling the person skilled in the art to gain a better understanding of the aspects of the present disclosure. The person skilled in the art recognizes that he or she can readily use the present disclosure as a basis for developing or modifying other methods and structures to achieve the same purposes and / or the same advantages as the embodiments or examples presented herein.

Claims

[1] Method for manufacturing a semiconductor device, the method comprising: Formation of a first fin structure (20) and a second fin structure (20) over a substrate (10); Forming an insulating layer (30) over the substrate (10) such that lower sections of the first and second fin structure (20) are embedded in the insulating layer (30) and upper sections of the first and second fin structure (20) are exposed by the insulating layer (30); Formation of a gate structure (40) over channel areas of the first and second fin structures (20); Omission of source / drain areas of the first and second fin structure (20); and Forming an epitaxial source / drain structure (60) over the recessed first and second fin structures (20), wherein the epitaxial source / drain structure (60) is a united structure with a fusion point and comprises a first, second, third and fourth epitaxial layer (68) formed in that order over the recessed first and second fin structure (20), wherein a P concentration of the second epitaxial layer (64) is highest in the first to fourth epitaxial layers (62, 64, 66, 68), and wherein the height of a base of the intergrowth point, starting from an upper surface of the insulation layer (30), is 50% or more of the height of the channel areas of the first and second fin structures (20), starting from the upper surface of the insulation layer (30). [2] Method according to claim 1, wherein the height of the base of the ingrowth point, starting from an upper surface of the insulation layer (30), is 75% or more of the height of the channel areas of the first and second fin structures (20), starting from the upper surface of the insulation layer (30). [3] Method according to claim 1 or 2, wherein the first epitaxial layer (62) over the recessed first fin structure (20) and the first epitaxial layer (62) over the recessed second fin structure (20) are not fused together, and the second epitaxial layer (64) forms the fusion point. [4] Method according to any of the preceding claims, wherein the first epitaxial layer (62) comprises As. [5] Method according to any of the preceding claims, wherein the third epitaxial layer (66) comprises SiP doped with Ge, and the fourth epitaxial layer (68) comprises SiP. [6] Method according to any of the preceding claims, wherein the third epitaxial layer (66) is in contact with the first epitaxial layer (62). [7] Method for manufacturing a semiconductor device, the method comprising: Formation of a first fin structure (20) and a second fin structure (20) over a substrate (10); Forming an insulating layer (30) over the substrate (10) such that lower sections of the first and second fin structure (20) are embedded in the insulating layer (30) and upper sections of the first and second fin structure (20) are exposed by the insulating layer (30); Formation of fin sidewalls on opposite side faces of source / drain areas of the first and second fin structures (20); Omission of source / drain areas of the first and second fin structure (20); Formation of a first epitaxial layer (62) over the recessed first and second fin structures (20) at a first temperature; Performing an etching process on the first epitaxial layer (62) at a second temperature; Forming a second epitaxial layer (64) with a different composition than the first epitaxial layer (62) over the first epitaxial layer (62) at a third temperature, wherein the second temperature is higher than the first temperature and / or the third temperature; Formation of a third epitaxial layer (66) with a different composition than the second epitaxial layer (64) above the second epitaxial layer (64), at a fourth temperature; Performing an etching process on the third epitaxial layer (66) at a fifth temperature; and Formation of a fourth epitaxial layer (68) which has a different composition than the third epitaxial layer (66) over the third epitaxial layer (66) at a sixth temperature. [8] Method according to claim 7, wherein: the second epitaxial layer (64) forms a fused second epitaxial layer (64) with a point of fusion, and a height of a base of the ingrowth point originating from an upper surface of the insulation layer (30) is 50% or more of a height of the channel areas of the first and second fin structures (20) originating from the upper surface of the insulation layer (30). [9] Method according to claim 7 or 8, wherein the formation of the second epitaxial layer (64) comprises one or more deposition phases and one or more etching phases, which are carried out alternately. [10] Method according to claim 8 or 9, wherein: the formation of the second epitaxial layer (64) includes the formation of a lower layer over the first epitaxial layer (62) that does not form the fused second epitaxial layer (64), and the formation of an upper layer over the lower layer that forms the second epitaxial layer (64), and The formation of the upper layer does not include an etching phase. [11] Method according to any one of claims 7 to 10, wherein the fourth temperature is higher than the third temperature. [12] Method according to claim 11, wherein the fifth temperature is higher than the fourth temperature. [13] A semiconductor device comprising: an insulating layer (30) arranged over a substrate (10); a first fin structure (20) and a second fin structure (20) arranged above the substrate (10) a gate structure (40) arranged over channel areas of the first and second fin structures (20); and a source / drain epitaxy layer (60) arranged over source / drain regions of the first and second fin structure (20), where: the source / drain epitaxy layer (60) has a united structure with a point of fusion, a height of a base of the ingrowth point starting from an upper surface of the insulation layer (30) is 65% or more of a height of the channel areas of the first and second fin structures (20) starting from the upper surface of the insulation layer (30), the source / drain epitaxy layer (60) has a first, second, third and fourth epitaxy layer (62, 64, 66, 68) which are formed in this order over the source / drain regions of the first and second fin structures (20), and a P concentration of the second epitaxial layer (64) is highest in the first to fourth epitaxial layer (62, 64, 66, 68). [14] Semiconductor device according to claim 13, wherein a vertical thickness of the ingrowth point is in a range of 10% to 30% of the height of the source / drain epitaxy layer (60) starting from an upper surface of the insulation layer (30). [15] Semiconductor device according to claim 13 or 14, wherein the first epitaxial layer (62) comprises SiAs and the second epitaxial layer (64) comprises SiP.

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