Field effect transmitters with channel areas comprising a two-dimensional material, on a mandrel, and methods for forming these field effect transmitters

Abstract

Structure for a field-effect transistor, wherein the structure comprises: a first mandrel (38, 56) composed of a dielectric material, wherein the first mandrel (38, 56) comprises a plurality of side surfaces (39, 59), the plurality of side surfaces (39, 59) comprising a first side surface and a second side surface; a second mandrel (38, 56) composed of the dielectric material, wherein the second mandrel (38, 56) comprises a side surface, and the second mandrel (38, 56) is arranged above the first mandrel (38, 56); a gate electrode having a section (43) that is enveloped around the first side surface and the second side surface of the first mandrel (38, 56); a first channel layer (34) comprising a channel region (70), wherein the channel region (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56) and is positioned partly between the first side surface of the first mandrel (38, 56) and the section (43) of the gate electrode and partly between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode; and a second channel layer (34) comprising a channel region (70) that is partially positioned between the side surface of the second mandrel (38, 56) and the section (43) of the gate electrode, wherein the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material.

Description

BACKGROUND

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits and in particular structures for a field-effect transistor and methods for forming a structure for a field-effect transistor.

[0002] Complementary metal-oxide semiconductor (CMOS) processes can be used to build p-type and n-type field-effect transistors, which are used, for example, to construct logic cells. Field-effect transistors generally comprise a channel region within a semiconductor body, a source, a drain, and a gate electrode above the body. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, a carrier flux occurs in the channel region between the source and the drain to generate a device output current.

[0003] Nanosheet field-effect transistors represent a type of non-planar field-effect transistor that can be fabricated with increased packing density in an integrated circuit. A nanosheet field-effect transistor comprises multiple nanosheet channel layers arranged in a structured stack of layers above the top surface of a substrate, and source / drain regions connected to the lateral ends of the nanosheet channel layers. The nanosheet channel layers are initially arranged in the structured stack with sacrificial layers containing a material (e.g., silicon-germanium) that alternates with the nanosheet channel layers and can be selectively etched with respect to the material (e.g., silicon) representing the nanosheet channel layers. The source / drain regions can be formed by epitaxial growth of semiconductor material from the lateral ends of the nanosheet channel layers.The sacrificial layers are etched and removed to expose the nanosheet channel layers and provide space for the formation of a gate electrode. Sections of the gate electrode can surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. During operation with a control voltage applied to the gate electrode, the horizontal flux of carriers in the nanosheet channel layers generates the device output current. Nanosheet field-effect transistors can experience scaling difficulties because reductions in nanosheet thickness eventually reach a point where quantum confinement significantly degrades performance. Additionally, short-channel effects can limit the ability to continue shrinking the gate length. As such, limitations regarding electrostatic control can restrict the scaling of nanosheet field-effect transistors.

[0004] From US patent 2015 / 0041873A1, a vertical ferroelectric field-effect transistor is known. This comprises an insulating core surrounded by a layer of a transition metal dichalcogenide material, which in turn is surrounded by a gate dielectric. The gate dielectric is surrounded by a conductive gate material. Furthermore, US Patent 10,388,732 B1 discloses a field-effect transistor structure in which a plurality of channel layers are stacked and connected to a source / drain region. A gate structure with multiple sections surrounds the plurality of channel layers, which comprise a two-dimensional semiconductor material. The source / drain regions also consist of a two-dimensional semiconductor material.

[0005] Improved structures for a field-effect transistor and methods for forming a structure for a field-effect transistor are needed. BRIEF SUMMARY

[0006] In embodiments of the invention, a structure for a field-effect transistor is provided. The structure comprises a first mandrel composed of a dielectric material, wherein the first mandrel comprises a plurality of side surfaces, the plurality of side surfaces comprising a first side surface and a second side surface; a second mandrel composed of the dielectric material, wherein the second mandrel comprises a side surface, and the second mandrel is arranged above the first mandrel; and a gate electrode having a section that is enveloped around the first side surface and the second side surface of the first mandrel.The structure further comprises a first channel layer comprising a channel region, wherein the channel region of the first channel layer extends around all of the side surfaces of the first mandrel and is partially positioned between the first side surface of the first mandrel and the gate electrode section, and partially between the second side surface of the first mandrel and the gate electrode section; and a second channel layer comprising a channel region that is partially positioned between the side surface of the second mandrel and the gate electrode section. The first channel layer and the second channel layer are composed of a two-dimensional material.

[0007] In embodiments of the invention, a method for forming a field-effect transistor is provided. The method comprises forming a first channel layer and a second channel layer, both channel layers comprising a channel region; forming a first dielectric mandrel comprising a plurality of side surfaces; forming a second dielectric mandrel comprising a side surface and arranged above the first dielectric mandrel; and forming a gate electrode having a section that is enveloped around a first side surface and a second side surface of the plurality of side surfaces of the first dielectric mandrel.The channel region of the first channel layer extends around all of the side surfaces of the first mandrel, and is partially positioned between the first side surface of the first dielectric mandrel and the gate electrode section, and partially between the second side surface of the first mandrel and the gate electrode section. The channel region of the second channel layer is partially positioned between the side surface of the second dielectric mandrel and the gate electrode section. The first and second channel layers are composed of a two-dimensional material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated into and form part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments. In the drawings, the same reference numerals refer to the same features in the different views. Fig. Figure 1 is a top view of a device structure in an initial manufacturing stage of a processing method according to embodiments of the invention. Fig. 2 is a cross-sectional view along a line 2-2 in Fig. 1. Fig. Figure 3 is a top view of a device structure at a manufacturing stage following Fig. 1. Fig. 4 is a cross-sectional view overall along a line 4-4 in Fig. 3. Fig. 4A is a cross-sectional view along a line 4A-4A in Fig. 3. Fig. 4B is a cross-sectional view along a line 4B-4B in Fig. 3. Fig. Figures 5-10, 5A-10A, and 5B-10B are respective cross-sectional views of the fixture structure in successive manufacturing stages of the processing procedure following the Fig. 4, Fig. 4A, Fig. 4B. Fig. Figures 11-16, 11A-16A, and 11B-16B are cross-sectional views of the device structure in successive manufacturing stages of a processing method according to alternative embodiments. DETAILED DESCRIPTION

[0009] With reference to the Fig. 1, Fig. 2 and according to embodiments of the invention, one or more nanosheet channel layers 10, one or more sacrificial layers 12, and a sacrificial layer 14 are arranged in a layer stack 15 located on a substrate 11. The sacrificial layer 14 is arranged vertically between the substrate 11 and the lowest sacrificial layer 12. The substrate 11 can be composed of a single-crystal semiconductor material, such as single-crystal silicon. The nanosheet channel layers 10, the sacrificial layers 12, and the sacrificial layer 14 can be formed on the substrate 11 by an epitaxial growth process, during which the layer composition is varied by varying the reactants supplied to the deposition tool. The number of nanosheet channel layers 10 and sacrificial layers 12 in the layer stack 15 can differ from the representative embodiment.In particular, the number of nanosheet channel layers 10 and sacrificial layers 12 in the layer stack 15 can be greater than the number in the representative embodiment by adding pairs of nanosheet channel layers 10 and sacrificial layers 12 to the layer stack 15.

[0010] The nanosheet channel layers 10 are composed of a single-crystal semiconductor material, and the sacrificial layers 12 are composed of a single-crystal semiconductor material with a composition selected to be selectively removed with respect to the single-crystal semiconductor material of the nanosheet channel layers 10. The sacrificial layer 14 is composed of a single-crystal semiconductor material with a composition selected to be selectively removed with respect to the single-crystal semiconductor material of both the nanosheet channel layers 10 and the sacrificial layers 12. As used herein, the term "selective" with respect to a material removal process (e.g., etching) means that, with the choice of a suitable etchant, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least one other material subjected to the material removal process.

[0011] In one embodiment, the semiconductor material representing the nanosheet channel layers 10 can be single-crystal silicon, the semiconductor material representing the sacrificial layers 12 can be single-crystal silicon-germanium, which, due to its germanium content, is etched at a higher rate than silicon, and the semiconductor material representing the sacrificial layer 14 can be silicon-germanium, which, due to its higher germanium content than the sacrificial layers 12, is etched at a higher rate than the sacrificial layers 12. In one embodiment, the nanosheet channel layers 10 are germanium-free, the germanium content of the sacrificial layers 12 can range from fifteen atomic percent (15 at%) to thirty-five atomic percent (35 at%), and the germanium content of the sacrificial layer 14 can range from fifty atomic percent (50 at%) to seventy-five atomic percent (75 at%).

[0012] A hard mask 16 is deposited over the layer stack 15 and then patterned by lithography and etching processes. Sections of the hard mask 16 cover sections of the layer stack 15. The hard mask 16 can be composed of a dielectric material, such as silicon nitride, deposited by chemical vapor deposition (CVD).

[0013] With reference to the Fig. 3, Fig. 4, Fig. 4A, Fig. 4B, in which identical reference signs refer to identical features in the Fig. 1, Fig. 2, and in a subsequent manufacturing stage, the nanosheet channel layers 10, sacrificial layers 12, and sacrificial layer 14 are structured using an etching process, such as an anisotropic etching process like reactive ion etching, to define fins 18. The prior structuring of the sections of the hard mask 16 creates the structure for the fins 18.

[0014] The substrate 11 can be etched by the etching process, and in particular, self-aligning trenches can be defined in the substrate 11 between adjacent side walls 19 of the fins 18. Subsequently, shallow trench insulation areas 20 are formed in the trenches between the adjacent side walls 19 of the fins 18 by depositing a layer composed of a dielectric material, such as silicon dioxide, in the trenches and removing the deposited layer by an etching process.

[0015] Sacrificial gate structures 22 are formed, overlapping and enveloping a section of each fin 18. The term “sacrificial gate structure” as used herein refers to a placeholder structure for a gate structure to be formed subsequently. The sacrificial gate structures 22 are spaced apart along the length of the fins 18 and are oriented transversely to the longitudinal axes of the fins 18. The sacrificial gate structures 22 may comprise a thin oxide layer covering the outer surfaces of the fins 18 and a thicker layer containing a sacrificial material, such as amorphous silicon. The sacrificial gate structures 22 may be patterned from these stock layers by lithography and reactive ion etching (RIE) processes using a hard mask. The sacrificial gate structures 22 are each covered by a hard mask cap 24.The hard mask cap 24, which contains a dielectric material such as silicon nitride, may be a residue of the hard mask from the lithography and etching processes used to structure the sacrificial gate structures 22.

[0016] The sacrificial layer 14 can be removed from each fin 18 by a selective etching process to create spaces beneath the fins 18. As used herein, the term "selective" in relation to a material removal process (e.g., etching) means that, with the choice of a suitable etchant, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least one other material subjected to the material removal process. Sidewall spacers 26 can then be formed adjacent to the sidewalls of the sacrificial gate structures 22. The sidewall spacers 26 can be formed by depositing a conformal layer composed of a dielectric material, such as a low-k dielectric material (e.g., SiBCN, SiOC, or SiOCN), and etching the deposited conformal layer using an anisotropic etching process, such as reactive ion etching.Sections of the deposited conformal layer fill the spaces created by the removal of the structured sections of the operable layer 14 to define a lower dielectric insulating layer 28 beneath the fins 18.

[0017] Recesses 25 can be formed in the fins 18 by an etching process that is self-aligning through the sidewall spacers 26 and sacrificial gate structures 22. The etching process can be stopped at the lower dielectric insulating layer 28. Each of the fins 18 includes sidewalls 19 adjacent to the recesses, and adjacent sidewalls 19 of the fins 18 are separated by a gap of one dimension, S.

[0018] With reference to the Fig. 5, Fig. 5A, Fig. 5B, in which the same reference signs refer to the same features in the Fig. 4, Fig. 4A, Fig. 4B, and in a subsequent manufacturing stage, the sacrificial layers 12 are recessed by an etching process that selectively removes the material of the sacrificial layers 12 with respect to the material of the nanosheet channel layers 10. By depositing a conformal layer of dielectric material, such as silicon nitride, which fills the recesses adjacent to the opposite ends of the recessed sacrificial layers 12, and then performing an anisotropic etching process to remove the conformal layer from an outside of the recesses, inner spacers 30 are formed.

[0019] With reference to the Fig. 6, Fig. 6A, Fig. 6B, in which the same reference signs refer to the same features in the Fig. 5, Fig. 5A, Fig. 5B, and in a subsequent manufacturing stage, the nanosheet channel layers 10 are completely removed by an etching process to form spaces 32 that extend across the full width of the sacrificial layers 12 and sidewall spacers 26. For example, the etching process can be a remote plasma-assisted dry etching process (e.g., a frontier etch) that exposes the nanosheet channel layers 10 to radicals (i.e., uncharged or neutral species) generated from a gas mixture of nitrogen trifluoride (NF3) and hydrogen (H2). In conventional processes, the nanosheet channel layers 10 are not sacrificial and would be present in the final device structure.

[0020] With reference to the Fig. 7, Fig. 7A, Fig. 7B, in which identical reference signs refer to identical features in the Fig. 6, Fig. 6A, Fig. 6B, and in a subsequent manufacturing stage, a two-dimensional (2D) material is conformally deposited, partially filling each of the spaces 32 with substitute channel layers 34 and forming a layer 36 that encases the sidewall spacers 26 and the hard mask cap 24. The two-dimensional material is also deposited on the lower dielectric insulating layer 28. The substitute channel layer 34 only partially fills each space 32 with the two-dimensional material. The substitute channel layer 34 and the layer 36 define a continuous thin film composed of the two-dimensional material.

[0021] The two-dimensional material forming the replacement channel layers 34 and layer 36 can be a thin conformal coating deposited, for example, by atomic layer deposition or chemical vapor deposition. Deposition temperature limitations are reduced because deposition occurs in the process flow before the metal gate structures that replace the sacrificial gate structures 22 are formed. In one embodiment, the two-dimensional material can be characterized by a carrier mobility greater than that of silicon. In another embodiment, the two-dimensional material can be composed of a transition metal dichalcogenide comprising a transition metal (e.g., molybdenum (Mo) or tungsten (W)) and a chalcogen atom (sulfur (S), selenium (Se), or tellurium (Te)).Exemplary transition metal dichalcogenides include, but are not limited to, molybdenum disulfide (MoS₂), hafnium disulfide (HfS₂), zirconium disulfide (ZrS₂), tungsten disulfide (WS₂), tin sulfide (SnS), and tungsten diselenide (WSe₂). In an alternative embodiment, the two-dimensional material may be composed of graphene (C). In one embodiment, the two-dimensional material, and in particular the two-dimensional material 34 contained in each of the substitute channel layers 34, may comprise a single monolayer of atoms arranged in a thin layer. In an alternative embodiment, each substitute channel layer 34 may contain one to two monolayers of the two-dimensional material. In an alternative embodiment, each substitute channel layer 34 may contain two or more monolayers of the two-dimensional material.

[0022] With reference to the Fig. 8, Fig. 8A, Fig. 8B, in which identical reference signs refer to identical features in the Fig. 7, Fig. 7A, Fig. 7B, and in a subsequent manufacturing stage, mandrels 38 are formed that fill the remainder of each space 32 not occupied by the substitute channel layers 34. The mandrels 38 can be composed of a dielectric material, such as a low-k dielectric material (e.g., SiBCN, SiOC, or SiOCN), deposited as a layer by atomic layer deposition and etched with an isotropic etching process to remove portions of the layer outer to the spaces 32. The deposited layer can be pinched off within the spaces 32 to form the mandrels 38. The mandrels 38 are formed after the substitute channel layers 34 and layer 36 have been formed. The mandrels 38 have a stacked arrangement created by the spaces 32 and substitute channel structures 34.

[0023] Each mandrel 38 comprises opposing end surfaces 37, spaced apart from each other in a lateral direction, and side surfaces 39 positioned between the opposing end surfaces 37. The side surfaces 39 are arranged around the circumference of each mandrel 38. One of the side surfaces 39 of each mandrel 38 is an upper side surface, positioned furthest (i.e., farther away) from the substrate 11, and another of the side surfaces 39 of each mandrel 38 is a lower side surface, positioned closest (i.e., nearer) to the substrate 11. The upper and lower side surfaces 39 of each mandrel 38 may be contained in parallel or substantially parallel planes. In one embodiment, each mandrel 38 may have a rectangular cross-section parallel to its longitudinal axis.The two-dimensional material in each replacement channel layer 34 is enveloped around (i.e., surrounds or extends completely around) all of the side surfaces 39 of one of the mandrels 38 and, as a result, is positioned on the upper and lower side surfaces 39 as well as all other side surfaces 39. In one embodiment, the two-dimensional material in each replacement channel layer 34 is in direct contact with the side surfaces 39 of one of the mandrels 38. The opposite side surfaces 37 of each mandrel 38 are not covered by the two-dimensional material.

[0024] The two-dimensional material in layer 36 may be doped, as indicated by the single-pointed arrows labeled with reference numeral 35 in Fig. Figure 8 is shown diagrammatically to increase its electrical conductivity. In one embodiment, the two-dimensional material in layer 36 can be doped after its deposition and after the mandrels 38 have been formed. In another embodiment, the two-dimensional material in layer 36 can be doped by a non-destructive doping process, such as plasma doping. In one embodiment, the two-dimensional material in layer 36 can be doped with a p-type dopant, which provides p-type electrical conductivity. In an alternative embodiment, the two-dimensional material in layer 36 can be doped with an n-type dopant, which provides n-type electrical conductivity. The substitute channel layers 34 are masked and are not doped by the process doping layer 36.

[0025] With reference to the Fig. 9, Fig. 9A, Fig. 9B, in which identical reference signs refer to identical features in the Fig. 8, Fig. 8A, Fig. Source / drain contacts 40 are formed in the recesses 25 in a subsequent manufacturing stage, based on layer 8B. These source / drain contacts are coupled to the two-dimensional material of the substitute channel layers 34 via layer 36. The source / drain contacts 40 can be composed of a metal, such as tungsten or titanium nitride, which is deposited and recessed using a back-etching process. The two-dimensional material in layer 36, which may be doped, surrounds each source / drain contact 40. This relationship maximizes the contact area, which can reduce the contact resistance.

[0026] The replacement channel layers 34 in each fin 18 are arranged laterally between different source / drain contacts 40 and are coupled to these different source / drain contacts 40. The mandrels 38 extend completely transversely through each fin 18 in a lateral direction from one of the source / drain contacts 40 to another of the source / drain contacts 40, and the opposite end surfaces 37 of each mandrel 38 terminate at, and directly contact, one of the source / drain contacts 40. The end surfaces 37 of each mandrel 38 are free of the two-dimensional material, which facilitates the direct contact and electrical insulation of the different replacement channel layers 34 in each fin 18.

[0027] After the formation of the source / drain contacts 40, the layer 36 can be bent using an isotropic etching process such that the different source / drain contacts 40 are separated from each other. The height of the source / drain contacts 40 can determine the degree of bentness of the layer 36.

[0028] A dielectric interlayer 41 is deposited and planarized to fill the spaces above the source / drain contacts 40. The dielectric interlayer 41 can be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and can be planarized by chemical-mechanical polishing. The planarization can remove the hard mask caps 24, thus opening the sacrificial gate structures 22 for subsequent removal.

[0029] With reference to the Fig. 10, Fig. 10A, Fig. 10B, in which the same reference signs refer to the same features in the Fig. 9, Fig. 9A, Fig. 9B, and in a subsequent manufacturing stage, the sacrificial gate structures 22 are removed by one or more etching processes. The sacrificial layers 12 are then removed by an etching process that selectively removes the material of the sacrificial layers 12 with respect to the materials of the replacement channel layers 34 and the inner spacers 30.

[0030] In the spaces opened by the removal of the sacrificial gate structures 22 and sacrificial layers 12, gate structures 42 are formed to complete the formation of a field-effect transistor in a substitute-gate process. The gate structures 42 can comprise a gate dielectric layer composed of a dielectric material, such as a high-k dielectric like hafnium oxide, and a gate electrode comprising one or more barrier metal layers and / or working-function metal layers, such as titanium aluminum carbide or titanium nitride. The gate dielectric layer is positioned between the gate electrode and the substitute channel layers 34.

[0031] The replacement channel layers 34 are arranged in a vertical stack, with each replacement channel layer 34 being enveloped around the side surfaces 39 by one of the mandrels 38. Sections 43 of the gate electrode of each gate structure 42 are located in the spaces formerly occupied by the removed sacrificial layers 12. Each gate electrode section 43 can enclose a channel area 70 of one of the replacement channel layers 34 and the associated mandrel 38 in a gate-all-around arrangement.

[0032] Each replacement channel layer 34 also includes extension regions 72 located at the opposite lateral ends of the channel region 70. The channel region 70 is therefore positioned laterally between the extension regions 72. The extension regions 72 couple opposite ends of the channel region 70 of each replacement channel layer 34 to one of the source / drain contacts 40. The channel region 70 and the extension regions 72 of each replacement channel layer 34 are enveloped around all of the side surfaces 39 by one of the mandrels 38 (i.e., they surround or extend completely around them). The extension areas 72, as well as the respective lateral sections of the mandrel 38 on which the extension areas 72 are located, extend through the gap between adjacent inner spacers 30. One of the inner spacers 30 is arranged in a vertical direction between the extension areas 72 of adjacent canal layers 34.

[0033] Self-aligning contact caps 44, composed of a dielectric material such as silicon nitride, are formed in the spaces above each of the gate structures 42 located between the sidewall spacers 26. The dielectric interlayer 41 can be removed to open spaces above the source / drain contacts 40, and trench silicide contacts (not shown) can be formed in these opened spaces, extending to contact the source / drain contacts 40.

[0034] Subsequently, Middle-of-Line (MOL) and Back-End-of-Line (BEOL) processing is used to form an intermediate interconnect structure with contacts coupled to the field-effect transistor.

[0035] The introduction of the two-dimensional material into the substitute channel layer 34 enables the formation of a stacked two-dimensional field-effect transistor characterized by an improved effective width and enhanced process flexibility. The improved process flexibility is at least partially achieved because the two-dimensional material is formed prior to the formation of the source / drain contacts 40 and the gate structures 42. Therefore, the two-dimensional material can be deposited with a more aggressive thermal balance due to a reduced risk of metal interdiffusion and damage to the gate structures 42. The improved electrostatic control of the substitute channel layers 34, enabled by the two-dimensional material, can allow for a downward scaling of the gate length.

[0036] The arrangement of layer 36 and the source / drain contacts 40 provides a wrap-around contact (WAC) that can reduce contact resistance. Because the source / drain contacts 40 do not contain epitaxial semiconductor material, as in conventional field-effect transistors, the field-effect transistor comprises the equivalent channel layers of the two-dimensional material without a junction. By adjusting the doping of the two-dimensional material in layer 36 and the metal used to form the source / drain contacts 40, either n-type or p-type field-effect transistors can be created.

[0037] With reference to the Fig. 11, Fig. 11A, Fig. 11B, in which the same reference signs refer to the same features in the Fig. 4, Fig. 4A, Fig. Referring to 4B, and according to an alternative embodiment, the nanosheet channel layers 10 can be formed in the layer stack with a reduced thickness. Spacers 50 can be formed adjacent to the sidewalls of the fins 18. The spacers 50 can be formed by depositing a conformal layer composed of a dielectric material, such as titanium oxide, and etching the deposited conformal layer using an anisotropic etching process, such as reactive ion etching. A dielectric interlayer 52 is deposited and planarized to fill the spaces between the fins 18 and sacrificial gate structures 22. The dielectric interlayer 52 can be composed of a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and can be planarized by chemical-mechanical polishing.Planarization can remove the hard mask caps 24 to open the sacrificial gate structures 22.

[0038] With reference to the Fig. 12, Fig. 12A, Fig. 12B, in which the same reference signs refer to the same features in the Fig. 11, Fig. 11A, Fig. 11B, and in a subsequent manufacturing stage, the sacrificial gate structures 22 are removed by one or more etching processes to define spaces 54. The sacrificial layers 12 are then removed by an etching process that selectively removes the material of the sacrificial layers 12 with respect to the materials of the replacement channel layers 34 and the inner spacers 30.

[0039] Mandrels 56 are formed to fill the spaces vacated by the removed sacrificial layers 12. The mandrels 56 can be composed of a low-k dielectric material, such as SiBCN, SiOC, or SiOCN, conformally deposited as a layer by atomic layer deposition and etched using an isotropic etching process to remove sections of the layer outer to the spaces. The deposited layer can be pinched off within the spaces to form the mandrels 56. The dielectric interlayer 52 blocks the deposition of the layer between the sacrificial gate structures 22. Each mandrel 56 comprises opposite end surfaces 57, spaced apart from each other in a lateral direction, and side surfaces 59 positioned between the opposite end surfaces.The end surfaces 57 and side surfaces 59 are similar to the end surfaces 37 and side surfaces 39 of the mandrels 38, as previously described.

[0040] With reference to the Fig. 13, Fig. 13A, Fig. 13B, in which the same reference signs refer to the same features in the Fig. 12, Fig. 12A, Fig. Referring to 12B, and in a subsequent manufacturing stage, the nanosheet channel layers 10, as described above, are completely removed by an etching process to form the spaces 32, which extend across the full width of the fins 18 and sidewall spacers 26. The mandrels 56 are then thinned by an isotropic etching process, which also removes the spacers 50 to define spaces 51 that are connected to the spaces 32.

[0041] With reference to the Fig. 14, Fig. 14A, Fig. 14B, in which the same reference signs refer to the same features in the Fig. 13, Fig. 13A, Fig. Referring to 13B, and in a subsequent manufacturing stage, the substitute channel layers 34 and layer 36, which are composed of a two-dimensional material, are formed as described above. In the alternative embodiment, the mandrels 56 are formed before the substitute channel layers 34 and layer 36 are formed, and the substitute channel layers 34 are formed on the outer surfaces of the mandrels 56 and the inner spacers 30. The relationship between the substitute channel layers 34 and the side surfaces 59 of the mandrels 56 is similar to the relationship between the substitute channel layers 34 and the side surfaces 39 of the mandrels 38, as described above. However, the extent regions 72 of the substitute channel layers 34 do not surround the mandrels 56.Instead, the extension areas 72 of the replacement channel layers 34 are short segments that completely fill the spaces 32 and 51 formed by the removal of the nanosheet channel layers 10 between the inner spacers 30. The opposite end surfaces 57 of each mandrel 56 terminate at, and directly contact, one of the inner spacers 30.

[0042] With reference to the Fig. 15, Fig. 15A, Fig. 15B, in which the same reference signs refer to the same features in the Fig. 14, Fig. 14A, Fig. Referring to 14B, and in a subsequent manufacturing stage, composite plugs 45 are formed in the spaces 32 between the mandrels 56 and can be in direct contact with the replacement channel layers 34. The composite plugs 45 can comprise the conformally deposited gate dielectric layer of the gate structure 42, a cover layer composed, for example, of titanium nitride, and a central core composed, for example, of p-type polysilicon. When the composite plugs 42 are present, a curing process can be performed to improve the physical properties and reliability of the gate dielectric layer.

[0043] In the space above the uppermost mandrel 56, sections of the two-dimensional material of layer 36 are exposed and are removed by an etching process. The removal of these exposed sections of the two-dimensional material of layer 36 defines a recess 57 above each of the uppermost inner spacers 30. The composite plugs 42 protect the replacement channel layers 34 during the formation of the recesses 57.

[0044] With reference to the Fig. 16, Fig. 16A, Fig. 16B, in which the same reference signs refer to the same features in the Fig. 15, Fig. 15A, Fig.15B, and in a subsequent manufacturing stage, the recesses 57 above the uppermost inner spacers 30 are filled with a dielectric material, which can be the same dielectric material (e.g., silicon nitride) that constitutes the inner spacers 30. The top layer and the central core of the composite plugs 45 are then removed by an etching process, leaving behind the gate dielectric layer of the gate structures 42. The gate electrodes of the gate structures 42 are formed as described above. The gate electrode sections 43 of each gate structure 42 are positioned in the spaces between the mandrels 56 and enclose the channel regions 70 of the substitute channel layers 34 and the associated mandrels 56. Then the gate electrodes of the gate structures 42 and the self-aligning contact caps 44 are formed.

[0045] The dielectric interlayer layer 52 is removed, exposing layer 36. The two-dimensional material in layer 36 can then be doped, as described above, to increase its electrical conductivity. The source / drain contacts 40, which are coupled through layer 36 to the extension regions of the substitute channel layers 34, are then formed in the recesses 25.

[0046] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare die chips, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate or a final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.

[0047] References herein to expressions modified by approximation language, such as "about," "approximately," and "essentially," are not to be limited to the specified precise value. The approximation language may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may be + / - 10% of the specified value(s).

[0048] References herein to terms such as "vertical," "horizontal," etc., are made for illustrative purposes only and not to limit or establish a frame of reference. The term "horizontal," as used herein, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0049] A feature "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature "at" or "contacting" another feature can be directly at or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly at" or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly related” or “indirect contact” with another feature if at least one intervening feature is present.

Claims

[1] Structure for a field-effect transistor, wherein the structure comprises: a first mandrel (38, 56) composed of a dielectric material, wherein the first mandrel (38, 56) comprises a plurality of side surfaces (39, 59), the plurality of side surfaces (39, 59) comprising a first side surface and a second side surface; a second mandrel (38, 56) composed of the dielectric material, wherein the second mandrel (38, 56) comprises a side surface, and the second mandrel (38, 56) is arranged above the first mandrel (38, 56); a gate electrode having a section (43) that is enveloped around the first side surface and the second side surface of the first mandrel (38, 56); a first channel layer (34) comprising a channel region (70), wherein the channel region (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56) and is positioned partly between the first side surface of the first mandrel (38, 56) and the section (43) of the gate electrode and partly between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode; and a second channel layer (34) comprising a channel region (70) that is partially positioned between the side surface of the second mandrel (38, 56) and the section (43) of the gate electrode, wherein the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material. [2] Structure according to claim 1, wherein the first side surface and the second side surface of the first mandrel (38, 56) are contained in respective planes which are substantially parallel. [3] Structure according to claim 1 or claim 2, wherein the first channel layer (34) comprises an extension area (72), the second channel layer (34) comprises an extension area (72), and further comprising: a source / drain contact (40) which is connected to the channel area (70) of the first channel layer (34) through the extension area (72) of the first channel layer (34) and to the channel area (70) of the second channel layer (34) through the extension area (72) of the second channel layer (34). [4] Structure according to claim 3, wherein the first mandrel (38, 56) and the second mandrel (38, 56) each terminate at the source / drain contact (40) in direct contact with the source / drain contact (40), the extension area (72) of the first channel layer (34) extends completely around the first mandrel (38, 56), and the extension area (72) of the second channel layer (34) extends completely around the second mandrel (38, 56). [5] Structure according to claim 4, further comprising: an inner spacer (30) which is positioned in a first direction between the section (43) of the gate electrode and the source / drain contact (40), wherein the inner spacer (30) is positioned in a second direction between the extension area (72) of the first channel layer (34) and the extension area (72) of the second channel layer (34). [6] Structure according to claim 1, wherein the first channel layer (34) comprises a first extension area (72), and further comprising: a first source / drain contact (40) which is connected to the channel area (70) of the first channel layer (34) by the first extension area (72) of the first channel layer (34). [7] Structure according to claim 6, wherein the first channel layer (34) comprises a second extension area (72), the channel area (70) of the first channel layer (34) is positioned between the first extension area (72) and the second extension area (72) of the first channel layer (34), and further comprising: a second source / drain contact (40) which is connected to the channel area (70) of the first channel layer (34) via the second extension area (72) of the first channel layer (34). [8] Structure according to claim 7, wherein the channel area (70), the first extension area (72) and the second extension area (72) of the first channel layer (34) extend around all of the side surfaces (39, 59) of the first mandrel (38, 56). [9] Structure according to claim 6, further comprising: a layer (36) of the two-dimensional material that couples the first extension area (72) of the first channel layer (34) with the first source / drain contact (40). [10] Structure according to claim 9, wherein the layer (36) of the two-dimensional material contains a dopant that is effective for increasing the electrical conductivity of the two-dimensional material. [11] Structure according to claim 6, further comprising: a first inner spacer (30) and a second inner spacer (30) positioned in a first direction between the section (43) of the gate electrode and the first source / drain contact (40), wherein the first extension area (72) is positioned in a second direction between the first inner spacer (30) and the second inner spacer (30), and the first mandrel (38, 56) terminates at the first inner spacer (30) and the second inner spacer (30). [12] Structure according to any one of claims 1 to 11, wherein the two-dimensional material is a transition metal dichalcogenide. [13] Structure according to any one of claims 1 to 12, wherein the two-dimensional material is molybdenum disulfide, hafnium disulfide, zirconium disulfide, tungsten disulfide, tin sulfide, or tungsten diselenide. [14] Method for forming a field-effect transistor, the method comprising: Forming a first channel layer (34) and a second channel layer (34), wherein both channel layers (34) comprise a channel area (70); Forming a first dielectric mandrel (38, 56) comprising a plurality of side surfaces (39, 59); Forming a second dielectric mandrel (38, 56) which includes a side surface and is arranged above the first dielectric mandrel (38, 56); and Forming a gate electrode having a section (43) enclosed around a first side surface and a second side surface of the plurality of side surfaces (39, 59) of the first dielectric mandrel (38, 56); wherein the channel region (70) of the first channel layer (34) extends around all of the side surfaces (39, 59) of the first mandrel (38, 56), and the channel region (70) of the first channel layer (34) is positioned partly between the first side surface of the first dielectric mandrel (38, 56) and the section (43) of the gate electrode and partly between the second side surface of the first mandrel (38, 56) and the section (43) of the gate electrode, wherein the channel region (70) of the second channel layer (34) is partially positioned between the side surface of the second dielectric mandrel (38, 56) and the section (43) of the gate electrode, and wherein the first channel layer (34) and the second channel layer (34) are composed of a two-dimensional material. [15] Method according to claim 14, wherein the first channel layer (34) and the second channel layer (34) are formed before the first dielectric mandrel (38, 56) and the second dielectric mandrel (38, 56) are formed. [16] Method according to claim 14, wherein the first channel layer (34) and the second channel layer (34) are formed after the first dielectric mandrel (38, 56) and the second dielectric mandrel (38, 56) are formed. [17] Method according to any one of claims 14 to 16, wherein the first channel layer (34) and the second channel layer (34) are formed before the gate electrode is formed.

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