3D FERAM WITH HIGH DENSITY

Abstract

A three-dimensional ferroelectric RAM memory device comprising: a first channel (204c); a second channel (204c) above the first channel (204c); a gate structure (212) surrounding the first and second channels (204c), the gate structure (212) comprising a ferroelectric layer (210) surrounding the first and second channels and a gate metal layer surrounding the ferroelectric layer; two first electrodes (206) connected to two sides of the first channel (204c); two second electrodes (206) connected to two sides of the second channel (204c); a dielectric layer (202) between the first and second electrodes (206); and an inner spacer layer (208) between the two first electrodes (206) and the gate structure (212).

Description

GENERAL STATE OF THE ART

[0001] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and IC design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling-down has also increased the complexity of IC processing and manufacturing. Thus, semiconductor manufacturing processes require continuous improvement.One area for improvement is how to increase the cell density of ferroelectric memory (FeRAM, FRAM, F-RAM, or FERAM) for various applications, including embedded memory and standalone memory. FERAM is one of the candidates for next-generation non-volatile memory (NVM) due to its fast read / write speed and small size. Thus, increasing the density of FERAM is highly desirable.

[0002] US 2020 / 0 035 696 A1 discloses a memory device having first and second columnar active regions formed on a substrate and extending upward. US 2020 / 0 013 870 A1 discloses semiconductor devices and methods for their fabrication. WO 2019 / 168 541 A1 describes a stacked non-silicon CMOS device structure.

[0003] The invention is defined by the independent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood by reference to the following detailed description when taken in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of explanation. Fig. 1A illustrates a perspective view of a stacked FERAM structure in part according to various aspects of the present disclosure. Fig. 1B and Fig. 1C illustrate a top view and a cross-sectional view of the stacked FERAM structure in Fig. 1A. Fig. Figure 1D illustrates a perspective view of certain components of the stacked FERAM structure in Fig. 1A according to one embodiment. Fig. Figure 2 illustrates a perspective view of a portion of a semiconductor device incorporating a stacked FERAM structure, such as that shown in Fig. 1A, according to various aspects of the present disclosure. Fig. 3 shows a flowchart of a method for forming a stacked FERAM structure according to various aspects of the present disclosure. Fig. 4A, 4B, 4C, 4D-1, 4D-2, 4D-3, 4E-1, 4E-2, 4E-3, 4F-1, 4F-2, 4F-3, 4G, 4H, 4I, 4J, 4K, and 4L illustrate various perspective views and cross-sectional views of a portion of a stacked FERAM structure during various manufacturing stages of the process in Fig. 3 according to some embodiments of the present disclosure. Fig. 5A, Fig. 5B and Fig. 5C show schematic views of a semiconductor device having a stacked FERAM structure, according to some embodiments of the present disclosure. Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E and Fig. 6F illustrate various embodiments of a single-bit FERAM (1T FERAM) that can be stacked in a stacked FERAM structure, according to the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially related terms such as "underlying," "beneath," "lower," "above," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.When a number or range of numbers is described with "approximately," "about," and the like, the term further encompasses numbers that are within certain variations (such as + / - 10% or other variations) of the described number, according to the knowledge of one skilled in the art with respect to the specific technology disclosed herein, unless otherwise indicated. For example, the term "about 5 nm" may encompass the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0007] The present disclosure relates generally to semiconductor manufacturing processes and structures thereof, and more particularly to processes for forming a three-dimensional ferroelectric random access memory array (3D ferroelectric random access memory array) (FeRAM, FERAM, F-RAM, or FRAM) to achieve high-density memory. The disclosed 3D FERAM may be a standalone memory IC or integrated with MOSFETs (such as CMOSFETs, FinFETs, gate-all-around (GAA) transistors such as nanowire FETs and nanosheet FETs, or other types of multi-gate FETs) in an IC to enhance the functionality of the IC. The disclosed 3D FERAM achieves high-density memory. According to the present disclosure, a 3D FERAM array comprises multiple layers stacked on top of each other, and each layer comprises a 2-dimensional array (2D array) of 1-T FERAM cells (single-channel or single-transistor FERAM cells).The 2D arrays on different layers are vertically aligned and stacked to form the 3D FERAM array. In each layer, the 1-T FERAM cells are arranged in rows and columns. The FERAM cells in the same column share source and drain electrodes, which are connected to the supply line (SL) and bit line (BL) of the FERAM array. The FERAM cells in the same row share a common word line (WL) of the FERAM array. The vertically aligned FERAM cells share a common gate electrode, which can be connected to the WL. Access to the FERAM cells can be enabled by setting appropriate voltages on the SL, BL, and WL. Dielectric internal spacers are provided between the gate electrode (such as a metal gate) and the source / drain electrodes to reduce the coupling capacitance between them.The present disclosure offers the following advantages. First, by using the disclosed 3D FERAM structure, a high-density FERAM memory array can be achieved. Second, in some embodiments, the source / drain electrodes are formed as part of an initial multilayer stack before the gate electrode is formed, naturally connecting all channel layers in the same row. Thus, additional process steps for forming the source / drain electrodes are not required (but can, of course, be implemented if desired), simplifying the manufacturing process. Third, the dielectric internal spacers reduce the coupling capacitance between the gate electrodes and the source / drain electrodes, thereby increasing the operating speed of the FERAM. These and other aspects of the present disclosure are further described by reference to the accompanying figures.

[0008] Fig. Figure 1A illustrates a portion of a 3D FERAM structure 200 constructed in accordance with an embodiment of the present disclosure. The 3D FERAM structure 200 is also referred to as the structure 200 or the FERAM array 200 in the present disclosure. In the Fig. 1A, the structure 200 comprises three FERAM layers 201 stacked vertically (along the "z" direction), and each FERAM layer 201 comprises three FERAM cells (or unit cells) 250 arranged in a column (along the "y" direction). Thus, the structure shown in Fig. 1A has 9 unit cells 250. In various embodiments, the structure 200 may include two or more (such as 2, 3, 4, 5, and so on) FERAM layers 201, and each FERAM layer 201 may include any number of unit cells 250 in a column and any number of columns to form a 2D array in the respective FERAM layer 201. Furthermore, in various embodiments, the 3D FERAM structure 200 may be a standalone memory device, an embedded memory integrated with other circuitry in an IC, or part of a stacked 3D IC structure. In the present disclosure, for ease of explanation, a column of unit cells 250 along the "y" direction in Fig. 1A and are a row of unit cells 250 along the “x” direction in Fig. 1A arranged.

[0009] Fig. 1B illustrates a top view of a portion of the FERAM layer 201 according to one embodiment, Fig. 1C illustrates a cross-sectional view of a portion of the structure 200 according to one embodiment, and Fig. 1D illustrates a perspective view of certain components of the unit cell 250 in a disassembled state according to one embodiment.

[0010] With reference to Fig. 1D, a unit cell 250 includes an isolation structure 202, a semiconductor layer 204 (providing approximately a source region 204s, a drain region 204d, and a channel region 204c for the unit cell 250), an FE layer 210 wrapping around the channel region 204c, a metal layer 206 (providing approximately a source electrode and a drain electrode and supporting a source via 220 and a drain via 222, respectively), a spacer feature (or internal spacer) 208, and a gate electrode 212 wrapping around the FE layer 210. The semiconductor layer 204 is disposed over the isolation structure 202. The metal layer 206 is disposed over the semiconductor layer 204. The inner spacer 208 is disposed above the semiconductor layer 204 and laterally (along the “x” direction) between the FE layer 210 and the metal layer 206.

[0011] With reference to Fig. 1A, Fig. 1B and Fig. 1C, the structure 200 includes a gate spacer (or gate insulation) 214 extending vertically from an isolation structure 199 (such as an interlevel dielectric layer) and disposed laterally (along the "y" direction) between the gate electrodes 212 of adjacent rows for isolating the gate electrodes 212 from each other.

[0012] In one embodiment, the isolation structure 202 comprises a dielectric material, such as silicon nitride (Si3N4), or silicon oxide (SiO2), another suitable dielectric material, or a combination thereof. The isolation structure 202 may have a thickness (along the "z" direction) in a range from about 10 nm to about 100 nm in some embodiments. In one embodiment, the semiconductor layer 204 comprises an oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), another suitable oxide semiconductor, or a combination thereof. In another embodiment, the semiconductor layer 204 comprises polysilicon. In yet another embodiment, the semiconductor layer 204 comprises silicon or another suitable semiconductor material.The semiconductor layer 204 may have a thickness (along the "z" direction) in a range of approximately 10 nm to approximately 60 nm in some embodiments. In one embodiment, the metal layer 206 comprises a conductive material, such as titanium nitride, tantalum nitride, ruthenium, tungsten, other suitable conductive materials, or a combination thereof. The metal layer 206 may have a thickness (along the "z" direction) in a range of approximately 10 nm to approximately 60 nm in some embodiments.

[0013] In one embodiment, the FE layer 210 comprises hafnium oxide (HfO2); hafnium zirconium oxide (Hf x Zr 1-x O2); HfO2 doped with Si, Y, Ge, La or other suitable elements; aluminum scandium nitride (Al 1-x Sc xN); aluminum nitride (AlN); or other suitable ferroelectric materials. The FE layer 210 may have a thickness in a range of about 5 nm to about 30 nm in some embodiments. In one embodiment, the inner spacer 208 comprises a low-k dielectric material, for example, a dielectric material with a dielectric constant (k value) less than 10, such as in a range of about 3 to about 10. For example, the inner spacer 208 may comprise SiCN, SiC, SiON, SiOCN, Al2O3, or other suitable dielectric materials. Since the FE layer 210 is generally a high-k dielectric material, forming the inner spacers 208 from a low-k dielectric material (or lower-k material) reduces the coupling capacitance between the gate electrode 212 and the metal layer 206, thereby increasing the operating speed of the MRAM 200.The inner spacers 208 may have a length (dimension along the "x" direction) in a range from about 5 nm to about 30 nm in some embodiments. If the inner spacer 208 is too thin (such as thinner than about 5 nm), it may not effectively reduce the coupling capacitance between the gate electrode 212 and the metal layer 206 and could increase the risk of shorting the gate electrode 212 and the metal layer 206. If the inner spacer 208 is too thick (such as thicker than about 30 nm), it would unnecessarily increase the footprint of the unit cell 250 and reduce the storage density of the 3D FERAM structure 200.

[0014] In one embodiment, the gate electrode 212 includes a p-type work function layer such that the FERAM unit cell 250 has a positive threshold voltage. For example, the gate electrode 212 may include a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The gate electrode 212 may further include a low-resistivity metal, such as aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the gate electrode 212 includes an n-type work function layer, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the vias 220 and 222 may each comprise one or more conductive materials, such as Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, TaN, Ni, TiSiN, or combinations thereof.In some embodiments, the gate insulation 214 comprises a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material.

[0015] Fig. 2 illustrates a perspective view of a portion of a semiconductor device 100 (such as an integrated circuit) incorporating a 3D FERAM structure 200, according to various aspects of the present disclosure. The FERAM layers 201 are patterned into a stair structure 260. Vias 220 and 222 are disposed on the metal layer 206 at each step of the stair structure 260. In addition to the features of the 3D FERAM structure 200 previously discussed, the semiconductor device 100 includes source lines (SL) 230 and bit lines (BL) 232 connected to the vias 220 and 222, respectively, and word lines (WL) 112 connected to the gate electrodes 212. In the Fig. 2, the WLs 112 are further connected to gate vias 110 arranged over the gate electrodes 106 of various transistors 150. The transistors 150 are implemented in or on a substrate 102 and include source / drain regions 104, gate electrodes 106, and gate spacers 108. The transistors 150 are isolated from each other by an isolation structure (such as shallow trench isolation, STI) 105. The transistors 150 may be planar MOS transistors, FinFET, gate-all-around transistors (GAA transistors), or other types of transistors. In the embodiment shown in Fig. 2, the WL 112 are connected to the gate electrodes 212 from below the lowest FERAM layer 201. In another embodiment, the WL 112 are connected to the gate electrodes 212 from above the uppermost FERAM layer 201. In the embodiment shown in Fig. 2, the 3D FERAM structure 200 may be implemented at the Nth interconnect layer (or metal layer) of the semiconductor device 100 above the transistors 150, where N is a natural number. For example, the 3D FERAM structure 200 may be implemented at the 4th interconnect layer of the semiconductor device 100 (in other words, the 3D FERAM structure 200 may be implemented between the 3rd and 5th interconnect layers of the semiconductor device 100). Fig. The device 100 shown in Figure 2 is an example where the 3D FERAM structure 200 is implemented at the BEOL of the device 100 and above the transistors 150 implemented at the FEOL of the device 100.

[0016] Fig. 3 is a flow diagram of a method 10 for manufacturing a semiconductor device according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations may be provided before, during, and after the method 10, and some of the described operations may be shifted, replaced, or removed by additional embodiments of the method 10. The method 10 is described below in connection with Fig. 4A-4L are described, which illustrate various perspective and cross-sectional views of a 3D FERAM structure 200 at various steps of fabrication according to Method 10, according to some embodiments. In some embodiments, the 3D FERAM structure 200 is a stand-alone memory device.In some embodiments, the 3D FERAM structure 200 is a part of an IC chip, a system-on-chip (SoC), or a part thereof that may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanolayer FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS), bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components or combinations thereof.For example, the 3D FERAM structure 200 can be implemented at the back-end-of-line (BEOL) of an IC and above CMOS transistors implemented at the front-end-of-line (FEOL) of the IC. Fig. 4A-4L have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to structure 200, and some of the features described below may be replaced, modified, or removed in other embodiments of structure 200.

[0017] In operation 12, the procedure 10 ( Fig. 1A) provides a stack of multilayers 201 as an intermediate structure of the 3D FERAM structure 200. Referring to Fig. 4A, in the present embodiment, each multilayer 201 includes an insulating layer 202, a semiconductor layer 204 over the insulating layer 202, and a metal layer 206 over the semiconductor layer 204. The 3D FERAM structure 200 further includes another insulating layer 202 on the stack of multilayers 201 in the present embodiment. In other words, both the bottom layer and the top layer are insulating layers 202. The Fig. 4A has three multilayers 201 in the stack. In another embodiment, the structure 200 may have two or more multilayers 201 in the stack. The materials and thicknesses for layers 202, 204, and 206 were previously described with reference to Fig. 1A to 1D. Each of the layers 202, 204, and 206 may be formed by CVD, PVD, ALD, or other suitable processes.

[0018] In operation 14, the procedure 10 ( Fig. 1A) Gate trenches 205 in a channel region 203 of the stack of multilayers 201, such as in Fig. 4B. In one embodiment, operation 14 includes performing a photolithography process to form an etch mask over the structure 200. The photolithography process may include forming a resist layer over the structure 200 (e.g., by spin coating), performing a pre-exposure bake process, performing an exposure process using a photomask, performing a post-exposure bake process, and developing the exposed resist layer in a developing solution. After development, the patterned resist layer has a resist pattern corresponding to the photomask, wherein the resist pattern provides openings corresponding to the gate trenches 205 while covering the remainder of the structure 200. Alternatively, the exposure process may be implemented or replaced by other methods, such as maskless lithography, e-beam writing, ion beam writing, or combinations thereof.

[0019] After the etch mask is formed, operation 14 etches the stack of multilayers 201 through the openings in the etch mask to form the gate trenches 205. Operation 14 may apply one or more etch processes that selectively target the materials of layers 206, 204, and 202. Operation 14 may apply a cyclic multiple etch process in one embodiment. For example, operation 14 may apply a first etch process targeting the materials of layers 202, a second etch process targeting the materials of layers 206, and a third etch process targeting the materials of layers 204. Operation 14 may repeatedly apply the first, second, and third etch processes in a cyclic order until all layers in structure 200 are etched through.In the present embodiment, the various etching processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process may implement a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), ammonia, argon, other suitable gases, and / or plasmas, and / or combinations thereof. After the gate trenches 205 are etched, operation 14 removes the etch mask, for example, using resist stripping or other methods.

[0020] In operation 16, the procedure 10 ( Fig. 1A) cantilevered channel layers 204c in the gate trenches 205, such as in Fig. 4C. In one embodiment, operation 16 includes performing a photolithography process to form an etch mask over structure 200. The etch mask exposes channel region 203 of structure 200 while covering the remainder of structure 200. After the etch mask is formed, operation 16 applies one or more etch processes that selectively etch insulation layer 202 and metal layer 206 with minimal (to no) etching of semiconductor layers 204, thereby forming cantilevered channel layers 204c. In one embodiment, the various etch processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etching process may implement a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), other suitable gases and / or plasmas, and / or combinations thereof.For example, a wet etching process may include etching in hydrofluoric acid (HF); diluted hydrofluoric acid (DHF); sulfuric acid (H2SO4); hydrogen chloride (HCl), phosphoric acid (H3PO4); or another suitable wet etchant. As a result of the etching, the semiconductor layers 204 may extend slightly past the insulation layers 202 and the metal layer 206 to the gate trenches 205 along the "x" direction (this is also shown in FIGS. Fig. 4D-2 and 4D-3).

[0021] In operation 18, the procedure saves 10 ( Fig. 1A) the metal layer 206 laterally from the gate trenches 205 to form gaps 207 vertically between adjacent layers 204 and 202, as in Fig. 4D-1, 4D-2, and 4D-3. The etch mask formed in operation 16 may, in one embodiment, be retained and reused in operation 18. Alternatively, the etch mask formed in operation 16 is removed before operation 18 is performed. Operation 18 applies one or more etch processes that selectively etch the metal layer 206 with minimal (to no) etching of the insulation layer 202 and the semiconductor layers 204, thereby forming the gaps 207. In one embodiment, the various etch processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In various embodiments, the depth d1 of the gaps 207 ( Fig. 4D-3) is controlled to be in a range of approximately 5 nm to approximately 30 nm along the "x" direction, measured from an edge of the insulation layer 202 opposite the gate trenches 205. Likewise, the semiconductor layers 204 extend past the insulation layers 202 and the metal layer 206 toward the gate trenches 205 along the "x" direction. The thickness t1 of the metal layer 206 (also the height of the columns 207 along the "z" direction) is in a range of approximately 10 nm to approximately 60 nm in some embodiments.

[0022] For operation 20, procedure 10 ( Fig. 1A) deposit an inner spacer layer on the surfaces of layers 202, 204 (including 204c) and 206 exposed by gate trenches 205 and columns 207, such as in Fig. 4E-1, 4E-2, and 4E-3. In particular, the inner spacer layer 208 fills the gaps 207. In one embodiment, the inner spacer layer 208 comprises a low-k dielectric material, for example, a dielectric material having a dielectric constant less than 10, such as in a range of about 3 to about 10. For example, the inner spacer layer 208 may comprise SiCN, SiC, SiON, SiOCN, Al2O3, or other suitable dielectric materials. Example low-k dielectric materials suitable for the inner spacer layer 208 include fluorine-doped silicate glass, carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, benzocyclobutene (BCB), polyimide, other low-k dielectric material, or combinations thereof. In the present embodiment, the inner spacer layer 208 is deposited using ALD.In alternative embodiments, the inner spacer layer 208 may be deposited using CVD or other suitable methods. The inner spacer layer 208 has a thickness t2 (. Fig. 4E-3) in a range from approximately 5 nm to approximately 20 nm in the present embodiment. In particular, the thickness t2 is greater than half the thickness t1, so that the inner spacer layer 208 merges within the gaps 207 and completely fills the gaps 207.

[0023] In operation 22, the procedure etches 10 ( Fig. 1A) peel back the inner spacer layer 208 to remove it from the surfaces of the layers 202 and 204 that face the gate trenches 205, leaving remaining portions of the inner spacer layer 208 in the columns 207 as the inner spacer features 208, such as in Fig. 4F-1, 4F-2, and 4F-3. In various embodiments, the etch-back process may employ dry etching, wet etching, or reactive ion etching selectively matched with respect to the material of the inner spacer layer 208, and with minimal (to no) etching of the semiconductor layers 204 and the insulation layers 202. For example, the etch-back process may employ an isotropic wet etching process. As a result of operation 22, the channel regions 204c in the gate trenches 205 are exposed, and the surfaces of the layers 202 and 204 opposite the gate trenches 205 are also exposed. In one embodiment, the inner spacer features 208 completely fill the columns 207, and the length L1 of the inner spacer features 208 along the "x" direction substantially corresponds to the depth d1 of the columns 207, such as in Fig. 4F-3. In another embodiment, the inner spacer features 208 partially fill the gaps 207 and the length L1 of the inner spacer features 208 along the "x" direction is less than the depth d1 of the gaps 207. For example, the length L1 is about 80% to about 90% of the depth d1. In various embodiments, the length L1 may be in a range from about 5 nm to about 30 nm. If the length L1 is too small (such as shorter than about 5 nm), the inner spacer features 208 may not effectively reduce the coupling capacitance between the gate electrode 212 and the metal layer 206, and the risk of shorting the gate electrode 212 and the metal layer 206 may be too great. If the length L1 is too large (such as greater than 30 μm), then the inner spacer 208 would unnecessarily increase the footprint of the unit cell 250 and reduce the storage density of the 3D FERAM structure 200.

[0024] In operation 23, the procedure 10 ( Fig. 1A) optionally source / drain features (S / D features) 209 in the semiconductor layers 204. As in Fig. 6B, Fig. 6D, Fig. 6E and Fig. 6F, S / D features 209 may be formed in some embodiments of the MRAM unit cells 250. In embodiments where the semiconductor layer 204 comprises an oxide semiconductor material (as in Fig. 6B and Fig. 6D), the S / D features 209 may be formed by annealing the device 200 (for example, in an oxygen environment or a nitrogen environment) such that the metal layer 206 reacts with the semiconductor layer 204 to form the S / D features 209. In embodiments where the semiconductor layer 204 comprises polysilicon or other non-oxide semiconductor materials (such as in Fig. 6E and Fig. 6F), the S / D features 209 may be formed by doping suitable p- or n-type dopants into the semiconductor layer 204, for example, by ion implantation.

[0025] In operation 24, procedure 10 ( Fig. 1A) deposits an FE layer 210 on the various surfaces (including the surfaces of the isolation structure 202, the semiconductor layer 204, and the internal spacer features 208) exposed in the gate trenches 205. An embodiment thereof is shown in Fig. 4G. In particular, the FE layer 210 is deposited to surround each of the channel regions 204c, while a space S (see Fig. 1C) is left between the FE layer 210 on vertically adjacent channel regions 204c. The space S is large enough to fill the gate electrode 212 therein for a desired deposition technique, such as ALD, CVD, PVD, or plating. In one embodiment, the FE layer 210 is deposited to have a substantially uniform thickness on the various areas previously discussed. The thickness of the FE layer 210 may range from about 5 nm to about 30 nm in various embodiments. In one embodiment, the FE layer 210 is deposited using ALD to control the accuracy of the deposited thickness. In some embodiments, the FE layer 210 may be deposited using CVD, PVD, or other deposition techniques. In the present embodiment, the FE layer 210 comprises hafnium oxide (HfO2); Hafnium zirconium oxide (Hf x Zr 1-xO2); HfO2 doped with Si, Y, Ge, La or other suitable elements; aluminum scandium nitride (Al 1-x Sc x N); aluminum nitride (AlN); or other suitable ferroelectric materials.

[0026] In some embodiments, prior to depositing the FE layer 210, operation 24 may optionally deposit an interface layer 211 over the various surfaces exposed in the gate trenches 205 and then deposit the FE layer 210 over the interface layer. For example, the interface layer 211 is provided in the embodiments described in Fig. 6B, Fig. 6D, Fig. 6E and Fig. 6F. For example, the interface layer may enhance the adhesion between the FE layer 210 and the various surfaces located beneath the FE layer 210. The material for the interface layer 211 may be selected depending on the material of the semiconductor layer 204. When the semiconductor layer 204 comprises an oxide semiconductor material, the interface layer 211 may comprise aluminum oxide (e.g., AlO2), silicon oxide (e.g., SiO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), or another suitable material in various embodiments. When the semiconductor layer 204 comprises silicon, polysilicon, or another non-oxide semiconductor material, the interface layer 211 may comprise silicon oxide (e.g., SiO2), a native oxide of the material included in the semiconductor layer 204, or another suitable material in various embodiments.

[0027] In operation 26, procedure 10 ( Fig. 1A) deposit one or more gate electrode layers 212 in the gate trenches 205, which fill the gate trenches 205 and wrap around the FE layer 210, as in Fig. 4H. In one embodiment, the gate electrode 212 includes a p-type work function layer, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. In an alternative embodiment, the gate electrode 212 includes an n-type work function layer, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the gate electrode 212 may include both p-type work function layer(s) and n-type work function layer(s) to achieve a desired work function. In some embodiments, the gate electrode 212 may further include a low-resistivity metal, such as aluminum, tungsten, cobalt, copper, and / or other suitable materials, deposited over the p-type and / or n-type work function layers.The gate electrode 212 may be deposited using ALD, CVD, PECVD, plating, or other suitable methods.

[0028] In operation 28, the procedure etches 10 ( Fig. 1A) the gate electrode 212 and the FE layer 210 to form gate isolation trenches 215, such as in Fig. 4I. As a result of operation 28, a plurality of stacks of unit cells 250 are formed. Operation 28 may include a plurality of processes, such as photolithography and etching. In one embodiment, operation 28 comprises performing a photolithography process to form an etch mask (such as a pattern comprising a resist pattern) over structure 200, which is similar to the photolithography process explained with reference to operation 14. The etch mask provides openings corresponding to gate isolation trenches 215. After the etch mask is formed, operation 28 etches gate electrode 212 and FE layer 210 through the openings in the etch mask to form gate isolation trenches 215.Operation 28 may apply one or more etch processes that selectively target the materials of layers 212 and 210 with no (or minimal) etching with respect to isolation structure 202, semiconductor layer 204, and internal spacer features 208. In the present embodiment, the various etch processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. After gate isolation trenches 215 are etched, operation 28 removes the etch mask, for example, using resist stripping or other techniques.

[0029] In operation 30, the procedure 10 ( Fig. 1A) a gate insulation 214 in the gate isolation trenches 215, such as in Fig. 4J. In one embodiment, after depositing and overfilling a dielectric material in the gate isolation trenches 215, operation 30 performs a CMP process to planarize the top surface of the structure 200 and expose the gate electrode 212. The remaining dielectric material becomes the gate insulation 214. In some embodiments, the gate insulation 214 comprises a dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating material. The gate insulation 214 may be deposited using CVD, PECVD, flowable CVD, or other suitable methods in various embodiments.

[0030] In operation 32, the procedure 10 ( Fig. 1A) a staircase structure 260, such as in Fig. 4K. Each step in the staircase structure 260 has a FERAM layer 201. In the middle region (the channel region) of the FERAM layer 201, a plurality of channel regions 204c (see Fig. 1A, Fig. 1B and Fig. 1C) arranged in a column (along the "y" direction), FE layers 210 each surrounding the plurality of channel regions 204c, gate electrodes 212 each surrounding the FE layers 210, and gate insulation 214 separating and insulating the gate electrodes 212. On both sides of the center region, the FERAM layer 201 includes the insulation structure 202, the semiconductor layer 204 (source and drain regions), the internal spacer features 208, and the metal layer 206. The stair structure 260 can be formed using multiple photolithography, etching, and trimming processes. For example, a first etch mask is formed to cover the area of ​​the structure 200 corresponding to the top step of the stair structure 260, and then the structure 200 is etched until the metal layer 206 is exposed.A second etch mask is then formed to cover the area of ​​structure 200 corresponding to the top step and one step below the top step of stair structure 260. Structure 200 is then etched until the next metal layer 206 is exposed. This process may be repeated until stair structure 260 is formed. The various etching processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. The etch masks for the various etching processes may be formed using photolithography and trimming processes to achieve the desired shape.

[0031] In operation 34, the procedure 10 ( Fig. 1A) Vias 220 and 222 for contacting the metal layer 206 in the S / D regions at each step of the staircase structure 260 and forms vias 224 for contacting the gate electrodes 212, as in Fig. 4L. In one embodiment, operation 34 includes depositing one or more dielectric layers (not shown) over the stair structure 260; forming an etch mask (such as using a photolithography process) over the one or more dielectric layers, where the etch mask provides openings corresponding to the vias 220, 222, and 224; etching via holes into the one or more dielectric layers to expose the metal layer 206 at each step of the stair structure 260; and depositing one or more conductive materials in the via holes to form the vias 220, 222, and 224. For simplicity, the one or more dielectric layers are not shown in Fig. 4L. The one or more dielectric layers may comprise oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The one or more dielectric layers may be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable processes. The vias 220, 222 and 224 may comprise one or more conductive materials, such as Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, TaN, Ni, TiSiN or combinations thereof and may be formed by ALD, CVD, PVD, plating and / or other suitable processes.

[0032] In operation 36, the procedure 10 ( Fig. 1A) performs further fabrication. For example, it may form interconnect layers above the MRAM 200. For example, the interconnect layers may include word lines (WL), bit lines (BL), and source lines (SL), each electrically connected to the vias 224, 222, and 220. For example, Fig. 2 the SL 230 and the BL 232, which are each electrically connected to the vias 220 and 222. Fig. Figure 2 illustrates a WL formed beneath MRAM 200 in one embodiment. In an alternative embodiment (not shown), the WL may be formed above MRAM 200 and electrically connected to gate vias 224.

[0033] Fig. 5A illustrates a schematic top view of MRAM 200 according to one embodiment. Fig. Figure 5B illustrates a portion of an equivalent 3D circuit of the MRAM 200 shown in Fig. 5A, while Fig. 5C illustrates a portion of a condensed 2D circuit of the MRAM 200 shown in Fig. 5A. With reference to Fig. 5A, the word lines WL are aligned along the "x" direction and connected to the gate electrodes through vias 224. The bit lines BL and the source lines SL are aligned along the "y" direction and connected to the source / drain features through vias 222 and 220, respectively. In the Fig. In the embodiment illustrated in Figure 5A, there are m bit lines BL and m source lines SL per column of MRAM cells (for example, there are m steps in the staircase structure 260). Two columns of MRAM cells are arranged in a stepped manner, and each column provides L stacks of unit cells 250 (thus, two columns provide 2 L stacks of unit cells 250), with each stack of unit cells 250 being addressed by a word line WL. The word lines WL are routed to a WL decoder. The bit lines are routed to a BL decoder. The source lines are routed to an SL decoder. By controlling the WL decoder, the BL decoder, and the SL decoder, each MRAM unit cell 250 can be accessed.

[0034] Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E and Fig. 6F illustrate various embodiments of a portion of the unit cell 250 that may be implemented in the MRAM 200, according to the present disclosure. In particular, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 6D, Fig. 6E and Fig. 6F illustrate schematic cross-sectional views of the semiconductor layer 204 (including the optional S / D 209 and the channel region 204c), the metal layer 206, the optional interface layer 211, the FE layer 210, and the gate electrode 212 in various configurations. These are non-limiting examples of the unit cell 250 according to the present disclosure. In the Fig. 6A, the FE layer 210 lies directly on the semiconductor layer 204, which comprises an oxide semiconductor material. This embodiment does not include the S / D 209 and the interface layer 211. In the embodiment shown in Fig. 6B, the FE layer 210 lies directly on an interface layer 211, which lies directly on the semiconductor layer 204 comprising an oxide semiconductor material. This embodiment does not include the S / D 209. In the embodiment shown in Fig. 6C, the FE layer 210 lies directly on the semiconductor layer 204, which comprises an oxide semiconductor material. In this embodiment, the semiconductor layer 204 has an S / D 209 formed in the semiconductor layer 204. In the embodiment shown in Fig. In the embodiment shown in Figure 6D, the FE layer 210 lies directly on an interface layer 211, which lies directly on the semiconductor layer 204 comprising an oxide semiconductor material. In this embodiment, the semiconductor layer 204 has an S / D 209 formed in the semiconductor layer 204. In the embodiment shown in Fig. 6E, the FE layer 210 lies directly on an interface layer 211, which lies directly on the semiconductor layer 204, which comprises polysilicon. In this embodiment, the semiconductor layer 204 has an S / D 209 formed in the semiconductor layer 204. Using polysilicon as the semiconductor material in the semiconductor layer 204 reduces the cost of manufacturing the MRAM 200 compared to embodiments that use crystalline silicon as the semiconductor material in the semiconductor layer 204. In the embodiment shown in Fig. 6F, the FE layer 210 lies directly on an interface layer 211, which lies directly on the semiconductor layer 204, which comprises silicon (such as crystalline silicon) or another suitable semiconductor material. In this embodiment, the semiconductor layer 204 has an S / D 209 formed in the semiconductor layer 204. For embodiments shown in Fig. 6E and Fig. 6F, the interface layer 211 may comprise silicon oxide (SiO2) in one embodiment. For embodiments shown in Fig. 6A, Fig. 6B, Fig. 6C and Fig. 6D, the semiconductor layer 204 may comprise indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), another suitable oxide semiconductor, or a combination thereof. For embodiments shown in Fig. 6B, the interface layer 211 may comprise aluminum oxide (Al2O3), silicon oxide (SiO2), or other suitable materials in some embodiments. For embodiments shown in Fig. 6D, the interface layer 211 may comprise aluminum oxide (e.g., Al2O3), silicon oxide (e.g., SiO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), or other suitable material in various embodiments.

[0035] While not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the disclosed 3D FERAM structure enable a high-density FERAM memory array. In another example, in some embodiments, the source / drain electrodes of the disclosed FERAM array are formed as part of an initial multi-layer stack before the gate electrode is formed and naturally connect all channel layers in the same row. Thus, additional process steps for forming the source / drain electrodes are not required, simplifying the manufacturing process. In yet another example, the dielectric internal spacers in the disclosed FERAM array reduce the coupling capacitance between the gate electrodes and the source / drain electrodes, thereby increasing the operating speed of the FERAM array.

[0036] In one exemplary aspect, the present disclosure is directed to a device comprising a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, the gate structure comprising a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further comprises two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

[0037] In some embodiments, the inner spacer layer also lies between the two second electrodes and the gate structure. In one embodiment, the device further comprises a gate via disposed on and connected to the gate structure; a source via disposed on and connected to one of the first electrodes; and a bitline via disposed on and connected to another of the first electrodes. In another embodiment, the device further comprises one or more transistors; and an Nth metal layer over the one or more transistors, where N is a natural number, wherein the first channel is disposed over the Nth metal layer. In yet another embodiment, the device further comprises an interface layer between the FE layer and each of the first and second channels.

[0038] In one embodiment of the device, the FE layer comprises HfO2; Hf x Zr 1-x O2; HfO2 doped with Si, Y, Ge, or Laa; AlScN, or AlN. In another embodiment, the first and second channels comprise an oxide semiconductor or polysilicon. In some embodiments, the inner spacer layer comprises a dielectric material having a dielectric constant less than 10.

[0039] In one embodiment of the device, the first and second electrodes comprise TiN, TaN, Ru, or W. In another embodiment of the device, the first and second electrodes extend longitudinally along a first direction, and the first electrodes extend longer than the second electrodes.

[0040] In another exemplary aspect, the present disclosure is directed to a device comprising a plurality of transistors; and a 3D FERAM structure above the plurality of transistors. The 3D FERAM structure comprises a plurality of unit cells stacked vertically one on top of the other. Each unit cell comprises a semiconductor layer, a ferroelectric (FE) layer surrounding a portion of the semiconductor layer, a gate layer over the FE layer surrounding the portion of the semiconductor layer, an insulating layer below the semiconductor layer, a metal layer over the semiconductor layer, and a dielectric spacer layer over the semiconductor layer and between the FE layer and the metal layer.

[0041] In one embodiment of the device, the dielectric spacer layer comprises a dielectric material having a dielectric constant less than 10. In one embodiment, the FE layer comprises HfO2, Hf x Zr 1-x O2, HfO2 doped with Si, Y, Ge, or La, AlScN, or AlN; the metal layer comprises TiN, TaN, Ru, or W; and the semiconductor layer comprises an oxide semiconductor or polysilicon. In one embodiment, the device further comprises an interface layer between the FE layer and the portion of the semiconductor layer.

[0042] In another exemplary aspect, the present disclosure is directed to a method comprising forming a stack of multilayers, each multilayer comprising a first insulating layer, a semiconductor layer over the first insulating layer, and a first metal layer over the semiconductor layer.The method further comprises etching the stack of multilayers to form gate trenches in a channel region of the stack of multilayers; removing the first insulating layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first insulating layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions of the semiconductor layers and overlying sidewalls of the gate trenches, the inner spacer layer being laterally disposed between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer, filling the gate trenches.

[0043] In one embodiment of the method, forming the inner spacer layer comprises depositing a dielectric material surrounding the channel portions of the semiconductor layers and filling the gaps; and etching the dielectric material such that the dielectric material is removed from outer surfaces of the channel portions of the semiconductor layers, but at least a portion of the dielectric material remains in the gaps, wherein the portion of the dielectric material remaining in the gaps becomes the inner spacer layer.

[0044] In one embodiment, the method further comprises etching the metal gate layer and the FE layer to form metal gates separated by isolation trenches, and filling the isolation trenches with a second isolation layer. In another embodiment, the method further comprises etching the second isolation layer and the stack of multilayers to form a staircase structure having multiple steps one above the other, each step comprising a portion of the second isolation layer, two portions of the inner spacer layer adjacent to an upper part of the portion of the second isolation layer, and two portions of one of the multilayers sandwiching both the portion of the second isolation layer and the two portions of the inner spacer layer.In another embodiment, the method comprises forming vias on the first metal layer at each of the multiple stages. In some embodiments of the method, the inner spacer layer comprises a dielectric material having a dielectric constant less than 10.

[0045] In yet another exemplary aspect, the present disclosure is directed to a method comprising forming a stack of multilayers, where each multilayer comprises a first insulating layer, a semiconductor layer over the first insulating layer, and a first metal layer over the semiconductor layer; forming gate trenches in a channel region of the stack of multilayers, wherein channel portions of the semiconductor layers are exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first insulating layers and the semiconductor layers; forming an inner spacer layer in the gaps;forming a ferroelectric layer (FE layer) surrounding each of the channel portions of the semiconductor layers and overlying sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and each of the first metal layers; and forming metal gates over the FE layer, each of the metal gates engaging a plurality of the channel portions of the semiconductor layers disposed one above the other.

[0046] In one embodiment of the method, forming the gate trenches comprises etching the stack of multilayers in a channel region of the stack of multilayers by a first etching process, resulting in gate trenches; and removing the first insulation layers and the first metal layers from the channel region by a second etching process different from the first etching process, resulting in the channel portions of the semiconductor layers being exposed in the gate trenches.

[0047] In one embodiment of the method, forming the inner spacer layer comprises: depositing a dielectric material surrounding the channel portions of the semiconductor layers and filling the gaps; and etching the dielectric material such that the dielectric material is removed from the channel portions of the semiconductor layers, but at least a portion of the dielectric material remains in the gaps, wherein the portion of the dielectric material remaining in the gaps becomes the inner spacer layer.

[0048] In one embodiment of the method, forming the metal gates comprises: depositing one or more metal gate layers over the FE layer and filling the gate trenches; etching the one or more metal gate layers and the FE layer to form the metal gates separated by isolation trenches; and filling the isolation trenches with a second isolation layer.

Claims

[1] Three-dimensional ferroelectric RAM memory device comprising: a first channel (204c); a second channel (204c) above the first channel (204c); a gate structure (212) surrounding the first and second channels (204c), the gate structure (212) comprising a ferroelectric layer (210) surrounding the first and second channels and a gate metal layer surrounding the ferroelectric layer; two first electrodes (206) connected to two sides of the first channel (204c); two second electrodes (206) connected to two sides of the second channel (204c); a dielectric layer (202) between the first and second electrodes (206); and an inner spacer layer (208) between the two first electrodes (206) and the gate structure (212). [2] A three-dimensional ferroelectric RAM memory device according to claim 1, wherein the inner spacer layer (208) is also located between the two second electrodes (206) and the gate structure (212). [3] A three-dimensional ferroelectric RAM memory device according to claim 1 or 2, further comprising: a gate via (224) disposed on and connected to the gate structure (212); a source via (220) disposed on and connected to one of the first electrodes (206); and a bit line via (222) disposed on and connected to another of the first electrodes (206). [4] A three-dimensional ferroelectric RAM memory device according to any preceding claim, further comprising: one or more transistors (150); and an N-th metal layer over the one or more transistors (150), where N is a natural number, wherein the first channel (204c) is disposed over the N-th metal layer. [5] A three-dimensional ferroelectric RAM memory device according to any preceding claim, further comprising: an interface layer (211) between the ferroelectric layer (210) and each of the first and second channels (204c). [6] Three-dimensional ferroelectric RAM memory device according to one of the preceding claims, wherein the ferroelectric layer (210) comprises HfO2, Hf x Zr 1-x O2, HfO2 doped with Si, Y, Ge or La, AlScN or AlN. [7] A three-dimensional ferroelectric RAM memory device according to any preceding claim, wherein the first and second channels (204c) comprise an oxide semiconductor or polysilicon. [8] A three-dimensional ferroelectric RAM memory device according to any preceding claim, wherein the inner spacer layer (208) comprises a dielectric material having a dielectric constant less than 10. [9] A three-dimensional ferroelectric RAM memory device according to any preceding claim, wherein the first and second electrodes (206) comprise TiN, TaN, Ru or W. [10] A three-dimensional ferroelectric RAM memory device according to any preceding claim, wherein the first and second electrodes (206) extend lengthwise along a first direction and the first electrodes (206) extend longer than the second electrodes (206). [11] Method comprising: Forming a stack of multilayers (201), each multilayer (201) comprising a first insulating layer, a semiconductor layer (204) over the first insulating layer, and a first metal layer over the semiconductor layer (204); Etching the stack of multilayers (201) to form gate trenches (205) in a channel region (203, 204c) of the stack of multilayers (201); Removing the first insulation layers and the first metal layers from the channel region (203, 204c), resulting in channel portions of the semiconductor layers (204) being exposed in the gate trenches (205); laterally recessing the first metal layers from the gate trenches (205), resulting in gaps (207) between adjacent layers of the first insulation layers and the semiconductor layers (204); forming an inner spacer layer (208) in the gaps (207); Forming a ferroelectric layer (210) surrounding each of the channel portions of the semiconductor layers (204) and overlying sidewalls of the gate trenches (205), wherein the inner spacer layer (208) is disposed laterally between the ferroelectric layer and the first metal layers; and Depositing, over the ferroelectric layer (210), a metal gate layer filling the gate trenches (205). [12] The method of claim 11, wherein forming the inner spacer layer comprises: Depositing a dielectric material surrounding the channel portions of the semiconductor layers (204) and filling the gaps (207); and Etching the dielectric material such that the dielectric material is removed from outer surfaces of the channel portions of the semiconductor layers (204), but at least a portion of the dielectric material remains in the gaps (207), wherein the portion of the dielectric material remaining in the gaps (207) becomes the inner spacer layer (208). [13] The method of claim 11 or 12, further comprising: etching the metal gate layer and the ferroelectric layer (210) to form metal gates separated by isolation trenches (215); and Filling the insulation trenches (215) with a second insulation layer. [14] The method of claim 13, further comprising: Etching the second insulation layer and the stack of multilayers (201) to form a staircase structure (260) having a plurality of steps one above the other, each step comprising a portion of the second insulation layer, two portions of the inner spacer layer (208) adjacent to an upper part of the portion of the second insulation layer, and two portions of one of the multilayers (201) sandwiching both the portion of the second insulation layer and the two portions of the inner spacer layer (208). [15] The method of claim 14, further comprising: Forming vias (220, 222) on the first metal layer at each of the plurality of stages. [16] The method of any one of the preceding claims 11 to 15, wherein the inner spacer layer (208) comprises a dielectric material having a dielectric constant less than 10. [17] Device comprising: a plurality of transistors (150); and a 3D FERAM structure above the plurality of transistors (150), the 3D FERAM structure comprising a plurality of unit cells stacked vertically one above the other, each unit cell comprising a semiconductor layer (204), a ferroelectric layer surrounding a portion of the semiconductor layer (204), a gate layer above the ferroelectric layer (210) surrounding the portion of the semiconductor layer (204), an insulation layer (202) below the semiconductor layer (204), a metal layer (206) above the semiconductor layer (204), and a dielectric spacer layer above the semiconductor layer (204) and between the ferroelectric layer (210) and the metal layer (206). [18] The device of claim 17, wherein the dielectric spacer layer comprises a dielectric material having a dielectric constant less than 10. [19] Apparatus according to claim 17 or 18, further comprising: an interface layer (211) between the ferroelectric layer (210) and the portion of the semiconductor layer (204). [20] Device according to one of the preceding claims 17 to 19, wherein the ferroelectric layer (210) comprises HfO2, Hf x Zr 1-x O2, HfO2 doped with Si, Y, Ge or La, AlScN or AlN; the metal layer (206) comprises TiN, TaN, Ru or W; and the semiconductor layer (204) comprises an oxide semiconductor or polysilicon.

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