THREE-DIMENSIONAL STORAGE DEVICE AND METHOD

Abstract

Method comprising: forming a word line (62, 114) between a pair of first dielectric layers (72, 106); depositing a data storage layer (116A) on side walls of the first dielectric layers (72, 106) and a side wall of the word line (62, 114); forming a first isolation region (118A) on the data storage layer (116A); structuring a first opening (130) in the first isolation region (118A); and forming a channel layer (138) and a return gate (144) in the first opening (130), wherein the return gate (144) is surrounded by the channel layer (138).

Description

GENERAL STATE OF THE ARTSemiconductor memories are used in integrated circuits for electronic applications including, for example, radios, televisions, mobile phones and personal computer devices. Semiconductor memories comprise two main categories. One is volatile memory and the other is nonvolatile memory. Volatile memories include random access memories (RAMs) which can be further divided into two sub-categories, static random access memories (SRAMs) and dynamic random access memories (DRAMs). Both SRAMs and DRAMs are volatile because they will lose the information they store when not energized.On the other hand, nonvolatile memories may retain the data stored therein. One type of nonvolatile semiconductor memory is a ferroelectric random access memory (FeRAM). The advantages of an FeRAM include its fast read / write speed and its small size.From document US 2020 / 0 227 439 A1 a method is known comprising forming a word line between a pair of first dielectric layers, depositing a data storage layer and forming a channel layer and a back gate. From the document US 2016 / 0 012 901 A1, a device is known, comprising a source line, a bit line and a back gate, which extend in a first direction, as well as a word line, which extends in a second direction orthogonal to the first direction. The device further includes a data storage layer extending along the wordline.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 is a block diagram of a random access memory. FIGS. 2A and 2B are various views of a memory array. FIGS. 3A through 20C are various views of intermediate stages in the fabrication of a memory array, in accordance with some embodiments. FIGS. 21A to 21D are plan views of a memory array according to some embodiments. FIGS. 22A and 22B are top views of a memory array, in accordance with some embodiments. FIGS. 23A, 23B, and 24 are sectional views of a semiconductor device according to some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course merely examples. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "below," "above," "above," and the like may be used herein to simplify the description to describe the relationship of an element or feature to (another) element(s) or feature(s) depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may also be interpreted accordingly.According to various embodiments, a three-dimensional memory array is formed of programmable thin film transistors (TFTs) with back gates. The data storage layers of the TFTs are disposed between the back gates and the word lines for the TFTs. During a write operation (e.g., an erase or program operation) for a TFT, a bias voltage is applied to the back gate of the TFT, thereby increasing the write voltage applied across the data storage layer of the TFT during the write operation. Increasing the write voltage applied across the data storage layer during the write operation may help increase the speed and accuracy of the write operation. This may increase the performance of the memory array.FIG. 1 is a block diagram of a random access memory 50. the random access memory 50 includes a memory array 52, a row decoder 54, and a column decoder 56. The memory array 52, the row decoder 54, and the column decoder 56 may each be part of a same semiconductor die or may be parts of different semiconductor dies. For example, the memory array 52 may be part of a first semiconductor die, while the row decoder 54 and the column decoder 56 may be parts of a second semiconductor die.The memory array 52 includes memory cells 58, word lines 62, bit lines 64B, and source lines 64S. The memory cells 58 are arranged in rows and columns. The word lines 62, the bit lines 64B, and the source lines 64S are electrically connected to the memory cells 58. The word lines 62 are conductive traces that extend along the rows of memory cells 58. The bit lines 64B and the source lines 64S are conductive traces that extend along the columns of the memory cells 58.The row decoder 54 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like. During operation, by activating the word line 62, the row decoder 54 selects memory cells 58 desired for the row in a row of the memory array 52. the column decoder 56 may be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like, and may include writer drivers, sense amplifiers, combinations thereof, or the like. In operation, the column decoder 56 selects the desired memory cells 58 from columns of the memory array 52 in the selected row and reads or writes data to the selected memory cells 58 via the bit lines 64B and the source lines 64S.FIGS. 2A and 2B are various views of a memory array 52. FIG. 2A is a circuit diagram of the memory array 52. FIG. 2B is a three-dimensional view of a portion of the memory array 52, and is described in conjunction with FIG. 2A. Each memory cell 58 of the memory array 52 is a flash memory cell comprising a programmable TFT.FIGS. 2A and 2B illustrate three orthogonal directions D 1, D 2 and D 3 to which the following figures are referred for clarity. The first direction D 1 is parallel to a main surface of an underlying substrate. The second direction D 2 is orthogonal to the first direction D 1 and parallel to the main surface of the underlying substrate. The third direction D 3 is orthogonal to the first direction D 1, the second direction D 2 and the main surface of the underlying substrate.In some embodiments, the memory array 52 is a flash memory array, such as a NOR flash memory array. In some embodiments, the memory array 52 is another type of non-volatile memory array, such as a magneto-resistive random access memory (MRAM) array, a resistive random access memory (RRAM) array, or the like. Each of the memory cells 58 is a flash memory cell having a TFT 68. The gate of each TFT 68 is electrically connected to a corresponding word line 62, a first source / drain region of each TFT 68 is electrically connected to a corresponding bit line 64B, and a second source / drain region of each TFT 68 is electrically connected to a corresponding source line 64S (each electrically connected to ground). The memory cells 58 in a same row of the memory array 52 have a common word line 62, while the memory cells in a same column of the memory array 52 have a common bit line 64B and a common source line 64S.The memory array 52 includes a plurality of horizontally disposed conductive traces (e.g., the word lines 62), each of the word lines 62 being disposed between dielectric layers 72. The word lines 62 extend in the first direction D 1. The word lines 62 may have a staircase configuration such that lower word lines 62 are longer than upper word lines 62 and extend laterally beyond their endpoints. For example, in FIG. 2B, multiple stacked layers of word lines 62 are illustrated, with the top word lines 62T being the shortest lines and the bottom word lines 62B being the longest lines. The respective lengths of the word lines 62 increase in a direction toward the underlying substrate. In this way, a portion of each wordline 62 may be accessible from above the memory array 52, such that conductive contacts may be formed at an exposed portion of each wordline 62.The bit lines 64B and the source lines 64S are vertically arranged conductive lines. The bit lines 64B and the source lines 64S extend in the third direction D 3. Between adjacent bit lines 64B and source lines 64S, an isolation region 74 is arranged, which isolates them. The boundaries of each memory cell 58 are formed by pairs of the bit lines 64B and the source lines 64, and a crossing word line 62. Between adjacent TFTs 68 (e.g., adjacent pairs of the bit lines 64B and the source lines 64S), an isolation region 76 is disposed to isolate them. Although FIGS. 2A and 2B illustrate a particular positioning of the bit lines 64B with respect to the source lines 64S, it should be understood that the positioning of the bit lines 64B and the source lines 64S may be reversed in other embodiments.The memory array 52 further includes semiconductor strips 82 and tunneling strips 84. The tunneling stripes 84 are in contact with the word lines 62. The semiconductor strips 82 are arranged between the tunnelling strips 82 and the isolation regions 74. In this embodiment, the semiconductor strips 82 are also disposed between the tunneling strips 84 and each of the bit lines 64B and the source lines 64S. In another embodiment (which will be discussed in greater detail below with reference to FIGS. 20A-20C), the semiconductor strips 82 are disposed between the isolation regions 74 and each of the bit lines 64B and the source lines 64S.The semiconductor strips 82 provide channel regions for the TFTs 68 of the memory cells 58 and may also be referred to as channel layers. For example, when an appropriate voltage (e.g., higher than a respective threshold voltage of a corresponding TFT 68) is applied by a corresponding word line 62, a portion of a semiconductor strip 82 intersecting the word line 62 may allow current to flow from a bit line 64B to a corresponding source line 64S (e.g., in a first direction D 1). In the illustrated embodiment, each semiconductor strip 82 is in contact with a surface of a corresponding word line 62, thereby providing shallow channel regions for the TFTs 68. In another embodiment, the word lines 62 are formed such that each semiconductor strip 82 is in contact with multiple areas of each corresponding word line 62, thereby providing three-dimensional channel regions for the TFTs 68.The tunneling strips 84 may be polarized in one of two different directions by applying an appropriate voltage across the tunneling strips 84, and may also be referred to as data storage layers. A threshold voltage of a corresponding TFT 68 varies depending on the polarization direction of a particular portion of a tunneling stripe 84, and a digital value (e.g., 0 or 1) may be stored. For example, if a portion of a tunneling strip 84 has a first electrical polarization direction, the corresponding TFT 68 may have a relatively low threshold voltage, while the corresponding TFT 68 may have a relatively high threshold voltage if the portion of the tunneling strip has a second electrical polarization direction. The difference between the two threshold voltages may be referred to as the threshold voltage offset. A larger threshold voltage shift makes reading the digital value stored in the corresponding memory cell 58 easier (less error prone). In some embodiments, the tunneling stripes 84 are formed of a high-k ferroelectric material, and thus the memory array 52 may also be referred to as a ferroelectric random access memory (FeRAM) array.In order to perform a write operation on a particular memory cell 58, a write voltage is applied across a portion of the tunneling stripe 84 corresponding to the memory cell 58. The write voltage may be applied, for example, by applying appropriate voltages to the word line 62, the bit line 64B, and the source line 64S corresponding to the memory cell 58. By applying the write voltage across the portion of the tunneling stripe 84, a polarization direction of the portion of the tunneling stripe 84 can be changed. As a result, the corresponding threshold voltage of the corresponding TFT 68 may be switched from a low threshold voltage to a high threshold voltage (or vice versa), such that a digital value may be stored in the memory cell 58. Since the word lines 62 and the bit lines 64B intersect each other in the memory array 52, individual memory cells 58 may be selected and described.In order to perform a read operation on a particular memory cell 58, a read voltage (a voltage between the low and high threshold voltages) is applied to the word line 62 corresponding to the memory cell 58. Depending on the polarization direction of the corresponding portion of the tunneling strip 84, the TFT 68 of the memory cell 58 may or may not be turned on. As a result, the bit line 64B may be discharged (e.g., to ground) or not discharged through the source line 64S, so that the digital value stored in the memory cell 58 may be determined. Since the word lines 62 and the bit lines 64B intersect each other in the memory array 52, individual cells can be selected and read out.As will be discussed in more detail below, back gates (not shown in FIGS. 2A and 2B, see FIGS. 20A through 20C ) are formed that extend through the isolation regions 74. Applying the write voltage during a write operation for a memory cell 58 also includes applying a bias voltage to the back gate corresponding to the memory cell 58. Applying the bias voltage to the back gate increases the write voltage applied across the portion of the tunneling stripe 84 corresponding to the memory cell 58. Increasing the write voltage applied during the write operation may help to increase the speed and accuracy of the write operation. And since a bias voltage is applied, the voltages applied to the word line 62, the bit line 64B, and the source line 64S during the write operation can be reduced, which reduces the complexity of the row decoder and / or the column decoder for the memory array 52. The back gates are not used during read operations and may be left floating during read operations.FIGS. 3A through 20C are various views of intermediate stages in the fabrication of a memory array 52, in accordance with some embodiments. Each memory cell 58 of the memory array is a flash memory cell that includes a programmable TFT 68 (see Figs. 20A-20C). FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A are three-dimensional views. FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are sectional views taken along the reference cross section B-B in FIG. 19A. FIG. 20C is a sectional view taken along reference cross section C-C in FIG. 19A. A portion of the memory array 52 is shown. Some features such as the staircase arrangement of the word lines (see Fig. 2B) are not shown for clarity.In FIGS. 3A and 3B, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 102 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 102 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. The substrate 102 may include a dielectric material. For example, the substrate 102 may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for the substrate 102 include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like, or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like. In some embodiments, the substrate 102 is formed of silicon carbide.A multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 includes alternating dielectric layers 106 and sacrificial layers 108. The dielectric layers are formed of a first dielectric material and the sacrificial layers are formed of a second dielectric material. The dielectric materials may be selected from the candidate dielectric materials of the substrate 102, respectively.The multilayer stack 104 is patterned in subsequent processing. Therefore, dielectric materials of both the dielectric layers 106 and the sacrificial layers 108 have high etch selectivity from the etching of the substrate 102. The patterned dielectric layers 106 will be used to isolate subsequently formed TFTs. The patterned sacrificial layers 108 may also be referred to as dummy layers and will be selectively replaced with word lines for the TFTs during subsequent processing. Therefore, the second dielectric material of the sacrificial layers 108 also has a high etch selectivity from the etching of the first dielectric material of the dielectric layers 106. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 may be formed of silicon oxide and the sacrificial layers 108 may be formed of silicon nitride. Other combinations of dielectric materials having acceptable etch selectivity to each other may also be used.Each layer of the multilayer stack 104 may be formed by an acceptable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. A thickness of each of the layers may be in the range of about 40 nm to about 50 nm. In some embodiments, the dielectric layers 106 are formed to a different thickness than the sacrificial layers 108. For example, the sacrificial layers 108 may be formed to a thickness greater than the dielectric layers 106. In the illustrated embodiment, the multilayer stack 104 includes five dielectric layers 106 and four sacrificial layers 108. It should be appreciated that the multilayer stack 104 may include other numbers of dielectric layers 106 and sacrificial layers 108. The multilayer stack 104 may have a total height H 1 in the range of about 1000 nm to about 10000 nm.As will be discussed in more detail below, FIGS. 4A-11B illustrate a process in which a multi-patterning process is used to form some of the features of the TFTs. The multi-patterning process may be a double patterning process, a quad-patterning process, or the like. FIGS. 4A to 11B illustrate a double patterning process. In a dual patterning process, trenches 1104 (see FIGS. 4A and 4B ) are patterned in regions of the multilayer stack 104 by a first etching process, and features for a first subset of the TFTs are formed in the trenches 110A. Then, by a second etching process, trenches 110B (see FIGS. 8A and 8B ) are formed in other regions of the multilayer stack 104, and features for a second subset of the TFTs are formed in the trenches 110B. Forming the features of the TFTs by a multi-patterning process allows each patterning process to be performed with a low pattern density, which may help reduce defects while still allowing the memory cell 52 to have a sufficient memory cell density. Further, forming the features of the TFTs by a multi-patterning process also allows for avoiding each patterned portion of the multi-layer stack 104 from having an excessively high aspect ratio, thereby improving the structural stability of the resulting memory device.In FIGS. 4A and 4B, trenches 1104 are patterned in the multilayer stack 104. In the illustrated embodiment, the trenches 110A extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the trenches 110A extend through some, but not all, layers of the multilayer stack 104. The trenches 110A may be patterned using acceptable photolithography and etching techniques, such as by an etching process selective to the multilayer stack 104 (e.g., the dielectric materials of the dielectric layers 105 and the sacrificial layers 108 selectively removed at a faster rate than the material of the substrate 102). The etching may be any acceptable etching process such as a reactive ion etch (RIE), a neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the sacrificial layers 108 are formed of silicon nitride, the trenches 110A may be formed by a dry etching process using a fluorine-based gas (e.g., C 4 F 6) mixed with hydrogen gas (H2gas) or oxygen gas (O2gas). After patterning, respective portions of the multilayer stack 104 are disposed between respective trenches 110A. Each portion of the multilayer stack 104 has a width W 1 in the second direction D 2( see FIGS. 2A and 2B ), which may be in the range of about 50 nm to about 500 nm. In addition, the individual portions of the binocular stack 104 are separated in the second direction D 2 by a separation distance S 1, which may be in the range of about 50 nm to about 200 nm.In FIGS. 5A and 5B, the trenches 110A are extended to form sidewall recesses 112A. Specifically, portions of the sidewalls of the sacrificial layers 108 exposed by the trenches 110A are recessed to form the sidewall recesses 112A. Although the sidewalls of sacrificial layers 108 are depicted as being straight, the sidewalls may be concave or convex. The sidewall recesses 112A may be formed by an acceptable etching process, such as one that is selective to the material of the sacrificial layers 108 (e.g., selectively removing the material of the sacrificial layers 108 at a faster rate than the material or materials of the dielectric layers 106 and the substrate 102). The etching may be isotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the sacrificial layers 108 are formed of silicon nitride, the trenches 110A may be extended by wet etching using phosphoric acid (H 3 PO 4) In another embodiment, dry etching selective to the material of the sacrificial layers 108 may be used.After formation, the sidewall recesses 112A have a depth D 4 in the second direction D 2( see FIGS. 2A and 2B ) that extends beyond the sidewalls of the dielectric layers 106. A time-controlled etch may be used to stop the etching of the sidewall recesses 112A after the sidewall recesses 112A have reached a desired depth D 4. For example, the sidewall recesses 112A may have a depth D 4 in the range of about 10 nm to about 60 nm. Forming the sidewall recesses 112A may reduce the widths of the sacrificial layers 108 by about 5% to about 30%. Continuing with the previous example, after the etching, the sacrificial layers 108 may have a width W 2 in the second direction D 2 that may be in the range of about 50 nm to about 450 nm.In FIGS. 6A and 6B, conductive features 114A (e.g., metal lines) are formed in the sidewall recesses 112A, thereby completing a process for replacing first portions of the sacrificial layers 108. The conductive features 114A may each include one or more layers such as seed layers, adhesive layers, barrier layers, diffusion layers, fill layers, and the like. In some embodiments, the conductive features 114A each include a seed layer 114A S( or barrier layer) and a main layer 114A M. Each seed layer 114A S extends along three sides (e.g., the top surface, a sidewall, and the bottom surface) of a corresponding main layer 114A M, which is located in a corresponding sidewall recess 112A. The seed layers 114A S are formed of a first conductive material that may be used to assist growth or assist adhesion of a subsequently deposited material, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The main layers 114A M may be made of a second conductive material, such as a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold. Alloys thereof or the like can be formed. The material of the seed layers 114A S is a material having good adhesion to the material of the dielectric layers 106, and the material of the main layers 114A M is a material having good adhesion to the material of the seed layers 114A S. In embodiments where the dielectric layers 106 are formed of an oxide such as silicon oxide, the seed layers 114A S may be formed of titanium nitride or tantalum nitride, and the main layers 114A M may be formed of tungsten. The materials of the seed layers 114A S and the main layers 114A M may be formed by acceptable deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. An acceptable etching process, such as a dry etch (e.g., a reactive ion etch (RIE), a neutral beam etch (NBE), the like), a wet etch, the like, or a combination thereof, may be performed to remove excess material from the sidewalls of the dielectric layers 106 and the top surface of the substrate 102. The etching may be anisotropic. Each of the conductive features 114A may have a similar overall thickness as the sacrificial layers 108 (discussed above for FIGS. 3A and 3B ), and may have a similar overall width as the depth D 4 of the sidewall recesses 112A (discussed above for FIGS. 5A and 5B ). Each seed layer 114A S may have a thickness in the range of about 1 nm to about 10 nm, and each main layer 114A M may have a thickness in the range of about 15 nm to about 35 nm, wherein the thickness of the seed layer 114A S is greater than the thickness of the main layer 114A M.In FIGS. 7A and 7B, tunneling stripes 116A and isolation regions 118A are formed in the trenches 110A. In particular, a tunnelling strip 116A and an isolation region 118A are formed in each trench 110A. In this processing step, no semiconductor stripes are formed. Rather, as will be discussed in more detail below, semiconductor strips are formed by openings in the isolation regions 118A in a subsequent processing step.The tunnelling strips 116A are formed of an acceptable material for storing digital values. In some embodiments, the tunneling strips 116A are formed of a high-k ferroelectric material such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), or the like; undoped hafnium oxide (HfO); or the like. In some embodiments, the tunneling strips 116A include one or more low-k dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, or the like. The material of the tunneling strips 116A may be formed by an acceptable deposition process such as ALD, CVD, physical vapor deposition (PVD), or the like. In some embodiments, the tunneling strips 116A are formed of HfZrO deposited by an ALD.Isolation regions 118A are formed of an acceptable material for protecting and electrically isolating underlying tunneling strips 1116A. Acceptable dielectric materials for the isolation regions 118A include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like, or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. The material of the isolation regions 118 may be formed by an acceptable deposition process such as an ALD, a CVD, a flowable CVD (FCVD), or the like. In some embodiments, isolation regions 118A are formed from an oxide, such as silicon oxide, deposited by an FCVD.The tunneling stripes 116A and the isolation regions 118A may be formed by a combination of deposition, etching, and planarization. For example, a tunneling layer is conformally deposited on the multilayer stack 104 and in the trenches 110A (e.g., on the sidewalls of the conductive features 114A and the sidewalls of the dielectric layers 106). In particular, the tunnel layer extends along the sidewalls of the dielectric layers 106 and the sidewalls of the conductive features 114A (e.g., the sidewalls of the seed layers 114A S and the main layers 114A M, which are exposed by the trenches 110A). The tunneling layer may optionally be anisotropically etched to remove portions of the tunneling layer at the bottoms of the trenches 110A, thereby exposing the substrate 102 and separating the tunneling stripes from horizontally adjacent TFTs along the direction D 2 (see FIGS. 2A and 2B ). Then, an insulating material is conformally deposited on the tunnel layer and in the remaining portions of the trenches 110A. A removal process is then applied to the various layers to remove excess materials over the top dielectric layers 106 / sacrificial layers 108. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The portions of the tunnel layer and the isolation material remaining in the trenches 110A form the tunnel strips 116A and the isolation regions 118A, respectively. The planarization process exposes the top dielectric layers 106 / sacrificial layers 108 such that top surfaces of the isolation regions 118A, tunneling strips 116A, and the top dielectric layers 106 / sacrificial layers 108 are coplanar after the planarization process (within process variations).In FIGS. 8A and 8B, the trenches 110B are patterned in the multilayer stack 104. In the illustrated embodiment, the trenches 110B extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the trenches 110B extend through some, but not all, layers of the multilayer stack 104. The trenches 110B may be patterned using acceptable photolithography and etching techniques, such as by an etching process selective to the multilayer stack 104 (e.g., the dielectric materials of the dielectric layers 106 and the sacrificial layers 108 selectively removed at a faster rate than the material of the substrate 102). The etching may be any acceptable etching process, and in some embodiments may be similar to the etching used to form the trenches 110A (discussed above for FIGS. 4A and 4B ).After patterning, respective portions of the multilayer stack 104 are disposed between respective pairs of the trenches 110A, 110B. Each portion of the multilayer stack 104 has a width W 3 in the second direction D 2( see FIGS. 2A and 2B ), which may be in the range of about 50 nm to about 500 nm. Further, each portion of the multilayer stack 104 is separated in the second direction D 2 by a separation distance S 2, which may be in the range of about 50 nm to about 200 nm. During the structuring of the trenches 110B, an offset may occur. When an offset occurs, the patterned portions of the multilayer stack 104 do not all have a same width W 3. When no offset occurs, the patterned portions of the multilayer stack 104 have a same width W 3.In FIGS. 9A and 9B, the trenches 110B are extended to form sidewall recesses 112B. Specifically, the remaining portions of the sacrificial layers 108 are removed to form the sidewall recesses 112B. The sidewall recesses 112B therefore expose the sidewalls of the conductive features 114A (e.g., the sidewalls of the seed layers 114As). The sidewall recesses 112B may be formed by an acceptable etching process, such as one that is selective to the material of the sacrificial layers 108 (e.g., selectively removing the material of the sacrificial layers 108 at a faster rate than the material or materials of the dielectric layers 106 and the substrate 102). The etching may be any acceptable etching process and, in some embodiments, may be similar to the etching used to form the sidewall recesses 112A (discussed above for FIGS. 5A and 5B ).After formation, the sidewall recesses 112B have a depth D 5 in the second direction D 2( see FIGS. 2A and 2B ) that extends beyond the sidewalls of the dielectric layers 106. A time-controlled etch may be used to stop the etching of the sidewall recesses 112B after the sidewall recesses 112B have reached a desired depth D 5. As mentioned above, an offset may occur in patterning the trenches 110B. When an offset occurs, the depth D 5 is different from the depth D 4( (discussed above for FIGS. 5A and 5B ), e.g., is greater or less than). When no offset occurs, the depth D 5 is similar to the depth D 4.In FIGS. 10A and 10B, conductive features 114B are formed in the sidewall recesses 112B, thereby completing a process for replacing second portions of the sacrificial layers 108. The conductive features 114B may be formed from materials selected from the same group of candidate materials for the conductive features 114A, and may be formed using methods selected from the same group of candidate methods for forming the materials of the conductive features 114A. The conductive features 114A and the conductive features 114B may be formed of the same material or may include different materials. In some embodiments, the conductive features 114B each include a seed layer, 114B S( or barrier layer) and a main layer 114B M. The seed layers 114B S and the main layers 114B M may have similar thicknesses as the seed layers 114A S and the main layers 114A M respectively. In some embodiments, seed layers 114A S and seed layers 114B S are formed from similar materials, in which case seed layers 114A S and seed layers 114B S may merge into one another during formation, such that there are no detectable interfaces therebetween. In another embodiment, the seed layers 114A S and the seed layers 114B S are formed from different materials, in which case the seed layers 114A S and the seed layers 114A S may not merge with each other during formation, such that detectable interfaces are present therebetween. As mentioned above, an offset may occur in patterning the trenches 110B. When an offset occurs, the main layers 114A M have different widths along the second direction D 2( see FIGS. 2A and 2B ) than the main layers 114B M. When no offset occurs, the main layers 114A M have the same width along the second direction D 2 as the main layers 114B M. Portions of each seed layer 114A S, 114 B S are laterally disposed between a main layer 114A M and a main layer 114B M.The conductive features 114A and the conductive features 114B are collectively referred to as word lines 114 of the memory array. Adjacent pairs of the conductive features 114A and the conductive features 114B are in physical contact with each other and are electrically coupled to each other. Thus, each pair of conductive features 114A, 114B acts as a single word line 114.In FIGS. 11A and 11B, tunneling stripes 116B and isolation regions 118B are formed in the trenches 110B. In particular, a tunnelling strip 116B and an isolation region 118B are formed in each trench 110B. In this processing step, no semiconductor stripes are formed. Rather, as will be discussed in more detail below, semiconductor strips are formed by openings in the isolation regions 118B in a subsequent processing step.The tunneling strips 116B may be formed of a material selected from the same group of candidate materials for the tunneling strips 116A, and may be formed using a method selected from the same group of candidate methods for forming the material of the tunneling strips 116A. The tunneling strips 116A and the tunneling strips 116B may be formed of the same material or may include different materials. The tunneling strips 116A and the tunneling strips 116B are collectively referred to as tunneling strips 116. A thickness of the tunneling strips 116 may be in the range of about 2 nm to about 20 nm.The isolation regions 118B may be formed of a material selected from the same group of candidate materials for the isolation regions 118A, and may be formed using a method selected from the same group of candidate materials for forming the material of the isolation regions 118A. The isolation regions 118A and the isolation regions 118B may be formed of the same material or may include different materials. The isolation regions 118A and the isolation regions 118B are collectively referred to as isolation regions 118. A thickness of the isolation regions 118 may be in the range of about 42 nm to about 192 nm.The tunneling stripes 116B and the isolation regions 118B may be formed by a combination of deposition, etching, and planarization. For example, the tunneling strips 116B and isolation regions 118B may be formed by similar steps (discussed above for FIGS. 7A and 7B ) to those used for forming the tunneling strips 116A and isolation regions 116B.In FIGS. 12A and 12B, conductive lines including bit lines 120B and source lines 120S) are formed to extend through the isolation regions. The bit lines 120B and the source lines 120S are conductive pillars and may also be referred to as bit line pillars and source line pillars. Each TFT will have a bit line 120B and a source line 120S. The bit lines 120B and the source lines 120S also function as source / drain regions of the TFTs. Thus, in a subsequent processing step, semiconductor stripes including channel regions of the TFTs are formed in contact with the bit lines 120B / source lines 120S, so that the bit lines 120B / source lines 120S are adjacent to the channel regions of the TFTs.As an example of the formation of the bit lines 120B / source lines 120S), openings are formed through the isolation regions 118. The openings may be formed by an etching process that is selective to the isolation regions 118 (e.g., selectively removes the material of the isolation regions 118 at a faster rate than the material of the tunneling strips 116). For example, the openings through the isolation regions 118 may be formed through the isolation regions 118 by dry etching using ammonia (NH 3) and hydrogen fluoride (HF) gas, which may be performed using an etch mask having a structure of the bit lines 120B / source lines 120S. Then, a cladding such as a diffusion barrier layer, an adhesive layer or the like and a main layer are formed in the openings. The liner may be formed of a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, which may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may include an adhesion layer and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The main layer may be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like, which may be deposited by an ALD, a CVD, a PVD, or the like. In some embodiments, bit lines 120B / source lines 120S include a liner formed of titanium nitride and a main layer formed of tungsten. Then, a removal process is applied to the various layers to remove excess material or materials of the bit lines 120B / source lines 120S over the isolation regions 118, the tunneling strips 116, and the top dielectric layers 106 / word lines 114. The removal process may be chemical mechanical polishing (CMP), etch back, combination thereof, or the like. The bit lines 120B / source lines 120S are formed by the remaining material or materials in the openings. The planarization process exposes the uppermost dielectric layers 106 / word lines 114 such that top surfaces of the bit lines 120B / source lines 120S, isolation regions 118, tunneling strips 116, and uppermost dielectric layers 106 / word lines 114 are coplanar (within process variations) after the planarization process.As will be discussed in greater detail below, FIGS. 13A-19B illustrate a process in which portions of the isolation regions 118 are replaced with the remaining features of the TFTs. In particular, portions of the isolation regions 118 are replaced with isolation regions 136 (see FIGS. 16A and 16B ), semiconductor strips 138 (see FIGS. 17A and 17B ), and back gates 144 (see FIGS. 19A and 149B ) for the TFTs. The semiconductor strips 136 have channel regions of the TFTs. The isolation regions 136 surround the back gates 144 and separate the back gates 144 from the semiconductor strips 138, e.g., the channel regions. The remaining portions of the isolation regions 118 separate the features from horizontally adjacent TFTs along the direction D 1( see FIGS. 2A and 2B ). As mentioned above, the back gates 144 are used to provide a bias voltage during write operations (e.g., erase or program operations) of the TFTs. The back gates 144 may also help control the surface potential of the semiconductor strips 138 (particularly the portions of the semiconductor strips 138 distal from the wordlines 114) during write operations.In FIGS. 13A and 13B, portions of the isolation regions 118 are eliminated to form openings 130. The openings 130 may be formed by an etching process that is selective with respect to the isolation regions 118 (e.g., selectively removing the material of the isolation regions 118 at a faster rate than the materials of the tunneling strips 116 and the bitlines 120B (source lines 120S). For example, the openings 130 may be formed through the isolation regions 118 by dry etching using ammonia (NH 3) and hydrogen fluoride (HF) gas, which may be performed using an etch mask having a structure of the openings 130.In FIGS. 14A and 14B, a semiconductor layer 132 is conformally deposited in the openings 130 and on the top dielectric layers 106 / word lines 114, the isolation regions 118, and the bit lines 120B / source lines 120S. The semiconductor layer 132 is then patterned to form semiconductor strips having channel regions of the TFTs. The semiconductor layer 132 is formed of an acceptable material for providing channel regions for the TFTs, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polysilicon, amorphous silicon, or the like. The material of the semiconductor layer 132 may be formed by an acceptable deposition process such as ALD, CVD, PVD, or the like. In some embodiments, the semiconductor layer 132 is IGZTO deposited by an ALD. The semiconductor layer 132 may have a thickness in the range of about 9 nm to about 11 nm.In FIGS. 15A and 15B, a dielectric layer 134 is conformally deposited on the semiconductor layer 132 and in the openings 130. The dielectric layer 134 may be formed from materials selected from the same group of candidate materials for the dielectric layer 106 and may be formed using methods selected from the same group of candidate methods for the formation of the materials of the dielectric layer 106. The dielectric layer 106 and the dielectric layer 134 may be formed of the same material or may include different materials. In some embodiments, the dielectric layer 134 is an oxide, such as silicon oxide, deposited by an ALD. In another embodiment, the dielectric layer 134 may be formed of a ferroelectric material having a high k value, such as a material selected from the same group of candidate materials for the tunneling stripes 116. The dielectric layer 134 may have a thickness in the range of about 1 nm to about 100 nm.In FIGS. 16A and 16B, the dielectric layer 134 is patterned to form isolation regions 136 in the openings 130. A suitable etching process is performed on the dielectric layer using the semiconductor layer 132 as an etch stop layer. The etching process is selective to the dielectric layer 134 (e.g., selectively removes the material of the dielectric layer 134 at a faster rate than the material of the semiconductor layer 132). The etching may be anisotropic. The etching process removes the horizontal regions of the dielectric layer 134, thereby extending the openings through the dielectric layer 134 and exposing the semiconductor layer 132. After the etching process, the isolation regions 136 include the remaining vertical portions of the dielectric layer 134.In FIGS. 17A and 17B, the semiconductor layer 132 is patterned to form semiconductor stripes 138 in the openings 130. A suitable etching process is carried out on the semiconductor layer 132 using the insulation regions 136 as an etching mask. The etching process is selective to the semiconductor layer 132 (e.g., selectively removes the material of the semiconductor layer 132 at a faster rate than the material or materials of the dielectric layer 134 and the tunneling strips 116). The etching may be anisotropic. The etching process removes the horizontal portions of the semiconductor layer 132 not masked by the isolation regions 136, thereby extending the openings 130 through the semiconductor layer 132 and exposing the tunneling strips 116.Optionally, the openings 130 may be further extended through the tunneling strips 116 and the substrate 102. As will be discussed in more detail below, in some embodiments, the memory array 52 is embedded in another semiconductor device. In particular, the memory arrangement 52 may be formed in the interconnect structure of the semiconductor device. In such embodiments, the openings 130 are elongated through the tunneling strips 116 and the substrate 102 to allow subsequently formed back gates to be coupled to metallization layers of the interconnect structure underlying the memory array 52. An appropriate etching process may be performed on the tunneling strips 116 and the substrate 102 using the isolation regions 136 and the semiconductor strips 138 as an etch mask. The etching process is selective with respect to the tunneling strips 116 and the substrate 102 (e.g., selectively removes the material or materials of the tunneling strips 116 and the substrate 102 at a faster rate than the material or materials of the isolation regions 136 and the semiconductor strips 138). The etching may be anisotropic. In some embodiments, the etching process includes multiple etching operations. For example, a first etch may be performed to extend the openings 130 through the tunneling strips 116 and a second etch may be performed to extend the openings 130 through the substrate 102.In FIGS. 18A and 18B, a conductive layer 142 is formed in the openings 130 and on the top dielectric layers 106 / word lines 114, the isolation regions 118, the bit lines 120B / source lines 120S, the isolation regions 136, and the semiconductor strips 138. The conductive layer 142 may be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like, which may be deposited by an ALD, a CVD, a PVD, or the like. The conductive layer 142 may be conformally deposited. In some embodiments, the conductive layer 142 is a layer of tungsten.In FIGS. 19A and 19B, a removal process is performed on the conductive layer 142 to form back gates 144. The removal process removes excess conductive layer 142 material over the top dielectric layers 106 / word lines 114, isolation regions 118, bit lines 120B / source lines 120S, isolation regions 136, and semiconductor strips 138. The removal process may also remove excess materials of the semiconductor layer 132 (see FIGS. 14A and 14B ) and / or the dielectric layer 134 (see FIGS. 15A and 15B ) that may remain over the uppermost dielectric layers 106 / word lines 114, the isolation regions 118, and the bit lines 120B / source lines 120S. The removal process may be a planarization process such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining material of the conductive layer 142 in the openings 130 forms the back gates 144. The back gates 144 are conductive pillars disposed between and parallel to the bit lines 120B and the source lines 120S. The planarization process exposes the top dielectric layers 106 / word lines 114 such that the top surfaces of the top dielectric layers 106 / word lines 114, isolation regions 118, bit lines 120B / source lines 120S, isolation regions 136, semiconductor strips 138, and back gates 144 are coplanar (within process variations) after the planarization process.In FIGS. 20A, 20B, and 20C, an interconnect structure is formed over the intermediate structure. The interconnect structure 160 may include, for example, metallization structures 162 in a dielectric material 164 (not shown in FIG. 20A, see FIGS. 20B and 20C ). The dielectric material 164 may include one or more dielectric layers, such as one or more layers of a low-k dielectric material (an LK dielectric material) or an extra-low-k dielectric material (an ELK dielectric material). Metallization structures 162 may be metal interconnects (e.g., conductive traces 162L, conductive vias 162V, etc.) formed in one or more dielectric layers. The interconnect structure 160 may be formed by a damascene process such as a single damascene process, a dual damascene process, or the like. The metallization patterns 162 of the interconnect structure 160 are electrically connected to the bit lines 120B / source lines 120S and connect the TFTs 68 together to form functional memories.FIGS. 21A through 21D are top views of a memory array 52, in accordance with some embodiments. Some features of an interconnect structure are illustrated. FIG. 21A illustrates conductive vias in a first level of an interconnect structure (e.g., first level conductive vias 162V 1 in FIGS. 20B and 20C ). FIG. 21B shows conductive traces in a first level of an interconnect structure (e.g., conductive traces 162L 1 of the first level in FIGS. 20B and 20C ). FIG. 21C shows conductive vias in a second level of an interconnect structure (e.g., second level conductive vias 162V 2 in FIGS. 20B and 20C ). FIG. 21D shows conductive traces in a second level of an interconnect structure (e.g., conductive traces 162L 2 of the second level in FIGS. 20B and 20C ).Referring to FIG. 21A, conductive vias 162V are located in 1 over and are connected to bit lines 120B / source lines 120S. The bit lines 120B and the source lines 120S are formed in an alternating pattern along rows and columns of the memory array 52 in plan view. Forming the bit lines 120B and the source lines 120S in an alternating pattern helps to short adjacent bit lines 120B / source lines 120S when a word line 114 (see FIGS. 20B and 20C ) is activated. In this embodiment, adjacent bit lines 120B and adjacent source lines 120S are laterally aligned with each other along the first direction D 1( see FIGS. 2A and 2B ). In some embodiments, the center of each conductive via 162V is aligned in 1 laterally with the center of the respective underlying bit line 120B / source line 120S.Referring to FIG. 21B, conductive traces 162L are 1 over and connected to conductive vias 162V 1. The conductive traces 162L 1 extend in the first direction D 1( see FIGS. 2A and 2B ), laterally offsetting the interconnect with the underlying bitlines 120B / source lines 120S. In other words, the conductive traces 162L 1 connected to the bit lines 120B (see FIG. 21A ) are laterally offset from the conductive traces 162L 1 connected to the source lines 120S (see FIG. 12A ) along the second direction D 2( see FIGS. 2A and 2B ).Referring to FIG. 21C, conductive vias 162V are 2 over and are connected to conductive traces 162L 1. Thus, because the conductive traces 162L 1 laterally offset the interconnect to the underlying bit lines / source lines, the center of each conductive via 162V 2 is laterally offset from the center of the respective underlying bit line / source line and from the center of the respective underlying conductive via 162V 1. The conductive vias 162V 2 may be larger than (e.g., may have a width larger than) the conductive vias 162V 1.Referring to FIG. 21D, conductive traces 162L are 2 over and connected to conductive vias 162V 2. Traces 162L 2 include bit line interconnects 162B (connected to bit lines 120B, see FIG. 21A ) and source line interconnects 162B (connected to source lines 120S, see FIG. 21A ). Thus, because the conductive traces 162L 2( see FIG. 12C ) laterally offset the connection to the underlying bit lines / source lines, the bit line interconnects 162B and the source line interconnects 162S may be straight conductive segments extending in the second direction D 2( see FIGS. 2A and 2B ).FIGS. 22A and 22B are top views of a memory array 52, in accordance with some embodiments. Some features of an interconnect structure are illustrated. FIG. 22A shows conductive vias in a first level of an interconnect structure (e.g., first level conductive vias 162V 1 in FIGS. 20B and 20C ). FIG. 22B shows conductive traces in a first level of an interconnect structure (e.g., conductive traces 162L 2 of the first level in FIGS. 20B and 20C ).Referring to FIG. 22A, the bit lines 120B and the source lines 120S are formed in a staggered arrangement in this embodiment. In other words, the bit lines 120S and the source lines 120S are still formed in an alternating pattern, but adjacent bit lines 120B and adjacent source lines 120S are also laterally offset from each other along the first direction D 1( see FIGS. 2A and 2B ). Conductive vias 162V 1 are located over and are connected to bit lines 120B / source lines 120S.Referring to FIG. 22B, conductive traces 162L are 1 over and connected to conductive vias 162V 1. Traces 162L 1 include bit line interconnects 162B (connected to bit lines 120B, see FIG. 22A ) and source line interconnects 162S (connected to source lines 120S, see FIG. 22A ). Since the bit lines 120B and the source lines 120S are formed in a staggered arrangement, lateral interconnects may be omitted in the interconnect structure and the bit line interconnects 162B and the source line interconnects 162S may thus be formed at a lowest level of the interconnect structure over the bit lines 120B / source lines 120S.In the embodiments described above for FIGS. 3A through 20C, the memory array 52 is formed over a substrate 102, such as a dielectric substrate. In some embodiments, memory array 52 is formed as part of a stand-alone device (e.g., a memory die) that is unified with other devices (e.g., a logic die) by device packaging. In some embodiments, the memory array 52 is embedded in another device such as a logic die. In such embodiments, the substrate 102 may be omitted or may be an underlying layer such as an underlying dielectric layer, an underlying semiconductor substrate, or the like.FIGS. 23A, 23B, and 24 are cross-sectional views of a semiconductor device 200 in accordance with some embodiments. Figures 23A and 23B are shown along a similar cross-section to Figure 20B. FIG. 24 is shown along a similar cross-section to FIG. 20C. Figures 23, 24A and 24B are simplified views with some features omitted for clarity of illustration. The semiconductor device 200 includes a logic region 200L and a memory region 200M. In the storage area 200M, storage devices (e.g., flash memories) are formed, and in the logic area 200L, logic devices (e.g., logic circuits) are formed. For example, a memory array 52 (see FIG. 1 ) may be formed in the memory region 200M, and the row decoder 54 and the column decoder 56 (see FIG. 1 ) may be formed in the logic region 200L. The memory area 200M may be disposed at an edge of the logic area 200L, or the logic area 200L may surround the memory area 200M.The logic region 200L and the memory region 200M are formed over a same semiconductor substrate 202. The semiconductor substrate 202 may be doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 22 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.Devices 204 are formed on the active surface of the semiconductor substrate 202. The devices 204 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors, or the like, formed by any suitable formation method. The devices 204 are connected to each other to form the memory devices and the logic devices of the semiconductor device 200.On the semiconductor substrate 22, one or more inter-layer dielectric layers (inter-layer dielectric layers) are formed. ILD layers) 206, and electrically conductive features such as contact plugs 208 are formed electrically connected to the devices 204. The ILD layer 206 or layers 206 may be formed of any suitable dielectric material, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like; a nitride such as silicon nitride; or the like. The ILD layer or layers may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. The electrically conductive features in the ILD layer or layers may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), the like, or combinations thereof.An interconnect structure 210 is formed over the semiconductor substrate 202. The interconnect structure 210 interconnects the devices 204 to form integrated circuits in each of the logic region 200L and the memory region 200M. The interconnect structure 210 includes a plurality of metallization layers M 1 to M 5. Although five metallization layers are illustrated, it should be understood that more or fewer metallization layers may be included. Each of the metallization layers M 1 to M5 includes metallization structures in dielectric layers. The metallization structures are coupled to the devices 204 of the semiconductor substrate 202 and include metal lines L 1 to L 5 and metal vias V 1 to V 5, respectively, formed in one or more inter-metal dielectric layers (IMD layers). The interconnect structure 210 may be formed by a damascene process such as a single damascene process, a dual damascene process, or the like. In some embodiments, the contact plugs 208 also form a portion of the metallization structures, such as a portion of the lowermost layer of metal vias V 1.In this embodiment, the memory array 52 is formed in the interconnect structure 210. The memory array 52 may be formed in any of the metallization layers M 1 to M 5, illustrated as being formed in an intermediate metallization layer M 4, although it could also be formed in lower metallization layers M 1 to M 3 or in an upper metallization layer M 5. The memory array 52 is electrically connected to the devices 204. For example, a metallization layer overlying the memory array (e.g., metallization layer M 5) may include interconnects to source lines 120S and bit lines 120B (see FIG. 24 ) of memory array 52. Similarly, a metallization layer underlying the memory array 52 (e.g., metallization layer M 3) may include interconnects to the back gates 144 (see FIGS. 23A and 23B ) of the memory array 52.In some embodiments, the interconnect structure 210 may be formed by first forming the layers underlying the memory array 52, e.g., metallization layers M 1 to M 3. Then, the memory arrangement 52 may be formed on the metallization layer M 3, wherein the substrate 102 is an etch stop layer on the IMD of the metallization layer M 3. After the formation of the memory array 52, the rest of the metallization layer M 4 may be formed, such as by depositing and planarizing the IMD for the metallization layer M 4 and then forming metal lines M 4 and metal vias M 4. Then, the layers overlying the memory array 52, such as metallization layer M 5, may be formed.The back gates 144 are connected to underlying conductive traces in a similar manner as discussed above for FIGS. 17A and 17B by extending the openings for the back gates 144 through the tunneling strips 116 and the substrate 102. In the embodiment of FIG. 23A, multiple back gates 144 are connected to a single underlying conductive trace (e.g., a back gate interconnect 212), whereby multiple back gates 144 may be connected to and controlled by a single device 204, e.g., a single transistor. In the embodiment of FIG. 23B, each backgate 144 is connected to a different underlying conductive trace (e.g., backgate interconnects 212), whereby each backgate 144 may be connected to and controlled by its own device 204, e.g., its own transistor. In other words, each back gate 144 may be the single back gate 144 connected to an underlying back gate interconnect 212, or one of a plurality of back gates 144 connected to an underlying back gate interconnect 212.The embodiments may achieve advantages. The back gates 144 may help control the surface potential of the semiconductor strips 138 (particularly the portions of the semiconductor strips 138 distal from the wordlines 114) during write operations. For example, the work function of the material (e.g., tungsten) of the back gates 144 may help reduce the surface potential of the semiconductor strips 138. This allows the window for write operations to be expanded. Additionally, during write operations, a bias voltage may be applied to a back gate 144, thereby increasing the write voltage applied across a corresponding tunneling strip 116 during write operation. This can improve the performance of the memory array 52.It is the object of the invention to further develop a method for producing a storage arrangement or a corresponding device in such a way that it has a better performance. The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.

Claims

A method comprising: forming a word line (62, 114) between a pair of first dielectric layers (72, 106); depositing a data storage layer (116A) on sidewalls of the first dielectric layers (72, 106) and a sidewall of the word line (62, 114); forming a first isolation region (118A) on the data storage layer (116A); patterning a first opening (130) in the first isolation region (118A); and forming a channel layer (138) and a back gate (144) in the first opening (130), wherein the back gate (144) is surrounded by the channel layer (138).The method of claim 1, wherein forming the channel layer (138) and the back gate (144) comprises forming the channel layer (138) in a first portion of the first opening (130); and forming the back gate (144) in a second portion of the first opening (130) after forming the channel layer (138).The method of claim 2, wherein forming the channel layer (138) comprises depositing a semiconductor layer (132) in the first opening (130), depositing a second dielectric layer (134) over the semiconductor layer (132), patterning the second dielectric layer (134) using a first etching process to form a second isolation region (136), the first etching process using the semiconductor layer (132) as an etch stop layer, and patterning the semiconductor layer (132) using a second etching process to form the channel layer (138), the second etching process using the second isolation region (136) as an etch mask.The method of claim 3, further comprising extending the first opening (130) through the data storage layer (116A) after patterning the semiconductor layer (132).The method of claim 2, wherein forming the back gate (144) comprises depositing a conductive layer (142) over the channel layer (138) and in the first opening (130) and removing portions of the conductive layer (142) over the channel layer (138), the back gate (144) having portions of the conductive layer (142) remaining in the first opening (130).The method of claim 5, wherein the conductive layer (142) is formed of tungsten.The method of claim 1, wherein forming the wordline (62, 114) comprises etching a first trench (110A) in a multilayer stack (104), the multilayer stack (104) comprising the first dielectric layers (72, 106) and a sacrificial layer (108) between the first dielectric layers (72, 106), replacing a first portion of the sacrificial layer (108) exposed by the first trench (110A) with a first conductive feature (114A), etching a second trench (110B) in the multilayer stack (104), and replacing a second portion of the sacrificial layer (108) exposed by the second trench (110B) with a second conductive feature (114B), the wordline (62, 114) comprising the first conductive feature (114A) and the second conductive feature (114B), comprising.The method of claim 7, wherein depositing the data storage layer (116A) comprises depositing the data storage layer (116A) in the first trench (1104) prior to etching the second trench (110B) in the multilayer stack (104).A device, comprising: a source line (120S) extending in a first direction; a bit line (120B) extending in the first direction; a back gate (144) between the source line (120S) and the bit line (120B), the back gate (144) extending in the first direction; a channel layer (138) surrounding the back gate (144); a word line (114) extending in a second direction, the second direction being orthogonal to the first direction; and a data storage layer (116A) extending along the word line (114), the data storage layer (116A) being located between the word line (114) and the channel layer (138), the data storage layer (116A) being located between the word line (114) and the bit line (120B), the data storage layer (116A) being located between the word line (114) and the source line (120S).The device of claim 9, further comprising an isolation region (136) surrounding the back gate (144), the isolation region (136) separating the back gate (144) from the channel layer (138).The device of claim 9, wherein the data storage layer (116A) comprises a ferroelectric material, and wherein each of the back gate (144), the bit line (120B), the source line (120S), and the word line (114) comprises a metal.The device of claim 9, wherein the back gate (144) extends through the channel layer (138).The apparatus of claim 9, further comprising: a source line interconnect (162S) located over and connected to the source line (120B); a bit line interconnect (162B) located over and connected to the bit line (120B); and a back gate interconnect (212) located under and connected to the back gate (144).The apparatus of claim 13, wherein the back gate (144) is the only back gate (144) connected to the back gate interconnect (212).The apparatus of claim 13, wherein the back gate (144) is one of a plurality of back gates connected to the back gate interconnect (212).A device, comprising: a back gate (144) extending in a first direction; an isolation region (136) surrounding the back gate (144); a channel layer (138) surrounding the isolation region (136); a data storage layer (116A) in contact with the channel layer (138); and a word line (114) extending in a second direction, the second direction being orthogonal to the first direction, the word line (114) comprising a first main layer (114A M), a second main layer (114B M) and a seed layer (114A S) the seed layer (114A S) being laterally disposed between the first main layer (114A M) and the second main layer (114B M) the first main layer (114A M) being in contact with the data storage layer (116A).The device of claim 16, further comprising: a source line (120S) extending in the first direction, the source line (120S) being in contact with the data storage layer (116A); and a bit line (120B) extending in the first direction, the bit line (120B) being in contact with the data storage layer (116A), each of the back gate (144), the isolation region (136), and the channel layer (138) being disposed between the bit line (120B) and the source line (120S).The apparatus of claim 17, further comprising: a source line interconnect (162S) located over and connected to the source line (120S); a bit line interconnect (162B) located over and connected to the bit line (120B); and a back gate interconnect (212) located under and connected to the back gate (144).The device of claim 16, wherein the first main layer (114A M) and the second main layer (114B M) have different widths.The device of claim 16, wherein the first main layer (114A M) and the second main layer (114B M) have the same width.

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