Planar transistor device comprising at least one layer of two-dimensional (2D) material

Abstract

A planar transistor device (100) having a gate (101) with a gate length (GL) extending in a gate longitudinal direction and a gate width (GW) extending in a gate width direction, the transistor device (100) comprising: a gate structure (106) arranged over a semiconductor substrate (103), the semiconductor substrate (103) having a substantially planar top surface; a channel region (115); a source region (111); a drain region (113); and at least one layer of a 2D material arranged in at least one of the source region (111), drain region (113), or channel region (115), the at least one layer of 2D material having a substantially planar top surface (104U).a substantially planar bottom surface (104R) and a substantially uniform vertical thickness over an entire length of the at least one layer of 2D material in the gate longitudinal direction and over an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar top surface (104U) and the substantially planar bottom surface (104R) of the at least one layer of 2D material are arranged approximately parallel to a substantially planar surface of the semiconductor substrate (103), wherein the at least one layer of 2D material extends over the entirety of the channel region (115), wherein the source region (111) is substantially free of the at least one layer of 2D material and the drain region (113) is substantially free of the at least one layer of 2D material,and wherein the planar transistor device (100) further comprises: a first region of epi-semiconductor material (120) arranged in the source region (111), and a second region of epi-semiconductor material (120) arranged in the drain region (113), wherein the first region of epi-semiconductor material (120) conductively contacts a first edge of the at least one layer of 2D material and the second region of epi-semiconductor material (120) conductively contacts a second edge of the at least one layer of 2D material.

Claims

[1] A planar transistor device (100) comprising a gate (101) having a gate length (GL) extending in a gate longitudinal direction and a gate width (GW) extending in a gate width direction, the transistor device (100) comprising: a gate structure (106) disposed over a semiconductor substrate (103), the semiconductor substrate (103) having a substantially planar top surface; a channel area (115); a source area (111); a drain area (113); and at least one layer of a 2D material arranged in at least one of the source region (111), drain region (113) or channel region (115), wherein the at least one layer of 2D material has a substantially planar top surface (104U), a substantially planar bottom surface (104R) and a substantially uniform vertical thickness over an entire length of the at least one layer of 2D material in the gate longitudinal direction and over an entire width of the at least one layer of 2D material in the gate width direction, wherein the substantially planar top surface (104U) and the substantially planar bottom surface (104R) of the at least one layer of 2D material are arranged approximately parallel to a substantially planar surface of the semiconductor substrate (103), wherein the at least one layer of 2D material extends over the entirety of the channel region (115), wherein the source region (111) is substantially free of the at least one layer of 2D material and the drain region (113) is substantially free of the at least one layer of 2D material, and wherein the planar transistor device (100) further comprises: a first region of epi-semiconductor material (120) arranged in the source region (111), and a second region of epi-semiconductor material (120) arranged in the drain region (113), wherein the first region of epi-semiconductor material (120) conductively contacts a first edge of the at least one layer of 2D material and the second region of epi-semiconductor material (120) conductively contacts a second edge of the at least one layer of 2D material. [2] The planar transistor device (100) of claim 1, wherein the at least one layer of 2D material comprises a plurality of layers of 2D material (104) arranged in a vertically stacked arrangement. [3] The planar transistor device (100) of claim 2, wherein the plurality of layers of 2D material (104) comprises four individual layers of 2D material (104A-104D). [4] The planar transistor device (100) of claim 2, wherein each of the plurality of layers of 2D material (104A-104D) is formed from a same 2D material. [5] The planar transistor device (100) of claim 2, wherein each of the plurality of layers of 2D material (104) has a vertical thickness that is substantially the same. [6] The planar transistor device (100) of claim 1, wherein the at least one layer of 2D material comprises one of silicon, silicon germanium, a metal chalcogenide-based material, a transition metal dichalcogenide, graphene, MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, HfS2, HfSe2, ZrS2, ZrSe2, NbSe2, or ReSe2, and wherein the semiconductor substrate (103) comprises one of a semiconductor-on-insulator substrate or a semiconductor bulk substrate. [7] The planar transistor device (100) of claim 1, wherein the at least one layer of 2D material extends over an entire portion of the source region (111), an entire portion of the channel region (115), and an entire drain region (113). [8] The planar transistor device (100) of claim 7, wherein the at least one layer of 2D material comprises a plurality of layers of 2D material (104) arranged in a vertically stacked arrangement, and wherein the device further comprises a first conductive source / drain contact structure (112) conductively coupled to a topmost layer of the plurality of layers of 2D material (104) in the source region (111) and a second conductive source / drain contact structure (112) conductively coupled to a topmost layer of the plurality of layers of 2D material (104) in the drain region (113). [9] The planar transistor device (100) of claim 1, wherein the at least one layer of 2D material comprises a plurality of layers of 2D material (104) arranged in a vertically stacked arrangement, and wherein the first and second regions of epi-semiconductor material (120) are arranged on and in contact with the substantially planar surface of the semiconductor substrate (103). [10] The planar transistor device (100) of claim 1, further comprising a first source / drain contact structure (112) conductively coupled to the first region of epi semiconductor material (120) and a second source / drain contact structure (112) conductively coupled to the second region of epi semiconductor material (120). [11] The planar transistor device (100) of claim 1, wherein the gate structure (106) is disposed on a substantially planar top surface of the semiconductor substrate (103), and wherein the at least one layer of 2D material is disposed along the entirety of the source region (111) and along the entirety of the drain region (113), wherein a portion of the semiconductor substrate (103) disposed below the gate structure (106) comprises the channel region (115), and wherein the channel region (115) is substantially free of the at least one layer of 2D material. [12] The planar transistor device (100) of claim 11, wherein the at least one layer of 2D material comprises a plurality of layers of 2D material (104) arranged in a vertically stacked arrangement, and wherein the device further comprises a first conductive source / drain contact structure (112) conductively coupled to a topmost layer of the plurality of layers of 2D material (104) in the source region (111) and a second conductive source / drain contact structure (112) conductively coupled to a topmost layer of the plurality of layers of 2D material (104) in the drain region (113). [13] The planar transistor device (100) of claim 12, wherein at least one sidewall spacer (108) is disposed between the gate structure (106) and the at least one layer of 2D material in the source region (111) and the at least one layer of 2D material in the drain region (113). [14] The planar transistor device (100) of claim 12, further comprising a gate cap (110) disposed over the gate structure (106), wherein a topmost layer of the plurality of layers of 2D material (104) in the source region (111) and a topmost layer of the plurality of layers of 2D material (104) in the drain region (113) are substantially coplanar with a top surface (110S) of the gate cap (110). [15] The planar transistor device (100) of claim 12, wherein a topmost layer of the plurality of layers of 2D material (104) in the source region (111) and a topmost layer of the plurality of layers of 2D material (104) in the drain region (113) have a top surface located at a level above a level of a top surface of the gate structure (106). [16] The planar transistor device (100) of claim 2, wherein each of the plurality of layers of 2D material (104) has a periodic crystallographic pattern, the periodic crystallographic pattern of one of the plurality of layers of 2D material (104) being rotated relative to the periodic crystallographic pattern of another of the plurality of layers of 2D material (104). [17] A planar transistor device (100) comprising a gate (101) having a gate length (GL) extending in a gate longitudinal direction and a gate width (GW) extending in a gate width direction, the transistor device comprising: a gate structure (106) disposed over a semiconductor substrate (103), the semiconductor substrate (103) comprising a substantially planar top surface; a sidewall spacer (108) disposed adjacent to the gate structure (106); a channel area (115); a source area (111); a drain area (113); at least one layer of a 2D material disposed beneath the gate structure (106) and the sidewall spacer (108), wherein the source region (111) is substantially free of the at least one layer of 2D material and wherein the drain region (113) is substantially free of the at least one layer of 2D material, wherein the at least one layer of 2D material has a substantially planar top surface (104U), a substantially planar bottom surface (104R), and a substantially uniform vertical thickness over an entire length of the at least one layer of 2D material in the gate longitudinal direction and over an entire width of the at least one layer of 2D material in the gate width direction,wherein the substantially planar top surface (104U) and the substantially planar bottom surface (104R) of the at least one layer of 2D material are arranged approximately parallel to the substantially planar top surface of the semiconductor substrate (103); and, first and second regions of epi-semiconductor material (120) arranged in the source region (111) and the drain region (113), respectively, wherein the first region of epi-semiconductor material (120) conductively contacts a first edge of the at least one layer of 2D material, the second region of epi-semiconductor material (120) conductively contacts a second edge of the at least one layer of 2D material, and wherein the first and second regions of epi-semiconductor material (120) are arranged on and in contact with the substantially planar top surface of the semiconductor substrate (103).

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