Magnetic storage devices with a magnetic tunnel junction having a synthetic free layer for SOT-MRAMs and methods for manufacturing the same

Abstract

Magnetic storage device, comprising: a spin Hall electrode, SHE (10), wherein the SHE comprises a spin Hall metal; a magnetic tunnel junction stack, MTJ stack (100), disposed over the SHE (10), the MTJ having a synthetic antiferromagnetic free layer (30) forming an interface with the SHE (10), the synthetic antiferromagnetic free layer (30) comprising a first magnetic layer (32), a second magnetic layer (36) and a spacer layer (34) disposed between the first magnetic layer (32) and the second magnetic layer (36); a first conductive line (130A) connected to a first end of the SHE (10); and a second conductive line (130A) connected to a second end of the SHE (10); wherein the spacer layer (34) is configured to prevent a crystal structure of the first magnetic layer (32) from spreading into the second magnetic layer (36), and wherein the crystal structure of the first magnetic layer (32) is different from a crystal structure of the second magnetic layer (36).

Description

BACKGROUNDMagnetic random access memory (MRAM) provides comparable performance to static random access memory (SRAM), and at lower power consumption, comparable density to dynamic random access memory (DRAM). Compared to non-volatile memory (NVM), MRAM provides much faster access times and minimally degrades over time, while flash memory can be overwritten a limited number of times. One type of MRAM is spin transfer torque (MRAM). In an STT MRAM, a magnetic tunneling junction (MTJ) is used, which is written at least partially by a current driven by the MTJ. Another type of MRAM is a spin orbit torque (MRAM) which generally requires a lower switching current than an STT MRAM.The document DE 10 2013 109 012 A1 describes a magnetic memory which has magnetic contacts and an active spin-orbit coupling (SO) layer. Each of the magnetic contacts has a data storage layer that is magnetic. The SO active layer is adjacent to the data storage layer of the magnetic contact. The SO active layer is configured to apply an SO torque to the data storage layer due to a current passing through the SO active layer. The data storage layer is configured to be switchable using the SO torque. The publication US 2014 / 0 252 439 A1 describes a magnetoresistive memory, wherein bottom electrodes are applied to a SHE metal layer in regions outside the MTJ stack. The bottom electrodes contact the SHE metal layer to provide a bi-directional spin Hall effect recording current and switch the magnetization of a recording layer accordingly.US 2016 / 0 300 999 A1 describes an MRAM memory cell having three terminals, independent read and write paths, a composite data storage layer and a bias magnetic field for the data storage layer.The document US 2020 / 0 136 023 A1 likewise relates to a magnetic storage device.The object is to improve corresponding storage devices.The object is achieved by the magnetic storage devices according to patent claims 1 and 10 and the method according to patent claim 16.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1-3 are schematic views of a SOT MRAM cell, in accordance with some embodiments. FIGS. 4A, 4B, and 4C are diagrams of MTJ film stacks according to various embodiments. FIG. 5 is a cross-sectional view of a SOT MRAM device, in accordance with some embodiments. FIGS. 6 through 21 are intermediate steps used in forming a SOT MRAM device, in accordance with some embodiments. FIG. 22 is a cross-sectional view of a SOT MRAM device, in accordance with some embodiments. FIG. 23 is a perspective view of a SOT MRAM device, in accordance with some embodiments. FIG. 24 is a circuit diagram of a SOT MRAM device, in accordance with some embodiments. FIG. 25 illustrates operations of a SOT MRAM cell, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity of illustration and does not alone dictate a relationship between the various embodiments and / or configurations discussed.Further, for convenience of description herein, terms of spatial relationship such as "below", "below", "lower", "above", "upper", and the like may be used to describe the relationship of one element or feature to (one) other element(s) or feature(s) as illustrated in the figures. The terms spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices may be otherwise oriented (rotated 90 degrees or having different orientations) and the spatial relationship descriptors used herein may likewise be interpreted accordingly. In addition, the term "made of" may mean either "comprising" or "consisting of.". Further, in the following manufacturing method, there may be one or more additional operations in / between the described operations, and the order of the operations may be changed. In the present disclosure, an expression "one of A, B, and C" means "A, B, and / or C" (A, B, C, A, and B, A and C, B, and C, or A, B, and C"), and does not mean an element of A, an element of B, and an element of C, unless otherwise described. Materials, configurations, dimensions, methods, and / or operations described with respect to one embodiment may be employed in the other embodiments, and detailed explanation thereof may be omitted.In some embodiments, instead of using a free layer as a single layer, a synthetic free layer is used in an MTJ film stack. The synthetic free layer has a pair of magnetic layers separated by a spacer layer. When current flows through the spin Hall electrode to induce a SOT on the free layer, the resulting magnetic field is tilted away from the x-axis. This tilting can be used to switch the magnetization of the free layer without requiring an external field and without having to manually tilt the spin Hall electrode or the MTJ ellipse structure when the orientation of the spin Hall electrode is fixed.Spin transfer torque MRAM (STT-MRAM) is one of the next generation memory technologies for CMOS ICs. However, for fast access applications such as a low level cache, fast speeds are required and the write speed is much slower than the read speed. The cache application for a central processing unit (CPU) and / or a microcontoller (MCU) also requires low power consumption. However, an STT RAM requires a significant amount of current to change the magnetization state during the write operation. An STT-MRAM cell generally includes a magnetic tunnel junction (MTJ) film stack that includes a free magnetic layer, a reference or pinned magnetic layer, and a tunnel barrier layer made of a non-ferromagnetic material such as MgO. The free layer is the magnetic layer which has two energy-equivalent magnetic states, the magnetization in the free layer running parallel or antiparallel to the magnetization of the reference layer. By applying a current perpendicular to the MTJ film stack, the magnetic orientation (magnetic moment) of the free magnetic layer can be changed, thereby writing data into the STT-MRAM cell.In contrast, in spin orbital transfer (or spin orbital torque) (SOT) magnetic switching, the potential is to provide write current and speed enhancement on the order of one-to-one fold. SOT has promising applications for high speed, low power cache memories.In a SOT MRAM, the magnetic moment is switched using the spin orbit interaction effect caused by a current flowing in the vicinity of the MTJ film stack. This current may flow in a spin hall electrode (SHE). Manipulating the free magnetic layer causes a change in resistance through the free magnetic layer, which can be used to determine a data value in the cell. The magnetic moment of the free magnetic layer may be switched by utilizing only the spin orbit interaction effect, or the magnetic moment of the free magnetic layer may be switched by utilizing a combination of effects.There are three general SOT MRAM types that vary based on the shape and orientation of the MTJ stack with respect to current flow through the spin Hall electrode. In order to switch the magnetic moment of the free layer using the SOT, a field is required and this field may be internally generated or may be externally generated. Externally generated SOT MRAM devices are undesirable because of their complexity, space requirements, and energy required to use an externally generated field. An x-type SOT MRAM has an MTJ film stack elongated in the X direction and a magnetic moment parallel to the current through the spin Hall electrode, and usually requires an externally generated magnetic field that is orthogonal to the plane of current flow in the spin Hall electrode. A y-type SOT MRAM has an MTJ film stack elongated in the Y-direction and a magnetic moment that is perpendicular to but in the same plane as the current through the spin Hall electrode. A z-type SOT MRAM has an MTJ film stack that is typically circular (although it may be elliptical) and has a magnetic moment that is orthogonal to the plane of current flow through the spin Hall electrode.Each of the different types of SOT MRAM devices have certain advantages and disadvantages. The x-type of SOT MRAM is desirable because it requires the lowest energy for operation and occupies the smallest space among the three, but usually requires an externally generated magnetic field to assist in switching the free layer. Various changes have been tried on the x-type design of the SOT MRAM in an attempt to eliminate the need for an externally generated auxiliary magnetic field. In other words, such changes are made in an attempt to provide an internally generated auxiliary field. In such a variation, the MTJ stack, which is normally oriented with its longest axis in a direction with the X axis and in a direction with the current through the spin Hall electrode, is instead tilted or rotated about the Z axis as the current through the spin Hall electrode continues to flow along the X axis, thereby generating a magnetic moment that has both X and Y components of significance. Any angle of rotation from 0° to 90° may be realized, and in some embodiments, the angle of rotation may be about 5° to 45°, although other angles may be used. These complex fields can be used to switch the free layer without requiring an external auxiliary field. However, since the MTJ stack is rotated, it occupies more space, and thus the storage density is reduced.As indicated above, the embodiments disclosed herein use a synthetic free layer comprising two magnetic layers separated by a spacer layer. This arrangement provides a magnetic moment offset from the X axis and containing both X and Y components of interest without requiring the MTJ stack to rotate about the Z axis, thereby providing a greater storage density than some devices. The resulting magnetic moment can be switched by spin orbit torque without requiring an external auxiliary magnetic field.Although the present disclosure generally relates to an x-type SOT MRAM, some of the aspects described herein may be transferable to the other types of SOT MRAM devices.FIG. 1 shows a schematic view of the SOT MRAM functional elements of a SOT MRAM cell 90 (see FIG. 3 ) in accordance with some embodiments of the present disclosure. These elements may include a bottom electrode 5, a spin hall electrode 10, an MTJ film stack 100, an optional cap layer 70 over the MTJ film stack 100, and a top electrode 75 over the cap layer 70. It is understood that these layers may comprise multiple sub-layers comprising different materials, which will be described in detail below. The spin Hall electrode 10 serves as a spin orbit interaction active layer to provide an induction influence on the MTJ film stack 100.Although the basic structure of the MTJ film stack 100 and the spin Hall electrode 10 is the same for the various embodiments described herein, various configurations may be employed that vary in the materials used in the various layers and in their corresponding crystal structures. A synthetic free layer 30 is arranged above the spin Hall electrode 10, a barrier layer 40 is arranged above the synthetic free layer 30, and a reference layer structure 50 is arranged above the barrier layer 40. An antiferromagnetic layer 60 is disposed over the reference layer structure 50. In some embodiments, a capping layer 70 may be disposed over the antiferromagnetic layer 60. The reference layer structure 50 may include a reference layer 52 and a pinned layer 56, wherein a spacer is arranged between the reference layer 52 and the pinned layer 56. In some embodiments, instead of a separate pinned layer 56, the antiferromagnetic layer 60 may be used as the pinned layer. The arrangement shown in FIG. 1 is considered a "top pinned" device because the pinned layer is positioned on top of the MTJ film stack 100.Referring to FIG. 1, the magnetic moment of the synthetic free layer 30 is switched by the spin orbit interaction effect. In some embodiments, the magnetic moment of the synthetic free layer 30 is switched only by the spin orbit interaction effect. In other embodiments, the magnetic moment of the synthetic free layer 30 is switched by a combination of effects. For example, the magnetic moment of the synthetic free layer 30 is switched by a spin transfer torque as a primary effect, which can be supported by the torque induced by the spin orbit interaction. In other embodiments, the primary switching mechanism is the torque induced by the spin orbit interaction. In such embodiments, another effect, e.g., but not limited to spin transfer torque, may assist in switching.The spin Hall electrode 10 may be formed over an optional bottom electrode 5. The lower electrode 5 may include one or more layers of Ta, TiN, TaN, Ru, Au, W, or Cu. The lower electrode 5 may be deposited by any suitable method, e.g. a damascene method in the case of a lower Cu electrode 5 or by depositing a metal plug in the case of a lower W electrode 5.As stated above, the spin Hall electrode 10 is a spin orbit active interface which has a strong spin orbit interaction and which can be used in switching the magnetic moment of the synthetic free layer 30. The spin Hall electrode 10 is used in generating a spin orbit magnetic field H y (see FIG. 2 ). Specifically, a in-plane current Jc is driven through the spin Hall electrode 10. Due to the spin Hall effect, the spin orbit magnetic field H y is generated perpendicularly (orthogonally) to the direction of the current Jc. This spin orbit magnetic field H y is equivalent to the spin orbit torque T for magnetization, where T=-γ[M×H y] in the synthetic free magnetic layer 30. This reflects the fact that the spin orbit interaction is the origin of the spin orbit torque and the spin orbit field. The spin orbit torque occurs for the current Jc driven in a plane in the spin Hall electrode 10 and a spin orbit interaction. In contrast, spin transfer torque is due to a perpendicular-to-plane current flow through the synthetic free layer 30, the barrier layer 40, and the reference layer structure 50, which injects spin-polarized charge carriers into the synthetic free layer 30. The spin orbit torque T can quickly deflect the magnetic moment of the synthetic free layer 30 from its equilibrium state. And due to the structure of the synthetic free layer, the equilibrium state is tilted away from the easy axis. Spin orbit torque T can flip the magnetization of synthetic free layer 30 much faster than a conventional STT torque of a similar maximum amplitude. In some embodiments, the switching may be completed using spin orbit torque. In other embodiments, another mechanism, e.g., spin transfer, may be used to complete the switching. The spin orbit field / spin orbit torque generated can thus be used in switching the magnetic moment of the synthetic free layer 30.For the spin Hall effect of the spin Hall electrode 10, a current Jc in the plane of the spin Hall electrode 10 (i.e., current in the plane, substantially in the X-Y plane in FIG. 1 ) is driven in a direction parallel to the longitudinal axis of the MTJ film stack 100. In other words, the current Jc is driven perpendicular to the stacking direction of the films including the spin Hall electrode 10 and the synthetic free layer 30 (i.e., perpendicular to the normal of the surface, the Z direction in FIG. 1 ). Charge carriers having spins of a certain orientation perpendicular to the direction of the current (y direction) accumulate on the surfaces of the spin Hall electrode 10. A majority of these spin-polarized carriers diffuse into the synthetic free layer 30. Since the torque for magnetization is equivalent to the effective magnetic field for magnetization, as stated above, the spin accumulation results in the field H y for the synthetic free layer 30. The spin orbit field for the spin Hall effect is the cross product of the spin orbit polarization and the magnetic moment of the synthetic free layer 30. The spin Hall effect can be used in switching the magnetic stacked layer shown in FIG. 1 when the polarization induced by the spin Hall effect is parallel to the easy axis of the synthetic free layer 30 (which is oblique to the magnetic equilibrium moment of the synthetic free layer 30). To obtain the spin orbit torque T, the current pulse is driven in-plane through the spin Hall electrode 10. The resulting spin orbit torque T counteracts a damping torque, which results in switching the magnetization of the synthetic free layer 30 in a manner analogous to the conventional STT switching.The synthetic free layer 30 is a data storage layer having a magnetic moment that is switchable. Within the MTJ film stack 100 of a SOT MRAM cell 90, the synthetic free layer 30 functions as a state-preserving layer and its magnetic state determines the state of the SOT MRAM cell 90. for example, the magnetic moment of the synthetic free layer 30 is controllable (e.g., by controlling a current flowing in the spin Hall electrode 10), and by controlling the magnetic moment of the synthetic free layer 30 in this way, the resistance of the SOT MRAM cell 90 can be brought into a high resistance state or a low resistance state. Whether the SOT MRAM cell 90 is in a high resistance state or a low resistance state depends on the relative orientations of the spin polarizations of the synthetic free layer 30 and the reference layer structure 50 (see below for more detail regarding the reference layer structure 50).The following descriptions of the synthetic free layer 30, the barrier layer 40, and the reference layer structure 50 apply generally to all embodiments described in more detail with respect to FIGS. 4A, 4B, and 4C. The descriptions of the various embodiments with respect to FIGS. 4A, 4B, and 4C further details that have been described with respect to FIG. 1.The synthetic free layer 30 may be formed of one or more ferromagnetic materials, e.g., cobalt-iron-boron (CoFeB), cobalt-palladium (CoPd), cobalt-iron (CoFe), cobalt-iron-boron-tungsten (CoFeW), iron-boron (FeB), Co, alloys thereof, the like, or combinations thereof, and one or more non-ferromagnetic materials, e.g., W, Ta, Mo, Cr, Ru, the like, or combinations thereof. The synthetic free layer 30 is configured to be antiferromagnetic by having at least two layers of ferromagnetic materials, e.g., FL1 32 and FL2 36, separated by a spacer layer 34 of a nonferromagnetic material. For example, the first magnetic layer FL 132 may be coupled to a second magnetic layer FL 2 36 by an RKKY coupling (Euserman-Kitzerland-Kasuya-Yosida coupling). When the spacer layer 34 has a thickness in a certain range, the coupling is antiferromagnetic. When such a synthetic free layer is operated with antiferromagnetic, it may be referred to as a synthetic antiferromagnetic free layer. For example, the spacer layer 34 may include W, Ta, Mo, Cr, or Ru.As the thickness of the spacer layer 34 increases, the magnetic coupling between FL1 32 and FL2 36 changes from parallel to anti-parallel and then back to parallel, etc. Thus, if the spacer layer 34 is too thin, the coupling becomes parallel (or ferromagnetic), but if the spacer layer 34 is thicker, then the magnetic coupling between FL1 32 and FL2 36 may be anti-parallel (or antiferromagnetic). As the thickness of the spacer layer 34 increases, the coupling strength (ferromagnetic or antiferromagnetic) between the first magnetic layer FL 1 32 and the second magnetic layer FL 2 36 decreases and become decoupled if the spacer is thicker than about between 2.5 nm and 3.0 nm. The effective thickness of the spacer layer 34 for antiferromagnetic coupling varies based on the materials of the FL 1 32, the spacer layer 34, and the FL 2 36. Various embodiments will be described below. For example, in some embodiments, if spacer layer 34 is W and FL1 32 and FL2 36 are CoFeB, spacer layer 34 may be about 0.4 nm to about 0.8 nm, e.g., about 0.5 nm to about 0.7 nm, although other values are contemplated and may be used (depending on the materials used for spacer layer 34). The first magnetic layer FL 1 32 and the second magnetic layer FL 2 36 may have a certain crystalline structure that, together with the spacer layer 34, increase and decrease their antiferromagnetic effect. For example, in some embodiments, FL 1 32 and FL 2 36 may both have the same crystal structure, e.g., face centered cubic (fcc), space centered cubic (bcc), or hexagonal close sphere packing (hcp), and in other embodiments, FL 1 32 may have a crystal structure and FL 2 36 may have a different crystal structure. In such embodiments, the spacer layer 34 may function as a structural barrier between FL 1 32 and FL 2 36, such that the crystal structures of FL 1 32 and FL 2 36 may be different.Layer FL 132 may be about 0.5 nm to 2.5 nm thick and layer FL 2 36 may be about 1.0 nm to 2.5 nm thick. The total thickness of the synthetic free layer 30 may be about 1.5 nm to about 5.0 nm.In some embodiments, the barrier layer 40 is formed from one or more materials such as magnesium oxide, aluminum oxide (AlO x) ( e.g., Al 2 O 3), MgAl 2 O 4, even semimetals, the like, or combinations thereof. In some embodiments, the material of barrier layer 40 comprises a crystalline material deposited to have a particular crystal structure, e.g., a bcc, fcc, or hcp structure, while in other embodiments, the material of barrier layer 40 may be deposited amorphously. In some embodiments, the material of the barrier layer 40 may be deposited to have the same crystal structure as FL 2 36 of the synthetic free layer 30. In some embodiments, the barrier layer 40 may have a thickness of about 0.5 nm to about 1.5 nm. In some cases, by controlling the thickness of the barrier layer 40, the resistance (R MTJ) of the MTJ film stack 100 may be controlled. For example, a thicker barrier layer 40 may increase the resistance of the MTJ film stack 100. In some embodiments, the performance of a SOT MRAM cell 90 may be improved by controlling the resistance R MTJ of the MTJ film stack 100 to match the parasitic resistance of the circuit(s) connected to the SOT MRAM cell 90. In some cases, by matching the resistors in this manner, the ranges of operating conditions over which the SOT MRAM cell 90 can be read can be increased. The barrier layer 40 may be thin enough that electrons are able to tunnel through the barrier layer 40.The reference layer structure 50 may be a synthetic antiferromagnetic structure similar to the synthetic free layer 30. However, the magnetic moment of the reference layer structure 50 does not change. The reference layer structure 50 may be made of any of the same materials as the synthetic free layer 30. In some embodiments, the reference layer structure 50 includes one or more layers of magnetic materials. In some embodiments, the reference layer structure 50 includes a reference layer RL 52, which may include Co, Fe, Ni, CoFe, NiFe, FeB, CoFeB, CoFeW, alloys thereof, the like, or combinations thereof. In some embodiments, the reference layer structure 50 may also include a pinned layer PL 56, which may also include Co, Fe, Ni, CoFe, NiFe, FeB, CoFeB, CoFeW, alloys thereof, the like, or combinations thereof, and which may or may not be different from the material of the RL 52. A spacer layer 54 is disposed between the RL 52 and the pinned layer 56. The spacer layer 54 may be made of any non-ferromagnetic material, such as Cu, Cr, Ru, Ir, Rh, Re, V, Nb, W, Ta, Mo, the like, or combinations thereof. Each of the layers in the reference layer structure 50 includes a crystalline material deposited to have a particular crystalline structure, e.g., an fcc, bcc, or hcp structure. The material of the reference layer RL 52 may be deposited to have the same crystalline structure as the barrier layer 40 in some embodiments, the spacer layer 54 may be used as a physical barrier, such that the pinned layer 56 may have a different crystalline structure type than the reference layer 52. In some embodiments, the pinned layer 56 may be omitted and the antiferromagnetic layer 60 may serve as the pinned layer 56.The antiferromagnetic (AFM) layer 60 is a hard bias layer that is used to confine the magnetization direction of the reference layer structure 50 in a fixed direction and may be referred to as a pinning layer. Together, the AFM layer 60 and the reference layer structure 50 may avoid generation of a stray field that may interfere with the synthetic free layer 30 of the SOT MRAM cell 90 or an adjacent SOT MRAM cell 90. The pinning of the magnetization direction of the reference layer structure 50 or reference layer 52 allows the SOT MRAM cell 90 to be switched back and forth between a low resistance state and a high resistance state by changing the magnetization direction of the synthetic free layer 30 with respect to the reference layer 52. In other embodiments, the AFM layer 60 may be a layer of one or more metals that have antiferromagnetic properties. For example, the AFM layer 60 may be made of platinum-manganese (PtMn), iridium-manganese (IrMn), iron-manganese (FeMn), or combinations thereof deposited to have an fcc crystal structure. In some embodiments, the AFM layer 60 may have a thickness of about 10 nm to about 30 nm. In some embodiments, a thicker AFM layer 60 may have stronger antiferromagnetic properties or may be more robust against external magnetic fields or thermal fluctuation.The capping layer 70 may be a single-layer or multi-layer structure that serves to protect the layers under the capping layer 70 during subsequent processes. In some embodiments, the capping layer 70 may also be used to provide an upper electrode for connection to an overlying via or metal line. The capping layer 70 may be formed of a non-ferromagnetic material such as Cu, Ru, Cr, Pt, W, Ta, Mo, Ti, TaN, TiN, the like, or combinations thereof. In some embodiments, the capping layer 70 may include two non-ferromagnetic material layers, between which another non-ferromagnetic material layer is disposed, e.g., another one of Cu, Ru, Cr, Pt, W, Ta, Mo, Ti, TaN, TiN, the like, or combinations thereof. For example, in some embodiments, the capping layer may include Ta or Ti interposed between two Ru layers. The thickness of the cover layer 70 may be about 3 nm to about 10 nm, although other thicknesses are contemplated. In embodiments where multiple layers are used for the capping layer 70, each layer may be about 1 nm to about 5 nm.A separate top electrode 75 may be disposed over the cover layer 70. The top electrode 75 may be used to provide electrical connection to a conductive structure coupled to the top of the MTJ film stack 100. The top electrode 75 may be formed of any suitable material such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, the like, or combinations thereof. The capping layer 70 and / or the top electrode 75 may collectively be referred to as a layer 80.FIG. 2 shows a simplified schematic top view of a SOT MRAM cell 90 according to an embodiment of the present disclosure. Some elements have been omitted or simplified for clarity. The MTJ film stack 100 is shown as having an ellipse shape in the X-Y plane, with the long axis of the ellipse being parallel to the X axis. Lower electrodes 5 are shown on each side of the MTJ film stack 100 and are positioned such that current flowing from one of the lower electrodes 5 to the other of the lower electrodes 5 (shown by arrow 92) also flows parallel to the X axis. Due to the antiferromagnetic device of the synthetic free layer 30, the magnetic moment 94 of the FL 1 32 may be intrinsically rotated away from the X axis by an angle θ 1 of about 5° to about 45°. The magnetic moment 96 of the FL 2 36 may also be rotated away from the X axis by an angle θ 2, which may be about 5° to about 45°. Due to the displacement of the magnetic moment 94 and the magnetic moment 96 from the X axis, the current Jc may provide spin orbit torque to switch the synthetic free layer 30 without an external field. The offset magnetic moment 94 and the offset magnetic moment 96 generate X and Y components, and the Y components contribute to switching without an external field. Rather than forcing the rotated magnetic moment by rotating the MTJ film stack 100, the long axis of the MTJ film stack 100 remains parallel to the X axis, so no additional lateral space is needed to implement the embodiments disclosed herein.FIG. 3 shows a simplified schematic view of a SOT MRAM cell 90 according to an embodiment of the present disclosure. Materials, configurations, dimensions, methods, and / or operations described with reference to FIG. 1 using the same reference numerals may be used in the following embodiments, and detailed explanation thereof may be omitted.In some embodiments, the spin hall electrode 10 is connected at one end to a switching device (e.g., a field effect transistor (FET)), referred to herein as FET 110. In some embodiments, the spin hall electrode 10 is connected to a drain (or source) of the FET 110 (or FET 1) through one or more conductive structures (e.g., a via, wiring, conductive lines, and / or a contact pad), and a gate of the FET is connected to a word line WL 1 120 through one or more conductive structures. A source (or drain) of the FET 1 is connected to a source line SL 1 125 through one or more conductive structures. Another end of the spin Hall electrode 10 is connected to another switching device (e.g., a field effect transistor (FET)), also referred to herein as FET 110 (or FET 2). In some embodiments, the spin hall electrode 10 is connected to a drain (or source) of the FET 2 through one or more conductive structures, and a gate of the FET 2 is connected to a word line WL 2 120 through one or more conductive structures. A source (or drain) of the FET 2 is connected to a source line SL 2 125 through one or more conductive structures.The MTJ film stack 100 is disposed along the vertical direction (film stack direction) (Z direction) above the spin Hall electrode 10. A bit line 160 is electrically connected to the top of the MTJ film stack 100 by one or more conductive structures.In some embodiments, the MTJ film stack 100 may be inverted and the spin Hall electrode 10 may be disposed over the MTJ film stack 100. In such embodiments, the capping layer 70 may be omitted, and the upper electrode 75 (see FIG. 1 ) may become a lower electrode 5, and the lower electrodes 5 may become upper electrodes 75. The synthetic free layer 30 of the MTJ film stack 100 may be disposed at a top of the inverted MTJ film stack 100. The wiring means may remain the same, wherein a drain (a source) of the FET 1 110 is connected to the one end of the spin Hall electrode 10 and a drain (a source) of the FET 2 110 is connected to the other end of the spin Hall electrode 10 through conductive structures. Similarly, the bit line 160 may be connected to the now bottom of the MTJ film stack 100 by one or more conductive structures. Referring to FIG. 1, by inverting the MTJ film stack 100 and disposing the spin Hall electrode over the inverted MTJ film stack 100, the top electrode 75 is now formed on the bottom surface; the top (now bottom) electrode 75 is overlaid with the AFM layer 60; the reference layer structure 50 is overlaid with the reference layer structure 50; the barrier layer 40 is overlaid with the barrier layer 40 is overlaid with the free layer 30; the free layer 30 is overlaid with the spin Hall electrode 10 is overlaid with the spin Hall electrode 10; and the bottom (now top) electrodes 5 are overlaid with the FETs 110 at each end of the spin Hall electrode 10, respectively.Using the arrangement of elements as shown in FIG. 3, the SOT MRAM cell 90 can implement an x-type memory element without the need to use an external field to assist in switching the synthetic free layer 30, and without rotating the MTJ film stack 100. In addition, by using SOT MRAM cells 90 instead of STT MRAM cells, power supply requirements are lower, so that the transistor size of the FETs 110 (FET 1 and FET 2) can also be reduced. In some embodiments, the area size of the SOT MRAM device 300 may be about 50% to 75% of the area size of a comparable SRAM device and about the same size as an STT MRAM device, requiring less current, which provides for faster switching and longer durability (a higher number of switching cycles).When word line WL1 120 receives a positive bias voltage and word line WL2 receives a positive bias voltage, the gate of FETs 110 (FET1 and FET2) is turned on. Then, the current Jc can flow in one direction through the spin Hall electrode 10, thereby inducing a change in the magnetization direction of the synthetic free layer 30. When the current direction is reversed, the current Jc can flow through the spin Hall electrode 10 in the opposite direction, thereby inducing a change in the magnetization direction of the synthetic free layer 30 in a reverse direction. However, when one of the FETs 110 (FET 1 and FET 2) is not turned on, current does not flow through the spin Hall electrode 10, and a read operation through the MTJ stack film 100 may be performed on the bit line 160. The read and write operations will be described in more detail below.FIGS. 4A, 4B, and 4C show various configurations of the MTJ film stack 100, according to various embodiments. The spin Hall electrode 10 is a spin orbit active layer that causes a strong spin orbit interaction with the synthetic free layer 30.In FIG. 4A, the spin Hall electrode 10 has an fcc crystal structure, while the barrier layer 40 may have a bcc crystal structure or may be amorphous. The first layer FL 1 32 of the synthetic free layer 30 has a crystal structure following that of the spin Hall electrode 10. The spacer layer 34 may function as a structural barrier between the crystal structure of the FL1 layer 32 (which follows the crystal structure of the spin Hall electrode 10) and the FL2 layer 36 (which allows the FL2 layer 36 to conform to the crystal structure of the barrier layer 40). The spacer layer 34 may be either amorphous or may have a bcc crystal structure. Then, the FL2 layer 36 may have a bcc crystal structure. The barrier layer 40 may be bcc or amorphous and the reference layer 52 of the reference layer structure 50 may also be bcc. The spacer layer 54 of the reference layer structure 50 may be hcp (e.g., at Ru) or fcc (e.g., at Ir), and the pinned layer 56 of the reference layer structure 50 may be fcc or bcc. The AFM 60 may be fcc.The spin Hall electrode 10 may be formed of platinum, palladium, gold, tantalum, tungsten, combinations thereof, or other suitable material and may be formed to have a thickness of about 3 nm to about 10 nm, although other values are contemplated and may be used. The FL132of the synthetic free layer 30 may be formed of CoFeB, CoFe, FeB, or NiFe, and may be about 0.5 nm to about 2.5 nm, although other values are contemplated and may be used. The spacer layer 34 of the synthetic free layer 30 may be formed of W, Ta, Mo, Cr, the like, or combinations thereof, and may have a thickness of about 0.3 nm to about 1.5 nm (the thickness depending on the materials used and sized to maintain antiferromagnetic coupling between the FL 1 32 and the FL 2 36, as described above). The barrier layer 40 may be formed of crystalline magnesium oxide or amorphous aluminum oxide (e.g., AlO x) or other suitable material and may have a thickness of about 0.5 nm to about 1.5 nm. The reference layer 52 of the reference layer structure 50 may be formed of a combination of CoFeB, FeB, Co, and CoFe in some embodiments. For example, a CoFeB layer may be in contact with the barrier layer 40, and a CoFe layer is formed on the CoFeB layer and forms an interface with the spacer layer 54 of the reference layer structure 50. the thickness of the CoFeB layer may be about 1.5 nm to about 3.5 nm, and that of the CoFe layer may be about 0.5 nm to about 1.5 nm, with a total thickness of the reference layer 52 being about 2 nm to about 5 nm. The spacer layer 54 of the reference structure 50 may be made of Ru or Ir and may have a thickness of about 0.2 nm to about 1.5 nm. The pinned layer 56 of the reference layer structure 50 may be made of CoFe or a combination of CoFe and Co and may have a total thickness of about 2 nm to about 4 nm. Although CoFe usually has a bcc crystal structure, the structure may be affected by the structure of the overlying AFM layer 60 to have an fcc crystal structure, for example, when the AFM layer 60 is formed of platinum-manganese. The AFM layer 60 may be formed of any suitable material, such as platinum-manganese, iridium-manganese, or iron-manganese, and may have a thickness of about 10 nm to about 30 nm. The total thickness of the MTJ film stack 100 may be about 20 nm to about 35 nm.In FIG. 4B, the spin Hall electrode 10 has a bcc crystal structure that may conform to the crystal structure of the barrier layer 40 (bcc). In some embodiments, the barrier layer 40 may be amorphous. The first layer FL 1 32 of the synthetic free layer 30 has a crystal structure following that of the spin Hall electrode 10. The spacer layer 34 may be either amorphous or have a bcc crystal structure. The FL 2 36 may have a bcc crystal structure. The barrier layer 40 may be bcc or amorphous and the reference layer 52 of the reference layer structure 50 may also be bcc. The spacer layer 54 of the reference layer structure 50 may be hcp (e.g., at Ru) or fcc (e.g., at Ir), and the pinned layer 56 of the reference layer structure 50 may be fcc or bcc. The AFM 60 may be fcc. Since the crystal structure of the FL 1 32 and the FL 2 36 may be the same as the crystal structure of the barrier layer 40, the magneto-resistance ratio of the MTJ film stack 100 during the read operations is improved by the structure matching.The magnetoresistance ratio (MR ratio) is a ratio equal to the antiparallel resistance of the combination of the free layer and the reference layer (Rap) minus the parallel resistance of the combination of the free layer and the reference layer (Rp) divided by the parallel resistance of the combination of the free layer and the reference layer (Rp). MR ratio = (Rap-Rp) / Rp.The spin Hall electrode 10 may be formed of tungsten, tantalum, platinum, other suitable materials, or combinations thereof, and may be formed to have a thickness of about 3 nm to about 10 nm, although other values are contemplated and may be used. The remaining layers may be formed from materials and in configurations similar to those listed above for FIG. 4A.In FIG. 4C, the spacer layer 34 is made of Ru, which enhances the antiferromagnetic coupling between FL1 32 and FL2 36. The higher antiferromagnetic coupling reduces the write current and therefore smaller write transistors can be used. However, Ru may have a negative interaction with B, thereby degrading the antiferromagnetic coupling in the synthetic free layer 30. Thus, in FIG. 4C, the spacer layer 34 is disposed between two CoFe thin layers, that is, disposed between two CoFeB thin layers. FL1 32 therefore has a CoFeB layer (layer 32B) which forms an interface with spin Hall electrode 10, and then a CoFe layer (layer 32A) on the CoFeB layer which forms an interface with spacer layer 34 of synthetic free layer 30. The FL2 36 is formed reversely, a CoFe layer (layer 36A) forms an interface with the spacer layer 34, and then a CoFeB layer (layer 36B) is disposed on the CoFe layer. In the FL 1 32, the CoFeB layer 32B may have a thickness of about 0.1 nm to 2.4 nm, the CoFe layer 32A may have a thickness of about 0.1 nm to about 0.4 nm, and a total thickness of the FL 1 32 may be about 0.5 nm to about 2.5 nm. In the FL 2 36, the CoFe layer 36A may have a thickness of about 0.1 nm to about 0.4 nm, the CoFeB layer 36B may have a thickness of about 0.9 nm to about 2.4 nm, and a total thickness of the FL 2 36 may be about 1 nm to about 2.5 nm.Similar to, among other things, described above with respect to FIG. 4A, the barrier layer 40 may be bcc and the reference layer 52 of the reference layer structure 50 may also be bcc. The spacer layer 54 of the reference layer structure 50 may be hcp and the pinned layer 56 of the reference layer structure 50 may be fcc or bcc. The AFM 60 may be fcc.With continued reference to FIG. 4C, the spin Hall electrode 10 may be formed of platinum, tungsten, tantalum, palladium, gold and may be formed to have a thickness of about 3 nm to about 10 nm, although other values are contemplated and may be used. The remaining layers may be formed from materials and in configurations similar to those listed above for FIG. 4A.FIGS. 5, 21, and 22 are schematic cross-sectional views of a portion of the SOT MRAM device 300 according to various embodiments. Some aspects of the illustrated layers of the SOT MRAM device 300 may be shown flattened in these cross-sectional views, and it should be appreciated that some layers are actually in other cross-sections. FIG. 23 is a three-dimensional representation of the SOT MRAM devices shown in FIGS. 5, 21, and 22. FIG. 24 is a circuit diagram consistent with the embodiments illustrated in FIGS. 5, 21, and 22.Materials, configurations, dimensions, methods, and / or operations described with reference to FIGS. 1 to 3 may also be used in the following embodiments, and detailed explanation thereof may be omitted. Referring generally to FIGS. 5, 14, and 15, in some embodiments, the SOT MRAM device has a layered structure including a multi-wiring layered structure. In some embodiments, the multi-wiring layer structure includes metal wiring layers "Mx" (x=0, 1, 2, 3,... ) located on respective planes disposed above a substrate, and vias (contacts) "Vy" (y=0, 1, 2, 3,... ) connecting the metal wiring layer My to the metal wiring layer My+1. The metal wiring layers include metal lines embedded in a dielectric material layer. The vias include conductive plugs embedded in an interlayer dielectric (ILD) material separating adjacent metal wiring layers. For purposes of illustration and designation, the elements ending with "A" correspond to planes x=0, y=0, the elements ending with "B" correspond to planes x=1, y=1, the elements ending with "C" correspond to planes x=3, y=3, etc. In some embodiments, the even numbered metal wiring layers extend in one direction (e.g., X) and the odd numbered metal wiring layers extend in another direction (e.g., Y) intersecting the one direction. In some embodiments, center distances for metal wirings may generally increase as the levels become higher. For example, the pitches of the metal wirings in the planes M 3 and M 4 may be the same, and pitches for the metal wirings M 5 or higher may be the same, and may be larger than the pitches for the metal wirings in M 3 and M 4.In some embodiments, the metal wirings and the vias are made of one or more of aluminum, cobalt, copper, a copper alloy, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, the like, or combinations thereof. The vias may also include barrier or bonding material layers surrounding the sides of the vias and formed from one or more layers of titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, ruthenium, rhodium, platinum, other noble metals, other refractory metals, their nitrides, combinations of these, or the like.In some embodiments, the ILD layers are formed of any suitable dielectric material, for example, a nitride such as silicon nitride, an oxide such as silicon oxide, SiOC, and SiOCN, SiCN, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), the like, or combinations thereof.The contact plugs 118 connect a source region 112S or a drain region 112D of the FETs 110 to the metal wiring layer M 0 (e.g., the conductive line 130A) through a dielectric layer 104. The source line SL 1 125 is located in the metal wiring layer M 0 and is connected to the source region 112S of the FET 1 110. The source line SL 2 125 is located in the metal wiring layer M 0 and is connected to the source region 112S of the FET 2 110. The drain region 112D of the FET 1 110 is connected to one end of the spin Hall electrode 10. The drain region 112D of the FET 2 110 is connected to the other end of the spin Hall electrode 10. The bit line BL 160 is located above the MTJ film stack 100 in the metal wiring layer M 2, and is connected to the top surface of the MTJ film stack 100. The word line WL1 is connected to the gate of the FET1 110, and the word line WL2 is connected to the gate of the FET2 110.It is also understood that the schematic of FIG. 5 is merely an illustration of an embodiment and changes may be made without departing from the spirit of the disclosure. For example, it is understood that multiple intermediate layers may be incorporated as required to accommodate a desired wiring layout. In particular, it is contemplated in the disclosure that when a particular element is described as being in a particular metal wiring layer, any desired number of metal wiring layers may be disposed between the described metal wiring layers. For example, where an element is described as being in the metal wiring layer M 2 and an element other than being in the metal wiring layer M 3, any number of metal wiring layers may be disposed between the metal wiring layer M 2 and the metal wiring layer M 3. In addition, as stated above, the MTJ film stack 100 may be formed such that the spin Hall electrode 10 is disposed above the MTJ film stack 100.In some embodiments, the FETs are planar FETs, fin FETs, or gate-all-around FETs. The electrode 75 is connected to a drain region 112D of an FET 110, and a source region 112S of the FET 110 is connected to the source line SL 1 125. In some embodiments, the source region 112S is shared between two adjacent FETs 110 (see FIG. 22 ). In some embodiments, one pair of FETs 110 (FET 1 and FET 2) is separated from another pair of FETs 110 by a dummy gate structure 121 (e.g., in MC 2 of FIG. 5 ). The word lines WL 120 are connected to the gates of the FETs 110 and switch whether a current can flow from the source line SL 125 through the MTJ film stack 100 to the bit line BL 160.Referring to FIG. 5, there are shown two SOT MRAM cells 90 of the SOT MRAM device 300 including MC 1 and MC 2. As shown in FIG. 5, the source regions 112S of adjacent SOT MRAM cells 90 may be separated by a dummy gate structure 121, similar to the separation of the drain regions 112D of the FETs 110 (FET 1 and FET 2) by the dummy gate structure 121. In some embodiments, two of the adjacent SOT MRAM cells 90 may share a common source region 112S (see, e.g., FIG. 22 ).The spin Hall electrode 10 may be disposed in the metal wiring layer M 1, and may be connected to the drain region 112D (or source region) of each of the FETs 110 of MC 1. The MTJ film stack 100 may be disposed on the spin Hall electrode 10 in the V1 layer, for example, in a lower portion V 1A of the V1 layer. A via 126B may connect the top of the MTJ film stack 100 to the bit line signal BL 160 in the metal wiring layer M 2. The source line SL 1 and the source line SL 2 may be disposed in the metal wiring layer M 0, and may be connected to the source region 112S (or drain region) of each of the FETs 110 (FET 1 and FET 2, respectively). The word line WL1 and the word line WL2 are connected to the gate electrodes of each of the FETs 110 (FET1 and FET2, respectively). These connections can be brought into the metal wiring layer M0 through vias and wiring structures in a different cross section. As illustrated in FIG. 5, the source lines (e.g., SL 1 and SL 2) are each directed in the Y direction and have a small cross section along the X direction.In some embodiments, the MTJ film stacks 100, the spin Hall electrode 10, the source lines SL 125, and the bit lines BL 160 may each be a metal wiring layer disposed lower or one or more metal wiring layers disposed upper.FIGS. 6 through 21 show intermediate steps in the formation of the SOT MRAM device 300 of FIG. 5.FIG. 6 illustrates a cross-sectional view of a substrate 102 and a plurality of FETs 110 formed on the substrate 102, in accordance with some embodiments. The FETs 110 are part of the subsequently formed SOT MRAM cells 90 of the SOT MRAM device 300. Some example FETs 110 are labeled in FIG. 6. The substrate 102 may be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials such as germanium; a compound semiconductor, e.g., silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, e.g., multilayer substrates or gradient substrates, may also be used.In some embodiments, FETs 110 are fin field effect transistors (FinFETs) that include fins 116, gate structures 114, and source regions 112S and drain regions 112D. As shown in FIG. 6, the fins 116 are formed on the substrate 102 and may comprise the same material as the substrate 102 or a different material. In some embodiments, dummy fins (not shown) may be formed between some fins 116 to improve process uniformity. The gate structures 114 are formed over a plurality of fins 116 and extend in a direction perpendicular to the fins 116. In some embodiments, spacers (not shown in the figures) may be formed on the sidewalls of the gate structures 114. The dummy gate structures 121 may be considered "dummy transistors" or "dummy FinFETs" in some embodiments. Some gate structures 114 are used as word lines in the SOT MRAM device 300 (as described in more detail below) and are labeled as "WL", e.g., "WL2", respectively. The source regions 112S and the drain regions 112D are formed in the fins on each side of the gate structures 114. The source regions 112S and the drain regions 112D may be, for example, implanted regions of the fins 116, or an epitaxial material grown in recesses formed in the fins 116. In the embodiment illustrated in FIG. 6, one side of each fin 116 is adjacent to source regions 112S and the other side of each fin 116 is adjacent to drain regions 112D.The FETs 110 illustrated in the figures are exemplary and some features of the FETs may have been omitted from the figures for clarity of illustration. In other embodiments, the arrangement, configuration, sizes, or shapes of features such as fins 116, dummy fins, gate structures 114, dummy gate structures 21, source regions 112S, drain regions 112D, or other features may be other than illustrated. In other embodiments, the FETs 110 may be another type of transistor, e.g., planar transistors.In FIG. 7, a dielectric layer 104 is formed over the substrate 102, and is patterned to expose the source regions 112S and the drain regions 112D, in accordance with some embodiments. The dielectric layer 104 may cover the FETs 110 and may be considered as an interlayer dielectric (ILD) layer in some embodiments. The dielectric layer 104 may be formed of any suitable dielectric material, for example, one of the materials listed above for an ILD. The dielectric layer 104 may be formed by any acceptable deposition method, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. In some embodiments, the dielectric layer 104 may be a low-k dielectric material, for example, a dielectric material having a dielectric constant (k-value) of less than about 3.0.The dielectric layer 104 may be patterned to form openings 106 exposing the source regions 112S and the drain regions 112D for the subsequent formation of contact plugs 118 (see FIG. 3 ). The dielectric layer 104 may be patterned by a suitable photolithography and etching process. For example, a photoresist pattern (not shown) may be formed and patterned over the dielectric layer 104. The openings 106 may be formed by etching the dielectric layer 104 using the patterned photoresist pattern as an etch mask. The dielectric layer 104 may be etched by a suitable anisotropic etching method, e.g., a wet etching method or a dry etching method.Turning now to FIG. 8, in accordance with some embodiments, contact plugs 118 are formed to electrically connect to the source regions 112S and the drain regions 112D. In some embodiments, the contact plugs 118 are formed by depositing a barrier layer (not individually shown) extending into the openings 106, depositing a conductive material over the barrier layer, and performing a planarization process, e.g., a chemical mechanical polishing (CMP) process or a grinding process, to remove excess portions of the overlying conductive barrier layer and the conductive material. The barrier layer or conductive material of the contact plugs 118 may be formed by a suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, or the like. The barrier layer, if used, may be formed of any suitable material, such as TiN, Ti, TaN, Ta, the like, or combinations thereof.Turning now to FIG. 9, conductive lines 130A are formed therein to electrically connect the contact plugs 118 and to provide electrical routing within the SOT MRAM device. The conductive lines 130A may be formed within a dielectric layer 128A formed over the dielectric layer 104. Dielectric layer 128A may be a material similar to those described above for dielectric layer 104 (see FIG. 7 ), and may be deposited by techniques similar to dielectric layer 104. The dielectric layer 128A may be considered an inter-metal dielectric (IMD) layer in some embodiments.The conductive lines 130A may be formed by any suitable technique, such as damascene technique, dual damascene technique, plating, deposition, the like, or combinations thereof. In some embodiments, the conductive lines 130A are formed by first depositing the dielectric layer 128A and patterning the dielectric layer 128A to form openings (e.g., by a suitable photolithography and etching process), and then filling the openings in the dielectric layer 128A with conductive material. For example, the conductive lines 130A may be formed by depositing an optional capping barrier layer (not individually shown) over the patterned dielectric layer 128A, depositing a conductive material over the capping barrier layer, and performing a planarization process, e.g., a CMP process or a grinding process, to remove excess portions of the capping conductive layer and the conductive material. The barrier layer or conductive material may be similar to that described above for the contact plugs 118 (see FIG. 8 ), and may be deposited by similar techniques. In some embodiments, the conductive material of the contact plugs 118 and the conductive lines 130A may be deposited in the same step, for example, when a dual damascene process is applied to form the contact plugs 118 and the conductive lines 130A.In some embodiments, the conductive lines 130A are formed by first depositing the optional capping barrier layer over the dielectric layer 104 and the contact plugs 118, depositing a conductive material over the capping barrier layer, and then patterning (e.g., by a suitable photolithography and etching process) the barrier layer and the conductive material to form the conductive lines 130A. The dielectric layer 128A may be deposited over the conductive lines 130A and a planarization process may be performed to expose the conductive lines 130A.In FIG. 10, vias 126A are formed within a dielectric layer 124A to electrically connect to the conductive lines 130A, in accordance with some embodiments. In some embodiments, first, dielectric layer 124A is formed over conductive lines 130A and dielectric layer 128A. Dielectric layer 124A may be a material similar to those described above for dielectric layer 104, and vias 126A may be formed by methods and using materials similar to those described above with respect to contact plugs 118. In some embodiments, vias 126A may be formed by a single damascene process and may be a Cu, W, or TiN plug. In some embodiments, the vias 126A may serve as the bottom electrode 5 (see FIG. 1 ). An optional barrier layer may also be used, as described above with respect to the contact plugs 118, to prevent diffusion of the material of the contact plugs 118 into the surrounding dielectric layer 124A. In some embodiments, additional wiring layers are incorporated between the Mo layer and the Vo layer, and the Vo layer represents the layer immediately below the subsequently formed SHE 10. The methods of forming the conductive lines and the vias are repeated to form a desired number of metal wiring layers.As shown in FIG. 10, after forming the vias 126A, the spin Hall electrode 10 may be formed. In some embodiments, the vias 126A may serve as the bottom electrode 5 (shown in other figures, e.g., FIG. 1 ). In some embodiments, buffer layer 7 (see FIG. 1 ) may be formed over vias 126A by any suitable method, e.g., by CVD, PVD, the like, or combinations thereof. In embodiments where a buffer layer is used, the buffer layer may include MgO or the like deposited to a thickness of about 0.2 nm to 0.9 nm. The bottom electrodes 5 may also be formed via the techniques described above with respect to forming the conductive lines 130A.After forming the buffer layer 7 (if used), the spin Hall electrode 10 may be formed. The spin Hall electrode 10 is formed by methods and using materials such as those described above with respect to FIG. 1. In some embodiments, after the spin Hall electrode 10 is deposited, the MTJ film stack 100 is gradually deposited as described below without breaking the vacuum during the methods of depositing the optional buffer layer 7, the spin Hall electrode 10, and the MTJ film stack 100.Referring to FIG. 11, in successive layers, as shown in FIG. 1, the MTJ film stack 100 is deposited according to the embodiments shown in FIGS. 4A, 4B, and 4C. Layers for the MTJ film stack 100 are formed over the spin Hall electrode 10, including the synthetic free layer 30, the barrier layer 40, the reference layer structure 50, and the AFM layer 60. The layer 80 that may include the capping layer 70 and the top electrode 75 (see FIG. 1 ) may be formed next. In some embodiments, the top electrode 75 may be formed as part of the hard mask layer 95. In some embodiments, the hard mask layer 95 may include a composite film stack including a metal layer and a dielectric layer over the metal layer. The hard mask layer 95 may be deposited by any suitable method and may be made of any suitable material, such as silicon nitride or a conductive metal layer, e.g., tantalum, tungsten, titanium nitride, the like, or combinations thereof, such as a first layer of conductive metal and a second layer of dielectric, e.g., silicon nitride. When the hard mask layer 95 is used in forming the MTJ film stack 100 as described above, the dielectric layer of the hard mask layer 95 may be mostly consumed and the remaining metal layer may serve as the upper electrode 75. Each of the layers of the MTJ film stack 100, the layer 80, and the hard mask layers 95 may be formed by suitable film formation methods including physical vapor deposition (PVD), e.g., sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam epitaxy; The chemical vapor deposition (CVD) or inferred CVD methods may include, for example, low pressure CVD (LPCVD), ultra high vacuum CVD (UHVCVD), REDUCED PRESSURE CVD (RPCVD); electroplating, or any combinations thereof.Referring to FIG. 12, the hard mask layer 95 is patterned to protect regions of the SOT MRAM device 300 where the pillars of the MTJ film stack 100 are to be formed. The patterning may be performed by any suitable method, for example, by a photolithography method.FIG. 13 illustrates the SOT MRAM device 300 after patterning the MTJ film stacks 100. The MTJ film stacks 100 may be patterned by any suitable method, e.g., a dry etching method, e.g., reactive ion etching (RIE) and / or ion beam etching (IBE) to etch through each of the successive layers with suitable etchants. In some embodiments, the entire hard mask layer 95 or a portion of the hard mask layer 95 may be removed by the etching process or by a subsequent removal process. As indicated above, in some embodiments, during etching, a dielectric layer may be completely or mostly consumed, while an underlying metal layer may remain to serve as the top electrode 75 or as part of the top electrode 75. In some embodiments, e.g., when the hard mask layer 95 is a metal layer, the hard mask layer 95 may remain after the etching process and may be retained in the structure of the finished device. After patterning the MTJ stacks of films 100, each of the MTJ stacks of films 100 may have a transverse shape or a mesa shape in cross section. In addition, as illustrated in FIG. 2, each of the MTJ film stacks 100 may have an elliptical shape in a plan view having a long axis parallel to the x axis and parallel to the direction of current flow in the spin Hall electrode 10. Structuring the MTJ stacks of films 100 with their long axis parallel to the x-axis allows for greater storage density than if the MTJ stacks of films 100 were rotated about the z-axis.However, since a synthetic free layer 30 is used in the MTJ film stack 100, the natural magnetic moment of the synthetic free layer 30 is rotated about the Z axis to be oblique to the x axis which is parallel to the direction of current flow through the spin Hall electrode 10. As noted above, this occurs without the need to rotate the MTJ film stacks 100. Due to the oblique magnetic moment, the switching of the synthetic free layer 30 can be achieved exclusively by the spin orbit torque and without the need for an external field.In FIG. 14, a conformal insulating layer 210 is deposited to encapsulate the patterned MTJ film stacks 100 and deposited over the spin Hall electrode 10. The conformal insulating layer 210 may be formed of any suitable insulating material, such as a nitride such as silicon nitride, silicon carbide, the like, or combinations thereof. The conformal insulating layer 210 may be formed by any suitable deposition method, such as physical vapor deposition (PVD), e.g., sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam deposition; chemical vapor deposition (CVD), etc.In FIG. 15, a mask 215 may be deposited next over the spin Hall electrode 10 and over the MTJ film stacks 100. The mask 215 may include any suitable light sensitive materials and may be deposited by any suitable method, e.g., spin coating or other method. In some embodiments, the mask may include non-photosensitive materials and may be patterned by a separately formed photomask over mask 215 which is used to etch mask 215.In FIG. 16, the mask 215 is patterned to protect a portion of the spin Hall electrode 10 to be left. The mask 215 may be patterned via acceptable photopatterning techniques applied to either the mask 215 itself or a separate overlying mask, which is then used to etch the mask 215.In FIG. 17, the insulating layer 210 and the spin Hall electrode 10 are etched to form the shape and structure of the spin Hall electrode 10. The spin Hall electrode 10 may be etched by any suitable method, e.g., a dry etching method, to etch through each of the successive layers with suitable etchants. The buffer layer 7 (if used) may also be etched using the mask 215 such that the buffer layer 7 has the same shape and footprint as the spin Hall electrode 10.In some embodiments, an annealing process may be performed, for example, before or after patterning the MTJ film stack 100 and the spin Hall electrode 10. In addition, the annealing process may be carried out under a vacuum of about 1×10 -7 Torr to about 1×10 -6 Torr and optionally in the presence of a magnetic field. For example, the annealing process may be performed in an in-plane (horizontal) in situ magnetic field of about 0.5 Tesla to about 5 Tesla to adjust the AFM 60.In FIG. 18, after the spin Hall electrode 10 is patterned, the mask 215 is removed. The mask 215 may be removed by, for example, an ashing method or wet etching. Next, the ILD 128B is deposited. The ILD 128B may be deposited over and surrounding the spin Hall electrodes 10 and the MTJ film stacks 100. In the illustrated embodiment, an upper portion of the ILD 128B is referred to as the ILD 124B, or an additional ILD layer, ILD 124B, may be deposited in a separate process. The ILD 124B may be flattened after deposition by a planarization process, e.g., a CMP process, to remove protrusions of the MTJ film stack 100, which may be located in the top surface of the ILD 124B after deposition.An alternative method according to some embodiments is illustrated in FIGS. 19 to 20. In the illustrated method, layer 80 is only cover layer 70 and has thus been re-designated. In the illustrated method, a separate top electrode 75 is formed. Openings may be formed in the ILD 124B, and a metal of an upper electrode 75 may be deposited in the openings. In some embodiments, the top electrode 75 may be a single metal layer and in other embodiments, the top electrode may be a multi-layered structure as indicated above. In some embodiments, a TiN plug, a W plug, or Cu formed by single damascene processes may be used for the upper electrode 75. The top electrode 75 may be deposited by any suitable method, such as physical vapor deposition (PVD), e.g., sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam deposition; chemical vapor deposition (CVD), etc. In FIG. 20, the metal of the top electrode 75 is planarized to bring a top surface of the top electrode 75 equal to a top surface of the ILD 124B.FIG. 21 illustrates an embodiment following the process flow of FIG. 18, however, it should be appreciated that the additional features illustrated in FIG. 21 and others may be incorporated into the embodiments illustrated in FIGS. 19 and 20, for example, by depositing an additional ILD layer 124B and corresponding other method. After forming the ILD 124B, additional vias (e.g., vias 126B in FIG. 21 ) may be formed through the ILD 124B, if necessary, to electrically connect to the top of the MTJ film stacks 100, using methods similar to those described above for the contact plugs 118, for example. In some embodiments, vias 126B may contact top electrodes 75 (which may be formed as part of hard mask 95), while in other embodiments, vias 126B may be used as a portion of top electrode 75, but vias 126B do not extend through capping layer 70 which remains in place as a guard for MTJ film stack 100.In FIG. 21, conductive lines 130C are formed to electrically connect vias 126B and provide electrical routing within SOT MRAM device 300 to bitlines 160. The conductive lines 130C may be formed within a dielectric layer 128C formed over the ILD 124B. Dielectric layer 128C may be a material similar to that described above for dielectric layer 104, and may be deposited using techniques similar to dielectric layer 104. The dielectric layer 128C may be considered an inter-metal dielectric (IMD) layer in some embodiments.FIG. 22 illustrates an embodiment of a SOT MRAM device 400 where the source region 112S of adjacent FETs 110 is shared by two SOT MRAM cells 90, e.g., MC 1 and MC 2. Sharing the source line SL (e.g., SL 2 / 3 as shown) and the source regions 112S allows for a greater device density. The SOT MRAM device 400 may be formed by methods and using materials similar to those used to form the SOT MRAM device 300.FIG. 23 illustrates a three-dimensional view of a SOT MRAM cell 90, e.g., MC 1, of the SOT MRAM device 300 of FIG. 21, in accordance with some embodiments. Materials, configurations, dimensions, methods, and / or operations described with reference to FIGS. 1 to 21 may be employed in the following embodiments, and detailed explanation thereof may be omitted.In some embodiments, word lines 120 (connected to a gate of FET 110) extend in the Y direction and source lines SL 1 and SL 2 125 extend in the X direction. The spin Hall electrode 10 is disposed above the source or drain regions of two adjacent FETs 110 and is connected to the corresponding source or drain regions of the two adjacent FETs 110 through vias and metal wiring layers at each end. The spin Hall electrode 10 may have a direction that predominantly extends in the X direction in some embodiments.As shown in FIG. 23, the MTJ film stack 100 is disposed over the spin Hall electrode 10. The MTJ film stack 100 may have a rounded elliptical pillar shape or an elongated cylindrical shape that may taper as shown in other figures. The bit line 160 is electrically connected to the top surface of the MTJ film stack 100 through a via and / or a top electrode of the MTJ film stack 100, and may extend in the X direction.FIG. 24 is a portion of a circuit diagram of a SOT MRAM device consistent with the SOT MRAM device 300, in accordance with some embodiments. Materials, configurations, dimensions, methods, and / or operations described with reference to FIGS. 1 to 21 may be used in the following embodiments, and detailed explanation thereof may be omitted.In some embodiments, both the bit lines BL and the source lines SL 1 / SL 2 extend in a row direction and the word lines WL 1 / WL 2 extend in a column direction. The SOT MRAM cells are arranged at locations defined by one bit line BL, two word lines WL 1 / WL 2, and two source lines SL 1 / SL 2 in some embodiments. The number of memory cells connected to the same word lines and / or the same bit lines is not limited to three or four and may be more than 3, e.g., 4, 8, 16, 32, 64, 128, 256, 512 or 1024 or more. The word lines WL1 / WL2 are connected to a word driver circuit (row decoder), and source lines SL1 / SL2 (a bundle of N lines represented by a single line) are connected to a current source circuit which also functions as a write driver circuit in conjunction with the word driver circuit. One end of the spin Hall electrode 10 is connected to a source or a drain of an FET 110, and the other end of the spin Hall electrode 10 is connected to another source or a drain of an FET 110. One end of the MTJ film stack M is connected to the spin Hall electrode 10 between the two connections to the FETs to control the current flow direction. The other end of the MTJ film stack M is connected to a corresponding bit line M. The gates of the FETs 110 are connected to the word lines WL1 / WL2, and the drain or the source of the respective FETs 110 are connected to the source lines SL1 / SL2.In the embodiment of FIG. 24, vertically adjacent SOT MRAM cells along the column direction are connected to the same word lines WL 1 / WL 2. Horizontally adjacent SOT MRAM cells along the row direction are connected to the same bit lines BL and individual source lines SL 1 / SL 2. In some embodiments, adjacent FETs 110 in adjacent SOT MRAM cells share the same source lines SL 1 and SL 2 along the row direction.FIG. 25 illustrates operations of a SOT MRAM cell according to an embodiment of the present disclosure. In a write operation, a write current flows through the spin Hall electrode 10. The first source line SL 1 is set to a first potential (e.g., a write voltage "Vw"), and the second source line SL 2 is set to a second potential (e.g., ground or 0 V), the first potential being higher than the second potential. The bit line BL may be at floating ("f") potential. Electrons flowing in the spin Hall metal of the spin Hall electrode 10 have a positive spin Hall angle and induce SOT on the synthetic free layer 30 to cause the spin characteristics of the electrons of the synthetic free layer 30 to change.When writing a second type of data (e.g., "1") into the MTJ film stack 100, the word line WL 1 and the word line WL 2 are set to turn on the gate electrodes of the FETs 110. The first source line SL 1 is set to the second potential (e.g., ground or 0 V) and the second source line SL 2 is set to the first potential (e.g., a write voltage "Vw"), the first potential being higher than the second potential. The bit line BL may be at floating ("f") potential. Electrons flowing in the reverse direction in the spin Hall metal of the spin Hall electrode 10 have a negative spin Hall angle and induce an SOT on the synthetic free layer 30 to cause the spin characteristics of the electrons of the synthetic free layer 30 to change.When reading data from the MTJ film stack 100, the read operation may be performed in various ways. One of the word lines WL1 or WL2 turns on the corresponding FET 110 while the other is turned off. The SL 1 or the SL 2 connected to the turned-off gate may be at floating potential ("f"), while the SL 1 or the SL 2 connected to the turned-on gate is connected to a current source. The potential Vread at the bit line may be used to calculate the resistance of the spin Hall electrode 10 and the MTJ film stack 100, thereby determining whether the MTJ is set to a state "1" or a state "0". The amplitude of Vreadis about 1 / 10 to about 1 / 30 of Vwin some embodiments. In other embodiments, the read current flows in the opposite direction, from the bit line BL to the source line SL 1 or SL 2, from the MTJ film stack 100 to the spin Hall electrode 10, in other words, from the read bit line BL to the source line SL. In such a case, Vreadis higher than the source line voltage (e.g., Vreadis positive).In some embodiments, a synthetic free layer of a SOT MRAM device is advantageously used that is configured to be antiferromagnetic and provide a magnetic moment that is not aligned (i.e., tilted) with the direction of current through the underlying spin Hall metal. Thus, spin orbit torque can be used to switch the free layer without an external auxiliary field, so that the resistance through the MTJ film stack can be switched between states. In some embodiments, a crystalline structure and spacer materials are used to achieve antiferromagnetic effects while also increasing the magneto-resistance ratio of the MTJ film stack. Thus, an x-type SOT MRAM device may be provided that does not require a rotated MTJ film stack and that consumes less power for operation.One embodiment is a magnetic storage device including a spin Hall electrode, wherein the SHE may include a spin Hall metal. The magnetic memory device also includes a magnetic tunnel junction (MTJ) stack disposed over the SHE, the MTJ may include a synthetic antiferromagnetic free layer that interfaces with the SHE. The synthetic antiferromagnetic free layer may include a first magnetic layer, a second magnetic layer, and a spacer layer disposed between the first magnetic layer and the second magnetic layer. The device also includes a first conductive line connected to a first end of the SHE. The device also includes a second conductive line connected to a second end of the SHE. The spacer layer is configured to prevent a crystal structure of the first magnetic layer from propagating into the second magnetic layer, wherein the crystal structure of the first magnetic layer is different from a crystal structure of the second magnetic layer. In an embodiment of the magnetic memory device, the SHE may include tungsten, platinum, or tantalum, and the spacer layer may include tungsten to a thickness of 0.4 nm to 0.8 nm. In an embodiment, the first magnetic layer and the second magnetic layer are in a synthetic antiferromagnetic configuration. In an embodiment, a crystal structure of a barrier layer of the MTJ stack is consistent with a crystal structure of the SHE. In an embodiment, the spacer layer may include ruthenium, tungsten, tantalum, molybdenum, or chromium. In an embodiment, the spacer layer may include ruthenium and the first magnetic layer may include a first sublayer of CoFe interfacing with the spacer layer and a second sublayer of CoFeB interfacing with the SHE. In an embodiment, the MTJ stack has an elliptical shape in a plan view, and a long axis of the MTJ stack is parallel to a direction of current flow between the first end of the SHE and the second end of the SHE. In one embodiment, the synthetic antiferromagnetic free layer has a preset magnetic moment that is tilted away from the long axis of the MTJ stack.Another embodiment is a magnetic storage device including a spin hall electrode (SHE). The magnetic memory device also includes a spin-top magnetic tunnel junction (MTJ) stack disposed over the SHE, the MTJ stack may include: a spacer layer disposed between a first free layer of the MTJ stack and a second free layer of the MTJ stack, the first free layer and the second layer being magnetically coupled by an antiferromagnetic configuration; a reference layer structure disposed over the second free layer, the reference layer structure may have a synthetic antiferromagnetic configuration; and a barrier layer disposed between the second free layer and the reference layer structure. The first free layer includes a first layer of CoFeB interfacing with the SHE and a second layer of CoFe interfacing with the spacer layer, and the spacer layer includes ruthenium. In an embodiment, the MTJ stack has an elongated shape with an axis of the MTJ stack parallel to a current flow direction through the SHE. In one embodiment, the first free layer and the second free layer have magnetic moments that have a non-zero X component and a non-zero Y component. In an embodiment, a thickness of the spacer layer is configured to cause the first free layer and the second free layer to be in the antiferromagnetic configuration, the thickness being 0.4 nm to 0.8 nm. In an embodiment, the magnetic storage device may include: a first conductive line connected to a first end of the SHE, the first conductive line connected to a source / drain of a first transistor; and a second conductive line connected to a second end of the SHE, the second conductive line connected to a source / drain of a second transistor. In an embodiment, the MTJ stack may further include an antiferromagnetic layer over the reference layer stack.Another embodiment is a method comprising depositing a spin Hall metal layer over an interlayer dielectric of an interconnect structure. The method also includes depositing a sequence of layers of a magnetic tunnel junction (MTJ) film stack, the depositing including: depositing a synthetic antiferromagnetic free layer structure over the spin Hall metal, depositing a barrier layer over the free layer structure, and depositing a reference layer structure over the barrier layer. The MTJ film stack is patterned into at least one MTJ pillar. The spin Hall metal layer is patterned into a spin Hall electrode for each column of the at least one MTJ column. Depositing the synthetic antiferromagnetic free layer comprises: depositing a first layer of magnetic material on the spin Hall metal layer; depositing a spacer layer on the first layer of magnetic material; and depositing a second layer of magnetic material on the spacer layer, the spacer layer having a first thickness, the first thickness causing the first layer of magnetic material and the second layer of magnetic material to be antiferromagnetic. Depositing the first layer of magnetic material includes depositing the first layer of magnetic material to have a first crystal structure, wherein depositing the second layer of magnetic material includes depositing the second layer of magnetic material to have a second crystal structure different from the first crystal structure. In an embodiment, depositing the spin Hall metal layer may include depositing the spin Hall metal layer to have a first crystal structure, wherein depositing the barrier layer may include depositing the barrier layer to have a second crystal structure different from the first crystal structure. In an embodiment, the method may comprise: providing a current from a first end of the spin Hall electrode to a second end of the spin Hall electrode, wherein the current causes a spin orbit interaction in the spin Hall electrode to induce a corresponding spin orbit torque in a free magnetic layer structure, wherein the spin orbit torque causes a magnetic moment of the free magnetic layer structure to change from a first state to a second state, wherein the first state corresponds to a magnetic moment of the free magnetic layer structure that is oblique to a direction of a flow of the current.

Claims

A magnetic storage device, comprising: a spin Hall electrode, SHE (10), the SHE comprising a spin Hall metal; a magnetic tunnel junction, MTJ, stack (100) disposed over the SHE (10), the MTJ comprising a synthetic antiferromagnetic free layer (30) interfacing with the SHE (10), the synthetic antiferromagnetic free layer (30) comprising a first magnetic layer (32), a second magnetic layer (36), and a spacer layer (34) disposed between the first magnetic layer (32) and the second magnetic layer (36); a first conductive line (130A) connected to a first end of the SHE (10); and a second conductive line (130A) connected to a second end of the SHE (10); wherein the spacer layer (34) is configured to prevent a crystal structure of the first magnetic layer (32) from spreading into the second magnetic layer (36), and wherein the crystal structure of the first magnetic layer (32) is different from a crystal structure of the second magnetic layer (36).The magnetic memory device of claim 1, wherein the SHE (10) comprises tungsten, platinum, or tantalum and the spacer layer (34) comprises tungsten to a thickness of 0.4 nm to 0.8 nm.The magnetic storage device of claim 1 or 2, wherein the first magnetic layer (32) and the second magnetic layer (36) are in a synthetic antiferromagnetic configuration.The magnetic memory device of any preceding claim, wherein a crystal structure of a barrier layer (40) of the MTJ stack (100) matches a crystal structure of the SHE (10).The magnetic memory device of claim 4, wherein the barrier layer (40) is disposed between a reference layer structure (50) of the magnetic memory device and the second magnetic layer (36).The magnetic storage device of any preceding claim, wherein the spacer layer (34) comprises ruthenium, tungsten, tantalum, molybdenum, or chromium.The magnetic memory device of claim 6, wherein the spacer layer (34) comprises ruthenium, and the first magnetic layer (32) comprises a first sublayer of CoFe interfacing with the spacer layer (34) and a second sublayer of CoFeB interfacing with the SHE (10).The magnetic storage device according to any one of the preceding claims, wherein the MTJ stack (100) has an elliptical shape in a plan view, and a long axis of the MTJ stack (100) is parallel to a direction of current flow between the first end of the SHE (10) and the second end of the SHE (10).The magnetic storage device according to any one of the preceding claims, wherein the synthetic antiferromagnetic free layer (30) has a preset magnetic moment tilted away from the long axis of the MTJ stack (100).A magnetic memory device, comprising: a spin hall electrode, SHE (10); and a top pinned magnetic tunnel junction, MTJ, stack (100) disposed over the SHE (10), the MTJ stack (100) comprising: a spacer layer (34) disposed between a first free layer (32) of the MTJ stack (100) and a second free layer (36) of the MTJ stack (100), the first free layer (32) and the second free layer (36) being magnetically coupled by an antiferromagnetic configuration, a reference layer structure (50) disposed over the second free layer (36), and a barrier layer (40) disposed between the second free layer (36) and the reference layer structure (50); and wherein the first free layer (32) comprises a first layer of CoFeB interfacing with the SHE (10) and a second layer of CoFe interfacing with the spacer layer (34), the spacer layer (34) comprising ruthenium.The magnetic storage device of claim 10, wherein the MTJ stack (100) has an elongated shape, wherein an axis of the MTJ stack (100) is parallel to a current flow direction through the SHE (10).The magnetic storage device of claim 10 or 11, wherein the first free layer (32) and the second free layer (36) have magnetic moments that have a non-zero x component and a non-zero y component.The magnetic memory device of any of claims 10 to 12, wherein a thickness of the spacer layer (34) is configured to cause the first free layer (32) and the second free layer (36) to be in the antiferromagnetic configuration, the thickness being 0.4 nm to 0.8 nm.The magnetic memory device of any of claims 10 to 13, wherein the reference layer structure (50) comprises a reference layer adjacent to the barrier layer (40), a pinned layer, and a second spacer layer disposed between the reference layer and the pinned layer, wherein the reference layer structure (50) is in an antiferromagnetic configuration.The magnetic storage device of any one of claims 10 to 14, wherein the SHE (10) comprises tungsten, platinum, or tantalum.A method comprising: depositing a spin-Hall metal layer (10) over an interlayer dielectric of an interconnect structure; depositing a sequence of layers of a magnetic tunnel junction, MTJ, film stack (100), the depositing comprising: depositing a synthetic antiferromagnetic free layer structure (30) over the spin-Hall metal, depositing a barrier layer (40) over the free layer structure (30), and depositing a reference layer structure (50) over the barrier layer (40); patterning the MTJ film stack (100) into at least one MTJ pillar; and patterning the spin-Hall metal layer (10) into a spin-Hall electrode for each pillar of the at least one MTJ pillar; wherein depositing the synthetic antiferromagnetic free layer (30) comprises: depositing a first layer (32) of magnetic material on the spin hall metal layer (10); depositing a spacer layer (34) on the first layer (32) of magnetic material; and depositing a second layer (36) of magnetic material on the spacer layer (34), the spacer layer (34) having a first thickness, the first thickness causing the first layer (32) of magnetic material and the second layer (36) of magnetic material to be antiferromagnetic; and wherein depositing the first layer (32) of magnetic material comprises depositing the first layer of magnetic material to have a first crystal structure, wherein depositing the second layer (36) of magnetic material comprises depositing the second layer of magnetic material to have a second crystal structure different from the first crystal structure.The method of claim 16, wherein depositing the spin Hall metal layer (10) comprises depositing the spin Hall metal layer to have a first crystal structure, wherein depositing the barrier layer (40) comprises depositing the barrier layer (40) to have a second crystal structure different from the first crystal structure.The method of any of claims 16 to 17, further comprising: providing a current from a first end of the spin Hall electrode to a second end of the spin Hall electrode, the current causing a spin orbit torque in the spin Hall electrode to induce a corresponding spin orbit torque in a free magnetic layer structure (30), the spin orbit torque causing a magnetic moment of the free magnetic layer structure to transition from a first state to a second state, the first state corresponding to a magnetic moment of the free magnetic layer structure that is oblique to a direction of a flow of the current.

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