INTEGRATED CIRCUIT AND AN OPERATING PROCEDURE FOR IT

Abstract

Integrated circuit (10-50), comprising: a control circuit (130) coupled between a first voltage terminal (VSS) and a first node (N1) and designed to generate an initialization voltage at the first node (N1); and a first voltage generation circuit (110) and a second voltage generation circuit (120) coupled to a first capacitive unit (200, M3) at the first node (N1) and coupled to a second capacitive unit (300, M4) at a second node (N2), wherein the first voltage generation circuit (110) is designed to generate a first control signal (CS2) based on a first supply voltage (VDD) from a second voltage terminal (VDD) to the second voltage generation circuit (120) in response to the initialization voltage at the first node (N1), and the second voltage generation circuit (120) is designed to generate, in response to the first control signal (CS2),which is received by the first voltage generation circuit (110), to generate a second control signal (CS1) to the first node (N1) based on a second supply voltage (VSS) that differs from the first supply voltage (VDD) from the first voltage terminal (VSS), wherein the first voltage generation circuit (110) comprises several first transistors (M0, M5, M8) coupled together in series, and the second voltage generation circuit (120) comprises several second transistors (M1, M7, M6) coupled together in series, wherein the control circuit (130) comprises several third transistors (M2, M6, M7, M9, M10) coupled together in series; wherein a number of the several first transistors (M0, M5, M8) differs from a sum of a number of the several second transistors (M1, M7, M6) and a number of the several third transistors (M2, M6, M7, M9, M10).,

Description

BACKGROUNDA decoupling capacitance circuit is designed as a basic component for stabilizing power supply voltages in standard integrated circuit cell circuits operating at high speed. However, as the thickness of the gate oxide layers in transistors of the integrated circuits becomes thinner and thinner, the decoupling capacitance circuit is subject to a higher risk of electrostatic discharge.The documents JP 2007-273 846 A and JP 2 676 807 B2 disclose active decoupling circuits. An active decoupling circuit with a short on-time is known from the publication US 2009 / 0 295 470 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may best be understood from the following detailed description when read with the accompanying figures. It should be appreciated that, in accordance with standard practices in the industry, various elements are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1A is a schematic diagram of a portion of an integrated circuit, in accordance with some embodiments. FIG. 1B is a schematic diagram of a portion of an integrated circuit according to various embodiments. FIG. 2 is a detailed schematic diagram corresponding to the integrated circuit of FIG. 1A, in accordance with some illustrative embodiments not in accordance with the present invention. FIG. 3 is a layout diagram corresponding to the integrated circuit of FIG. 1A, in accordance with some illustrative embodiments not in accordance with the present invention. FIG. 4 is a detailed schematic diagram of an integrated circuit corresponding to the integrated circuit in FIG. 1A, in accordance with various embodiments. FIG. 5A is a layout diagram corresponding to the integrated circuit in FIG. 4, in accordance with some embodiments. FIG. 5B is a layout diagram corresponding to the integrated circuit in FIG. 4, according to various embodiments. FIG. 6 is a detailed schematic diagram of an integrated circuit corresponding to the integrated circuit in FIG. 1A, in accordance with various embodiments. FIG. 7 is a detailed schematic diagram of an integrated circuit corresponding to the integrated circuit in FIG. 1B, in accordance with various illustrative embodiments not in accordance with the invention. FIG. 8 is a layout diagram corresponding to the integrated circuit of FIG. 7, in accordance with some illustrative embodiments not in accordance with the present invention. FIG. 9 is a detailed schematic diagram of an integrated circuit corresponding to the integrated circuit in FIG. 1B, in accordance with various embodiments. FIG. 10A is a layout diagram corresponding to the integrated circuit in FIG. 9, in accordance with some embodiments. FIG. 10B is a layout diagram corresponding to the integrated circuit in FIG. 9, according to various embodiments. FIG. 11 is a flow diagram of a method of operating an integrated circuit, in accordance with some embodiments. FIG. 12 is a block diagram of a system for designing the layout design of the integrated circuit according to some embodiments of the present disclosure. FIG. 13 is a block diagram of an integrated circuit fabrication system and an integrated circuit fabrication flow associated therewith, in accordance with some embodiments.DETAILED DESCRIPTIONAn improved decoupling capacitance circuit and method are provided by claims 1 and 10. The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Hereinafter, concrete examples of the components and arrangements will be described in order to simplify the present disclosure. The formation of a first element over or on a second element in the following description may include, for example, embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that the first and second elements may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which the respective term is used. The use of examples in this specification, including the examples of terms discussed herein, is illustrative only and does not in any way limit the scope and meaning of the disclosure or an exemplary term. Also, the present disclosure is not limited to various embodiments listed in this specification.As used herein, the terms "comprising," "including," "having," "including," "including," and the like are open-ended, i.e., to mean "including, but not limited to.".References throughout this specification to "one (1) embodiment," "one embodiment," or "some embodiments" mean that a / e particular / s feature, structure, implementation, or characteristic described in connection with the embodiment / s is included in at least one embodiment of the present disclosure. Thus, use of the phrases "in one (1) embodiment," or "in one embodiment," or "in some embodiments," at different places throughout the specification does not necessarily always refer to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.Further, spatially relative terms such as "below," "below," "lower," "over," "upper," and the like may be used herein to facilitate the description to describe the relationship of an element or feature to one or more other element(s) or feature(s) as illustrated in the figures. It is intended that the spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may also be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly. As used herein, the phrase "and / or" includes any and all combinations of one or more of the associated listed items.As used herein, terms such as "about", "about", "about" or "substantially" generally refer to any approximate value of a given value or range in which it varies depending on various compartments to which it relates and the scope of which is attributable to the broadest interpretation understood by those skilled in the art to which it relates, so as to encompass all such modifications and similar structures. In some embodiments, this generally means within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate. That is, the terms "about", "about", "about" or "substantially" may be inferred unless expressly stated or denote other approximate values.Reference is now made to FIG. 1A. FIG. 1A is a schematic diagram of a portion of an integrated circuit 10, in accordance with some embodiments. For illustrative purposes, integrated circuit 10 includes a starting circuit 100, a capacitive unit 200, and a capacitive unit 300. As shown in FIG. 1A, the starting circuit 100 is coupled between the capacitive unit 200 and the capacitive unit 300. The capacitive unit 200 and the capacitive unit 300 are coupled to the supply voltage terminal VSS and the supply voltage terminal VDD, respectively. In some embodiments, the supply voltage terminal VVS provides the supply voltage VSS (i.e., referred to as a ground providing a ground voltage) and the supply voltage terminal VDD provides the supply voltage VDD. In some embodiments, the supply voltage VDD has a higher voltage level than the supply voltage VSS.As shown in FIG. 1A, the startup circuit 100 includes a voltage generation circuit 110, a voltage generation circuit 120, and a control circuit 130. The voltage generation circuit 110 and the voltage generation circuit 120 are coupled to the capacitive unit 200 at the node N 1. The voltage generation circuit 110 and the voltage generation circuit 120 are coupled to the capacitive unit 300 at the node N 2. The control circuit 130 is coupled between the capacitive unit 200 and the node N 1. In some embodiments, the voltage generation circuit 110 is coupled to the supply voltage terminal VDD. The voltage generation circuit 120 and the control circuit 130 are coupled to the supply voltage terminal VSS. Alternatively stated, the control circuit 130 is coupled between the supply voltage terminal VSS and the voltage generation circuit 120.In some embodiments, integrated circuit 10 is configured to operate as a decoupling circuit. The control circuit 130, in some embodiments, is particularly configured to generate an initialization voltage at the node N 1. The voltage generation circuit 110 transmits the supply voltage VDD from the supply voltage terminal VDD to the voltage generation circuit 120 in response to the initialization voltage at the node N 1. Thus, the voltage generation circuit 120 transmits the supply voltage VSS to the node N 1 other than the supply voltage VDD in response to the supply voltage VDD from the voltage generation circuit 110. Alternatively stated, the voltage level of the node N 1 is pulled down from the initialization voltage to the supply voltage VSS by the voltage generation circuit 120. In some embodiments, the voltage generation circuit 120 is a pull-down circuit.In addition, as shown in FIG. 1A, the startup circuit 100 is configured to output the voltage level of the node N 1 to the capacitive unit 200 as the control signal CS 1 and output the voltage level of the node N 2 to the capacitive unit 300 as the control signal CS 2. The capacitive unit 200 and the capacitive unit 300 receive the control signal CS 1 and CS 2 from the startup circuit 100 to operate separately. As mentioned above, when the voltage generation circuit 110 pulls up the voltage level of the node N 2 to the supply voltage VDD and the voltage generation circuit 120 pulls down the voltage level of the node N 1 to the supply voltage VSS, there is a significant voltage difference between two terminals of the capacitive unit 200 and the capacitive unit 300, respectively. Accordingly, the capacitive unit 200 and the capacitive unit 300 have high capacitance values. The details of the operations of the integrated circuit 10 are discussed in the following sections.As mentioned above, in some embodiments, the voltage generation circuit 110 is further configured to generate the control signal CS 2 to the voltage generation circuit 120 based on the supply voltage VDD in response to the initialization voltage generated by the control circuit 130. The voltage generation circuit 120 is configured to generate the control signal CS 1 to the node N 1 based on the supply voltage VSS in response to the control signal CS 2 received from the voltage generation circuit 110.Reference is now made to FIG. 1B. FIG. 1B is a schematic diagram of a portion of the integrated circuit 10 according to various embodiments. Referring to the embodiments in FIG. 1A, like elements in FIG. 1B are denoted by like reference numerals for better understanding. The specific operations of similar elements already explained in detail in the above sections are omitted here for brevity.In comparison to FIG. 1A, instead of the control circuit 130 being coupled between the node N 1 and the capacitive unit 200, the control circuit 130 in FIG. 1B is coupled between the node N 2 and the capacitive unit 300. In some embodiments, the control circuit 130 is configured to generate the initialization voltage at the node N 2. The voltage generation circuit 120 transfers the supply voltage VSS from the supply voltage terminal VSS to the voltage generation circuit 110 in response to the initialization voltage at the node N 2. Thus, the voltage generation circuit 110 transmits the supply voltage VSS to the node N 2 other than the supply voltage VDD in response to the supply voltage VSS from the voltage generation circuit 120. Alternatively stated, the voltage level of the node N 2 is pulled up from the initialization voltage to the supply voltage VDD by the voltage generation circuit 110. In some embodiments, the voltage generation circuit 110 is a pull-up circuit.Reference is now made to FIG. 2. FIG. 2 is a detailed schematic diagram corresponding to integrated circuit 10 in FIG. 1A, in accordance with some illustrative embodiments not in accordance with the present invention. As shown in FIG. 2, the voltage generation circuit 110 in the startup circuit 100 includes a P-type transistor M 0. The voltage generation circuit 120 includes an N-type transistor M 1. The control circuit 130 includes an N-type transistor M 2. In some embodiments, transistors M 0-M 2 are implemented by metal oxide semiconductor field effect transistors (MOSFETs). A gate of the transistor M 0 is coupled to the node N 1, a source of the transistor M 0 is coupled to the supply voltage VDD, and the source of the transistor M 0 is coupled to the node N 2. A gate of the transistor M 1 is coupled to the node N 2, a source of the transistor M 1 is coupled to the supply voltage VSS, and a drain of the transistor M 1 is coupled to the node N 1. A gate and a source of the transistor M 2 are coupled to the node N 1, and a source of the transistor M 2 is coupled to the supply voltage VSS.The capacitive unit 200 includes a P-type transistor M 3 and the capacitive unit 300 includes an N-type transistor M 4. A gate of the transistor M 3 is coupled to the transistors Mo-M 2 at the node N 1, and a source and a drain of the transistor M 3 and the supply voltage terminal VDD are coupled to each other. A gate of the transistor M 4 and the transistor Mo-M 2 are coupled to the node N 2, and a source and a trin of the transistor M 4 and the supply voltage terminal VSS are coupled to each other.In some embodiments, transistor M 2 operates as a diode when operating. In particular, during an initial phase, the transistor M 2 generates at the node N 1 the initialization voltage equal to a threshold voltage of the transistor M 2. The initialization voltage is a low voltage level relative to the supply voltage VDD. Accordingly, the control signal CS 1 having the voltage level of the node N 1 is referred to as having a logic value 0. Consequently, the transistor M 0 is turned on in response to the control signal CS 1 having the logic value 0 (i.e., the voltage level of the node N 1) and is received at the gate of the transistor M 0, and the voltage level of the node 2 is adjusted based on the supply voltage VDD. Accordingly, the voltage level of the node N 2 is the supply voltage VDD, and the control signal CS 2 having the voltage level of the node N 2 may be referred to as having a logic value 1. The transistor M 1 is turned on in response to the control signal CS 2 having the logic value 1 (i.e., the voltage level of the node 2) received at the gate of the transistor M 1, and the voltage level of the node N 1 is equalized based on the supply voltage VSS. Accordingly, the voltage level of the node N 1 is pulled down from the initialization voltage equal to the threshold voltage of the transistor M 2 to the supply voltage VSS. In some embodiments, the supply voltage terminal VSS is a ground terminal, and the voltage level of the node N 1 is the voltage level of the ground.Based on the above discussion, transistor M3 is turned on when control signal CS1 is logic 1. When the control signal CS2 is logic 1, the transistor M4 is turned on. Meanwhile, because the voltage generation circuit 110 and the voltage generation circuit 120 provide stable voltages to the nodes N 1 and N 2, the transistor M 3 and the transistor M 4 have terminal voltages, occupy little area, and are decoupling capacitors having high capacitance.As shown in FIG. 2, in some embodiments, the integrated circuit 10 is in an ESD positive-to-VSS mode (i.e., ESD PS mode), and an ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS is discharged through three electrostatic discharge paths P 1-P 3.In particular, the control circuit 130 including the transistor M 2 and the capacitive unit 200 including the transistor M 3 are configured as the electrostatic discharge path P 1. A first part of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS flows from the drain and the source of the capacitive unit 200 through its gate (i.e., referred to as the gate oxide layer), the node N 1, the drain, and the source of the transistor M 2 to the supply voltage terminal VSS.Moreover, the voltage generation circuit 120 including the transistor M 1 and the capacitive unit 200 including the transistor M 3 are configured as the electrostatic discharge path P 2. A second part of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS flows from the drain and the source of the capacitive unit 200 to the supply voltage terminal VSS through its gate (i.e., referred to as the gate oxide layer), the node N 1, the drain, and the source of the transistor M 1.Moreover, the voltage generation circuit 110 including the transistor M 0 and the capacitive unit 300 including the transistor M 4 are configured as the electrostatic discharge path P 3. A third part of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS flows from the drain and the source of the transistor M 0, through the gate (i.e., referred to as the gate oxide layer) of the capacitive unit 300 and the drain and the source of the capacitive unit 300 to the supply voltage terminal VSS.In some approaches, gates of elements similar to capacitive units 200 and 300 are directly coupled in a decoupling circuit. As a gate oxide film tends to become thinner and thinner, a breakdown voltage of a transistor made up of a capacitive unit decreases. Therefore, in these approaches, the decoupling circuit tends to be sensitive to and / or degraded by the ESD current. In contrast, with the configurations in FIGS. 1A-2, the gates of the capacitive units 200 and 300 are first coupled to the startup circuit 100 that includes the nodes N 1 and N 2 of an internal network. Accordingly, the gate oxide film is prevented from being degraded. Meanwhile, the ESD protection capability of the integrated circuit is improved because the electrostatic discharge paths are comprised of the voltage generation circuits 110- 120 and the control circuit 130. In some embodiments of the present disclosure, the breakdown voltage increases overall by about 30% to about 50%.In further comparison, gate voltages of the elements, similar to capacitive units 200 and 300, are indeterminate in some approaches and are slowly charged by leakage currents in a corresponding network. In such arrangements, it takes a certain amount of time to initialize the circuit. Compared to the present disclosure, voltage generation circuits 110- 120 respond quickly by the determined initialization voltage (i.e., a threshold voltage) provided by control circuit 130, and generate voltages (having determined logic states) at nodes N 1-N 2. Accordingly, compared to some approaches in one of the embodiments of the present disclosure, the circuit acts faster than one in some approaches and no additional charging time is required. The speed of starting the integrated circuit in one of the embodiments of the present disclosure is about 20% faster than that of some approaches.Additionally, in some other approaches, the circuit may use only P-type transistors as capacitive devices and additional circuitry is needed to use N-type transistors as capacitive devices. At the same time, the gate voltages of the elements, similar to capacitive units 200 and 300, are indeterminate and, accordingly, a significant area is needed to increase the capacitive values of the capacitive units in some approaches. Therefore, the integrated circuit suffers a loss of area. However, the configurations of the present disclosure include P-type transistors and N-type transistors for capacitive devices, and constant gate voltages are provided for the capacitive devices. Compared to some approaches, the present disclosure provides higher capacitance values on a smaller area.The configurations in FIGS. 1A-2 are for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, the integrated circuit 10 is, for example, an ESD negative-to-VDD (ESD ND) mode, wherein the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS is also discharged in the above-mentioned electrostatic discharge path P 1-P 3. The flow direction of the ESD current in the ESD ND mode is opposite to that in the PS mode, while other configurations are similar. Accordingly, repetitive descriptions are omitted herein.Reference is now made to FIG. 3. FIG. 3 is a layout diagram corresponding to integrated circuit 10 in FIG. 1A, in accordance with some illustrative embodiments not in accordance with the present invention. Referring to the embodiments of FIGS. 1A-2, like elements in FIG. 3 are designated with like reference numerals for ease of understanding.As shown in FIG. 3, integrated circuit 10 includes active regions (i.e., oxide device) 301- 307, gates (i.e., poly) 401- 409, conductive segments (i.e., metal on diffusion; MD) 501- 507, conductive traces (i.e., metal zero layer; M0) 601- 604, and vias VD1-VD14, VG1-VG5. In some embodiments, active regions 301- 307 are disposed in a first layer, gates 401- 409, and conductive segments 501- 507 are disposed in a second layer over the first layer. The conductive traces 601- 604 are arranged in a third layer over the second layer. The vias VD 1-VD 14 are disposed between the first layer and the second layer or between the second layer and the third layer. The vias VG1-VG5 are disposed between the second layer and the third layer.In some embodiments, gate 402 corresponds to the gate of transistor M 3, conductive segment 501 corresponds to the drain / source of transistor M 3, and conductive segment 502 corresponds to the source / drain of transistor M 3 and the source of transistor M 0. Gate 403 corresponds to the gate of transistor M 0, conductive segment 503 corresponds to the drain of transistor M 0. Gate 406 corresponds to the gate of transistor M 4, conductive segment 504 corresponds to the drain / source of transistor M 4, and conductive segment 505 corresponds to the source / drain of transistor M 4 and the source of transistor M 1. Gate 407 corresponds to the gate of transistor M1, conductive segment 506 corresponds to the drain of transistor M1 and the drain of transistor M2. Gate 408 corresponds to the gate of transistor M 2, conductive segment 507 corresponds to the source of transistor M 2. In some embodiments, the gates 401, 404, 405 and 409 are configured as dummy gates, where "dummy gate" refers in some embodiments to not being electrically connected as the gate for MOS devices and not having a function in the circuit.For illustrative purposes, the active regions 301- 307 in FIG. 3 extend in the x-direction. In some embodiments, the active regions 301- 303 are included in an active region disposed in an N-type well (NW) in which the N-type is disposed on a substrate (not shown). The active regions 304- 307 are disposed on the substrate or in another active region disposed in a P-type well.The gates 401-409 extend in the y direction. The gates 401- 404 are separated from each other in the x direction and the gates 405- 409 are separated from each other in the x direction. As shown in FIG. 3, the gate 402 is disposed between the active regions 301 and 302. The gate 403 is disposed between the active regions 302 and 303. Gate 406 is disposed between active regions 304 and 305. Gate 407 is disposed between active region 305 and 306. Gate 408 is disposed between active regions 306 and 307. In some embodiments, gates 401- 404 in a layout diagram cross the active area including active areas 301- 303, and gates 405- 409 in the layout diagram cross the active area including active areas 304- 307.The conductive segments 501- 507 extend in the y-direction. Illustratively, conductive segment 501 crosses active region 301, conductive segment 502 crosses active region 302, conductive segment 503 crosses active region 303, conductive segment 504 crosses active region 304, conductive segment 505 crosses active region 305, conductive segment 506 crosses active region 306, and conductive segment 507 crosses active region 307.The conductor tracks 601- 604 extend in the x direction and are separated from one another in the y direction. In some embodiments, the conductive traces 601 and 602 are configured to transfer the supply voltages VDD and VSS, respectively, to the integrated circuit 10. The conductive path 603 corresponds to the node N 1. The conductive path 604 corresponds to the node N 2.In terms of the connection relationship, the active region 301 is coupled to the conductive segment 501 via the via VD 5, and the conductive segment 501 is coupled to the conductive path 601 via the via VD 6 to receive the supply voltage VDD. Similarly, active region 302 is coupled to conductive segment 502 via via VD 3 and conductive segment 502 is coupled to conductive trace 601 via via VD 4 to receive supply voltage VDD. Gate 402 is coupled to trace 603 via via VG2. As mentioned above, the drain and source of transistor M 3 and the drain of transistor M 0 are coupled to supply voltage terminal VDD, and the gate of transistor M 3 is coupled to node N 1.Gate 403 is coupled to trace 603 via via VG 1. Active region 303 is coupled to conductive segment 503 via via VD 1, and conductive segment 503 is coupled to conductive trace 604 via via VD 2. As mentioned above, the drain of transistor M0 is coupled to node N2 and the gate of transistor M0 is coupled to node N1.Active region 304 is coupled to conductive segment 504 via via via VD 13 and conductive segment 504 is coupled to trace 602 via via VD 14 to receive supply voltage VSS. Similarly, active region 305 is coupled to conductive segment 505 via via via VD 11, and conductive segment 505 is coupled to conductive trace 602 via via via VD 12 to receive supply voltage VSS. Gate 406 is coupled to trace 604 via via VG5. As mentioned above, the drain and source of transistor M 4 and the source of transistor M 1 are coupled to supply voltage terminal VSS, and the gate of transistor M 4 is coupled to node N 2.Gate 407 is coupled to trace 604 via via VG4. Active region 306 is coupled to conductive segment 506 via via via VD 8 and conductive segment 506 is coupled to conductive trace 603 via via VD 7. As mentioned above, the source of transistor M1 is coupled to node N1 and the gate of transistor M1 is coupled to node N2.Gate 408 is coupled to trace 603 via via VG 3. Active region 307 is coupled to conductive segment 507 via via VD 9 and conductive segment 507 is coupled to trace 602 via via VD 10. As mentioned above, the gate of transistor M 2 is coupled to node N 1 and the gate of transistor M 2 is coupled to supply voltage terminal VSS.In some embodiments, a portion of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS is discharged through the semiconductor structure of the transistors M 1-M 3 and the conductive traces 603. In some alternative embodiments, another portion of the ESD current is discharged through transistors M 0, M 4 and conductive trace 604.The configurations in FIG. 3 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, according to the actual requirement of ESD protection, for example, at least two of the transistors Mo-M4 do not share active regions.Reference is now made to FIG. 4. FIG. 4 is a detailed schematic diagram of an integrated circuit 20 corresponding to the integrated circuit 10 in FIG. 1A, in accordance with various embodiments. In some embodiments, integrated circuit 20 is configured with respect to, for example, integrated circuit 10. Referring to the embodiments of FIGS. 1A-3, like elements in FIG. 4 are designated with like reference numerals for ease of understanding.In comparison with FIG. 2, the voltage generation circuit 110, the voltage generation circuit 120, and the control circuit 130 in the integrated circuit 20 further each include a plurality of transistors coupled in series. The voltage generation circuit 110 further includes, in particular, a P-type transistor M 5 coupled in series with the transistor M 0. The voltage generation circuit 120 further includes an N-type transistor M 7 coupled in series with the transistor M 1. The control circuit 130 further includes an N-type transistor M 6 coupled in series with the transistor M 2.As shown in FIG. 4, a gate of the transistor M 5 and a gate of the transistor M 0 are coupled to the node N 1. In comparison with FIG. 2, instead of the source of the transistor M 0 being directly coupled to the supply voltage terminal VDD, the source of the transistor M 0 in FIG. 4 is coupled to the drain of the transistor M 5, and the source of the transistor M 5 is coupled to the supply voltage terminal VDD. Similarly, the gate of transistor M 6 and the gate of transistor M 1 are coupled to node N 2. In comparison with FIG. 2, instead of the source of the transistor M 1 being directly coupled to the supply voltage terminal VSS, the source of the transistor M 1 in FIG. 4 is coupled to the drain of the transistor M 6 and the source of the transistor M 6 is coupled to the supply voltage terminal VSS. In addition, the gate of transistor M 7 and the gate of transistor M 2 are coupled to node N 1. In comparison with FIG. 2, instead of the source of the transistor M 2 being directly coupled to the supply voltage terminal VSS, the source of the transistor M 2 in FIG. 4 is coupled to the drain of the transistor M 7, and the source of the transistor M 7 is coupled to the supply voltage terminal VSS.In some embodiments, voltage generation circuit 110, voltage generation circuit 120, and control circuit 130 form a multi-stage circuit by including multiple transistors to meet the requirements for ESD protection capacitance during operation of integrated circuit 20. In various embodiments, a breakdown voltage of the integrated circuit 20 increases by 1.0 V in the respective configurations of the voltage generation circuit 110 and the voltage generation circuit 120 including the two-stage transistor circuit shown in FIG. 4.The configurations in FIG. 4 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. For example, in some embodiments, voltage generation circuit 110, voltage generation circuit 120, and control circuit 130 of integrated circuit 20 each include more than two transistors coupled in series with one another.Reference is now made to FIG. 5A. FIG. 5A is a layout diagram corresponding to the integrated circuit 20 in FIG. 4, in accordance with some embodiments. Referring to the embodiments of FIGS. 1A-4, like elements in FIG. 5A are designated with like reference numerals for ease of understanding.In comparison to FIG. 3, integrated circuit 20 further includes active regions 308- 311, gates 410- 413, conductive segment 510, and vias VD 15- VD 16. The active regions 308- 311 are configured with respect to the active region 303, for example. The gates 410- 413 are configured with respect to the gate 403, for example. In some embodiments, the gate 413 is configured as a dummy gate. The conductive segment 510 is configured with respect to the conductive segment 505, for example. Vias VD 15-VD 16 are configured with respect to via VD 14, for example.In some embodiments, active region 302 corresponds to the source of transistor M 5, gate 410 corresponds to the gate of transistor M 5, and active region 308 corresponds to the drain of transistor M 5 and the source of transistor M 0. Gate 410 is coupled to trace 603 through via VG6. Accordingly, the gate of transistor M 5 is coupled to node N 1, the source of transistor M 5 is coupled to supply voltage terminal VDD, and the drain of transistor M 5 is coupled to the gate of transistor M 0.The active region 305 corresponds to the source of the transistor M 6, the gate 411 corresponds to the source of the transistor M 6, and the active region 309 corresponds to the gate of the transistor M 6 and the drain of the transistor M 1. Gate 411 is coupled to trace 604 via via via VG7. Accordingly, the gate of transistor M 6 is coupled to node N 2, the source of transistor M 6 is coupled to supply voltage terminal VSS, and the drain of transistor M 6 is coupled to the gate of transistor M 1.The active region 311 corresponds to the source of the transistor M 7, the gate 412 corresponds to the gate of the transistor M 7, and the active region 310 corresponds to the drain of the transistor M 7 and the source of the transistor M 2. Gate 412 is coupled to trace 603 via via VG8. Active region 311 is coupled to conductive segment 510 via via via VD 13 and conductive segment 510 is coupled to conductive trace 602 via via VD 16. Accordingly, the gate of transistor M 7 is coupled to node N 1, the source of transistor M 7 is coupled to supply voltage terminal VSS, and the drain of transistor M 7 is coupled to the source of transistor M 2.Reference is now made to FIG. 5B. FIG. 5B is a layout diagram corresponding to the integrated circuit 20 in FIG. 4, in accordance with various embodiments. Referring to the embodiments in FIGS. 1A-5A, like elements in FIG. 5B are designated with like reference numerals for ease of understanding.Compared to FIG. 5A, with respect to transistors sharing active regions, a part of the active regions of the transistors in FIG. 5B are separated from each other. As shown in FIG. 5B, integrated circuit 20 further includes active regions 308 a- 308 b, 309 a- 309 b, 310 a- 310 b, gates 414- 419, conductive segments 511- 513, and vias VD 17- 22. In some embodiments, the active regions 308 a- 308 bcorrespond to a first portion and a second portion of the active region 308 in FIG. 5A. The active regions 309 a- 309 bcorresponds to a first portion and a second portion of the active region 309 in FIG. 5A. The active regions 310 a- 310 bcorresponds to a first portion and a second portion of the active region 310 in FIG. 5A. The gates 414-419 are configured, for example, with respect to the gate 413. In some embodiments, the gates 414- 419 are dummy gates. The conductive segments 511- 513 are configured, for example, with respect to the conductive segment 503. Vias VD 17-VD 22 are configured with respect to via VD 1, for example.In some embodiments, gates 414-415 are not electrically connected to conductive segment 511. The gates 416-417 are not electrically connected to the conductive segment 512. The gates 418-419 are not electrically connected to the conductive segment 513.In some embodiments, active region 308 acorresponds to the drain of transistor M 5 and active region 308 bcorresponds to the source of transistor M 0. In addition, the active regions 308 a- 308 bare separated from each other in the x-direction. Alternatively stated, transistors M 0 and M 5 do not share the active region and may be referred to as separate active region (separate OD) structures. In some embodiments, the ESD resistance performance of integrated circuit 20 is improved by about 20%. In various embodiments, the occupied area of the separate active regions and the ESD resistance performance are comprehensively taken into account in the design of the integrated circuit 20.Similarly, active region 309a corresponds to the drain of transistor M6 and active region 309b corresponds to the source of transistor M1. The active regions 309 a- 309 bare separated from each other in the x direction. Alternatively stated, transistors M1 and M6 do not share the active region.The active region 310 acorresponds to the drain of the transistor M 7 and the active region 310 bcorresponds to the source of the transistor M 2. The active regions 310 a- 310 bare separated from each other in the x direction. Alternatively stated, transistors M2 and M7 do not share the active region.The configurations in FIGS. 5A-5B are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, the structure design of the separate active regions is adjusted for all active regions in integrated circuit 20, for example.Reference is now made to FIG. 6. FIG. 6 is a detailed schematic diagram of an integrated circuit 30 corresponding to the integrated circuit 10 in FIG. 1A, in accordance with various embodiments. Referring to the embodiments of FIGS. 1A-5B, like elements in FIG. 6 are designated with like reference numerals for ease of understanding.In comparison to FIG. 4, the integrated circuit 30 further includes a P-type transistor M 8. A drain of the transistor M 8 is coupled to the source of the transistor M 5, a source of the transistor M 8 is coupled to the supply voltage terminal VDD, and the gate of the transistor M 8 is coupled to the gates of the transistors M 5 and M 0 at the node N 1.In some embodiments, a number of P-type transistors in the voltage generation circuit 110 is different from a number of N-type transistors in the voltage generation circuit 120 and a number of N-type transistors in the control circuit 130. As shown in FIG. 6, the voltage generation circuit 110 includes three P-type transistors, and the voltage generation circuit 120 and the control circuit 130 each include two N-type transistors.As mentioned above, the number of P-type transistors in the voltage generation circuit 110 is different from a sum of the number of N-type transistors in the voltage generation circuit 120 and the number of N-type transistors in the control circuit 130. As shown in the embodiments of FIG. 6, the number of N-type transistors in the voltage generation circuit 120 and the control circuit 130 is larger than the number of P-type transistors in the voltage generation circuit 110. In some embodiments, the tolerance of the N-type transistors to ESD is lower than that of the P-type transistors due to the manufacturing process and physical properties. Therefore, the startup circuit 100 includes fewer P-type transistors and also meets the ESD performance requirements of the integrated circuit 30.The configurations in FIG. 6 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, voltage generation circuit 110 and voltage generation circuit 120 of integrated circuit 30 include, for example, the same set of transistors, for example three N-type transistors.Reference is now made to FIG. 7. FIG. 7 is a detailed schematic diagram of an integrated circuit 40 corresponding to the integrated circuit 10 in FIG. 1B, in accordance with various illustrative embodiments not in accordance with the present invention. Referring to the embodiments of FIGS. 1A-6, like elements in FIG. 7 are designated with like reference numerals for ease of understanding.As shown in FIG. 7, the control circuit 130 includes a P-type transistor M 9. A gate and a drain of the transistor M 9 are coupled to the node N 2. The source of transistor M 9 is coupled to supply voltage terminal VDD.In comparison to FIG. 2, instead of the control circuit 130 being configured to provide the initialization voltage at node N 1, in the embodiments of FIG. 7, the control circuit 130 is configured to provide the initialization voltage at node N 2. In some embodiments, transistor M 9 operates as a diode when operating. In particular, the transistor M 9 generates the initialization voltage at the node N 2 in the initialization phase, the initialization voltage being associated with a threshold voltage (i.e. Vth) of the transistor M 9 and the supply voltage VDD, the threshold voltage of the transistor M 9 being subtracted from the supply voltage VDD (VDD-Vth). The initialization voltage is a high voltage level relative to the supply voltage VSS. Accordingly, the control signal CS 2 having the voltage level of the node N 2 is referred to as having the logic value 1. Consequently, the transistor M 1 is turned on in response to the control signal CS 2 having the logic value 1 (i.e., the voltage level of the node N 2) and is received at the gate of the transistor M 1, and the voltage level of the node N 1 is adjusted based on the supply voltage VSS. Accordingly, the voltage level of the node N 1 is the supply voltage VSS, and the control signal CS 1 having the voltage level of the node N 1 may be referred to as having the logic value 0. The transistor M 0 is turned on in response to the control signal CS 1 having the logic value 0 (i.e., the voltage level of the node N 1) and is received at the gate of the transistor M 0, and the voltage level of the node N 2 is equalized based on the supply voltage VDD. Accordingly, the voltage level of the node N 2 is pulled up from the initialization voltage equal to the voltage VDD-Vth to the supply voltage VDD. The configurations of the integrated circuit 40 in FIG. 7 are similar to the integrated circuit 10. Thus, repetitive descriptions are omitted herein.In addition, the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS is further drained through the electrostatic discharge path P 4. Specifically, the control circuit 130 including the transistor M 9 and the capacitive unit 300 including the transistor M 4 are configured as the electrostatic discharge path P 4. A part of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS flows from the supply voltage terminal VDD to the gate (referred to as the gate oxide film) of the capacitive unit 300 through the source and drain of the transistor M 9 and the node N 2, and further flows to the supply voltage terminal VSS through the source and drain of the capacitive unit 300.The configurations in FIG. 7 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, voltage generation circuit 120 includes, for example, multiple N-type transistors, for example, more than two N-type transistors.Reference is now made to FIG. 8. FIG. 8 is a layout diagram corresponding to integrated circuit 40 in FIG. 7, in accordance with some illustrative embodiments not in accordance with the present invention. Referring to the embodiments of Figs. 1A-7, like elements in Fig. 8 are designated by like reference numerals for ease of understanding.In comparison to FIG. 3, rather than including relevant structures corresponding to transistor M 2, integrated circuit 40 includes active region 312, gate 420, conductive segment 514, and vias VD 21-VD 22. The active region 312 is configured with respect to the active region 303, for example. Gate 420 is configured with respect to gate 413, for example. In some embodiments, gate 420 is a dummy gate. The conductive segment 514 is configured with respect to the conductive segment 502, for example. Vias VD 21-VD 22 are configured with respect to via VD 4, for example.In some embodiments, active region 303 corresponds to the gate of transistor M 0 and the drain of transistor M 9, gate 404 corresponds to the gate of transistor M 9, and active region 312 corresponds to the source of transistor M 9. Gate 404 is coupled to trace 604 via via VG9. Active region 312 is coupled to conductive segment 514 via via VD21, and conductive segment 514 is coupled to conductive trace 601 via via VD22. Accordingly, the gate and drain of the transistor M 9 are coupled to the node N 2, and the source of the transistor M 9 is coupled to the supply voltage terminal VDD.In some embodiments, a portion of the ESD current between the supply voltage terminal VDD and the supply voltage terminal VSS is discharged through the semiconductor structure of the transistors M 0, M 4, M 9 and the conductive trace 604. In various embodiments, another portion of the ESD current is discharged through transistors M 1, M 3 and conductive trace 603.The configurations in FIG. 8 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. In some embodiments, integrated circuit 40 in FIG. 8 includes, for example, structures of separate active regions.Reference is now made to FIG. 9. FIG. 9 is a detailed schematic diagram of an integrated circuit corresponding to the integrated circuit in FIG. 1B, in accordance with various embodiments. Referring to the embodiments of Figs. 1A-8, like elements in Fig. 9 are designated by like reference numerals for ease of understanding.In comparison to FIG. 4, instead of the control circuit 130 including a plurality of N-type transistors, the control circuit 130 in FIG. 9 includes a plurality of P-type transistors M 9-M 10 coupled in series. A gate of the transistor M 10 and a gate of the transistor M 9 are coupled to the node N 2, a source of the transistor M 9 is coupled to a drain of the transistor M 10, and a source of the transistor M 10 is coupled to the supply voltage terminal VDD.The configurations in FIG. 9 are given for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. For example, in some embodiments, a number of multiple N-type transistors included in the voltage generation circuit 120 is larger than a sum of a number of P-type transistors included in the voltage generation circuit 110 and a number of P-type transistors included in the control circuit 130.Reference is now made to FIG. 10A. FIG. 10A is a layout diagram corresponding to the integrated circuit 50 in FIG. 9, in accordance with some embodiments. Referring to the embodiments of Figs. 1-9, like elements in Fig. 10A are designated by like reference numerals for ease of understanding.As compared to FIG. 5A, rather than including relevant structures corresponding to transistors M 2 and M 7, integrated circuit 50 includes active region 313, gates 421- 422, conductive segment 515, and vias VD 25-VD 26. The active region 313 is configured with respect to the active region 312, for example. The gates 421- 422 are configured with respect to the gate 404, for example. In some embodiments, the gate 422 is a dummy gate. For example, conductive segment 515 is configured with respect to conductive segment 505. Vias VD 25-VD 26 are configured with respect to via VD 4, for example. Via VG 9 is configured with respect to via VG 8, for example.In some embodiments, the active region 313 corresponds to a source of the transistor M 10, the gate 421 corresponds to a gate of the transistor M 10, and the active region 312 corresponds to a drain of the transistor M 10 and a source of the transistor M 9. Gate 421 is coupled to trace 604 via via VG10. Accordingly, the gate of transistor M 10 is coupled to node N 2, the source of transistor M 10 is coupled to supply voltage terminal VDD, and the drain of transistor M 10 is coupled to the source of transistor M 9.Reference is now made to FIG. 10B. FIG. 10B is a layout diagram corresponding to the integrated circuit 50 in FIG. 9, according to various embodiments. Referring to the embodiments of FIGS. 1A-10A, like elements in FIG. 10B are designated with like reference numerals for ease of understanding.As compared with FIG. 10A, with respect to transistors sharing active regions, a part of the active regions included in the transistors in FIG. 10B is separated from each other. As shown in FIG. 10B, compared to FIG. 5B, integrated circuit 50 further includes active regions 312 a- 312 b, gates 423- 424, conductive segment 516, and vias VD 27- 28. In some embodiments, the active regions 312 a- 312 bcorrespond to a first portion and a second portion of the active region 312 in FIG. 10A. The gates 423- 424 are configured with respect to the gates 414- 415, for example. In some embodiments, the gates 423- 424 are dummy gates. The conductive segment 516 is configured with respect to the conductive segment 512, for example. Vias VD 27-VD 28 are configured with respect to via VD 17, for example.In some embodiments, the gates 423- 424 are not electrically connected to the conductive segment 516.In some embodiments, active region 312a corresponds to the source of transistor M9, and active region 312b corresponds to the drain of transistor M10. In addition, the active regions 312 a- 312 bare separated from each other in the x direction. Alternatively stated, transistors M 9 and M 10 do not share the active regions.The configurations in FIGS. 10A-10B are provided for illustrative purposes. Various implementations are included within the contemplated scope of the present disclosure. For example, in some embodiments, all of the active regions in integrated circuit 50 have a separate active region structure. In various embodiments, transistors M 9-M 10 in integrated circuit 50 comprise a separate active region structure and transistors M 0-M 1 and M 5-M 6 comprise a shared active region structure.Reference is now made to FIG. 11. FIG. 11 is a flow diagram of a method 1100 of operating the integrated circuit 10, 20, 40, or 50, in accordance with some embodiments. It should be appreciated that additional operations may be provided before, during, and after the processes shown in FIG. 11, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable. In the various views and illustrative embodiments, like reference numerals are used to designate like elements. The method 1100 includes operations 1110- 1130 described below with reference to the integrated circuit 10 in FIG. 2.In operation 1110, as shown in FIG. 2, transistor M 2 generates the initialization voltage to turn on transistor M 0, with the gate and drain of transistor M 2 coupled to the gate of transistor M 0 at node N 1. As mentioned above, in some embodiments, the initialization voltage is equal to the threshold voltage of transistor M 2.In operation 1120, as shown in FIG. 2, transistor M 0 adjusts the voltage level of node N 2 according to supply voltage VDD. Transistor M 0 is coupled to transistor M 1 at node N 2.In some embodiments, adjusting the voltage level of node N 2 includes transmitting supply voltage VDD through transistor M 0 to node N 2 to turn on transistor M 1.In operation 1130, as shown in FIG. 2, the turned-on transistor M 1 sets the voltage level of the node N 1 according to the supply voltage VSS different from the supply voltage VDD.In some embodiments, adjusting the voltage level of node N 1 includes transferring supply voltage VSS to node N 1 through transistor M 1, and thus the voltage level of node N 1 is pulled down from the threshold voltage of transistor M 2 to supply voltage VSS. In some embodiments, the supply voltage VSS is a ground voltage.In some embodiments, the method 1100 further includes turning on the transistor M 3 in response to the initialization voltage, and thus the transistor M 3 operates as the decoupling capacitive unit 200. Transistor M 3 is coupled to node N 1.In some embodiments, the method 1100 further comprises conducting the ESD current from the transistor M 3, through the transistor M 2 (i.e. through the electrostatic discharge path P 1), to the supply voltage terminal VSS, which provides the supply voltage VSS.In a similar manner to the embodiments of FIG. 7, in operation 1110, transistor M 9 generates the initialization voltage to turn on transistor M 1, with the gate and drain of transistor M 9 coupled to the gate of transistor M 1 at node N 2. As mentioned above, in some embodiments, the initialization voltage is equal to the supply voltage VDDfrom which the threshold voltage of transistor M 9 is subtracted.In operation 1120, as shown in FIG. 7, transistor M 1 adjusts the voltage level of node N 1 according to supply voltage VSS. Transistor M 1 is coupled to transistor M 0 at node N 1.In some embodiments, adjusting the voltage level of the node N 1 includes transmitting the supply voltage VSS through the transistor M 1 to the node N 1 to turn on the transistor M 0.In operation 1130, as shown in FIG. 7, the turned-on transistor M 0 sets the voltage level of the node N 2 according to the supply voltage VDD different from the supply voltage VSS.In some embodiments, adjusting the voltage level of the node N 2 includes transmitting the supply voltage VDD to the node N 2 through the transistor M 0, and thus the voltage level of the node N 2 is pulled up to the supply voltage VDD.In some embodiments, the method 1100 further includes turning on the transistor M 4 in response to the initialization voltage, and thus the transistor M 4 operates as the decoupling capacitive unit 300. Transistor M 4 is coupled to node N 2.In some embodiments, the method 1100 further comprises conducting the ESD current from the transistor M 4, through the transistor M 9 (i.e. through the electrostatic discharge path P 4) to the supply voltage terminal VDD providing the supply voltage VDD.Reference is now made to FIG. 12. FIG. 12 is a block diagram of an electronic design automation (EDA) system 1200 for designing the integrated layout design, according to some embodiments of the present disclosure. EDA system 1200 is configured to implement one or more operations of method 1100 disclosed in FIG. 11 and is discussed in connection with FIGS. 1A-10B. In some embodiments, EDA system 1200 includes an APR system.In some embodiments, EDA system 1200 is a general purpose computing device that includes a hardware processor 1202 and a non-transitory computer readable storage medium 1204. Storage medium 1204 is encoded, i.e., stores, by, among other things, computer program code(s) 1206, i.e., a set of executable instructions. Execution of the instructions 1206 by hardware processor 1202 represents (at least in part) an EDA tool that implements a portion or all of, for example, the method 1100.Processor 1202 is electrically coupled to computer readable storage medium 1204 via bus 1208. Processor 1202 is also electrically coupled to an I / O interface 1210 and a manufacturing tool 1216 via bus 1208. A network interface 1212 is also electrically connected to processor 1202 via bus 1208. Network interface 1212 is connected to network 1214 such that processor 1202 and computer readable medium 1204 are capable of connecting to external elements via network 1214. The processor 1202 is configured to execute computer program code 1206, encoded in computer readable storage medium 1204, for causing EDA system 1200 to be usable to perform part or all of the recited processes and / or methods. In one or more embodiments, processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.In one or more embodiments, the computer readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). The computer readable storage medium 1204 includes, for example, a semiconductor or solid state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments using optical disks, computer readable storage medium 1204 includes a compact disk read-only memory (CD-ROM), a compact disk read / write memory (CD-R / W), and / or a digital video disk (DVD).In one or more embodiments, storage medium 1204 stores computer program code 1206 configured to cause EDA system 1200 (where such execution represents (at least in part) the EDA tool) to be usable to perform part or all of the recited processes and / or methods. In one or more embodiments, storage medium 1204 also stores information that enables part or all of the recited processes and / or methods to be performed. In one or more embodiments, storage medium 1204 stores IC layout diagram 1220 of standard cells comprising standard cells as disclosed herein, for example, a cell included in integrated circuits 10, 20, 40, and / or 50 discussed above with reference to FIGS. 1A-10B.EDA system 1200 includes I / O interface 1210. I / O interface 1210 is coupled to external circuitry. In one or more embodiments, I / O interface 1210 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or arrow keys for communicating information and commands to processor 1202.EDA system 1200 also includes network interface 1212 coupled to processor 1202. Network interface 1212 enables EDA system 1200 to communicate with network 1214 to which one or more other computer systems are connected. Network interface 1212 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1264. In one or more embodiments, a portion or all of the recited processes and / or methods are implemented in two or more systems 1200.EDA system 1200 also includes manufacturing tool 1216 coupled to processor 1202. The fabrication tool 1216 is configured to fabricate integrated circuits, such as integrated circuits 10, 20, and 40-50 illustrated in FIGS. 1A-10B, in accordance with the design files processed by the processor 1202.EDA system 1200 is configured to receive information through I / O interface 1210. The information received by I / O interface 1210 includes one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1202. The information is transmitted to processor 1202 via bus 1208. EDA system 1200 is configured to receive information related to a UI through I / O interface 1210. The information is stored in computer readable medium 1204 as design specification 1222.In some embodiments, some or all of the recited processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the recited processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the recited processes and / or methods are implemented as a software application used by the EDA system 1200. In some embodiments, a layout diagram including standard cells is generated using a tool, such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage units, for example one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.FIG. 13 is a block diagram of an IC manufacturing system 1300 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, (A) one or more semiconductor masks and / or (B) at least one component is fabricated in a layer of a semiconductor integrated circuit using IC fabrication system 1300.In FIG. 13, IC manufacturing system 1300 includes entities such as a design house 1320, a mask house 1330, and an IC paver / fab ("Fab") 1350 that interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1360. The entities in the IC manufacturing system 1300 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and / or receives services from one or more of the other entities. In some embodiments, two or more of design house 1320, mask house 1330, and IC fab 1350 belong to a single, larger enterprise. In some embodiments, two or more of design house 1320, mask house 1330, and IC fab 1350 coexist in a common facility and share common resources.Design house (or design team) 1320 generates an IC design layout diagram 1322. IC design layout diagram 1322 includes various geometric structures, for example, an IC layout design illustrated in FIGS. 3, 5A-5B, and 8, and 10A-10B and designed for an IC device 1360, for example, integrated circuits 10, 20, 40, and 50 discussed above with reference to FIGS. 1A-10B. The geometric patterns correspond to patterns of the metal, oxide, or semiconductor layers that form the various components of the IC device 1360 to be fabricated. The various layers connect to form various IC features. A portion of the IC design layout diagram 1322 includes, for example, various IC features such as an active region, gate electrode, source and drain, conductive segments or vias of an interlayer connection to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate. Design house 1320 implements a suitable design method for forming IC design layout diagram 1322. The design method includes one or more logic designs, physical design, or placement and routing. IC design layout diagram 1322 is presented in one or more data files containing geometric pattern information. IC design layout diagram 1322 may be expressed in, for example, a GDSII file format or a DFII file format.Mask house 1330 includes data preparation 1332 and mask fabrication 1344. Mask house 1330 uses IC design layout diagram 1322 to fabricate one or more masks 1345 to be used to fabricate the various layers of IC device 1360 in accordance with IC design layout diagram 1322. Mask house 1330 performs mask data editing 1332, where IC design layout diagram 1322 is translated into a representative data file ("RDF"). Mask data preparation 1332 provides the RDF to mask fabrication 1344. Mask fabrication 1344 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1353. The IC design layout diagram 1322 is manipulated by mask data handler 1332 to conform to certain characteristics of the mask writer and / or requirements of the IC fab 1350. In FIG. 13, data preparation 1332 and mask fabrication 1344 are illustrated as separate elements. In some embodiments, data preparation 1332 and mask fabrication 1344 may be collectively referred to as mask data preparation.In some embodiments, data conditioning 1332 includes Optical Proximity Correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as those that may result from diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1322. In some embodiments, data preparation 1332 further includes resolution enhancement techniques (RET) such as off-axis illumination, sub-resolution auxiliary functions, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, Inverse Lithography Technology (ILT) is also used that deals with OPC as an inverse imaging problem.In some embodiments, data preparation 1332 includes a mask rule checker (MRC) that checks the IC design layout diagram 1322 that has undergone processes in the OPC with a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1322 to compensate for restrictions during mask fabrication 1344, which undo some of the modifications made by OPC to meet mask generation rules.In some embodiments, data preparation 1332 includes lithography process checking (LPC) that simulates processing implemented by IC Fab 1350 to fabricate IC device 1360. LPC simulates this processing based on IC design layout diagram 1322 to produce a simulated fabricated device, such as IC device 1360. The processing parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors such as aerial contrast, depth of field ("DOF"), mask defect enhancement factor ("MEEF"), other suitable factors and the like, or combinations thereof. In some embodiments, after a simulated fabricated device is created by LPC, if the simulated device is not sufficiently close in shape to meet design rules, OPC and / or MRC are repeated to further refine IC design layout diagram 1322.It is to be understood that the above description of data preparation 1332 has been simplified for the sake of clarity. In some embodiments, data preparation 1332 includes additional features, such as a logic operation (LOP) for modifying IC design layout diagram 1322 according to manufacturing rules. Moreover, the processes applied to IC design layout diagram 1322 during data preparation 1332 may be performed in a variety of different orders.After data preparation 1332 and during mask fabrication 1344, a mask 1345 or a set of masks 1345 is fabricated based on the modified IC design layout diagram 1322. In some embodiments, mask fabrication 1344 includes performing one or more lithographic exposures based on IC design layout diagram 1322. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (photomask or reticle) 1345 based on the modified IC design layout diagram 1322. Mask 1345 may be formed in various technologies. In some embodiments, mask 1345 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary mask version of mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, mask 1345 is formed using phase shift technology. In a phase shift mask (PSM) version of mask 1345, various features in the structure formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and image quality. In various examples, the phase shift mask may be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication 1344 are used in a variety of processes. Such one or more mask(s) are employed, for example, in an ion implantation process to form various doped regions in semiconductor wafers 1353, an etching process to form various etching regions in semiconductor wafers 1353, and / or other suitable processes.IC Fab 1350 includes wafer fabrication 1352. IC fab 1350 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 1350 is a semiconductor foundry. For example, there may be one fabrication facility for front-end manufacturing a plurality of IC products (front-end-of-line (FEOL) manufacturing), while a second fabrication facility may provide back-end manufacturing for connection and packaging of the IC products (back-end-of-line (BEOL) manufacturing), and a third fabrication facility may provide other services for the foundry store.IC Fab 1350 uses mask(s) 1345 manufactured by mask house 1330 to fabricate IC device 1360. Thus, IC Fab 1350 at least indirectly uses IC design layout diagram 1322 to fabricate IC device 1360. In some embodiments, semiconductor wafer 1353 is fabricated from IC Fab 1350 using mask(s) 1345 to form IC device 1360. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1353 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).As described above, the integrated circuit of the present disclosure includes a starting circuit disposed between the two terminals of the electrostatic discharge path to increase the electric charge dissipation capability of the integrated circuit. Additionally, the integrated circuit also includes a control circuit that provides the initialization voltage to the startup circuit so that the pull-down circuit and the pull-up circuit included in the startup circuit, respectively, can quickly act in response to the initialization circuit. This improves the operating speed of the starting circuit. Moreover, P-type and N-type transistors having the configuration of the present disclosure used as capacitor units in the integrated circuit provide high decoupling capacitance values with a small area.In some embodiments, an integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node and generates an initialization voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitive unit at the first node and coupled to a second capacitive unit at a second node. The first voltage generation circuit generates a first control signal based on a first supply voltage from a second voltage terminal to the second voltage generation circuit in response to the initialization voltage at the first node. The second voltage generation circuit generates, in response to the first control signal received from the first voltage generation circuit, a second control signal to the first node based on a second supply voltage different from the first supply voltage from the first voltage terminal. In some embodiments, the control circuit includes a transistor having a source coupled to the second voltage terminal and a drain and a gate coupled to the first node. In some embodiments, the initialization voltage generated by the control circuit is associated with a threshold voltage of the transistor and the first supply voltage. In some embodiments, the first capacitive unit is coupled between the first node and the second voltage terminal, and the control circuit and the first capacitive unit are configured as an electrostatic discharge path between the first voltage terminal and the second voltage terminal. In some embodiments, the first control signal is associated with a voltage level of the second node and the second control signal is associated with a voltage level of the first node. In some embodiments, the first voltage generation circuit includes a P-type transistor having a gate coupled to the first node and a drain coupled to the second node. The second voltage generation circuit includes an N-type transistor having a gate coupled to the second node and a drain coupled to the first node. The first voltage generation circuit includes a plurality of first transistors coupled in series with each other, and the second voltage generation circuit includes a plurality of second transistors coupled in series with each other. The control circuit includes a plurality of third transistors coupled in series with one another. A number of the first transistors is different from a sum of a number of the second transistors and a number of the third transistors. In some embodiments, the first transistors are P-type and the second transistors and the third transistors are N-type. The number of first transistors is less than the sum of the number of second transistors and the number of third transistors. In some embodiments, the control circuit includes a transistor having a source coupled to the first voltage terminal and a drain and a gate coupled to the first node. When the first voltage terminal is a ground terminal, the initialization voltage is equal to a threshold voltage of the transistor. The second voltage generation circuit pulls down a voltage of the first node to a ground voltage of the ground terminal. In some embodiments, the second voltage generation circuit includes a transistor having a first terminal coupled to the first node, a second terminal coupled to the first voltage terminal, and a control terminal coupled to the second node. The second voltage generation circuit and the first capacitive unit are configured as an electrostatic discharge path for conducting an electrostatic discharge current from the first voltage terminal through the first capacitive unit and the first terminal and the second terminal of the transistor to the second voltage terminal.Also disclosed as an illustrative embodiment not according to the invention is an integrated circuit comprising a first conductive path and a second conductive path extending in a first direction, a first gate, a second gate, and a third active region and a third gate. The first gate is coupled to the first conductive trace and is disposed between a first active region and a second active region coupled to a first voltage terminal. The second gate and the third active region are coupled to the first conductive trace. The second gate is disposed between the third active region and a fourth active region coupled to a second voltage terminal. The third gate is separated from the second gate in the first direction, coupled to the second conductive path, and disposed between the third active region and a fifth active region coupled to the second voltage terminal. The first gate, the first active region, and the second active region are included in a structure that functions as a first transistor. The second gate, the third active region, and the fourth active region are included in a structure that functions as a second transistor. The third gate, the third active region, and the fifth active region are included in a structure that functions as a third transistor. The first to third transistors and the first conductive path discharge a first portion of an electrostatic discharge current between the first voltage terminal and the second voltage terminal. In some embodiments, the first conductive path and the second conductive path are disposed between the first active region and the fifth active region. In some embodiments, the integrated circuit further includes a fourth gate and a fifth gate. The fourth gate is coupled to the first conductive trace and is disposed between the first active region and a sixth active region coupled to the second conductive trace. The fourth gate, the fifth active region, and the sixth active region are included in a structure that functions as a fourth transistor. The fifth gate is coupled to the second conductive trace and is disposed between the fifth active region and a seventh active region coupled to the second voltage terminal. When the fourth transistor is turned on in response to a voltage generated from the first transistor to the first conductive path, the fourth transistor, the second conductive path, the fifth gate, and the fifth and seventh active regions are configured to discharge a second portion of the electrostatic discharge current between the first voltage terminal or the second voltage terminal. In some embodiments, the integrated circuit further includes a fourth gate separated from the second gate in the first direction and coupled to the first conductive trace. The fourth gate is included in a structure that functions as a fourth transistor. The second transistor and the fourth transistor are coupled in series between the first conductive path and the second voltage terminal. In some embodiments, the integrated circuit further includes a sixth active region and a seventh active region coupled to the sixth active region. The sixth active region is included in a structure corresponding to a source of the second transistor, and the seventh active region is included in a structure corresponding to a drain of the fourth transistor. The sixth active region and the seventh active region are separated from each other in the first direction.A method is also disclosed, comprising the operation of: generating, by a plurality of first transistors, an initialization voltage for turning on a plurality of second transistors, a gate and a first terminal of the plurality of first transistors coupled to a gate of the plurality of second transistors at a first node; adjusting, by the plurality of second transistors, a voltage level of a second node according to a first supply voltage, the plurality of second transistors coupled to a plurality of third transistors at the second node; and adjusting, by the plurality of third transistors, a voltage level of the first node according to a second supply voltage different than the first supply voltage. In some embodiments, adjusting the voltage level of the second node includes transmitting, by the at least one second transistor, the first supply voltage to the second node to turn on the at least one third transistor. In some embodiments, adjusting the voltage level of the first node includes pulling the voltage level of the first node from a threshold voltage of the at least one first transistor to the second supply voltage. In some embodiments, the method further comprises turning on, in response to the initialization voltage, a fourth transistor operating as a decoupling capacitive unit, wherein a gate of the fourth transistor is coupled to the first node. In some embodiments, the method further comprises conducting an electrostatic discharge current flowing from the fourth transistor through the at least one first transistor to a voltage terminal providing the second supply voltage.

Claims

An integrated circuit (10-50) comprising: a control circuit (130) coupled between a first voltage terminal (VSS) and a first node (N1) and configured to generate an initialization voltage at the first node (N1); and a first voltage generation circuit (110) and a second voltage generation circuit (120) coupled to a first capacitive unit (200, M3) at the first node (N1) and coupled to a second capacitive unit (300, M4) at a second node (N2), wherein the first voltage generation circuit (110) is configured to:, in response to the initialization voltage at the first node (N1), generating a first control signal (CS2) based on a first supply voltage (VDD) from a second voltage terminal (VDD) to the second voltage generating circuit (120), and the second voltage generating circuit (120) is configured to generate, in response to the first control signal (CS2) received from the first voltage generating circuit (110), a second control signal (CS1) to the first node (N1) based on a second supply voltage (VSS) different from the first supply voltage (VDD) from the first voltage terminal (VSS), wherein the first voltage generating circuit (110) comprises a plurality of first transistors (M0, M5, M8) coupled to each other in series, and the second voltage generation circuit (120) includes a plurality of second transistors (M 1, M 7, M 6) coupled to each other in series, wherein the control circuit (130) includes a plurality of third transistors (M 2, M 6, M 7, M 9, M 10) coupled to each other in series; wherein a number of the plurality of first transistors (M 0, M 5, M 8) is different from a sum of a number of the plurality of second transistors (M 1, M 7, M 6) and a number of the plurality of third transistors (M 2, M 6, M 7, M 9, M 10).The integrated circuit (10-50) of claim 1, wherein the control circuit (130) comprises: a transistor (M2, M6, M7, M9, M10) having a drain and a gate (401-424) coupled to the first node (N1).The integrated circuit (10-50) of claim 2, wherein the initialization voltage generated by the control circuit (130) is associated with a threshold voltage of the transistor (M2, M6, M7, M9, M10) and the first supply voltage (VDD).The integrated circuit (10-50) according to any of the preceding claims, wherein the first capacitive unit (200, M3) is coupled between the first node (N1) and the second voltage terminal (VDD), and the control circuit (130) and the first capacitive unit (200, M3) are arranged as an electrostatic discharge path (P1-3) between the first voltage terminal (VSS) and the second voltage terminal (VDD).The integrated circuit (10-50) of any preceding claim, wherein the first control signal (CS2) is associated with a voltage level of the second node (N2) and the second control signal (CS1) is associated with a voltage level of the first node (N1).The integrated circuit (10-50) of any preceding claim, wherein the first voltage generation circuit (110) comprises a P-type transistor having a gate (401-424) coupled to the first node (N1) and a drain coupled to the second node (N2), and the second voltage generation circuit (120) comprises an N-type transistor having a gate (401-424) coupled to the second node (N2) and a drain coupled to the first node (N1).The integrated circuit (10-50) of any preceding claim, wherein the plurality of first transistors (M0, M5, M8) are P-type and the plurality of second transistors (M1, M7, M6) and the plurality of third transistors are N-type (M2, M6, M7); wherein the number of the plurality of first transistors (M0, M5, M8) is less than the sum of the number of the plurality of second transistors (M1, M7, M6) and the number of the plurality of third transistors (M2, M6, M7).The integrated circuit (10-50) of any preceding claim, wherein the control circuit (130) comprises: a transistor (M2, M6, M7, M9, M10) having a source coupled to the first voltage terminal (VSS), a drain, and a gate (401-424) coupled to the first node (N1), wherein when the first voltage terminal (VSS) is a ground terminal, the initialization voltage is equal to a threshold voltage of the transistor (M2, M6, M7, M9, M10); wherein the second voltage generation circuit (120) is configured to pull down a voltage of the first node (N1) to a ground voltage of the ground terminal.The integrated circuit (10-50) of any preceding claim, wherein the second voltage generation circuit (120) comprises: a transistor (M1, M7, M6) having a first terminal, a second terminal coupled to the first voltage terminal (VSS), and a control terminal coupled to the second node (N2); wherein the second voltage generation circuit (120) and the first capacitive unit (200, M3) are configured as an electrostatic discharge path (P1-3) to conduct an electrostatic discharge current from the first voltage terminal (VSS), through the first capacitive unit (200, M3), and the first terminal and the second terminal of the transistor (M1, M7, M6) to the second voltage terminal (VDD).A method comprising: generating, by a plurality of series-coupled first transistors (M2, M6, M7, M9, M10), an initialization voltage for turning on a plurality of series-coupled second transistors (M0, M5, M8), wherein a gate (401-424) and a first terminal of the plurality of first transistors (M2, M6, M7, M9, M10) are coupled to a gate (401-424) of the plurality of second transistors (M0, M5, M8) at a first node (N1); setting, by the plurality of second transistors (M0, M5, M8), a voltage level of a second node (N2) according to a first supply voltage (VDD), wherein the plurality of second transistors (M0, M5, M8) are coupled to a plurality of third transistors (M1, M7, M6) coupled in series at the second node (N2); and setting, by the plurality of third transistors (M1, M7, M6), a voltage level of the first node (N1) according to a second supply voltage (VSS) different from the first supply voltage (VDD), wherein a number of the plurality of first transistors (M0, M5, M8) is different from a sum of a number of the plurality of second transistors (M1, M7, M6) and a number of the plurality of third transistors (M2, M6, M7, M9, M10).The method of claim 10, wherein adjusting the voltage level of the second node (N2) comprises: transmitting, by the plurality of second transistors (M0, M5, M8), the first supply voltage (VDD) to the second node (N2) to turn on the plurality of third transistors (M1, M7, M6).The method of claim 10 or 11, wherein adjusting the voltage level of the first node (N1) comprises: pulling down the voltage level of the first node (N1) from a threshold voltage of the plurality of first transistors (M2, M6, M7, M9, M10) to the second supply voltage (VSS).The method of any of claims 10 to 12, further comprising: turning on, in response to the initialization voltage, a fourth transistor (M3) operating as a decoupling capacitive unit, wherein a gate (401-424) of the fourth transistor (M3) is coupled to the first node (N1).The method of claim 13, further comprising: directing an electrostatic discharge current flowing from the fourth transistor (M3) through the plurality of first transistors (M2, M6, M7, M9, M10) to a voltage terminal providing the second supply voltage (VSS).

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