Semiconductor structure and method for measuring a breakdown voltage

Abstract

Semiconductor structure (2) for measuring a breakdown voltage of a pn junction, wherein the semiconductor structure (2) comprises: a substrate (4); a sensor element (6) in the substrate (4) comprising an optically active region (8) which includes the pn junction, wherein the sensor element (6) is configured to apply a blocking bias to the pn junction; and an emitter (10) adjacent to the optically active region (8) in the substrate (4), wherein the emitter (10) is separated from the optically active region (8) by a trench insulation (12), and wherein the emitter (10) is configured to provide charge carriers to the optically active region (8) to trigger the breakdown of the pn junction when the blocking bias is equal to or greater than the breakdown voltage.

Description

SPECIALIZATION

[0001] The invention relates to the determination of the breakdown voltage and in particular the determination of the breakdown voltage of a pn junction in a sensor component. BACKGROUND

[0002] Photosensors, such as single-photon avalanche diodes (SPADs), are used in a so-called Geiger mode to count individual photons. In this operating mode, the device is reverse-biased via the breakdown voltage. Accurate determination of the breakdown voltage is crucial for the correct operation of the device.

[0003] Existing methods use external heat or light sources to trigger breakdown in order to measure the breakdown voltage of the component.

[0004] WO 2019 / 020 472 A1 discloses a SPAD device comprising a single-photon avalanche diode and another single-photon avalanche diode integrated in the same device, the breakdown voltages of which are the same or differ by less than 10%. The single-photon avalanche diode is configured to enable triggering or to have a dark count rate higher than that of the other single-photon avalanche diode.

[0005] US 2010 / 0 245 809 A1 discloses an avalanche photodiode and a sensor array comprising an array of the said avalanche photodiodes. SUMMARY

[0006] Aspects of the invention provide semiconductor structures and methods for measuring the breakdown voltage as well as an image sensor according to the attached claims.

[0007] Preferred embodiments are described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a schematic representation of a cross-section of a semiconductor structure according to one embodiment; Fig. Figure 2 shows a schematic representation of a cross-section of part of a semiconductor structure according to one embodiment; Fig. 3a shows a schematic top view of a semiconductor structure without an emitter; Fig. Figure 3b shows a schematic top view of a semiconductor structure with an emitter according to one embodiment; and Fig. Figure 4 shows a flowchart with the steps of a procedure for measuring the breakdown voltage according to one embodiment. DETAILED DESCRIPTION

[0008] Avalanche photodiodes (APDs) operate below their breakdown voltage, while single-photon avalanche diodes (SPADs) operate above their breakdown voltage. In both cases, the breakdown voltage should be accurately determined for optimal device operation. The breakdown voltage of APDs and SPADs can be determined by triggering breakdown while simultaneously measuring the bias voltage. A fundamental condition for avalanche breakdown is the presence of at least one carrier in the avalanche junction to initiate the breakdown. In some applications, particularly in dark or dimly lit environments, this condition may not be reliably met, and the avalanche may not be triggered quickly enough. If charge carriers are lacking when the breakdown voltage is reached, breakdown may be delayed, resulting in an artificially high breakdown voltage being measured.If the incorrect value for the breakdown voltage is used, the wrong bias voltage may be applied to the sensor component, which can disrupt the functionality of the component and / or reduce its performance.

[0009] To overcome this problem, additional charge carriers can be provided at the avalanche transition by thermal charge carrier generation or by illuminating the sensor. If heating or illumination is not possible, the holding time of the measurement for a charge carrier to trigger the breakthrough can also be extended, but this can be detrimental to the clocking behavior.

[0010] Fig. Figure 1 shows a cross-sectional view of a semiconductor structure 2 according to one embodiment. The structure 2 comprises a substrate 4 (which is typically a silicon substrate), a sensor device 6 comprising an optically active region 8 formed in the substrate 4, and a photodiode with a pn junction, wherein the optically active region 8 corresponds to the depletion region around the pn junction, from which charge carriers generated by absorbed photons can be detected. The structure 2 further comprises an emitter 10, which includes a plurality of emitter regions 10a and 10b (two shown) for providing charge carriers to the optically active region 8 to trigger the sensor device 6. For example, if the sensor device 6 is a single-photon avalanche diode (SPAD), the emitter 10 can be biased to generate charge carriers that trigger an avalanche current in the optically active region 8.The emitter 10 is separated from the optically active area 8 by trench insulation (STI) 12. A backside stack 14 is arranged on the substrate 4, comprising metallization and dielectric layers between the metals, and providing connections to the emitters 10a and 10b and to the sensor element 6.

[0011] Each emitter region 10a and 10b can comprise a heavily n-doped region (n++) and a heavily p-doped region (p++), wherein the n++ region is preferably self-aligned relative to the p++ region, which can protect the device from process deviations. The emitter 10 can preferably be configured to operate at a relatively low reverse bias voltage in the range of 1 V to 5 V. The sensor device can comprise a peripheral region surrounding the optically active region, in which the device's circuitry can be arranged. In preferred embodiments, the emitter 10 is arranged in the peripheral region, which can reduce the device's area requirement and increase the device density. That is, in preferred embodiments, the emitter 10 is structured and positioned such that the area requirement of the semiconductor structure 2 is equal to that of a corresponding semiconductor structure without an emitter.The emitter regions 10a and 10b can be arranged symmetrically around the optically active region 8 and can have an essentially triangular shape (viewed from above), which allows the emitter regions 10a and 10b to be arranged completely within the peripheral area of ​​the sensor element 6.

[0012] Fig. Figure 2 shows a portion of a semiconductor structure 2 according to one embodiment. The structure 2 can be described in Fig. The structure shown in Figure 1 is not intended to be a standard feature; corresponding features in different figures have been given the same reference symbols for clarity and are not meant to restrict these features. The semiconductor structure 2 comprises a sensor device 6 (e.g., a SPAD or APD) that includes an optically active region 8 in a silicon substrate 4. A trench 12 filled with STI material separates the optically active region 8 from an emitter 10. The emitter 10 includes a heavily n-doped region 16 (n++) that is laterally adjacent to and self-aligned with a heavily p-doped region 18 (p++). The n++ region 16 is self-aligned at the edge of the STI 12 (because the doping does not extend through the STI 12, so that an edge of the n++ region 16 is defined by the STI 12). The other side of the n++ area 16 (towards the p++ area 18) is defined by the lacquer mask for n-doping (not shown).To minimize tolerances, the p++ region 18 is positioned below the n++ region 16, such that only the edge of the n-doping mask defines the second edge of the n++ region 16. Therefore, the tolerances of the n++ region 16 relative to the STI 12 are defined by the superposition error and the critical dimension (CD) error of the n-doping mask. If, however, the p-doping had been designed so that the p-doping mask abutted the n-doping mask, additional superposition and critical dimension tolerances of p++ would increase the overall tolerances. The relevant pn transition of emitter 10 is formed at the point where the n++ edge intersects the p++ region 18. By allowing the p++ area 18 to completely overlap the n++ area 16, process tolerances can be minimized and more stable emitter behavior can be provided.

[0013] Both the n++ region 16 and the p++ region 18 are arranged in a p-doped well 20 in the substrate 4. The emitter 10 is configured to provide charge carriers to the optically active region 8 by applying a reverse bias voltage to the emitter 10. For example, the emitter can be configured to operate with a reverse bias voltage of 2.9 V and a current of 1 mA to inject charge carriers into the optically active region 8, thereby triggering a breakdown in the sensor device 6 (if the reverse bias voltage across a pn junction of the device 6 is equal to or greater than the breakdown voltage of the pn junction).

[0014] Fig. 3a and Fig. Figure 3b shows schematic top views of a semiconductor structure 2 without an emitter and of a semiconductor structure 2 according to an embodiment comprising an emitter 10. Both structures 2 have a sensor element 6 with an optically active area 8, which is surrounded by a peripheral area 22 in which the wiring for connection to the optically active area 8 is arranged.

[0015] In Fig. 3b comprises an emitter 10 comprising four emitter regions 10a, 10b, 10c, and 10d, which are arranged symmetrically around the optically active region 8 in the peripheral region 22 of the sensor device 6. The emitter regions 10a, 10b, 10c, and 10d have a triangular shape, so that they are completely contained within the peripheral region 22, thereby reducing the area requirement of the device 6 compared to that of the device 6 in Fig. 3a does not increase. This means that no additional area is occupied by structure 2, and the fill factor of component 2 can remain unchanged. Emitter 10 only needs one additional contact to apply a voltage to emitter 10.

[0016] An image sensor (e.g., a time-of-flight sensor) can comprise a variety of semiconductor structures, as described herein, to form an array of sensor devices (e.g., an array of SPADs). Each semiconductor structure in the variety can be fabricated on the same wafer using the same process steps (usually in a CMOS process).

[0017] Fig. Figure 4 is a flowchart that describes the steps of a method for measuring the breakdown voltage of a pn junction, such as the pn junction in the optically active region of a SPAD. The method includes providing a semiconductor structure comprising a substrate, a sensor element in the substrate encompassing the optically active region containing the pn junction, and an emitter located adjacent to the optically active region in the substrate (step S1). That is, the semiconductor structure (e.g., a structure such as that found in one of the Fig. 1, Fig. 2 or Fig.The pn junction under test (as shown in Figure 3b) is provided in step S1. Step S1 typically involves forming the semiconductor structure in a CMOS process. The procedure then includes applying an initial reverse bias to the pn junction (step S2), applying a second reverse bias to the emitter to cause the emitter to provide charge carriers for the optically active region (step S3), and detecting the breakdown of the pn junction by monitoring a current output by the semiconductor structure (step S4). The procedure further includes determining the breakdown voltage from the initial reverse bias when breakdown is detected (step S5). The reverse bias applied to the pn junction in step S2 can be increased continuously or incrementally until breakdown is detected in step S4.The procedure can then, after determining the breakdown voltage, include deactivating the emitter by removing or reducing the second blocking bias (step S6).

[0018] The emitter can be used for a short time (e.g., < 1 ms) to accurately measure the breakdown voltage; after this time, the emitter can be deactivated and left disconnected from ground. While the emitter is deactivated, the sensor device can operate normally, and the presence of the emitter does not affect the device's performance during normal operation. For example, between breakdown voltage measurements, the emitter can be deactivated and the SPAD or APD can operate normally without any reduction in device performance compared to a comparable SPAD or APD without an emitter. At a later time, the emitter can be reactivated to measure the breakdown voltage again. In this way, any drift in the breakdown voltage can be detected. The measurement process can be performed cyclically, with the emitter being activated at regular intervals for a predetermined duration.

[0019] Embodiments of the invention can provide an improved component and method for reliably measuring the breakdown voltage of a pn junction, e.g., in an avalanche photodiode (APD) or a single-photon avalanche diode (SPAD), without requiring an external heat or light source to trigger the breakdown. An additional pn junction can be formed within the periphery of the sensor component to generate charge carriers by backward biasing the pn junction.

[0020] One advantage of the described embodiments is that they enable precise detection of breakthrough under dark environmental conditions. The emitter is configured to provide charge carriers that support the avalanche mechanism in the sensor element during breakthrough. Furthermore, the detection method can be independent of environmental factors such as temperature, time delay during measurement, and the intensity of light sources.

Claims

[1] Semiconductor structure (2) for measuring a breakdown voltage of a pn junction, wherein the semiconductor structure (2) comprises: a substrate (4); a sensor element (6) in the substrate (4) comprising an optically active region (8) which includes the pn junction, wherein the sensor element (6) is configured to apply a blocking bias to the pn junction; and an emitter (10) adjacent to the optically active region (8) in the substrate (4), wherein the emitter (10) is separated from the optically active region (8) by a trench insulation (12), and wherein the emitter (10) is configured to provide charge carriers to the optically active region (8) to trigger the breakdown of the pn junction when the blocking bias is equal to or greater than the breakdown voltage. [2] Semiconductor structure (2) according to claim 1, wherein the emitter (10) is configured to provide charge carriers when it is reverse biased. [3] Semiconductor structure (2) according to claim 1 or 2, wherein the emitter (10) is configured to be reverse biased in use by a voltage in the range of 1 V to 5 V. [4] Semiconductor structure (2) according to claim 1, 2 or 3, wherein the emitter (10) comprises a heavily n-doped region (16) and a heavily p-doped region (18). [5] Semiconductor structure (2) according to claim 4, wherein the heavily n-doped region (16) is self-adjusting at an edge of the s trench insulation (12). [6] Semiconductor structure (2) according to claim 4 or 5, wherein the heavily n-doped region (16) is self-adjusted relative to the heavily p-doped region (18). [7] Semiconductor structure (2) according to one of the preceding claims, wherein the sensor element (6) further comprises a peripheral area (22) surrounding the optically active area (8) and comprising a circuit connected to the optically active area (8). [8] Semiconductor structure (2) according to claim 7, wherein the emitter (10) is arranged within the peripheral area (22). [9] Semiconductor structure (2) according to claim 7 or 8, wherein the emitter (10) comprises a plurality of emitter regions (10a, 10b, 10c, 10d) arranged in the peripheral region (22). [10] Semiconductor structure (2) according to claim 9, wherein the emitter regions (10a, 10b, 10c, 10d) are arranged symmetrically around the optically active region (8). [11] Semiconductor structure (2) according to claim 9 or 10, wherein the plurality of emitter regions (10a, 10b, 10c, 10d) includes four emitter regions (10a, 10b, 10c, 10d). [12] Semiconductor structure (2) according to claim 9, 10 or 11, wherein each emitter region (10a, 10b, 10c, 10d) has a substantially triangular shape when viewed from above. [13] Image sensor comprising a plurality of semiconductor structures (2) according to any one of claims 1 to 12. [14] Method for measuring a breakdown voltage of a pn junction with a semiconductor structure (2) according to any one of claims 1 to 12. [15] Method for measuring a breakdown voltage of a pn junction, the method comprising: Providing a semiconductor structure (2) comprising a substrate (4), a sensor element (6) in the substrate (4) comprising an optically active region (8) comprising the pn junction, and an emitter (10) adjacent to the optically active region (8) in the substrate (4), wherein the emitter (10) is separated from the optically active region (8) by a trench isolation (12); Applying an initial blocking bias to the pn junction; Applying a second blocking bias to the emitter (10) to cause the emitter (10) to provide charge carriers for the optically active region (8); Determining the breakdown of the pn junction by monitoring a current output by the semiconductor structure (2); and Determining the breakdown voltage from the first blocking bias when the breakdown is detected. [16] The method of claim 15, further comprising: Deactivating the emitter (10) by removing or reducing the second blocking bias; and Activation of the emitter (10) after a period of time in order to determine the breakdown voltage at a later time.

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