Rear signal wiring

Abstract

Semiconductor structure comprising: a first transistor having a first S / D element and a first gate; a second transistor having a second S / D element and a second gate; a multilayer interconnect structure disposed over the first and second transistors; a signal circuit (406) among the first transistor and the second transistor; and a power supply rail (284) under the signal circuitry (406) and electrically isolated from the signal circuitry (406), the signal circuitry (406) electrically connecting one of the first S / D element and the first gate to one of the second S / D element and the second gate, the first transistor further comprising a third S / D element, further comprising: a third via under the first transistor electrically connecting the third S / D element to the power supply rail (284).

Description

BACKGROUND

[0001] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and demanding functions. To meet these demands, there has been a continuing trend in the integrated circuit (IC) industry toward producing lower-cost, higher-performance, and lower-power ICs. To date, these goals have largely been achieved by reducing IC dimensions (e.g., the minimum IC feature size), thereby improving production efficiency and reducing associated costs. However, such scaling has also increased the complexity of IC manufacturing processes. Therefore, implementing continuous advances in IC devices and their performance requires similar advances in IC manufacturing processes and technology.

[0002] For example, in standard cell designs, along with the reduction in IC feature size, the size (or area requirement) of standard cells (such as inverter, AND, OR, and NOR cells) is also being reduced to increase circuit density. Consequently, the area for signal interconnections (such as in Mo, M1, M2 layers, etc.) per standard cell has decreased. This has caused some adverse effects, such as congested routing, increased parasitic capacitance, and so on. Therefore, although existing approaches in semiconductor manufacturing have generally been suitable for their intended purposes, they have not been entirely satisfactory in all respects.

[0003] US 2008 / 0 054 313 A1 discloses device structures having backside contacts extending from a backside of a substrate through the substrate to electrically contact semiconductor devices on the frontside. The substrate preferably also includes one or more alignment structures disposed therein, each of which is sufficiently visible on the backside of the substrate. In this way, lithographic backside alignment can be performed using such alignment structures to form at least one backside contact opening in a patterned resist layer over the backside of the substrate. The formed backside contact opening is lithographically aligned with the frontside semiconductor device and can be etched to form a backside contact via extending from the backside of the substrate to the frontside semiconductor device.Filling the backside contact via with a conductive material results in a conductive backside contact that electrically contacts the front semiconductor device. Further details of this technology are known from US 2018 / 0 323 174 A1.

[0004] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various elements may be arbitrarily exaggerated or reduced for the sake of clarity of explanation. Fig. 1A and Fig. 1B show a flow diagram of a method of forming a semiconductor device with backside signal interconnections and backside power rails according to various aspects of the present disclosure. Fig. 2A shows a perspective view of a portion of a semiconductor device according to some embodiments, and Fig. 2B shows a cross-sectional view of the semiconductor device in Fig. 2A. Fig. 2C shows a plan view of a portion of the semiconductor device in Fig. 2A, and Fig. 2D and Fig. 2E show cross-sectional views of a portion of the semiconductor device of Fig. 2A along the DD line and the EE line respectively in Fig. 2C according to some embodiments. Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 9, Fig. 10, Fig. 11A, Fig. 12, Fig. 13, Fig. 14 and Fig. 15 show perspective views of a portion of the semiconductor device in Fig. 2A according to some embodiments. Fig. 8B and Fig. 11B show a plan view of a portion of the semiconductor device in Fig. 2A according to some embodiments. Fig. 16A, Fig. 16B, Fig. 16C, Fig. 16D and Fig. 16E show schematic layout views of a portion of the semiconductor device in Fig. 2A according to some embodiments. Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D, Fig. 17E, Fig. 17F, Fig. 17G, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 18D, Fig. 18E, Fig. 18F, Fig. 18G and Fig. 18H show perspective views of a portion of the semiconductor device in Fig. 2A according to some embodiments. Fig. 19A shows a schematic view of a portion of the semiconductor device in Fig. 2A according to some embodiments. Fig. 19B and Fig. 19C show layout views of the portion of the semiconductor device in Fig. 19A according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.Still further, when a number or range of numbers is described with "approximately," "about," and the like, the term includes numbers that, according to the knowledge of one skilled in the art with respect to the specific technology disclosed herein, are within certain variations (such as + / - 10% or other variations) of the described number, unless otherwise specified. For example, the term "about 5 nm" may encompass the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0008] This application generally relates to semiconductor structures and manufacturing processes, and more particularly to semiconductor devices with rear-side signal interconnects and rear-side power rails. As discussed above, signal interconnects (or signal routing) have become increasingly congested with the ongoing miniaturization of devices. An object of the present disclosure includes providing signal interconnects on a rear (or back) side of a structure including transistors, in addition to an interconnect structure on a front (or front) side of the structure. The transistors may include gate-all-around (GAA) transistors, FinFET transistors, and / or other types of transistors.The backside signal interconnections can be fabricated between one source / drain element and another source / drain element, between one source / drain element and a gate, and between one gate and another gate. The structure is further provided with backside power supply rails (or power routing paths) beneath the backside signal interconnections, in addition to power supply rails in the frontside interconnect structure. Therefore, the structure is provided with an increased number of signal routing traces and power routing traces for directly connecting to source / drain elements and gates of transistors. Using the present disclosure, building blocks (such as standard cells) of ICs can be made smaller, and the circuit density of ICs can be made higher.The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanying drawings, which illustrate a process for fabricating a GAA device according to some embodiments. A GAA device refers to a device comprising vertically stacked, horizontally aligned, multi-channel transistors, such as nanowire transistors and nanofoil transistors. GAA devices are promising candidates for advancing CMOS to the next stage of the roadmap due to their better gate control capability, lower leakage current, and full compatibility with the FinFET device layout. The present disclosure can thus be used to fabricate FinFET devices having backside signal interconnections and backside power rails.For simplicity, the present disclosure uses ATM devices as an example. One of ordinary skill in the art should recognize that they can readily use the present disclosure as a basis for designing and modifying other processes and structures, such as FinFET devices, to perform the same tasks and / or achieve the same benefits of the embodiments presented herein.

[0009] Fig. 1A and Fig. 1B is a flow diagram of a method 100 for manufacturing a semiconductor device according to various aspects of the present disclosure. Additional processing is contemplated by the present disclosure. Additional operations may be provided for additional embodiments of the method 100 before, during, and after the method 100, and some of the described operations may be relocated, replaced, or eliminated.

[0010] The method 100 is described below in connection with Fig. 2A to Fig. 15, which illustrate various top, cross-sectional, and perspective views of a semiconductor device (or semiconductor structure) 200 at various steps of fabrication according to method 100, according to some embodiments. In some embodiments, device 200 is a portion of an integrated circuit chip, a system on a chip (SoC), or a portion thereof that includes various passive and active microelectronic devices, such asResistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NEFTEs), FinFET, nanofoil FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. Figures 2A through 15 have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to the device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the device 200.

[0011] At operation 102, the procedure 100 ( Fig. 1A) provides a semiconductor structure (or a semiconductor device or device) 200 comprising a substrate 201, a device layer 500 over the front side of the substrate 201, and an interconnect structure (or multilayer interconnect) 600 over the device layer 500. The device layer 500 comprises transistors. Fig. 2A shows a perspective view of a portion of the semiconductor device 200, and Fig. 2B shows a cross-sectional view of a portion of the device 200. The device 200 may include other layers or features described in Fig. 2A are not shown, such as a passivation layer over the interconnect structure 600. The substrate 201 is located on a back side of the device 200 and the interconnect structure 600 is located on a front side of the device 200. In other words, the substrate 201, the device layer 500 and the interconnect structure 600 are arranged one above the other from the back side to the front side of the device 200.

[0012] The substrate 201, in the present embodiment, is a bulk silicon (Si) substrate, such as a silicon wafer. In alternative embodiments, the substrate 201 comprises other semiconductors, such as germanium (Ge), a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), or an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GeAsP), and gallium indium phosphide (GaInP). In some embodiments, the substrate 201 may comprise a silicon on insulator (SOI) substrate, be strained and / or stressed for performance improvement, have epitaxial regions, have doped regions, and / or have other suitable features or layers.

[0013] Device layer 500 includes active semiconductor regions (such as semiconductor fins) and various active devices (such as transistors) built in or on the active semiconductor regions. Device layer 500 may also include passive devices, such as capacitors, resistors, and inductors. Device layer 500 further includes local interconnects, isolation structures, and other structures.

[0014] The interconnect structure 600 is located above the device layer 500 and includes conductors 666 (such as metal lines and vias) embedded in one or more dielectric layers 664. The conductors 666 provide connectivity to the devices in the device layer 500. The conductors 666 may also provide power rails and ground planes for the device 200. The conductors 666 may comprise copper, aluminum, or other suitable materials, and may be formed using a single-damascene process, a dual-damascene process, or other suitable processes. The dielectric layers 664 may comprise silicon nitride, silicon oxynitride, silicon nitride with oxygen (O) or carbon (C) elements, oxide formed from tetraethylorthosilicate (oxide formed from TEOS), undoped silicate glass, or doped silicon oxide, such asBorosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.

[0015] Fig. 2C shows a top view of a portion of the device 200, and Fig. 2D and Fig. 2E show cross-sectional views of a portion of the device 200 along the DD line and the EE line, respectively, in Fig. 2C. The device 200 includes gate stacks 240 that are longitudinally aligned along the "y" direction and active regions (such as semiconductor fins) 204 that are longitudinally aligned along the "x" direction. Fig. The example shown in Figure 2C includes four transistors 202, each at an intersection of the gate stacks 240 and the semiconductor fins 204. As will be discussed, each transistor 202 includes two source / drain (S / D) elements 260 on opposite sides of the respective gate stack 240, and one or more channel layers 215 connecting the two S / D elements and engaging the respective gate stack 240. Fig. 2C, Fig. 2D and Fig. 2E show further details of the device layer 500. In particular, the DD line represents a cut along the longitudinal direction of a semiconductor fin 204 (the "x" direction), and the EE line represents a cut into the source / drain regions of the transistors and is parallel to the longitudinal direction of the gate stacks 240 (the "y" direction).

[0016] With reference to Fig. 2C to 2E, the semiconductor device 200 includes isolation elements 230 (or an isolation structure 230) over the substrate 201, semiconductor fins 204 extending from the substrate 201 and adjacent to the isolation elements 230, and source / drain (S / D) elements 260 over the semiconductor fins 204 in the S / D regions. The semiconductor device 200 further includes one or more channel semiconductor layers (or channel layers) 215 overhanging the semiconductor fins 204 and connecting the S / D elements 260 along the "x" direction, and gate stacks 240 between the S / D elements 260, enclosing each of the channel layers 215.The semiconductor device 200 further includes inner spacers 255 between the S / D elements 260 and the gate stack 240, an outer gate spacer 247 over sidewalls of the gate stack 240 and over the topmost channel layer 215, a contact etch stop layer (CESL) 269 adjacent to the gate spacer 247 and located over the S / D elements 260 and the isolation elements 230, an interlayer dielectric layer (ILD) 270 over the CESL 269, another CESL 269' over the ILD 270, and another ILD 270' over the CESL 269'. Over the gate stacks 240, the semiconductor device 200 further includes a self-aligned cap layer 352. In some implementations (as shown in FIG. Fig. 2D), an adhesive layer 357 may be deposited over the gate stacks 240 to improve adhesion between the gate stacks 240 and the gate vias 359 and to reduce a contact resistance thereof. Above the S / D elements 260, the semiconductor device 200 further includes silicide elements 273, S / D contacts 275, an S / D cap dielectric layer 356, and an S / D contact via 358. In the illustrated embodiment, the S / D cap dielectric layer 356 is disposed over some of the source / drain elements 260, and the S / D contact via 358 is disposed over other source / drain elements 260. The device 200 further includes a semiconductor layer 239 beneath some of the S / D elements 260. In one embodiment, the semiconductor layer 239 comprises a semiconductor material that is different from the semiconductor fin 204 and serves as a placeholder for a backside via formation.In an embodiment where device 200 is a FinFET device, channel layers 215 are combined into one channel layer (a semiconductor fin channel), and internal spacers 255 are omitted. Furthermore, in such a FinFET embodiment, gate stack 240 engages top and sidewalls of the semiconductor fin channel, and in the cross-sectional view of FIG. Fig. 2D, the gate stack 240 would be located only on top of the semiconductor fin channel. The various elements of the semiconductor device 200 are further described below.

[0017] In various embodiments, the semiconductor fins 204 may comprise silicon, silicon germanium, germanium, or another suitable semiconductor, and may be undoped, unintentionally doped, or lightly doped with n- or p-type dopants. The fins 204 may be patterned using any suitable method. For example, the fins 204 may be patterned using one or more photolithographic processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes, thereby enabling structures to be created that have, for example, smaller pitches than otherwise achievable using a single direct photolithographic process.For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used as a masking element to pattern fins 204. For example, the masking element may be used to etch recesses in semiconductor layers above or in substrate 201, thereby leaving fins 204 on substrate 201. The etching process may include a dry etch, a wet etch, reactive ion etching (RIE), and / or other suitable processes. For example, a dry etch process may use an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F6 ), a chlorine-containing gas (e.g. Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), a bromine-containing gas (e.g. HBr and / or CHBr 3 ), and an iodine-containing gas, other suitable gases and / or plasmas, or combinations thereof. For example, a wet etching process may involve etching in diluted hydrofluoric acid (DHF), a potassium hydroxide (KOH) solution, ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ) and / or acetic acid (CH 3 COOH), or in other suitable wet etchants. Numerous other embodiments of methods for forming fins 204 may be suitable.

[0018] The isolation elements 230 may comprise silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material (e.g., comprising silicon, oxygen, nitrogen, carbon, or another suitable isolation component), or combinations thereof. The isolation elements 230 may comprise various structures, such as shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures. In one embodiment, the isolation elements 230 may be formed by filling the trenches between fins 204 with an isolation material (e.g., by using a CVD process or a spin-on-glass process), performing a chemical mechanical polishing (CMP) process to remove excess isolation material and / or planarize a top surface of the isolation material layer, and etching back the isolation material layer to form isolation elements 230.In some embodiments, the isolation elements 230 have a multi-layer structure, such as a silicon nitride layer disposed over a thermal oxide liner layer.

[0019] Semiconductor layer 239 may be deposited using an epitaxial growth process or other suitable processes. In some embodiments, epitaxial growth of semiconductor layers 239 is achieved using a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, another suitable epitaxial growth process, or combinations thereof. Semiconductor layer 239 comprises a semiconductor material that is different from the semiconductor material incorporated in semiconductor fins 204 to achieve etch selectivity during subsequent processing.For example, semiconductor layer 239 and semiconductor fins 204 may comprise different materials, different atomic percentages of constituents, different weight percentages of constituents, and / or other characteristics to achieve a desired etch selectivity during an etch process. In one embodiment, semiconductor fins 204 comprise silicon, and semiconductor layer 239 comprises silicon germanium. In another embodiment, both semiconductor layer 239 and semiconductor fins 204 may comprise silicon germanium, but with a different silicon atomic percentage. The present disclosure contemplates the semiconductor layer 239 and semiconductor fins 204 comprising any combination of semiconductor materials capable of providing a desired etch selectivity, including any of the semiconductor materials described herein.The semiconductor layer 239 serves as a placeholder for backside vias and / or backside insulation.

[0020] The S / D elements 260 comprise epitaxially grown semiconductor materials, such as epitaxially grown silicon, germanium, or silicon germanium. The S / D elements 260 may be formed by any epitaxial process, including chemical vapor deposition (CVD) techniques, molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D elements 260 may be doped with n-type dopants and / or p-type dopants. In some embodiments, the S / D elements 260 for n-type transistors 202 comprise silicon and may be doped with carbon, phosphorus, arsenic, another n-type dopant, or combinations thereof (e.g., by forming epitaxial Si:CS / D elements, epitaxial Si:PS / D elements, or epitaxial Si:C:PS / D elements).In some embodiments, the S / D elements 260 for p-type transistors 202 comprise silicon germanium or germanium and may be doped with boron or another p-type dopant, or combinations thereof (e.g., by forming epitaxial Si:Ge:BS / D elements). The S / D elements 260 may comprise multiple epitaxial semiconductor layers having different levels of dopant density. In some embodiments, annealing processes (e.g., rapid thermal anneal (RTA) and / or laser annealing) are performed to activate dopants in the epitaxial S / D elements 260.

[0021] In embodiments, the channel layers 215 comprise a semiconductor material suitable for transistor channels, such as silicon, silicon germanium, or other semiconductor material(s). The channel layers 215 may, in various embodiments, be in the form of rods, bars, foils, or other shapes. In one embodiment, the channel layers 215 are initially part of a stack of semiconductor layers that alternately comprise layer-by-layer stacked channel layers 215 and other (sacrificial) semiconductor layers. The sacrificial semiconductor layers and the channel layers 215 have different material compositions (such as different semiconductor materials, different atomic percentages of the constituents, and / or different weight percentages of the constituents) to achieve etch selectivity.During a gate replacement process to form the gate stack 240, the sacrificial semiconductor layers are removed, leaving the channel layers 215 suspended over the semiconductor fins 204.

[0022] In some embodiments, the inner spacer layer 255 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacer layer 255 comprises a low-k dielectric material, such as those described herein. The inner spacer layer 255 may be formed using deposition and etch processes. For example, after S / D trenches are etched and before the S / D elements 260 are epitaxially grown from the S / D trench, an etch process may be used to recess the sacrificial semiconductor layers between the adjacent channel layers 215 to form vertical gaps between the adjacent channel layers 215.Then, one or more dielectric materials are deposited (for example, using CVD or ALD) to fill the gaps. A further etching process is performed to remove the dielectric materials outside the gaps, forming the inner spacer layer 255.

[0023] In the illustrated embodiment, each gate stack 240 includes a gate dielectric layer 349 and a gate electrode 350. The gate dielectric layer 349 may comprise a high-k dielectric material, such as HfO 2, HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, Ta 2 O 3 , Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4, hafnia-alumina alloy (HfO 2 -Al 2 O 3alloy), another suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials that have a high dielectric constant, for example, greater than that of silicon oxide (k ≈ 3.9). The gate dielectric layer 349 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the gate stack 240 further includes an interface layer between the gate dielectric layer 349 and the channel layers 215. The interface layer may include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer 350 includes an n-type or pure p-type work function layer and a metal fill layer.For example, an n-type work function layer may comprise a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-type work function layer may comprise a metal with a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal fill layer may comprise aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed using CVD, PVD, plating, and / or other suitable processes. Since the gate stack 240 includes a high-k dielectric layer and metal layer(s), it is also referred to as a high-k metal gate.

[0024] In one embodiment, the gate spacer 247 comprises a dielectric material, such as a dielectric material comprising silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In embodiments, the gate spacer 247 may comprise La 2 O 3 , Al 2 O 3 , ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2, Y 2 O 3, AlON, TaCN, ZrSi, or other suitable material(s). For example, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over a dummy gate stack (which is subsequently replaced by the high-k metal gate stack 240) and subsequently etched (e.g., anisotropically etched) to form gate spacers 247. In some embodiments, the gate spacers 247 comprise a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, is formed adjacent to the gate stack 240.For example, in embodiments, the gate spacer 247 may have a thickness of about 1 nm to about 40 nm.

[0025] In some embodiments, the SAC layer 352 comprises La 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3, AlON, TaCN, ZrSi, or other suitable material(s). The SAC layer 352 protects the gate stacks 240 from etching and CMP processes used to etch S / D contact holes. The SAC layer 352 may be formed by recessing the gate stacks 240 and optionally recessing the gate spacers 247, depositing one or more dielectric materials over the recessed gate stacks 240 and optionally over the recessed gate spacers 247, and performing a CMP process on the one or more dielectric materials.

[0026] In embodiments, CESLs 269 and 269' may each 2 O 3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3, AlON, TaCN, ZrSi or other suitable material(s); and may be formed using CVD, PVD, ALD or other suitable methods. The ILD layers 270 and 270' may each comprise tetraethyl orthosilicate oxide (TEOS) oxide, undoped silica glass or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorine-doped fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), a low-k dielectric material, other suitable dielectric material, or combinations thereof. The ILD layers 270 and 270' may each be formed using PECVD (plasma-enhanced CVD), FCVD (flowable CVD) or other suitable methods.

[0027] In some embodiments, the silicide elements 273 may comprise titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0028] In one embodiment, the S / D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed using CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed using CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted in the S / D contacts 275.

[0029] In some embodiments, the cover layer 356 comprises La 2 O3 , Al 2 O 3 , SiOCN, SiOC, SiCN, SiO 2 , SiC, ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2 , Si 3 N 4 , Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s). The cap layer 356 protects the S / D contacts 275 from etching and CMP processes and insulates the S / D contacts 275 from the interconnect structure formed thereon. In some embodiments, the SAC layer 352 and the cap layer 356 comprise different materials to achieve etch selectivity, for example, during the formation of the cap layer 356.

[0030] In one embodiment, the S / D contact vias 358 and the gate vias 359 may each include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed using CVD, PVD, ALD, and / or other suitable processes. The metal fill layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and may be formed using CVD, PVD, ALD, plating, or other suitable processes.In some embodiments, the conductive barrier layer is omitted from the S / D contacts 358 and / or the gate vias 359. In some embodiments, the adhesive layer 357 may comprise titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed using CVD, PVD, or ALD.

[0031] At operation 104, the method 100 ( Fig. 1A) the device 200 from its backside until the semiconductor fins 204, the semiconductor layer 239 and the isolation elements 230 are exposed from the backside of the device 200. The resulting structure is shown in accordance with one embodiment in Fig. 3. For simplicity, some of the features of the device 200 are shown in Fig. 3. It should be noted that the device 200 in Fig. 3, as well as in Fig. 4 to 15 and 17A to 18H is reversed, which is indicated by the “z” axis pointing upwards. In addition, in the illustrated embodiment, Fig. 3, some of the S / D elements 260 are n-type (denoted by 260(N)) and intended for n-type transistors 202, and some of the S / D elements 260 are p-type (denoted by 260(P)) and intended for p-type transistors 202. In one embodiment, the process 104 first flips the device 200 and attaches the front side of the device 200 to a carrier, and then applies a thinning process to the back side of the device 200. The thinning process may include a mechanical grinding process and / or a chemical thinning process. A substantial amount of substrate material may first be removed from the substrate 201 during a mechanical grinding process. Thereafter, a chemical thinning process may apply an etching chemical to the back side of the substrate 201 to further thin the substrate 201.

[0032] At operation 106, the procedure 100 ( Fig. 1A) backside vias 282 that are electrically connected to some of the S / D elements 260. An embodiment of the resulting structure is shown in Fig. 4. The process 106 includes a variety of processes. In one embodiment, the process 106 selectively etches the semiconductor layer 239 to form holes that expose the S / D elements 260. For example, the process 106 may employ a wet etch process, a dry etch process, a reactive ion etch process, or another suitable etch process, wherein the etch process is adjusted to selectively remove the semiconductor layer 239 with little to no etching of the semiconductor fins 204 and the isolation structure 230. After the S / D elements 260 are exposed in the holes, the process 106 may further partially recess the S / D elements 260. Next, the process 106 deposits one or more metals in the holes and over the S / D elements 260 to form the backside vias 282.The backside vias 282 may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed using CVD, PVD, ALD, plating, or other suitable processes. The backside vias 282 may comprise more than one layer of materials in some embodiments. For example, the backside via 282 may comprise a barrier layer and one or more low-resistivity metals on the barrier layer. The barrier layer may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), ruthenium (Ru) or other suitable material, and the low resistance metals may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al) or other metals.In some embodiments, the process 106 forms a silicide feature (not shown) over the exposed surfaces of the S / D features 260 and then forms the backside vias 282 on the silicide feature. The feature may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The process 106 may perform a CMP process to planarize the backside surface of the device 200 after depositing the one or more metals for the backside vias 282.

[0033] For operation 108, the procedure saves 100 ( Fig. 1A) partially forms the isolation structure 230 to thereby form a trench 400 over the backside of the device 200. An embodiment of the resulting structure is shown in Fig. 5. With reference to Fig. 5, the isolation structure 230 is etched back from the back side of the device 200 until a thin layer of the isolation structure 230 remains. In some embodiments, the remaining layer of the isolation structure 230 has a thickness T 1 in a range of approximately 4 nm to approximately 20 nm. This layer of the isolation structure 230 provides insulation between the subsequently formed signal circuitry 406 ( Fig. 11) and the gate stack 240 (see Fig. 18E). If this layer is too thin (such as less than 4 nm), the isolation may not be sufficient and there is a risk that the signal interconnection 406 and the gate stack 240 will short-circuit. If this layer is too thick (such as greater than 20 nm), then the backside structures may be too thick and some of the backside vias 282 (such as the backside via 282 in the back right corner of the device 200 in Fig. 14) may be too high and have too much resistance for certain applications.

[0034] In one embodiment, process 108 may employ a wet etch process, a dry etch process, a reactive ion etch process, or another suitable etch process, wherein the etch process is adjusted to selectively etch the isolation structure 230, with little to no etching of the semiconductor fins 204 and the backside vias 282. The etch process may be controlled using a timer to achieve the desired thinness of the isolation structure 230. In one embodiment, the etch is self-aligned with respect to the isolation structure 230 without the use of an etch mask. In another embodiment, process 108 forms an etch mask to cover areas of the device 200 (including areas of the isolation structure 230) on which signal interconnections will not be formed and etches the isolation structure 230 through the etch mask. After the etching is complete, the etch mask is removed.The etching creates the trench 400 on the backside of the device 200. Referring to . Fig. 5, the lower surface of the trench 400 is a surface of the isolation structure 230, the sidewalls of the trench 400 include sidewalls of the semiconductor fins 204 and sidewalls of the backside vias 282.

[0035] At operation 110, the procedure 100 ( Fig. 1A) forms a dielectric spacer 402 on surfaces of the trench 400 and over the backside of the device 200. An embodiment of the resulting structure is shown in Fig. 6. With reference to Fig. 6, the dielectric spacer 402 is deposited on the surfaces of the isolation structure 230, the semiconductor fins 204, and the backside vias 282 exposed in the trench 400. The dielectric spacer 402 is also deposited on the backside surface of the device 200. In one embodiment, the dielectric spacer 402 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In one embodiment, the dielectric spacer 402 is deposited to have a uniform or substantially uniform thickness on the various surfaces discussed above.For example, the dielectric spacer 402 may be deposited using ALD or other suitable processes to achieve a uniform or substantially uniform thickness. In some embodiments, the dielectric spacer 402 has a thickness T. 2 in a range of about 3 nm to about 8 nm. As will be discussed, the dielectric spacer 402 provides isolation between a subsequently formed signal interconnect 406 and some of the backside vias 282 (see Fig. 11B for an example in which the dielectric spacer 402 isolates the signal interconnection 406 from the via 282 in the back right corner. If the dielectric spacer 402 is too thin (such as less than 3 nm), the isolation may not be sufficient, and the risk of the signal interconnection 406 and some of the backside vias 282 shorting out may be high. As will be discussed further, the dielectric spacer 402 and the signal interconnection 406 together fill the trench 400 (see Fig. 11A for an example). Therefore, if the dielectric spacer 402 is too thick (such as greater than 8 nm), then, depending on the pitch between the adjacent backside vias 282 along the "y" direction, in some cases the signal interconnection may be too thin (and the resistance thereof may be too large). In various embodiments, the dielectric spacer 402 may comprise a single layer of one material or multiple layers of different materials.

[0036] In process 112, the procedure 100 ( Fig. 1A) the dielectric spacer 402 to expose areas of some of the backside vias 282 to be connected by backside signal interconnects. This may involve a variety of processes including photolithographic and etching processes. One embodiment of the process 112 is shown in Fig. 7, Fig. 8A and Fig. 8B, wherein the backside vias 282 in the back left and front right corners of the device 200, which in Fig. 7 to 8B are exposed after patterning of the dielectric spacer.

[0037] With reference to Fig. 7, a patterned etch mask 404 is formed over the backside of the device 200. The patterned etch mask 404 covers the portion of the dielectric spacer 402 that is not to be etched. The patterned etch mask 404 comprises a material that is different from a material of the dielectric spacer 402 to achieve etch selectivity. In some embodiments, the patterned etch mask 404 comprises a patterned photoresist (or resist). In some embodiments, the patterned etch mask 404 further comprises an anti-reflective coating (ARC) layer or other layer(s) beneath the patterned photoresist. The present disclosure contemplates other materials for the patterned etch mask 404, as long as etch selectivity is achieved during the etching of the dielectric spacer 402.In some embodiments, the patterned etch mask 404 is formed by a photolithographic process, which includes spin-coating a photoresist layer, performing a baking process before exposure, performing an exposure process using a mask, performing a baking process after exposure, and performing a development process. After development, the photoresist layer is patterned into the etch mask 404 corresponding to the mask. Alternatively, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or combinations thereof. It should be noted that in the embodiment shown in FIG. Fig. 7, the patterned etch mask 404 is present on the top surface of the dielectric spacer 402 in selected areas and may or may not be present on the sidewalls of the dielectric spacer 402 within the trench 400.

[0038] With reference to Fig. 8A, the process 112 etches the dielectric spacer 402 through the patterned etch mask 404, thereby exposing top and sidewall surfaces of the backside vias 282 formed by the backside signal interconnects (406 in Fig. 11A and Fig. 11B). It also exposes portions of the semiconductor fins 204 and the isolation structure 230. In the present embodiment, the etch process is a dry etch process and is anisotropic (vertical etch). Consequently, the portion of the dielectric spacer 402 on the sidewalls of the trench 400 and directly below the patterned etch mask 404 is not etched. The etch is adjusted to be selective to the materials of the dielectric spacer 402, with little to no etching of the semiconductor fins 204, the isolation structure 230, and the backside vias 282. After the etch is complete, the patterned etch mask 404 is removed, for example, by photoresist stripping, ashing, or another suitable process.

[0039] Fig. 8B shows a top view of the device 200 from the back of the device 200 after the process 112 has been completed. The shape of the exposed surface of the insulation structure 230, as shown in Fig. 8B, may be defined by the photolithography in process 112, as discussed above. As shown, the distance between the two backside vias 282 along the "y" direction P 1 , which is approximately the distance between the S / D elements 260(N) and 260(P) ( Fig. 3). The exposed surface of the insulation structure 230 has a central portion in the longitudinal direction parallel to the "x" direction and two projections extending from the two ends of the central portion and in opposite directions ("y" and "-y"). The central portion has a width W 1 in the “y” direction, and the two projections each have a width W 2 in the “y” direction. It is true that P 1 = W1 +2W 2 In some embodiments, the dimension P 1 in a range of about 20 nm to about 60 nm. In one embodiment, the width W 1 approximately half of the dimension P 1 , with a fluctuation in a range of about 3 nm to about 5 nm. In other words, W 1 = (1 / 2)P 1 ± Δ, where Δ is in a range from approximately 3 nm to approximately 5 nm. The deviation Δ takes into account mismatch and other inaccuracies during photolithography. As will be discussed, the shape of the exposed area of ​​the isolation structure 230, as shown in Fig. 8B, equal to the shape of the lower surface (when viewed from the rear of the device 200) of the signal circuit 406 ( Fig. 11A).

[0040] At operation 114, the procedure 100 ( Fig. 1B) the trench 400 with one or more metals 406. With reference to Fig. 9, the one or more metals 406 are deposited on the isolation structure 230 and in direct contact with sidewall surfaces of the backside vias 282 exposed in the trench 400. The one or more metals 406 are also in direct contact with sidewall surfaces of the semiconductor fins 204 exposed in the trench 400. As will be discussed, the semiconductor fins 204 are deposited in a later step ( Fig. 13) is replaced by an insulating material 408. Therefore, there is no concern about short circuits through the one or more metals 406 and the semiconductor fins 204. The one or more metals 406 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), or other metals, and may be formed using CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the one or more metals 406 may include a barrier layer and one or more low-resistivity metals on the barrier layer.The barrier layer may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), ruthenium (Ru) or other suitable material, and the low resistance metals may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al) or other metals.

[0041] At operation 116, the process etches 100 ( Fig. 1B) the one or more metals 406 and the backside vias 282. A resulting structure is shown in Fig. 10. The process 116 may apply one or more etch processes that are set to be selective to the materials of the one or more metals 406 and the backside vias 282, with little to no etching of the dielectric spacer 402 and the semiconductor fins 204. The etch processes may include a dry etch, a wet etch, reactive ion etch, or other suitable processes. A portion of the one or more metals 406 remains in the trench 400 and becomes the signal interconnect 406 (or metal interconnect 406). The etch processes may be controlled using a timer so that the metal interconnect 406 has a desired thickness T 3(along the "z" or "-z" direction), such as in a range of approximately 5 nm to approximately 20 nm. If the signal circuitry 406 is too thin (such as less than 5 nm), its resistance may be undesirably high for some applications. If the signal circuitry 406 is too thick (such as greater than 20 nm), the backside of the device 200 may be unnecessarily high. In addition, this would increase the length and resistance of some of the backside vias 282 connected to the backside power supply rails (such as the via 282 in the backside right corner of the device 200 in Fig. 14) undesirably increase. The area of ​​the contact interface of the signal interconnection 406 and the rear via 282 is T 3 *W 3 , where W 3 is the width of the via 282 along the "x" direction. In some embodiments, W 3in a range of approximately 10 nm to approximately 30 nm.

[0042] At operation 118, the process etches 100 ( Fig. 1B) the structured dielectric spacer 402. A resulting structure is shown in Fig. 11A. The process 118 may apply one or more etch processes that are set to be selective to the materials of the patterned dielectric spacer 402, with little to no etching of the signal circuitry 406, the backside vias 282, and the semiconductor fins 204. The etch processes may include a dry etch, a wet etch, reactive ion etch, or other suitable processes. A portion of the dielectric spacer 402 remains in the trench 400 and has an "L" shape in a front view. The vertical portion of the "L"-shaped spacer 402 is disposed between the signal circuitry 406 and the semiconductor fin 204. The horizontal portion of the "L"-shaped spacer 402 is disposed between the signal circuitry 406 and the isolation structure 230. Fig. 11B shows a plan view of the device 200 as viewed from the rear thereof. As in Fig. 11A and Fig. 11B, the dielectric spacer 402 has a thickness T 2 along the “y” direction. In one embodiment, the thickness T 2 in a range of about 3 nm to about 8 nm, the significance of which will be explained with reference to Fig. 6 was discussed.

[0043] As in Fig. 11A, the upper surface of the signal circuitry 406 is substantially flat, and the lower surface of the signal circuitry 406 has a stepped profile. A portion of the lower surface of the signal circuitry 406 is disposed on the isolation structure 230, and another portion of the lower surface of the signal circuitry 406 is disposed on the horizontal portion of the dielectric spacer 402. Therefore, the signal circuitry 406 has an inverted "L" shape in a front view, complementing the "L"-shaped spacer 402. The vertical portion of the inverted "L" shape is disposed directly on the isolation structure 230, and the horizontal portion of the inverted "L" shape is disposed directly on the dielectric spacer 402. The portion of the signal circuitry 406 disposed directly on the isolation structure 230 has the same shape and dimensions as the portion shown in Fig. 8B, the exposed area of ​​the insulation structure 230 - wherein a central portion has a width W 1 and is longitudinally parallel to the “x” direction and two projections extend from the two ends of the central portion and in opposite directions (“y” and “-y”) and each have a width W 2 The upper surface of the signal circuit 406 is in Fig. 11B and also has a longitudinal central portion parallel to the "x" direction and two projections extending from the two ends of the central portion and in opposite directions ("y" and "-y"). The central portion of the upper surface of the signal circuit 406 has a width W 4 and the two projections thereof each have a width T 2 in the “y” direction. It is true that P 1 = W 4 + 2T 2 . The signal interconnection 406 has a length L 1along the “x” direction. In one embodiment, the length L 1 in a range of approximately 20 nm to approximately 1,000 nm. As in Fig. 11A and Fig. 11B, a first sidewall surface of the signal interconnect 406 directly contacts the backside via 282 in the back left corner, and a second sidewall surface of the signal interconnect 406 directly contacts the backside via 282 in the front right corner, thereby connecting the two backside vias 282. Note that the device 200 in Fig. 11A is reversed. Therefore, when viewing the device 200 from the front, the top surface and bottom surface of the signal circuitry 406 discussed above are the bottom surface and top surface of the signal circuitry 406, respectively.

[0044] At operation 120, the procedure 100 ( Fig. 1B) forms an isolation element 408 over the signal circuitry 406, which fills the trench 400. A resulting structure is shown in Fig. 12. In one embodiment, the process 120 includes depositing one or more dielectric materials over the signal interconnection 406, filling the trench 400, and then performing a CMP process to planarize the backside surface of the device 200 and expose the backside vias 282 and the semiconductor fins 204. A portion of the one or more dielectric materials remains in the trench 400 and becomes the isolation element 408. The isolation element 408 may include one layer of dielectric material or multiple layers of dielectric materials, such as a dielectric liner layer and a dielectric fill layer over the dielectric liner layer. In one embodiment, the isolation element 408 includes a dielectric material including silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g.,Silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN)). In some embodiments, the insulation element 408 may comprise La. 2 O 3 , Al 2 O 3 , ZnO, ZrN, Zr 2 Al 3 O 9 , TiO 2 , TaO 2 , ZrO 2 , HfO 2, Y 2 O 3 , AlON, TaCN, ZrSi, or other suitable material(s). The insulation element 408 may be deposited using ALD, CVD, or other suitable methods.

[0045] For process 122, procedure 100 ( Fig. 1B) the semiconductor fins 204 by one or more dielectric materials. In one embodiment, the one or more dielectric materials are the same material(s) as those in the isolation element 408, as shown in Fig. 13. In another embodiment, the one or more dielectric materials are a material(s) different from those in the isolation element 408. The process 122 may include a variety of processes, including etching and deposition processes. For example, the process 122 may perform one or more etches to remove the semiconductor fins 204 and the semiconductor layer 239 thereunder. The etching processes may include a dry etch, a wet etch, reactive ion etch, or other suitable processes. The etching processes are set to be selective to the materials of the semiconductor fins 204 and the semiconductor layer 239, with little to no etching of the isolation element 408, the signal interconnection 406, the dielectric spacer 402, the isolation structure 230, and the backside vias 282.After the semiconductor fins 204 and the semiconductor layer 239 underneath are etched, trenches are formed on the backside of the device 200, exposing portions of some of the S / D elements 260, the inner spacers 255, and the gate stack 240. Next, the process 122 deposits one or more dielectric materials in the trenches and performs a CMP process to planarize the backside of the device 200 and expose some of the backside vias 282 to be connected to the backside power rails (such as the backside via 282 in the backside right corner in FIG. Fig. 13).

[0046] At operation 124, the procedure 100 ( Fig. 1B) one or more rear power rails 284. The resulting structure is shown in one embodiment in Fig. 14. As shown in Fig. 14, some of the rear vias 282 (such as the rear via 282 in the rear right corner in Fig. 14) are electrically connected to the backside power rails 284. In one embodiment, the backside power rails 284 may be formed using a damascene process, a dual-damascene process, a metal patterning process, or other suitable processes. The backside power rails 284 may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited using CVD, PVD, ALD, plating, or other suitable processes. Although in Fig. 14, the backside power rails 284 are embedded in one or more dielectric layers. The presence of backside power rails 284 advantageously increases the number of metal traces available in the device 200 for direct connection to source / drain contacts and vias. It also increases the gate density for greater device integration than other structures without the backside power rails 284. The backside power rails 284 may have a wider dimension than the first-level metal traces (Mo) on the front side of the device 200, which advantageously reduces the resistance of the backside power rail. The isolation element 408 arranged between the backside power rail 284 and the signal circuitry 406 has a thickness T 4In some embodiments, the thickness T 4 in a range of about 4 nm to about 20 nm. If the thickness T 4 is too small (such as less than 4 nm), the coupling capacitance between the signal interconnection 406 and the rear power rail 284 may be undesirably high for some applications, and the isolation effects may not be sufficient. If the thickness T 4 is too large (such as larger than 20 nm), the length and resistance of some of the backside vias 282 (such as the backside via 282 in the rear right corner in Fig. 14) may be undesirably large for some applications.

[0047] At operation 126, the procedure 100 ( Fig. 1B) performs further manufacturing processes on the device 200. For example, it may form one or more interconnect layers on the backside of the structure 200, form passivation layers on the backside of the device 200, and perform other back-end-of-line (BEOL) processes.

[0048] Fig. 15 shows a perspective view of the device 200 according to one embodiment. As in Fig. 15, the device 200 includes backside power rails 284 and backside vias 282. Some of the backside vias 282 vertically connect some of the S / D elements 260 to the backside power rails 284. Some of the backside vias 282 are connected to some of the S / D elements 260 but are isolated from the backside power rails 284 by the isolation elements 408. The signal interconnection 406 connects a plurality of backside vias 282. In this embodiment (as well as in the embodiment shown in Fig. 14), the signal interconnect 406 is isolated from the gate stacks 204. Channel layers 215 are stacked vertically and are connected between pairs of the S / D elements 260. The gate stacks 240 engage the channel layers 215 and enclose each of the channel layers 215. Some of the S / D elements 260 are provided with both front-side contacts 275 and back-side vias 282.

[0049] Fig. 16A-E illustrate various non-limiting examples in which signal circuitry 406 may be implemented in device 200. Fig. 16A shows an example in which the signal circuit 406 establishes a connection between one S / D of one transistor and another S / D of an adjacent transistor. Fig. 16B shows an example in which the signal circuit 406 establishes a connection between one S / D of one transistor and another S / D of another transistor that is not adjacent (i.e., there are intervening transistors between the two transistors). The signal circuit 406 in Fig. 16A and Fig. 16B can be used with the above-mentioned reference to Fig. 1A to 15 discussed processes are trained. Fig. 16C shows an example in which the signal circuit 406 establishes a connection between an S / D of a transistor and a gate of an adjacent transistor. Fig. 16D shows an example in which the signal circuit 406 establishes a connection between a gate of one transistor and another gate of an adjacent transistor. Fig. 16E shows an example in which the signal circuitry 406 establishes a connection between a gate of one transistor and another gate of another transistor that is not adjacent (i.e., there are intervening transistors between the two transistors).

[0050] Fig. 17A to G show perspective views of the device 200 during various operations in an embodiment of the method 100 in which the signal circuitry 406 establishes a connection between two gates (as in the examples in Fig. 16D and Fig. 16E). Some aspects of the Fig. 17A to G are the above-discussed Fig. 3 to 15. The device 200 in each of the Fig. 17A to G is provided upside down. In addition, the side view of the device 200 (exposing the gate stacks 240) may be provided as a cross-sectional view taken along the line FF in Fig. 2C. Therefore, the channel layers 215 in Fig. 17A to G not shown. Fig. 17A to G and the associated procedures are briefly discussed below.

[0051] As in Fig. 17A, the device 200 is provided with various elements 260, 356, 269, 270, 240, 230, 204, and 282, which were discussed above. Fig. 17A can be operated by operations 102, 104 and 106 ( Fig. 1A). In particular, the isolation structure 230 is provided on the backside of the gate stacks 240, and the backside vias 282 are formed and connected to some of the S / D elements 260.

[0052] How Fig. 17B, ​​the isolation structure 230 is etched back from the backside of the device 200 until a thin layer of the isolation structure 230 remains. In some embodiments, the remaining layer of the isolation structure 230 has a thickness T 1 in a range of about 4 nm to about 20 nm, the meaning of which is defined with reference to Fig. 5. The isolation structure 230 may be etched using any suitable etch process that is selective to the material of the isolation structure 230, with little to no etching of the semiconductor fins 204 and the backside vias 282. The etch process may be controlled using a timer to achieve the desired thinness of the isolation structure 230. In one embodiment, an etch mask is formed to cover areas of the device 200 on which signal interconnections are to be formed, and then the isolation structure 230 is etched through the etch mask. After the etching is complete, the etch mask is removed. The etching back of the isolation structure 230 results in a trench 400 on the backside of the device 200.

[0053] As in Fig. 17C, a dielectric spacer 402 is formed to cover various areas on the backside of device 200 that include various areas of trench 400, similar to process 110 discussed above. For example, dielectric spacer 402 may be formed to have a uniform or substantially uniform thickness. Then, dielectric spacer 402 and isolation structure 230 are patterned using photolithographic and etching processes to form holes 401 therein that expose gate stacks 240 for establishing signal connection thereto, similar to process 112 discussed above.

[0054] As in Fig. 17D, one or more metals 406 are deposited to fill the trench 400 and the holes 401, similar to the process 114 discussed above. Then, the one or more metals 406 are etched back, similar to the process 116 discussed above. The remaining portion of the one or more metals 406 becomes a signal interconnect (or metal interconnect) 406 connecting two gates 240 of two transistors. In this embodiment, the top surface of the signal interconnect 406 is flat or substantially flat, and the bottom surface of the signal interconnect 406 includes two protrusions whose bottom surfaces directly contact the gate stacks 240. It should be noted that the device 200 in Fig. 17D is reversed. Therefore, the top surface and bottom surface of the signal circuitry 406 discussed above are the bottom surface and top surface of the signal circuitry 406, respectively, when viewing the device 200 from the front.

[0055] As in Fig. 17E, the dielectric spacer 402 is partially etched back, similar to the process 118 discussed above. As shown in Fig. 17F, an isolation element 408 is formed over the signal circuitry 406, similar to the process 120 discussed above. As shown in Fig. 17G, the semiconductor fins 204 are replaced with an insulating material, similar to the process 122 discussed above.

[0056] Fig. 18A-H show perspective views of the device 200 during various operations in an embodiment of the method 100 in which the signal circuitry 406 establishes a connection between an S / D element and a gate (as in the example in Fig. 16C). Some aspects of the Fig. 18A to H are the above-discussed Fig. 3 to 15. The device 200 in each of the Fig. 18A to H is provided upside down. In addition, the side view of the device 200 (exposing the gate stacks 240) may be provided as a cross-sectional view taken along line FF in Fig. 2C. Therefore, the channel layers 215 in Fig. 18A to H are not shown. 18A to H and the associated processes are briefly discussed below.

[0057] Fig. 18A and Fig. 18B are each the Fig. 17A and Fig. 17B. Therefore, the discussion of Fig. 18A and Fig. 18B omitted here. As in Fig. 18C, a dielectric spacer 402 is formed to cover various areas on the backside of device 200 that include various areas of trench 400, similar to process 110 discussed above. For example, dielectric spacer 402 may be formed to have a uniform or substantially uniform thickness. Then, dielectric spacer 402 and isolation structure 230 are patterned using photolithographic and etching processes to form a hole 401 therein, exposing gate stack 240 for establishing a signal connection thereto, similar to process 112 discussed above.

[0058] As in Fig. 18D, the dielectric spacer 402 is again patterned using photolithographic and etching processes to form the backside via 282 for establishing a signal connection thereto, similar to the process 112 discussed above. Fig. 18D is selective to the material of the dielectric spacer 402, with little to no etching of the backside via 282, the semiconductor fin 204, and the isolation structure 230.

[0059] As in Fig. 18E, one or more metals 406 are deposited to fill the trench 400 and the hole 401, similar to process 114 discussed above. Then, the one or more metals 406 and the backside via 282 are etched back, similar to process 116 discussed above. The remaining portion of the one or more metals 406 becomes a signal interconnect (or metal interconnect) 406 connecting a gate 240 to an S / D element 260. In this embodiment, the top surface of the signal interconnect 406 is flat or substantially flat, and the bottom surface of the signal interconnect 406 includes two protrusions. The bottom surface of one of the protrusions directly contacts the gate stack 240, and the sidewall surface of the other of the protrusions directly contacts the backside via 282. Note that the device 200 in Fig. 18E is reversed. Therefore, when viewing the device 200 from the front, the top surface and the bottom surface of the signal circuitry 406 discussed above are the bottom surface and the top surface of the signal circuitry 406, respectively.

[0060] As in Fig. 18F, the dielectric spacer 402 is partially etched back, similar to the process 118 discussed above. As shown in Fig. 18G, an isolation element 408 is formed over the signal circuitry 406, similar to the process 120 discussed above. As shown in Fig. 18H, the semiconductor fins 204 are replaced with an insulating material, similar to the process 122 discussed above.

[0061] Fig. 19A shows a diagram of an example logic cell 300 that may benefit from aspects of the present disclosure. The logic cell 300 may be included in the device 200. The logic cell 300 implements an AOI (AND-OR-INVERTER) function and includes four PMOSFETs and four NMOSFETs. The logic cell 300 includes input terminals A1, A2, B1, and B2, an output terminal ZN, and an internal net n01.

[0062] Fig. 19B shows a layout implementation of the logic cell 300 according to the present embodiment. In particular, the input terminals A1, A2, B1, and B2, the internal net n01, and part of the output terminal ZN are implemented as signal interconnections on the front side of the logic cell 300; while another part of the output terminal ZN is implemented as a signal interconnection on the back side of the logic cell 300, such as the one shown in Fig. 14 and Fig. 15. Since part of the output terminal ZN is implemented as a backside signal circuit, the routing on the front side of the logic cell 300 is less crowded. In particular, the frontside signal circuit for ZN does not directly oppose any of the signal circuits for the input terminals A1, A2, B1, and B2, thereby reducing parasitic resistance thereof. In the layout of Fig. 19B, the gates are vertically aligned, while the active regions (such as channel regions and S / D regions) are horizontally aligned. The gates and active regions are implemented on the front side of logic cell 300. Logic cell 300 occupies an area spanning 5 gate-to-gate pitches. The front-side signal interconnections are implemented using 4 metal traces.

[0063] Fig. 19C shows another layout implementation of the logic cell 300 according to the present embodiment. In particular, the input terminals A1, A2, B1, and B2, the internal net n01, and part of the output terminal ZN are implemented as signal interconnections on the front side of the logic cell 300; while another part of the output terminal ZN is implemented as a signal interconnection on the back side of the logic cell 300, such as the one shown in Fig. 14 and Fig. 15 shown signal circuit 406. In the layout of Fig. 19C, the gates are vertically aligned, while the active regions (such as channel regions and S / D regions) are horizontally aligned. The gates and the active regions are implemented on the front side of the logic cell 300. The logic cell 300 occupies an area spanning 5 gate-to-gate pitches. The front side signal interconnections are implemented using 3 metal traces. The implementation of Fig. 19C uses a smaller area of ​​the silicon wafer than the implementation in Fig. 19B. However, the parasitic resistance of the output terminal ZN on the front side may be larger than that in Fig. 19B.

[0064] Although not intended to be limiting, embodiments of the present disclosure provide one or more advantages for semiconductor structures and manufacturing processes. For example, embodiments of the present disclosure provide signal interconnections on the backside of a device and among transistors. The backside signal interconnections can be used to establish connectivity between one S / D and another S / D, one S / D and a gate, and one gate and another gate. With the backside signal interconnections, the routing on the frontside of the device becomes less congested, and higher circuit density can be achieved. Embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0065] In one aspect example, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a first transistor having a first source / drain (S / D) element and a first gate; a second transistor having a second S / D element and a second gate; a multilayer interconnect structure disposed above the first and second transistors; signal interconnection below the first and second transistors; and a power supply rail below the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S / D element and the first gate to one of the second S / D element and the second gate.

[0066] In one embodiment, the semiconductor structure further comprises: a first via under the first transistor and electrically connected to the first S / D element; and a second via under the second transistor and electrically connected to the second S / D element, wherein the first and second vias are isolated from the power supply rail, and the signal circuitry directly contacts the first via and the second via. In another embodiment, a bottom surface of the signal circuitry is substantially flat, and a top surface of the signal circuitry has a step profile. In another further embodiment, a first sidewall surface of the signal circuitry directly contacts the first via, and a second sidewall surface of the signal circuitry directly contacts the second via.

[0067] In one embodiment of the semiconductor structure, the signal circuitry electrically connects the first gate to the second gate. In another embodiment, a lower surface of the signal circuitry is substantially flat, and an upper surface of the signal circuitry has two protrusions that directly contact the first gate and the second gate.

[0068] In one embodiment, the semiconductor structure further comprises a first via below the first transistor, electrically connected to the first S / D element, wherein the signal interconnection directly contacts the first via and the second gate. In another embodiment, a bottom surface of the signal interconnection is substantially flat, a sidewall surface of the signal interconnection directly contacts the first via, and a top surface of the signal interconnection directly contacts the gate.

[0069] In one embodiment of the semiconductor structure, the signal interconnection is part of a standard logic cell and is routed within the boundaries of the standard logic cell. According to the invention, the first transistor has a third S / D element, and the semiconductor structure has a third via below the first transistor that electrically connects the third S / D element to the power supply rail.

[0070] In another example aspect, the present disclosure is directed to a method comprising: providing a structure having first and second transistors over a substrate and a first isolation structure between the first and second transistors, the first transistor having a first source / drain (S / D) element and the second transistor having a second S / D element, the structure further comprising first and second vias connected to the first and second S / D elements, respectively, and extending to a backside of the structure. The method further comprises: partially removing the first isolation structure, thereby exposing a first sidewall surface of the first via and a second sidewall surface of the second via, wherein a first portion of the first isolation structure remains in the structure.The method further comprises: depositing a metal interconnect on the first portion of the first isolation structure that electrically contacts the first sidewall surface and the second sidewall surface; and forming an isolation element on the metal interconnect, the first via, and the second via.

[0071] In one embodiment, the method further comprises etching back the metal interconnect, the first via, and the second via prior to forming the isolation element. In another embodiment, the method further comprises forming a power supply rail on the isolation element.

[0072] In one embodiment of the method, the partial removal of the first isolation structure results in a trench, and the first and second sidewall surfaces are part of sidewalls of the trench. In another embodiment, the method further comprises, prior to depositing the metal interconnection, depositing a dielectric spacer on surfaces of the trench and patterning the dielectric spacer to expose the first sidewall surface and the second sidewall surface, wherein the metal interconnection is partially deposited on the dielectric spacer. In another embodiment, the method further comprises, after depositing the metal interconnection, partially removing the dielectric spacer before forming the isolation element.

[0073] In yet another aspect example, the present disclosure is directed to a method comprising: providing a structure having first and second transistors, the first transistor having a first source / drain (S / D) element and the second transistor having a second S / D element, the structure further comprising: a multi-layer interconnect over a front side of the first and second transistors, a first via disposed on a back side of the first S / D element, a second via disposed on a back side of the second S / D element, and a first isolation element disposed on a back side of the structure and adjacent to the first and second vias.The method further comprises partially removing the first isolation element, thereby forming a trench on the backside of the structure, the trench exposing a first sidewall surface of the first via and a second sidewall surface of the second via.The method further comprises: depositing a dielectric spacer on surfaces of the trench; patterning the dielectric spacer to expose the first sidewall surface and the second sidewall surface; depositing one or more metallic materials over a remaining portion of the dielectric spacer and filling the trench; and etching back the one or more metallic materials, the first via, and the second via, wherein a remaining portion of the one or more metallic materials becomes signal interconnection electrically connecting the first via and the second via.

[0074] In one embodiment, the method further comprises, after etching back, partially removing the remaining portion of the dielectric spacer. In another embodiment, the method further comprises, after etching back, forming a second isolation element on the signal interconnect, the first via, and the second via. In another embodiment, the method comprises forming a power supply rail on the second isolation element and on the backside of the structure.

Claims

[1] Semiconductor structure, comprising: a first transistor having a first S / D element and a first gate; a second transistor having a second S / D element and a second gate; a multilayer interconnect structure disposed over the first and second transistors; a signal circuit (406) between the first transistor and the second transistor; and a power supply rail (284) under the signal circuitry (406) and electrically isolated from the signal circuitry (406), the signal circuitry (406) electrically connecting one of the first S / D element and the first gate to one of the second S / D element and the second gate, the first transistor further comprising a third S / D element, further comprising: a third via under the first transistor electrically connecting the third S / D element to the power supply rail (284). [2] The semiconductor structure of claim 1, further comprising: a first via (282) under the first transistor and electrically connected to the first S / D element; and a second via (282) below the second transistor and electrically connected to the second S / D element, wherein the first and second vias (282) are isolated from the power supply rail (284) and the signal circuitry (406) directly contacts the first via (282) and the second via (282). [3] The semiconductor structure of claim 1 or 2, wherein a lower surface of the signal circuitry (406) is substantially flat and an upper surface of the signal circuitry (406) has a step profile. [4] The semiconductor structure of claim 2, wherein a first sidewall surface of the signal interconnection (406) directly contacts the first via (282) and a second sidewall surface of the signal interconnection (406) directly contacts the second via (282). [5] Semiconductor structure according to one of the preceding claims, wherein the signal circuit (406) electrically connects the first gate to the second gate. [6] The semiconductor structure of claim 5, wherein a lower surface of the signal circuit (406) is substantially flat and an upper surface of the signal circuit (406) has two protrusions that directly contact the first gate and the second gate. [7] The semiconductor structure of claim 1, further comprising: a first via (282) under the first transistor and electrically connected to the first S / D element, wherein the signal circuit (406) directly contacts the first via (282) and the second gate. [8] The semiconductor structure of claim 7, wherein a bottom surface of the signal interconnect (406) is substantially flat, a sidewall surface of the signal interconnect (406) directly contacts the first via (282), and a top surface of the signal interconnect (406) directly contacts the gate. [9] Semiconductor structure according to one of the preceding claims, wherein the signal interconnection (406) is part of a standard logic cell and is routed within boundaries of the standard logic cell. [10] A method comprising: Providing a structure comprising a first transistor and a second transistor over a substrate (201) and a first isolation structure between the first and second transistors, the first transistor comprising a first S / D element and the second transistor (202) comprising a second S / D element (260), the structure further comprising a first via (282) and a second via (282) respectively connected to the first and second S / D elements and extending to a backside of the structure; partially removing the first isolation structure, thereby exposing a first sidewall surface of the first via (282) and a second sidewall surface of the second via (282), wherein a first portion of the first isolation structure remains in the structure; depositing a metal interconnection (406) on the first portion of the first insulation structure that electrically connects the first sidewall surface and the second sidewall surface; and Forming an insulation element (230, 408) on the metal interconnection (406), the first via (282) and the second via (282). [11] The method of claim 10, further comprising, prior to forming the insulation element (230, 408): Etching back the metal interconnection (406), the first via (282) and the second via (282). [12] The method of claim 10 or 11, further comprising: Forming a power supply rail (284) on the insulation element (230, 408). [13] The method of any one of claims 10 to 12, wherein the partial removal of the first isolation structure results in a trench (400) and the first and second sidewall surfaces are part of sidewalls of the trench (400). [14] The method of claim 13, further comprising, prior to depositing the metal interconnect (406): Depositing a dielectric spacer (402) on surfaces of the trench (400); and Structuring the dielectric spacer (402) to expose the first sidewall surface and the second sidewall surface, wherein the metal interconnect (406) is partially deposited on the dielectric spacer (402). [15] The method of claim 14, further comprising, after depositing the metal interconnect (406): partially removing the dielectric spacer (402) before forming the insulation element (230, 408). [16] Method comprising: Providing a structure comprising a first transistor and a second transistor, the first transistor comprising a first source / drain, S / D element (260), and the second transistor (202) comprising a second S / D element, the structure further comprising: a multi-layer interconnect over a front side of the first transistor and the second transistor, a first via (282) disposed on a back side of the first S / D element, a second via (282) disposed on a back side of the second S / D element, and a first isolation element disposed on a back side of the structure and adjacent to the first via (282) and the second via (282); partially removing the first insulation element, thereby forming a trench (400) on the back side of the structure, the trench (400) exposing a first sidewall surface of the first via (282) and a second sidewall surface of the second via (282); depositing a dielectric spacer (402) on surfaces of the trench (400); Structuring the dielectric spacer (402) to expose the first sidewall surface and the second sidewall surface; depositing one or more metallic materials over a remaining portion of the dielectric spacer (402) filling the trench (400); and Etching back the one or more metallic materials, the first via (282) and the second via (282), wherein a remaining portion of the one or more metallic materials becomes a signal interconnect (406) electrically connecting the first via (282) and the second via (282). [17] The method of claim 16, further comprising: after etching back, partially removing the remaining portion of the dielectric spacer (402). [18] The method of claim 16 or 17, further comprising: after etching back, forming a second insulation element on the signal interconnection (406), the first via (282) and the second via (282). [19] The method of claim 18, further comprising: Forming a power supply rail (284) on the second insulation element and on the back of the structure.

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