INTEGRATED CIRCUIT STRUCTURE AND ITS MANUFACTURING METHOD

Abstract

Method comprising: depositing a dielectric cap (142) over a gate structure (130); Forming a source / drain contact (144) over a source / drain region (122) adjacent to the gate structure (130); oxidizing a top surface of the dielectric cap (142); after oxidizing the top surface of the dielectric cap (142), depositing an etch stop layer (146) over the dielectric cap (142) and an ILD layer (148) over the etch stop layer (146); Etching the ILD layer (148) and the etch stop layer (146) to form a via opening (O1, O2, O3, O4) extending through the ILD layer (148) and the etch stop layer (146); and Filling a source / drain via (150, 152) in the via opening (O1, O2, O3, O4); wherein the source / drain via (150, 152) is in contact with an oxidized region (1421) of the dielectric cap (142).

Description

BACKGROUND

[0001] Technical advances in IC materials and IC design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) achievable with a manufacturing process) has decreased. This scaling-down process generally provides benefits by increasing manufacturing efficiency and reducing associated costs.

[0002] US 2014 / 0 264 568 A1 discloses a method for manufacturing a semiconductor device, in which a trench is formed by removing an upper portion of a substrate. A gate insulating layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulating layer pattern. The gate electrode fills a lower portion of the trench. A cap layer is formed on the gate electrode and the gate insulating layer pattern. The cap layer is partially oxidized to form a first cap layer pattern and a second cap layer pattern. The first cap layer pattern is unoxidized, and the second cap layer pattern is oxidized. A third cap layer pattern is formed on the second cap layer pattern, the third cap layer pattern filling an upper portion of the trench. Similar prior art is known from US 2015 / 0 072 502 A1.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily exaggerated or reduced for the purpose of clarity of explanation. The Fig. 1 to 18D illustrate perspective and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure. The Fig. 19 to 23B illustrate exemplary cross-sectional views of various stages for fabricating an integrated circuit structure according to some further embodiments of the present disclosure. The Fig. 24 to 42D illustrate perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure according to some embodiments of the present disclosure. The Fig. 43 to 47B illustrate exemplary cross-sectional views of various stages for fabricating an integrated circuit structure according to some further embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may include embodiments where the first and second elements are formed in direct contact, and also embodiments where additional elements may be formed between the first and second elements such that the first and second elements need not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0006] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] As used herein, the terms "about," "approximately," "approximately," or "substantially" are generally intended to mean within 20 percent, within 10 percent, or within 5 percent of a particular value or range. Numerical quantities stated herein are approximate, meaning that the terms "about," "approximately," "approximately," or "substantially" can be inferred unless expressly stated.

[0008] The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for structures to be fabricated that have, for example, pitches smaller than what is otherwise achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers can then be used to pattern the fins.

[0009] After front-end-of-line (FEOL) processing is completed to fabricate transistors, source / drain contacts are formed over the source / drain regions of the transistors. Source / drain vias are then formed over the source / drain contacts to electrically connect the source / drain contacts to subsequently formed interconnect metal lines. Formation of the source / drain vias generally involves depositing an interlayer dielectric (ILD) layer over the source / drain contacts, forming via openings extending through the ILD layer using anisotropic etching, and then depositing one or more metal layers in the via openings to serve as the source / drain vias.To prevent overetching of the source / drain contacts during the anisotropic etching process, an additional etch stop layer (also called a middle contact etch stop layer (MCESL)) is formed over the source / drain contacts before the ILD layer is formed. The MCESL has a different etch selectivity than the ILD layer and can therefore slow down the etching process for forming via openings, which in turn prevents overetching of the source / drain contacts. To prevent overetching of dielectrics near the source / drain contacts during the MCESL etching process, an additional plasma treatment of the dielectrics can be performed before the MCESL is formed.The plasma treatment forms an oxidation region in the dielectrics that has a different etch selectivity than the MCESL, and therefore the oxidation region can slow down or even stop the etching process of forming via openings, which in turn prevents over-etching of the dielectrics beneath the oxidation region and results in a lower risk of leakage currents.

[0010] The Fig. 1 to 18D illustrate perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 100 according to some embodiments of the present disclosure. The transistors formed may include a p-type transistor (such as a p-FinFET) and an n-type transistor (such as an n-FinFET) according to some embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. However, it should be understood that additional operations may be performed before, during, and after the processes performed by the Fig. 1 to 18D, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable.

[0011] Fig. 1 illustrates a perspective view of a structure. The structure includes a substrate 12. The substrate 12 may be a semiconductor substrate (also called a wafer in some embodiments), which may be a silicon substrate, a silicon germanium substrate, or a substrate formed from other semiconductor materials. According to some embodiments of the present disclosure, the substrate 12 includes a bulk silicon substrate and an epitaxial silicon germanium (SiGe) layer or a germanium layer (without silicon therein) over the bulk silicon substrate. The substrate 12 may be doped with a p-type or an n-type dopant. Isolation regions 14, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 12. The portions of the substrate 12 between adjacent isolation regions 14 are referred to as semiconductor stripes 102.

[0012] The isolation regions 14 may include a liner oxide (not shown). The liner oxide may be formed from a thermal oxide formed by thermal oxidation of a surface layer of the substrate 12. The liner oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation regions 14 may also include a dielectric over the liner oxide, and the dielectric may be formed by flowable chemical vapor deposition (FCVD), spin-on coating, or the like.

[0013] With reference to Fig. 2, the isolation regions 14 are recessed such that the upper portions of the semiconductor stripes 102 protrude higher than the upper surfaces of the adjacent isolation regions 14 to form the protruding fins 104. The etching may be performed using a dry etching process, using NH3 and NF3 as the etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the isolation regions 14 is performed using a wet etching process. The etching chemical may, for example, include diluted HF.

[0014] In the embodiments illustrated above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing for structures to be fabricated that have, for example, pitches smaller than what is otherwise achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to pattern the fins.

[0015] The materials of the protruding fins 104 can also be replaced with materials different from those of the substrate 12. For example, if the protruding fins 104 serve for n-type transistors, the protruding fins 104 can be formed from Si, SiP, SiC, SiPC, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or the like. On the other hand, if the protruding fins 104 serve for p-type transistors, the protruding fins 104 can be formed from Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InSb, GaSb, InGaSb, or the like.

[0016] With reference to the Fig. 3A and Fig. 3B, dummy gate structures 106 are formed on the top surfaces and sidewalls of the protruding fins 104. Fig. Figure 3B illustrates a cross-sectional view obtained from a vertical plane including line BB in Fig. 3A. The formation of the dummy gate structures 106 includes sequentially depositing a gate dielectric layer and a dummy gate electrode layer over the fins 104, followed by patterning the gate dielectric layer and the dummy gate electrode layer. As a result of the patterning, the dummy gate structure 106 includes a gate dielectric layer 108 and a dummy gate electrode 110 over the gate dielectric layer 108. The gate dielectric layers 108 may be any acceptable dielectric layer, such as silicon oxide, silicon nitride, the like, or a combination thereof, and may be formed using any acceptable process, such as thermal oxidation, a spin-on process, CVD, or the like. The dummy gate electrodes 110 may be any acceptable electrode layer, e.g., including polysilicon, metal, or the like, or a combination thereof.The gate electrode layer may be deposited using any acceptable deposition process, such as CVD, plasma-enhanced CVD (PECVD), or the like. Each of the dummy gate structures 106 extends across a single or multiple protruding fins 104. The dummy gate structures 106 may have longitudinal directions perpendicular to the longitudinal directions of the corresponding protruding fins 104.

[0017] A mask pattern may be formed over the dummy gate electrode layer to assist in patterning. In some embodiments, a hard mask pattern includes the lower masks 112 over a cap layer of polysilicon and the upper masks 114 over the lower masks 112. The hard mask pattern is formed from one or more layers of SiO2, SiCN, SiON, Al2O3, SiN, or other suitable materials. In certain embodiments, the lower masks 112 comprise silicon oxide and the upper masks 114 comprise silicon nitride. By using the mask pattern as an etch mask, the dummy electrode layer is patterned into the dummy gate electrodes 110 and the overlay gate dielectric layer is patterned into the gate dielectric layers 108.

[0018] Next, as in Fig. 4 illustrates gate spacers 116 formed on sidewalls of dummy gate structures 106. In some embodiments of the gate spacer formation processes, a spacer material layer is deposited on substrate 12. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers 116. In some embodiments, the spacer material layer includes multiple layers, such as a first spacer layer 118 and a second spacer layer 120 formed over first spacer layer 118. First and second spacer layers 118 and 120 are each made of a suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.By way of example and without limitation, the first and second spacer layers 118 and 120 may be formed by sequentially depositing two different dielectrics over the dummy gate structures 106 using processes such as a CVD process, a subatmospheric CVD process (SACVD), a flowable CVD process, an ALD process, a PVD process, or another suitable process. An anisotropic etch process is then performed on the deposited spacer layers 118 and 120 to expose portions of the fins 104 that are not covered by the dummy gate structures 106 (e.g., in source / drain regions of the fins 104). Portions of the spacer layers 116 and 118 directly above the dummy gate structures 106 may be removed by this anisotropic etch process.Portions of the spacer layers 118 and 120 on sidewalls of the dummy gate structures 106 may remain and form gate sidewall spacers, referred to as gate spacers 116 for convenience. In some embodiments, the first spacer layer 118 is formed from silicon oxide, which has a lower dielectric constant than silicon nitride, and the second spacer layer 120 is formed from silicon nitride, which has a higher etch resistance to subsequent etch processes (e.g., etching source / drain recesses in the fin 104) than silicon oxide. In some embodiments, the gate sidewall spacers 116 may be used to offset subsequently formed doped regions, such as source / drain regions. The gate spacers 116 may further be used to design or modify the source / drain region profile.

[0019] After the formation of the gate sidewall spacers 116 is completed, source / drain structures 122 are formed on source / drain regions of the fin 104 that are not covered by the dummy gate structures 106 and the gate sidewall spacers 116. The resulting structure is shown in Fig. 5. In some embodiments, forming the source / drain structures 122 includes recessing source / drain regions of the fin 104 and then epitaxially growing semiconductor materials in the recessed source / drain regions of the fin 104.

[0020] The source / drain regions of the fin 104 may be recessed using a suitable selective etch process that attacks the semiconductor fin 104 but barely attacks the gate spacers 116 and the upper masks 114 of the dummy gate structures 106. Recessing the semiconductor fin 104 may be performed, for example, by dry chemical etching using a plasma source and an etching gas. The plasma source may be an inductively coupled plasma etch (ICR etch), a transformer-coupled plasma etch (TCP etch), an electron cyclotron resonance etch (ECR etch), a reactive ion etch (RIE etch), or the like, and the etching gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the semiconductor fin 104 at a faster etch rate than the gate spacers 116 and the top masks 114 of the dummy gate structures 106.In some further embodiments, the recessing of the semiconductor fin 104 may be performed by a wet chemical etch, such as an ammonium peroxide mixture (APM), NH4OH, tetramethylammonium hydroxide (TMAH), combinations thereof, or the like, which etches the semiconductor fin 104 at a faster etch rate than the gate spacers 116 and the upper masks 114 of the dummy gate structures 106. In some further embodiments, the recessing of the semiconductor fin 104 may be performed by a combination of dry chemical etching and wet chemical etching.

[0021] Once the recesses in the source / drain regions of fin 104 are created, source / drain epitaxial structures 122 are formed in the source / drain recesses in fin 104 using one or more epitaxial or epitaxial processes (Epi processes) that provide one or more epitaxial materials on semiconductor fin 104. During the epitaxial growth process, gate spacers 116 confine the one or more epitaxial materials to source / drain regions in fin 104. In some embodiments, the lattice constants of epitaxial structures 122 differ from the lattice constant of semiconductor fin 104 so that the channel region in fin 104 and between epitaxial structures 122 may be strained or stressed by epitaxial structures 122 to enhance charge carrier mobility of the semiconductor device and improve device performance.The epitaxial processes include CVD deposition techniques (e.g., PECVD, vapor phase epitaxy (VPE), and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial process may utilize gaseous and / or liquid precursors that interact with the composition of the semiconductor fin 104.

[0022] In some embodiments, the source / drain epitaxial structures 122 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or another suitable material. The source / drain epitaxial structures 122 may be doped in situ during the epitaxial process by introducing a doping species comprising: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drain epitaxial structures 122 are not doped in situ, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structures 122. In some example embodiments, the source / drain epitaxial structures 122 in an n-type transistor comprise SiP, while those in a p-type transistor comprise GeSnB and / or SiGeSnB.In embodiments with different device types, a mask, such as a photoresist, may be formed over n-type device regions while exposing p-type device regions, and p-epitaxial structures may be formed on the exposed fins 104 in the p-type device regions. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type device region while exposing the n-type device regions, and n-epitaxial structures may be formed on the exposed fins 104 in the n-type device region. The mask may then be removed.

[0023] Once the source / drain epitaxial structures 122 are formed, an annealing process may be performed to activate the p- or n-type dopants in the source / drain epitaxial structures 122. The annealing process may be, for example, a rapid thermal anneal (RTA), a laser anneal, a millisecond thermal anneal (MSA) process, or the like.

[0024] Next, Fig. 6, an interlayer dielectric (ILD) layer 126 is formed on the substrate 12. In some embodiments, a contact etch stop layer (CESL) is also formed prior to forming the ILD layer 126. In some examples, the CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials with a different etch selectivity than the ILD layer 126. The CESL may be formed by plasma-enhanced chemical vapor deposition (PECVD) and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 126 comprises materials such as oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectrics having a different etch selectivity than the CESL.The ILD layer 126 may be deposited using a PECVD process or other suitable deposition technique. In some embodiments, after the formation of the ILD layer 126, the wafer may be subjected to a high heat balance process to anneal the ILD layer 126.

[0025] In some examples, after the formation of the ILD layer 126, a planarization process may be performed to remove excess materials of the ILD layer 126. A planarization process may include, for example, a chemical mechanical planarization (CMP) process that removes portions of the ILD layer 126 (and the CESL, if present) that overlie the dummy gate structures 106. In some embodiments, the CMP process also removes the hard mask layers 112, 114 (as in Fig. 5) and exposes the dummy gate electrodes 110.

[0026] Next, as in Fig. 7 illustrates the remaining dummy gate structures 106 (see Fig. 6) is removed, resulting in gate trenches GT1 between corresponding gate sidewall spacers 116. The dummy gate structures 106 are removed using a selective etch process (e.g., selective dry etch, selective wet etch, or a combination thereof) that etches the materials in the dummy gate structures 106 at a faster etch rate than other materials (e.g., the gate sidewall spacers 116, the CESL, and / or the ILD layer 126).

[0027] Thereafter, exchange gate structures 130 are formed in the gate trenches GT1, as shown in Fig. 8. The gate structures 130 may be the final gates of the FinFETs. The final gate structures may each be a high-k / metal gate stack, but other compositions are also possible. In some embodiments, each of the gate structures 130 forms the gate associated with the three sides of the channel region provided by the fin 104. In other words, each of the gate structures 130 wraps around the fin 104 on three sides. In various embodiments, the high-k / metal gate structure 130 includes a gate dielectric layer 132 lining the gate trench GT1, a workfunction metal layer 134 formed over the gate dielectric layer 132, and a fill metal 136 formed over the workfunction metal layer 134 and filling a remainder of the gate trenches GT1. The gate dielectric layer 132 includes an interface layer (e.g.,a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. High-k gate dielectrics, as used and described herein, comprise dielectrics with a high dielectric constant, such as greater than that of thermal silicon oxide (~3.9). The work function metal layer 134 and / or the fill metal 136 used in the high-k / metal gate structures 130 may comprise a metal, a metal alloy, or a metal silicide. Formation of the high-k / metal gate structures 130 may include multiple deposition processes to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate materials.

[0028] In some embodiments, the interface layer of the gate dielectric layer 132 may include a dielectric, such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer of the gate dielectric layer 132 may include hafnium oxide (HfO2).Alternatively, the gate dielectric layer 132 may comprise other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations of which, contain.

[0029] The workfunction metal layer 134 may include workfunction metals to provide a suitable workfunction for the high-k / metal gate structures 130. For an n-type FinFET, the workfunction metal layer 134 may include one or more n-type workfunction metals (N-type metals). The n-type workfunction metals may include, for example, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials. On the other hand, in a p-type FinFET, the work function metal layer 134 may contain one or more p-type work function metals (P-metal).The p-work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials.

[0030] In some embodiments, the filler metal 136 may include, for example, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0031] Reference is now made to Fig. 9. An etch-back process is performed to etch back the replacement gate structures 130 and the gate spacers 116, resulting in recesses R1 above the etched-back gate structures 130 and the etched-back gate spacers 116. In some embodiments, a first selective etch process may first be performed to etch back the replacement gate structures 130 and lower the replacement gate structures 130 because the materials of the replacement gate structures 130 have a different etch selectivity than the gate spacers 116. Then, a second selective etch process is performed to lower the gate spacers 116. As a result, the upper surfaces of the replacement gate structures 130 may be at a different level than the upper surfaces of the gate spacers 116. In the illustrated embodiment as shown in Fig. 9, the replacement gate structures 130 have surfaces that are lower than the upper surfaces of the gate spacers 116. However, in some further embodiments, the upper surfaces of the replacement gate structures 130 may be at the same height as or higher than the upper surfaces of the gate spacers 116.

[0032] Subsequently, corresponding metal caps 138 are formed on the replacement gate structures 130 using a suitable process, such as CVD or ALD. In some embodiments, the metal caps 138 are formed on the replacement gate structures 130 using a bottom-up approach. For example, the metal caps 138 are selectively grown on the metal surface, such as the work function metal layer 134, and the fill metal 136, and therefore the sidewalls of the gate spacers 116 are substantially free of the growth of the metal caps 138. The metal caps 138 may be, for example, but are not limited to, substantially fluorine-free tungsten (FFW) films having a fluorine impurity content of less than 5 atomic percent and a chlorine impurity content of more than 3 atomic percent.The FFW films or FFW-containing films may be formed by ALD or CVD using one or more non-fluorine-based tungsten precursors, such as, but not limited to, tungsten pentachloride (WCl5) and tungsten hexachloride (WCl6). In some embodiments, portions of the metal caps 138 may overflow the gate dielectric layer 132, so that the metal caps 138 may also cover the exposed surface of the gate dielectric layers 132. Because the metal caps 138 are formed from the bottom up, their formation may be simplified, for example, by reducing repeated etch-back processes used to remove unwanted metal materials resulting from conformal growth.

[0033] In some embodiments where the metal caps 138 are formed using a bottom-up approach, the growth of the metal caps 138 has a different nucleation delay on metal surfaces (i.e., metals in gate structures 130) compared to dielectric surfaces (i.e., dielectrics in the gate spacers 116). The nucleation delay on the metal surface is shorter than on the dielectric surface. The difference in nucleation delay therefore enables selective growth on the metal surface. The present disclosure, in various embodiments, utilizes such selectivity to enable metal growth from the gate structures 130 while preventing metal growth on the gate spacers 116. As a result, the deposition rate of the metal caps 138 on the gate structures 130 is faster than on the spacers 116.In some embodiments, the resulting metal caps 138 have top surfaces that are lower than the top surfaces of the etched-back gate spacers 116. However, in some embodiments, the top surfaces of the metal caps 138 may be level with or higher than the top surfaces of the etched-back gate spacers 116.

[0034] Next, a dielectric cap layer 140 is deposited over the substrate 105 until the recesses R1 are overfilled, as shown in Fig. 10. The dielectric cap layer 140 includes SiN, SiC, SiCN, SiON, SiCON, a combination thereof, or the like, and is formed by a suitable deposition technique, such as CVD, plasma-enhanced CVD (PECVD), ALD, remote plasma ALD (RPALD), plasma-enhanced ALD (PEALD), a combination thereof, or the like. A CMP process is then performed to remove the cap layer outside the recesses R1, leaving portions of the dielectric cap layer 140 in the recesses R1 to serve as dielectric caps 142. The resulting structure is shown in Fig. 11 illustrates.

[0035] With reference to Fig. 12, source / drain contacts 144 are formed that extend through the ILD layer 126 (and the CESL, if present). The formation of the source / drain contacts 144 includes, for example and without limitation, performing one or more etch processes to form contact openings that extend through the ILD layer 126 to expose the source / drain epitaxial structures 122, depositing one or more metal materials that overfill the contact openings, and then performing a CMP process to remove excess metal materials outside the contact openings. In some embodiments, the one or more etch processes are selective etching that etches the ILD layer 126 at a faster etch rate than the etching of the dielectric caps 142 and the gate spacers 116.As a result, the selective etching is performed using the dielectric caps 142 and the gate spacers 116 as an etch mask, so that the contact openings and therefore the source / drain contacts 144 are formed self-aligned with the source / drain epitaxial structures 122 without using an additional photolithography process. In this case, the dielectric caps 142, which enable self-aligned formation of the source / drain contacts 144, may be referred to as self-aligned contact caps (SAC caps 142).

[0036] After the formation of the source / drain contacts 144 is completed, the dielectric caps 142 are treated in an oxygen-containing environment so that surface layers of the dielectric caps 142 are oxidized to form oxidized regions 1421 in the dielectric caps 142, while the remaining regions 1422 of the dielectric caps 142 are left unoxidized. The resulting structure is shown in Fig. 13. The treatment process may include an O2 plasma treatment in which the oxygen-containing gas is introduced into a process chamber in which the plasma is generated from the oxygen-containing gas. By way of example and without limitation, the semiconductor substrate 12 is coated with the Fig. 12 loaded into a plasma tool and exposed to a plasma environment formed by oxygen gas (O2 gas) or a gas mixture of O2 gas and one or more of Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z-Gas (where x, y, and z are greater than zero and not greater than nine), NF3 gas, carbonyl sulfide gas (COS gas), and SO2 gas. The plasma etching environment has a pressure between approximately 10 and approximately 100 mTorr, and the plasma is generated with an RF power between approximately 50 and approximately 1000 watts.

[0037] As a result of the O2 plasma treatment, oxidation occurs in the upper surfaces of the dielectric caps 142, resulting in the oxidized regions 1421. In some embodiments, for a 3 nm technology node, a thickness T1 of the oxidized regions 1421 is in a range from approximately 0.1 nm to approximately 5.0 nm (approximately 1 angstrom to approximately 50 angstroms). If the thickness T1 is less than approximately 0.1 nm (1 angstrom), the oxidized regions 1421 may be too thin to slow down or even stop a subsequent etch process. Furthermore, since the oxidized regions 1421 of the dielectric caps 142 have a thickness T1 of no more than approximately 5.0 nm (50 angstroms) in some embodiments, they can of course be pierced without etch stop concerns (i.e., without concern that the etch process will pass through the oxidized regions 1421 in the scenario of Fig. 19). For other technology nodes, such as 20 nm nodes, 16 nm nodes, 10 nm nodes, 7 nm nodes, and / or 5 nm nodes, the thickness T1 may range from approximately 1 nm to approximately 20 nm. The thicknesses of the oxidized regions 1421 may be controlled, by way of example and without limitation, by using RF power and / or bias power of the O2 plasma treatment. In some embodiments, the unoxidized region 1422 is thicker than the oxidized region 1421.

[0038] In some embodiments where the dielectric caps 142 are made of SiN, the O2 plasma treatment results in oxidized nitride regions (silicon oxynitride (SiO x N y)) 1421 in the dielectric caps 142 and an unoxidized nitride region 1422 under the oxidized nitride regions 1421. The oxidized nitride regions 1421 may form distinguishable interfaces with the unoxidized nitride region 1422 because they have different material compositions (e.g., the oxidized nitride regions 1421 have a higher oxygen atom content and / or a higher oxygen-to-nitrogen atom ratio than the unoxidized nitride region 1422).

[0039] In some embodiments, the oxidized region 1421 may have an oxygen concentration gradient due to the plasma treatment. For example, the oxygen atom fraction in the oxidized region 1421 may decrease in a depth direction from the top surfaces of the dielectric caps 142. In some embodiments where the dielectric caps 142 are made of silicon nitride, the oxygen-to-nitrogen atom ratio in the oxidized region 1421 may decrease in the depth direction from the top surfaces of the dielectric caps 142.

[0040] In some embodiments, during the O2 plasma treatment, upper portions of the source / drain contacts 144 may be inadvertently oxidized to form metal oxide regions 1441 in the source / drain contacts 144, while the remaining metal regions 1442 of the source / drain contacts 144 are left unoxidized. The resulting structure is shown in Fig. 13. The metal oxide regions 1441 may form distinguishable interfaces with the unoxidized metal region 1442 because they have different material compositions (e.g., the metal oxide regions 1441 may have a higher oxygen atom content and / or a higher oxygen-to-nitrogen atom ratio than the unoxidized metal region 1442).

[0041] In some embodiments, a thickness T2 of the metal oxide regions 1441 ranges from approximately 0.1 nm to approximately 5.0 nm (approximately 1 angstrom to approximately 50 angstroms). Due to the material difference between the source / drain contacts 144 and the dielectric caps 142, the oxidation of the metal oxide regions 1441 and the oxidized region 1421 may vary. For example, the thickness T1 of the oxidized region 1421 may be greater than, substantially equal to, or less than the thickness T2 of the metal oxide regions 1441.

[0042] In some embodiments, the metal oxide regions 1441 may have an oxygen concentration gradient due to the plasma treatment. For example, the oxygen atom fraction in the metal oxide regions 1441 may decrease in a depth direction from the top surfaces of the source / drain contacts 144. In some embodiments where the source / drain contacts 144 are made of metal, the oxygen-to-metal atom ratio in the metal oxide regions 1441 may decrease in the depth direction from the top surfaces of the source / drain contacts 144.

[0043] Once the oxidized region 1421 (and the metal oxide regions 1441) are formed, Fig. 14, a mid-contact etch stop layer (MCESL) 146 is formed over the source / drain contacts 144 and the dielectric caps 142. The MCESL 146 may be formed by a PECVD process and / or other suitable deposition processes. In some embodiments, the MCESL 146 is a silicon nitride layer and / or other suitable materials with a different etch selectivity than a subsequently formed ILD layer (as in Fig. 15) and the oxidized region 1421.

[0044] With reference to Fig. 15, another ILD layer 148 is formed over the MCESL 146. In some embodiments, the ILD layer 148 comprises materials such as oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectrics with a different etch selectivity than the MCESL 146. In certain embodiments, the ILD layer 148 is formed from silicon oxide (SiO x ). The ILD layer 148 may be deposited by a PECVD process or other suitable deposition technique.

[0045] With reference to Fig. 16A, the ILD layer 148 is patterned to form via openings O1 extending through the ILD layer 148 using a first etch process (also called a via etch process) ET1. The etch duration of the via etch process ET1 is controlled to allow piercing of the ILD layer 148, while the MCESL 146 serves as an etch stop layer for the etch process ET1. In some embodiments, a photolithography process is performed prior to the via etch process ET1 to define expected top-view structures of the via openings O1. The photolithography process may, for example, include spinning a photoresist layer over the ILD layer 148, as shown in Fig. 15, performing post-exposure burn-in processes and developing the photoresist layer to form a patterned mask with the top-view structures of the via openings O1. In some embodiments, patterning the photoresist to form the patterned mask may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process.

[0046] In some embodiments, the via etching process ET1 is an anisotropic etching process, such as a plasma etching. In plasma etching, for example, the semiconductor substrate 12 is Fig. 15 is loaded into a plasma tool and exposed to a plasma environment created by RF or microwave power in a gas mixture of a fluorine-containing gas such as C4F8, C5F8, C4F6, CHF3, or a similar species, an inert gas such as argon or helium, an optional weak oxidizer such as O2 or CO, or a similar species, for a time sufficient to etch through the ILD layer 148 and form the via openings O1. A plasma generated in a gas mixture containing C4F6, CF4, CHF3, O2, and argon can be used to etch through the ILD layer 148. The plasma etching environment has a pressure between about 10 and about 100 mTorr, and the plasma is generated with an RF power between about 50 and about 1000 watts.

[0047] In some embodiments, the aforementioned etchants and etch conditions of the via etch process ET1 are selected such that the MCESL 146 (e.g., SiN) has a slower etch rate than the ILD layer 148 (e.g., SiO x). In this way, the MCESL 146 can act as a detectable etch endpoint, which in turn prevents overetching and therefore etching of the MCESL 146. In other words, the via etch process ET1 is set to etch silicon oxide at a faster etch rate than the etching of silicon nitride. It has been observed that the etch rate of silicon nitride increases when the etch plasma is generated from a gas mixture containing a hydrogen gas (H2 gas). As a result, according to some embodiments of the present disclosure, the via etch process ET1 is performed using a hydrogen-free gas mixture to inhibit the silicon nitride etch rate. In other words, the plasma in the via etch process ET1 is generated in a gas mixture without hydrogen gas (H2 gas). In this way, the etch rate of silicon nitride is kept low in the via etch process ET1, which in turn inhibits the etching of silicon oxide (i.e., ILD material) with a faster etching rate than the etching of silicon nitride (i.e. MCESL material).

[0048] In some embodiments, as shown in Fig. 16A, the via openings O1 have a tapered sidewall profile due to the nature of the anisotropic etching. However, in some further embodiments, the etching conditions may be finely tuned to enable the via openings O1 to have a vertical sidewall profile, as shown in Fig. 16B is illustrated.

[0049] With reference to Fig. 17A, the MCESL 146 is patterned to form via openings O2 extending through the MCESL 146 using a second etch process (also called a via etch process) ET2. The etch duration of the via etch process ET2 is controlled to allow piercing of the MCESL 146, while the oxidized region 1421 serves as an etch stop layer for the etch process ET2.

[0050] In some embodiments, the etch process ET2 is an anisotropic etch process, such as a plasma etch (e.g., inductively coupled plasma (ICP), capacitively coupled plasma (CCP), or the like) using a different etchant and / or different etch conditions than in the via etch process ET1. The etchant and / or the etch conditions of the etch process ET2 are selected such that the oxidized region 1421 has a slower etch rate than the MCESL 146. In this way, the oxidized region 1421 may inhibit or slow down the overetching in the dielectric cap layer 140 during the etch process ET2. During plasma etching, for example, the semiconductor substrate 12 is exposed to the Fig. 16A or Fig. 16B is loaded into a plasma tool and exposed to a plasma environment generated by RF or microwave power in a gas mixture of a fluorine-containing gas (e.g., CHF3, CF4, C2F2, C4F6, C x Hy F z (x, y, z are greater than zero and not greater than nine) or a similar species), a hydrogen-containing gas (e.g., H2), an inert gas (e.g., argon or helium) for a time sufficient to etch through the MCESL 146, but not the oxidized region 1421. The plasma etching ambient has a pressure between about 10 and about 100 mTorr, and the plasma is generated with an RF power between about 50 and about 1000 watts.

[0051] Plasma generated from a hydrogen-containing gas mixture can etch silicon nitride at a faster etch rate than etching silicon oxynitride, and therefore, the etching process ET2 using a hydrogen-containing gas mixture etches the oxidized region 1421 at a slower etch rate than etching the MCESL 146. In this way, the oxidized region 1421 can prevent or slow over-etching during the etching process ET2. In some embodiments, the etching process ET2 uses a gas mixture of CHF3 gas and H2 gas with a flow rate ratio of CHF3 gas to H2 gas of about 1:1 to about 1:100. In some embodiments, the etching process ET2 uses a gas mixture of CF4 gas and H2 gas with a flow rate ratio of CF4 gas to H2 gas of about 1:1 to about 1:100.An excessively high H2 gas flow rate may result in an etch rate that is too fast when etching through the MCESL 146, which in turn may result in a non-negligible deflection profile in the MCESL 146. A too low H2 gas flow rate may result in insufficient etch selectivity between the MCESL 146 and the oxidized region 1421. In some embodiments, the metal oxide regions 1441 may be removed during the etch process ET2, so that the openings O2 expose the unoxidized regions 1442 of the source / drain contacts 144, as shown in FIGS. Fig. 17C and Fig. 17D. Furthermore, a portion of the oxidized region 1421 of the dielectric caps 142 is consumed in the etching process ET2, so that the unoxidized region 1422 of the dielectric caps 142 is exposed.

[0052] In some embodiments, due to process variations, some misalignment (or overlay error) may exist between the via openings O2 and the source / drain contacts 144. Or, in some embodiments, the size (or width) of the via openings O2 may be larger than the size (or width) of the source / drain contacts 144. In any case, the via openings O2 may expose portions of the oxidized regions 1421. However, due to the etch selectivity between the MCESL 146 and the oxidized regions 1421, the oxidized regions 1421 may slow down or even stop the etch process for forming the via openings O2, which in turn prevents over-etching of the dielectrics (e.g., the dielectric caps 142) and results in a lower risk of leakage currents.

[0053] In some embodiments, as shown in the Fig. 17A and Fig. 17C, the via openings O2 have a tapered sidewall profile due to the nature of the anisotropic etching of the etching process ET2. However, in some further embodiments, the etching conditions of the etching process ET2 and / or the preceding via etching process ET1 may be finely tuned such that the via openings O2 have a perpendicular sidewall profile, as shown in the Fig. 17B and Fig. 17D is illustrated.

[0054] With reference to Fig. 18A, source / drain vias 150 are then formed in the via openings O1 and O2 to establish a physical and electrical connection with the source / drain contacts 144. The source / drain vias 150 are formed, for example, by depositing one or more metal materials that overfill the via openings O1 and O2, followed by a CMP process to remove excess metal materials outside the via openings O1 and O2. As a result of the CMP process, the source / drain vias 150 have top surfaces that are substantially coplanar with the ILD layer 148. The source / drain vias 150 may comprise metal materials such as copper, aluminum, tungsten, combinations thereof, or the like, and may be formed using PVD, CVD, ALD, or the like.In some embodiments, the source / drain vias 150 may further include one or more barrier / adhesion layers (not shown) to protect the ILD layer 148 and / or the MCESL 146 from metal diffusion (e.g., copper diffusion). The one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed by PVD, CVD, ALD, or the like.

[0055] The source / drain vias 150 inherit the geometry of the via openings O1 and O2. In other words, the sidewalls of the source / drain via openings 150 extend linearly through an entire thickness of the ILD layer 148 and an entire thickness of the MCESL 146. More specifically, a source / drain via 150 forms a first linear interface 1501 with the ILD layer 148 and a second linear interface 1502 with the MCESL 146. The second linear interface 1502 extends downward from the first linear interface 1501, and the linear interfaces 1501 and 1502 are aligned with each other.

[0056] In some embodiments, as shown in the Fig. 18A and Fig. 18C, the source / drain vias 150 have a tapered sidewall profile due to the nature of the anisotropic etching of the etch process ET2. However, in some further embodiments, the etch conditions of the etch process ET2 may be finely tuned to enable the via openings O1, and therefore the source / drain vias 150, to have a vertical sidewall profile, as shown in FIGS. Fig. 18B and Fig. 18D. In the Fig. 18C and Fig. 18D, the source / drain via 150 has a stepped surface with an upper step contacting the oxidized regions 1421 and a lower step contacting the unoxidized region 1442 of the source / drain contact 144.

[0057] The Fig. 19 to 23B illustrate exemplary cross-sectional views of various stages for fabricating an integrated circuit structure 100 according to some further embodiments of the present disclosure. It should be understood that for further embodiments of the method, additional operations may be performed before, during, and after the steps described in FIGS. Fig. 19 to 23B, and that some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchangeable. In the following embodiments, the same or similar configurations, materials, processes, and / or operations as in the Fig. 1 to 18D and the detailed explanation may be omitted.

[0058] After the Fig. 15 is formed, the ILD layer 148 is patterned to form at least one gate contact opening O3 extending downward through the ILD layer 148, the MCESL 146 and the dielectric cap 142 to the metal cap 138. The resulting structure is shown in Fig. 19. The ILD layer 148 can be patterned using suitable photolithography and etching techniques.

[0059] Next, as in Fig. 20, a patterned mask layer M1 is formed over the substrate 12 to fill the gate contact opening O3. The patterned mask layer M1 has an opening O4 perpendicularly above a source / drain contact 144. In some embodiments, the patterned mask layer M1 may be a photoresist mask formed by a suitable photolithography process. The photolithography process may, for example, involve spin-coating a photoresist layer over the structure, as shown in Fig. 19, performing post-exposure burn-in processes and developing the photoresist layer to form the patterned mask layer M1. In some embodiments, patterning the photoresist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process.

[0060] With reference to Fig. 21, wherein the patterned mask layer M1 is present, a via etch process ET3 is performed to form a via opening O5 extending through the ILD layer 148. The etch duration of the via etch process ET3 is controlled such that the ILD 148 is removed and ends at the MCESL 146. Process details regarding the via etch process ET3 were previously described with respect to the via etch process ET1 and are therefore not repeated herein for brevity.

[0061] With reference to Fig. 22, an etch process ET4 is performed to etch the MCESL 146 and thus recess the via opening O5 downward into the metal oxide region 1441 of the source / drain contact 144 and a portion of the oxidized regions 1421 of the dielectric cap 142 between the source / drain contact 144 and the patterned mask layer M1. As a result of the etch process ET4, the metal oxide region 1441 of the source / drain contact 144 and the oxidized regions 1421 of the dielectric cap 142 are exposed at the bottom surfaces of the recessed via openings O5. Process details regarding the etch process ET4 were previously described with respect to the etch process ET2 and are therefore not repeated herein for brevity.

[0062] After the etching process ET4 is completed, the patterned mask layer M1 is removed from the gate contact opening O3 by ashing and / or wet stripping, and then a butt contact (or a butt via) 152 is formed to fill the via opening O5 and the gate contact opening O4. The resulting structure is shown in Fig. 23A and Fig. 23B. The details regarding the materials and manufacturing process of the butt contact 152 are similar to the details regarding the source / drain via openings 150 and are therefore not repeated here for brevity.

[0063] The butt contact 152 inherits the geometry of the via openings O3 and O5. In other words, the sidewalls of the butt contact 152 extend linearly through an entire thickness of the ILD layer 148 and an entire thickness of the MCESL 146. More specifically, the butt contact 152 forms a first linear interface 1521 with the ILD layer 148 and a second liner interface 1522 with the MCESL 146. The second linear interface 1522 extends downward from the first linear interface 1521, and the linear interfaces 1521 and 1522 are aligned with each other.

[0064] In some embodiments, a portion of the metal oxide region 1441 of the source / drain contact 144 (and a portion of the oxidized region 1421 of the dielectric cap 142) is formed during the etch process ET4 in Fig. 22. As such, the butt contact 152 contacts as shown in Fig. 23B shows the oxidized regions 1421 and the unoxidized region 1442 of the source / drain contact 144.

[0065] The Fig. 24 to 42D illustrate perspective views and cross-sectional views of intermediate stages in the formation of an integrated circuit structure 200 according to some embodiments of the present disclosure. The transistors formed may include a p-type transistor (e.g., a p-GAA FET) and an n-type transistor (e.g., an n-FAA FET) according to some embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. However, it should be understood that additional operations may be performed before, during, and after the processes performed by the Fig. 24 to 42D, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable.

[0066] The Fig. 24, Fig. 25, Fig. 26, Fig. 27A, Fig. 28A, Fig. 29A and Fig. 30A are perspective views of some embodiments of the integrated circuit structure 200 at intermediate stages during manufacturing. Fig. 27B, 28B, 29B, 30B, 31-33, 34A, 35-42D are cross-sectional views of some embodiments of the integrated circuit structure 200 at intermediate stages during manufacture along a first section (e.g., section XX in Fig. 27A), which runs along a longitudinal direction of the channel and perpendicular to an upper surface of the substrate. Fig. 34B is a cross-sectional view of some embodiments of the integrated circuit structure 200 at intermediate stages during manufacture along a second section (e.g., section YY in Fig. 27A), which is located in the gate region and perpendicular to the longitudinal direction of the channel.

[0067] As in Fig. 24, an epitaxial stack 220 is formed over the substrate 210. In some embodiments, the substrate 210 may include silicon (Si). Alternatively, the substrate 210 may include germanium (Ge), silicon germanium (SiGe), a III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or a combination thereof), or other suitable semiconductor materials. In some embodiments, the substrate 210 may include a semiconductor-on-insulator (SOI) structure, such as a buried dielectric layer. Alternatively, the substrate 210 may also include a buried dielectric layer, such as a buried oxide layer (BOX) formed by a process referred to as separation by implantation of oxygen (SIMOX) technology, wafer bonding, SEG, or another suitable process.

[0068] The epitaxial stack 220 includes epitaxial layers 222 of a first composition, with epitaxial layers 224 of a second composition sandwiched between them. The first and second compositions may be different. In some embodiments, the epitaxial layers 222 are SiGe and the epitaxial layers 224 are silicon (Si). However, other embodiments are possible, including those providing a first composition and a second composition with different oxidation rates and / or different etch selectivity. In some embodiments, the epitaxial layers 222 include SiGe, and when the epitaxial layers 224 include Si, the Si oxidation rate of the epitaxial layers 224 is lower than the SiGe oxidation rate of the epitaxial layers 222.

[0069] The epitaxial layers 224, or portions thereof, may form nanofoil channels of the multigate transistor. The term nanofoil is used herein to refer to any material portion with nanoscale or even microscale dimensions that has an elongated shape, regardless of the cross-sectional shape of that portion. Therefore, this term refers to both circular and substantially circular elongated material portions, as well as bar- or rod-shaped material portions that have, for example, a cylindrical shape or a substantially rectangular cross-section. The use of the epitaxial layers 224 to define a channel or channels of a device is further described below.

[0070] It should be noted that three layers of the epitaxial layers 222 and three layers of the epitaxial layers 224 are arranged alternately, as shown in Fig. 24, which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It should be understood that any number of epitaxial layers may be formed in the epitaxial stack 220; the number of layers depends on the desired number of channel regions for the transistor. In some embodiments, the number of epitaxial layers 224 is between 2 and 10.

[0071] As described in more detail below, the epitaxial layers 224 may serve as channel region(s) for a subsequently formed multigate device, and the thickness is chosen based on device performance considerations. The epitaxial layers 222 in a channel region(s) may be removed and serve to define a vertical spacing between adjacent channel regions for a subsequently formed multigate device, and the thickness is chosen based on device performance considerations. Accordingly, the epitaxial layers 222 may also be referred to as sacrificial layers, and the epitaxial layers 224 may also be referred to as channel layers.

[0072] The epitaxial growth of the layers of stack 220 may be performed, for example, by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers, such as epitaxial layers 224, comprise the same material as substrate 210. In some embodiments, epitaxially grown layers 222 and 224 comprise a different material than substrate 210. As mentioned above, in at least some examples, epitaxial layers 222 comprise an epitaxially grown silicon germanium (SiGe) layer, and epitaxial layers 224 comprise an epitaxially grown silicon (Si) layer.Alternatively, in some embodiments, each of the epitaxial layers 222 and 224 may comprise other materials, such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As described, the materials of the epitaxial layers 222 and 224 may be selected based on providing different oxidation and / or etch selectivity properties. In some embodiments, the epitaxial layers 222 and 224 are substantially dopant-free (i.e., having an extrinsic dopant concentration of approximately 0 cm-). -3 up to about 1×10 18 cm -3 ), for example, no intentional doping is carried out during the epitaxial growth process.

[0073] With reference to Fig. 25, a plurality of semiconductor fins 230 extending from the substrate 210 are formed. In various embodiments, each of the fins 230 comprises a substrate portion 212 formed from the substrate 210 and portions of each of the epitaxial layers of the epitaxial stack, including the epitaxial layers 222 and 224. The fins 230 may be formed using suitable processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, which enables the formation of structures having, for example, pitches smaller than what is otherwise achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process.Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 230 by etching the initial epitaxial stack 220. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0074] In the illustrated embodiment as shown in Fig. 24 and Fig. 25, prior to patterning the fins 230, a hard mask (HM) layer 910 is formed over the epitaxial stack 220. In some embodiments, the HM layer comprises an oxide layer 912 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 914 (e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer. The oxide layer 912 may act as an adhesion layer between the epitaxial stack 220 and the nitride layer 914 and serve as an etch stop layer for the etching of the nitride layer 914. In some examples, the HM oxide layer 912 comprises thermally grown oxide, chemical vapor deposition (CVD) deposited oxide, and / or atomic layer deposition (ALD) deposited oxide. In some embodiments, the HM nitride layer 914 is deposited on the HM oxide layer 912 by CVD and / or other suitable techniques.

[0075] The fins 230 may then be formed using suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer (not shown) over the HM layer 910, exposing the photoresist to a pattern, performing post-exposure bake processes, and developing the photoresist to form a patterned mask with the photoresist. In some embodiments, patterning the photoresist to form the patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process using light in the EUV region with a wavelength of, for example, approximately 1-200 nm.The patterned mask may then be used to protect regions of the substrate 210 and layers formed thereon, while an etching process through the HM layer 910, through the epitaxial stack 220, and into the substrate 210 forms trenches 202 in unprotected regions, leaving the plurality of extending fins 230. The trenches 202 may be etched using a dry etch (e.g., reactive ion etch), a wet etch, and / or a combination thereof. Numerous other embodiments of methods for forming the fins on the substrate may also be used, including, for example, defining the fin region (e.g., through mask or isolation regions) and epitaxially growing the epitaxial stack 220 in the shape of the fins 230.

[0076] Next, as in Fig. 26, the isolation regions 240 are formed, which are disposed between the fins 230. The material and process details for the isolation regions 240 are similar to those of the previously discussed isolation regions 14 and are therefore not repeated for brevity.

[0077] Reference is made to the Fig. 27A and Fig. 27B. The dummy gate structures 250 are formed over the substrate 210 and are disposed at least partially over the fins 230. The portions of the fins 230 underlying the dummy gate structures 250 may be referred to as the channel region. The dummy gate structures 250 may also define source / drain (S / D) regions of the fins 230, such as the regions of the fins 230 adjacent to and on opposite sides of the channel regions.

[0078] In the dummy gate formation process, a dummy gate dielectric layer 252 is first formed over the fins 230. Subsequently, a dummy gate electrode layer 254 and a hard mask, which may include multiple layers 256 and 258 (e.g., an oxide layer 256 and a nitride layer 258), are formed over the dummy gate dielectric layer 252. The hard mask is then patterned, followed by patterning the dummy gate electrode layer 252 using the patterned hard mask as an etch mask. In some embodiments, after patterning the dummy gate electrode layer 254, the dummy gate dielectric layer 252 is removed from the S / D regions of the fins 230. The etching process may include a wet etch, a dry etch, and / or a combination thereof.The etching process is selected such that the dummy gate dielectric layer 252 is selectively etched without substantially etching the fins 230, the dummy gate electrode layer 254, the oxide mask layer 256, and the nitride mask layer 258. The materials of the dummy gate dielectric layer and the dummy gate electrode layer are similar to those of the previously described dummy gate dielectric layer 108 and the dummy gate electrode layer 110 and are therefore not repeated for brevity.

[0079] After the formation of the dummy gate structures 250 is complete, gate spacers 260 are formed on sidewalls of the dummy gate structures 250. For example, a spacer material layer is applied to the substrate 210. The spacer material layer may be a conformal layer that is subsequently etched back to form gate sidewall spacers. In the illustrated embodiment, a spacer material layer 260 is conformally disposed on the top and sidewalls of the dummy gate structures 250. The spacer material layer 260 may comprise a dielectric such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and / or combinations thereof. In some embodiments, the spacer material layer 260 comprises multiple layers, such as a first spacer layer 262 and a second spacer layer 264 (illustrated in Fig. 27B) formed over the first spacer layer 262. The spacer material layer 260 may be formed, for example, by depositing a dielectric over the gate structures 250 using suitable deposition processes. An anisotropic etch process may then be performed on the deposited spacer material layer 260 to expose portions of the fins 230 that are not covered by the dummy gate structure 250 (e.g., in source / drain regions of the fins 230). Portions of the spacer material layer directly over the dummy gate structure 250 may be completely removed by this anisotropic etch process. Portions of the spacer material layer at the sidewalls of the dummy gate structure 250 may remain and form gate sidewall spacers, which are referred to as the gate spacers 260 for convenience. It is noted that although the gate spacers 260 are shown in the cross-sectional view of Fig. 27B Multilayer structures are, in the perspective view of Fig. 27A are illustrated as single-layer structures for simplicity.

[0080] As in the Fig. 28A and Fig. 28B, exposed portions of the semiconductor fins 230 that extend laterally beyond the gate spacers 260 (e.g., in source / drain regions of the fins 230) may then be etched using, for example, an anisotropic etch process that uses the dummy gate structure 250 and the gate spacers 260 as an etch mask, resulting in recesses R2 in the semiconductor fins 230 and between corresponding dummy gate structures 250. After the anisotropic etch, end surfaces of the epitaxial layers 222 and the channel layers 224 may be aligned with the corresponding outermost sidewalls of the gate spacers 260 due to the anisotropic etching. In some embodiments, the anisotropic etching may be performed by a dry chemical etch using a plasma source and a reactive gas.The plasma source may be an inductively coupled plasma (ICR) source, a transformer-coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, or the like, and the reaction gas may be, for example, a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, or the like), a chloride-based gas (e.g., Cl2), hydrogen bromide gas (HBr), oxygen gas (O2), or the like, or combinations thereof.

[0081] Next, the Fig. 29A and Fig. 29B, the epitaxial layers 222 are recessed laterally or horizontally using suitable etching techniques, such that lateral recesses R3 result vertically between the corresponding channel layers 224. This operation may be performed using a selective etching process. By way of example and without limitation, the epitaxial layers 222 are made of SiGe and the channel layers 224 are made of silicon, which enables the selective etching of the epitaxial layers 222. In some embodiments, the selective wet etch comprises an APM etch (e.g., ammonia hydroxide-hydrogen peroxide mixture) that etches SiGe at a faster etch rate than it etches Si. In some embodiments, the selective etch comprises a SiGe oxidation followed by a SiGeO x -removal. The oxidation can be carried out, for example, by O3 Clean and then SiGeO x be removed by an etchant such as NH4OH, which selectively removes SiGeO xat a faster etch rate than it etches Si. Because the oxidation rate of Si is much lower (sometimes 30 times lower) than that of SiGe, the channel layers 224 are not significantly etched by the process of laterally recessing the epitaxial layers 222. As a result, the channel layers 224 extend laterally beyond the opposite end faces of the epitaxial layers 222.

[0082] In the Fig. 30A and Fig. 30B, an inner spacer material layer 270 is formed to fill the recesses R3 created by the lateral etching of the epitaxial layers 222, as described above with reference to the Fig. 29A and Fig. 29B. The inner spacer material layer 270 may be a low-k dielectric, such as SiO2, SiN, SiCN, or SiOCN, and may be formed by a suitable deposition process, such as ALD. After deposition of the inner spacer material layer 270, an anisotropic etch process may be performed to trim the deposited inner spacer material 270 such that only portions of the deposited inner spacer material 270 remain, filling the recesses R3 left by the lateral etch of the epitaxial layers 222. The portions of the deposited inner spacer material remaining after the trimming process are referred to as inner spacers 270 for convenience. The inner spacers 270 serve to isolate metal gates from the source / drain regions formed in subsequent processing. In the example of Fig. 30A and Fig. 30B, the side walls of the inner spacers 270 are aligned with the side walls of the channel layers 224.

[0083] In Fig. 31, source / drain epitaxial structures 280 are formed over the source / drain regions S / D of the semiconductor fins 230. The source / drain epitaxial structures 280 may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins 230. During the epitaxial growth process, the dummy gate structures 250, gate sidewall spacers 60, and the inner spacers 270 confine the source / drain epitaxial structures 280 to the source / drain regions S / D. The material and process details about the source / drain epitaxial structures 280 of GAA-FETs are similar to the source / drain epitaxial structures 122 of FinFETs described previously and are therefore not repeated for brevity.

[0084] In Fig. 32, an interlayer dielectric (ILD) layer 310 is formed on the substrate 210. In some embodiments, a contact etch stop layer (CESL) is also formed prior to forming the ILD layer 310. The material and process details about the CESL and the ILD layer 310 are similar to those of the CESL 124 and the ILD layer 126 and are therefore not repeated for brevity. In some examples, after the ILD layer 310 is deposited, a planarization process may be performed to remove excess materials of the ILD layer 310. For example, a planarization process includes a chemical mechanical planarization (CMP) process in which portions of the ILD layer 310 (and the CESL layer, if present) overlying the dummy gate structures 250 are removed and a top surface of the integrated circuit structure 200 is planarized.In some embodiments, the CMP process also removes the hard mask layers 256, 258 (as shown in . Fig. 31) and exposes the dummy gate electrode layer 254.

[0085] After that, the dummy gate structures 250 (as in Fig. 32) and then the epitaxial layers (ie, sacrificial layers) 222 (as shown in Fig. 32). The resulting structure is shown in Fig. 33. In some embodiments, the dummy gate structures 250 are removed using a selective etch process (e.g., selective dry etch, selective wet etch, or a combination thereof) that etches the materials in the dummy gate structures 250 at a faster etch rate than other materials (e.g., the gate sidewall spacers 260 and / or the ILD layer 310), thus resulting in gate trenches GT2 between corresponding gate sidewall spacers 260 with the epitaxial layers 222 exposed in the gate trenches GT2. Subsequently, the epitaxial layers 222 in the gate trenches GT2 are removed using another selective etch process that etches the epitaxial layers 222 at a faster etch rate than the channel layers 224, thus forming openings O6 between adjacent epitaxial layers (i.e., channel layers) 224.In this way, the epitaxial layers 224 become nanofoils suspended above the substrate 210 and between the source / drain epitaxial structures 280. This operation is also referred to as a channel release process. During this intermediate processing operation, the openings O6 between the epitaxial layers (i.e., nanofoils) 224 may be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the epitaxial layers 224 may also be referred to as nanowires, nanoplates, and nanorings depending on their geometry. In some other embodiments, the epitaxial layers 224 may be trimmed to, for example, a substantially rounded shape (i.e., cylindrical) due to the selective etching process for completely removing the epitaxial layers 222. In this case, the resulting epitaxial layers 224 may be referred to as nanowires.

[0086] In some embodiments, the epitaxial layers 222 are removed using a selective wet etching process. In some embodiments, the epitaxial layers 222 are SiGe and the epitaxial layers 224 are silicon, which enables the selective removal of the epitaxial layers 222. In some embodiments, the selective wet etch comprises an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some embodiments, the selective removal comprises a SiGe oxidation followed by a SiGeO x -removal. The oxidation can be carried out, for example, by O3 Clean and then SiGeO x be removed by an etchant such as NH4OH, which selectively removes SiGeO xat a faster etching rate than it etches Si. Since the oxidation rate of Si is much lower (sometimes 30 times lower) than the oxidation rate of SiGe, the channel layers 224 cannot be significantly etched by the channel release process. It can be seen that both the channel release process and the preceding operation of lateral recessing of sacrificial layers (the operation as shown in the Fig. 29A and Fig. 29B) may use a selective etch process that etches SiGe at a faster etch rate than Si, and therefore, in some embodiments, these two operations may use the same etch chemistry. In this case, the etch time / duration of the channel release operation is longer than the etch time / duration of the preceding lateral sacrificial layer recess operation, so that the SiGe sacrificial layers are completely removed.

[0087] With reference to the Fig. 34A and Fig. 34B, the replacement gate structures 320 are formed in the gate trenches GT2 to surround each of the epitaxial layers 224 suspended in the gate trenches GT2. The gate structure 320 may be the final gate of a GAA-FET. The final gate structure may be a high-k / metal gate stack, but other compositions are possible. In some embodiments, each of the gate structures 320 forms the gate associated with the multi-channels provided by the multiple epitaxial layers 224. The high-k / metal gate structures 320 are formed within the openings O6 (as in Fig. 34A) provided by the exposure of the epitaxial layers 224. In various embodiments, the high-k / metal gate structure 320 includes a gate dielectric layer 322 formed around the epitaxial layers 224, a workfunction metal layer 324 formed around the gate dielectric layer 322, and a fill metal 326 formed around the workfunction metal layer 324 and filling a remainder of the gate trenches GT2. The gate dielectric layer 322 includes an interface layer (e.g., a silicon oxide layer) and a high-k gate dielectric layer over the interface layer. High-k gate dielectrics, as used and described herein, include dielectrics with a high dielectric constant, such as greater than that of thermal silicon oxide (~3.9).The work function metal layer 324 and / or the fill metal layer 326 used within the high-k / metal gate structures 320 may comprise a metal, a metal alloy, or a metal silicide. Fabrication of the high-k / metal gate structures 320 may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excess gate materials. As shown in a cross-sectional view of FIG. Fig. 34B illustrates a longitudinal axis of a high-k / metal gate structure 320. The high-k / metal gate structure 320 surrounds each of the epitaxial layers 224 and is therefore referred to as the gate of a GAA-FET. Materials and process details about the gate structures 320 of GAA-FETs are similar to those of the gate structures 130 of FinFETs and are therefore not repeated for brevity.

[0088] In Fig. 35, an etch-back process is performed to etch back the replacement gate structures 320 and the gate spacers 260, resulting in recesses above the etched-back gate structures 320 and the etched-back gate spacers 260. In some embodiments, the upper surfaces of the replacement gate structures 320 may be at a different level than the upper surfaces of the gate spacers 260, since the materials of the replacement gate structures 320 have a different etch selectivity than the gate spacers 260. In the illustrated embodiment as shown in Fig. 35, the replacement gate structures 320 have surfaces that are lower than the upper surfaces of the gate spacers 260. However, in some further embodiments, the upper surfaces of the replacement gate structures 320 may be at the same height as or higher than the upper surfaces of the gate spacers 260.

[0089] Then, corresponding metal caps 330 are formed on the replacement gate structures 320 by a suitable process, such as CVD or ALD. The metal caps 330 may be, for example, but are not limited to, substantially fluorine-free tungsten (FFW) films having a fluorine impurity content of less than 5 atomic percent and a chlorine impurity content of more than 3 atomic percent. Process details regarding the FFW formation were previously described with respect to the metal caps 138 and are therefore not repeated for brevity.

[0090] In Fig. 36, dielectric caps 340 are formed over the metal caps 330 and the gate spacers 260. Because the metal caps 330 have upper surfaces that are lower than the upper surfaces of the gate spacers 260, each of the dielectric caps 340 has a stepped lower surface with a lower step contacting an upper surface of a metal cap 330 and an upper step contacting an upper surface of the gate spacer 260. Material and process details for the dielectric caps are similar to those for the previously described dielectric caps 142 and are therefore not repeated for brevity.

[0091] In Fig. 37, source / drain contacts 350 are formed extending through the ILD layer 310. The formation of the source / drain contacts 350 includes, for example and without limitation, performing one or more etch processes to form contact openings extending through the ILD layer 310 (and the CESL, if present) to expose the source / drain epitaxial structures 280, depositing one or more metal materials that overfill the contact openings, and then performing a CMP process to remove excess metal materials outside the contact openings. In some embodiments, the one or more etch processes are selective etching that etches the ILD layer 310 at a faster etch rate than the etching of the dielectric caps 340 and the gate spacers 260.As a result, the selective etching is performed using the dielectric caps 340 and the gate spacers 260 as an etch mask, so that the contact openings and therefore the source / drain contacts 350 are formed self-aligned with the source / drain epitaxial structures 280 without using an additional photolithography process. In this case, the dielectric caps 340, which enable the formation of the self-aligned contacts 350, may be called SAC caps 340.

[0092] After the formation of the source / drain contacts 350, the dielectric caps 340 are treated in an oxygen-containing environment so that surface layers of the dielectric caps 340 are oxidized to form oxidized regions 341 in the dielectric caps 340, while the remaining regions 342 of the dielectric caps 340 are left unoxidized. The resulting structure is shown in Fig. 38. The treatment process may include an O2 plasma treatment in which the oxygen-containing gas is introduced into a process chamber in which the plasma is generated from the oxygen-containing gas. By way of example and without limitation, the semiconductor substrate 210 is coated with the Fig. 36 loaded into a plasma tool and exposed to a plasma environment formed by oxygen gas (O2 gas) or a gas mixture of O2 gas and one or more of Ar gas, He gas, Ne gas, Kr gas, N2 gas, CO gas, CO2 gas, C x H y F z-Gas (where x, y, and z are greater than zero and not greater than nine), NF3 gas, carbonyl sulfide gas (COS gas), and SO2 gas. The plasma etching environment has a pressure between approximately 10 and approximately 100 mTorr, and the plasma is generated using an RF power between approximately 50 and approximately 1000 watts.

[0093] As a result of the O2 plasma treatment, oxidation occurs in the upper surfaces of the dielectric caps 340, resulting in the oxidized regions 341. In some embodiments, for a 3 nm technology node, a thickness T3 of the oxidized regions 341 is in a range from approximately 0.1 nm to approximately 5.0 nm (approximately 1 angstrom to approximately 50 angstroms). If the thickness T3 is less than approximately 0.1 nm (1 angstrom), the oxidized regions 341 may be too thin to slow down or even stop a subsequent etch process. Furthermore, since the oxidized regions 341 of the dielectric caps 142 have a thickness T3 of no more than approximately 5.0 nm (50 angstroms) in some embodiments, they can of course be pierced without etch stop concerns (i.e., without concern that the etch process will pass through the oxidized regions 341 in the scenario of Fig. 43 could be stopped). For other technology nodes, such as 20 nm nodes, 16 nm nodes, 10 nm nodes, 7 nm nodes, and / or 5 nm nodes, the thickness T3 may be in a range from approximately 1 nm to approximately 20 nm. The thicknesses of the oxidized regions 341 may be controlled, by way of example and without limitation, by using RF power and / or bias power of the O2 plasma treatment.

[0094] In some embodiments where the dielectric caps 340 are made of SiN, the O2 plasma treatment results in oxidized nitride regions (silicon oxynitride (SiO x N y)) 341 in the dielectric caps 340 and an unoxidized nitride region 342 under the oxidized nitride regions 341. The oxidized nitride regions 341 may form distinguishable interfaces with the unoxidized nitride region 342 because they have different material compositions (e.g., the oxidized nitride regions 341 have a higher oxygen atom content and / or a higher oxygen-to-nitrogen atom ratio than the unoxidized nitride region 342).

[0095] In some embodiments, the oxidized region 341 may have an oxygen concentration gradient due to the plasma treatment. For example, the oxygen atom fraction in the oxidized region 341 may decrease in a depth direction from the top surfaces of the dielectric caps 340. In some embodiments where the dielectric caps 340 are made of silicon nitride, the oxygen-to-nitrogen atom ratio in the oxidized region 341 may decrease in the depth direction from the top surfaces of the dielectric caps 340.

[0096] In some embodiments, during the O2 plasma treatment, upper portions of the source / drain contacts 350 may be inadvertently oxidized to form metal oxide regions 351 in the source / drain contacts 350, while the remaining metal regions 352 of the source / drain contacts 350 are left unoxidized. The resulting structure is shown in Fig. 38. The metal oxide regions 351 may form distinguishable interfaces with the unoxidized metal region 352 because they have different material compositions (e.g., the metal oxide regions 351 have a higher oxygen atom content and / or a higher oxygen-to-nitrogen atom ratio than the unoxidized metal region 352).

[0097] In some embodiments, a thickness T4 of the metal oxide regions 351 ranges from approximately 0.1 nm (1 angstrom) to approximately 5.0 nm (50 angstroms). Due to the material difference between the source / drain contacts 350 and the dielectric caps 340, the oxidation of the metal oxide regions 351 and the oxidized region 341 may vary. For example, the thickness T3 of the oxidized region 341 may be greater than, substantially equal to, or less than the thickness T4 of the metal oxide regions 351.

[0098] In some embodiments, the metal oxide regions 351 may have an oxygen concentration gradient due to the plasma treatment. For example, the oxygen atom fraction in the metal oxide regions 351 may decrease in a depth direction from the top surfaces of the source / drain contacts 350. In some embodiments where the source / drain contacts 350 are made of metal, the oxygen-to-metal atom ratio in the metal oxide regions 351 may decrease in the depth direction from the top surfaces of the source / drain contacts 350.

[0099] Once the oxidized region 341 (and the metal oxide regions 351) are formed, Fig. 39, a mid-contact etch stop layer (MCESL) 360 is deposited over the source / drain contacts 350 and the dielectric caps 340. Subsequently, another ILD layer 370 is deposited over the MCESL 360. In some embodiments, the MCESL 360 is made of silicon nitride and the ILD layer 370 is made of silicon oxide (SiO x ).

[0100] With reference to Fig. 40A, the ILD layer 370 is patterned to form via openings O7 extending through the ILD layer 370 using a first etch process (also called a via etch process) ET5. The etch duration of the via etch process ET5 is controlled to allow piercing of the ILD layer 370, while the MCESL 360 serves as an etch stop layer for the etch process ET5. In some embodiments, a photolithography process is performed prior to the via etch process ET5 to define expected top-view structures of the via openings O7. The photolithography process may, for example, include spin-coating a photoresist layer onto the ILD layer 370, as shown in Fig. 39, performing post-exposure burn-in processes and developing the photoresist layer to form a patterned mask with the top-view structures of the via openings O7. In some embodiments, patterning the photoresist to form the patterned mask may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process. Process details regarding the etching process ET5 were previously described with respect to Fig. 16A and are therefore not repeated for the sake of brevity.

[0101] In some embodiments, as shown in Fig. 40A, the via openings O7 have a tapered sidewall profile due to the nature of the anisotropic etching. However, in some further embodiments, the etching conditions may be finely tuned to enable the via openings O7 to have a vertical sidewall profile, as shown in Fig. 40B is illustrated.

[0102] With reference to Fig. 41A, the MCESL 360 is patterned to form via openings O8 extending through the MCESL 360 by using a second etch process (also called a via etch process) ET6. The etch duration of the via etch process ET6 is controlled to allow piercing of the MCESL 360 while the oxidized region 341 serves as an etch stop layer for the etch process ET6. Process details regarding the etch process ET6 were previously described with respect to Fig. 17A and are therefore not repeated for brevity. In some embodiments, the metal oxide regions 351 may be removed during the etch process ET6, such that the openings O8 expose the unoxidized regions 352 of the source / drain contacts 350, as shown in FIGS. Fig. 41C and Fig. 41D is shown.

[0103] In some embodiments, due to process variations, some misalignment (or overlay error) may exist between the via openings O8 and the source / drain contacts 350. Or, in some embodiments, the size (or width) of the via openings O8 may be larger than the size (or width) of the source / drain contacts 350. In any case, the via openings O8 may expose portions of the oxidized regions 341. However, due to the etch selectivity between the MCESL 360 and the oxidized regions 341, the oxidized regions 341 may slow down or even stop the etch process for forming the via openings O8, which in turn prevents over-etching of the dielectrics (e.g., the dielectric caps 340) and results in a lower risk of leakage currents.

[0104] In some embodiments, as shown in the Fig. 41A and Fig. 41C, the via openings O8 have a tapered sidewall profile due to the nature of the anisotropic etching of the etching process ET6. However, in some further embodiments, the etching conditions of the etching process ET6 and / or the preceding via etching process ET5 may be finely tuned such that the via openings O8 have a perpendicular sidewall profile, as shown in the Fig. 41B and Fig. 41D is illustrated.

[0105] With reference to Fig. 42A, source / drain vias 380 are then formed in the via openings O7 and O8 to establish a physical and electrical connection with the source / drain contacts 350. Material and process details for the source / drain vias 380 are similar to those for the previously described source / drain vias 150 and are therefore not repeated for brevity. In some embodiments, as described in the Fig. 42A and Fig. 42C, the source / drain vias 380 have a tapered sidewall profile due to the anisotropic etching nature of the ET6 etch process. However, in some further embodiments, the etch conditions of the ET6 etch process may be finely tuned such that the via openings O7 and O8, and therefore the source / drain vias 380, have a vertical sidewall profile, as shown in FIGS. Fig. 42B and Fig. 42D is illustrated.

[0106] The Fig. 43 to 47B illustrate exemplary cross-sectional views of various stages for fabricating an integrated circuit structure 200a according to some further embodiments of the present disclosure. It should be understood that for further embodiments of the method, additional operations may be performed before, during, and after the steps described in the Fig. 43 to 47B, and that some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchangeable. In the following embodiments, the same or similar configurations, materials, processes, and / or operations as in the Fig. 24 to 42D and the detailed explanation can be omitted.

[0107] After the Fig. 39 is formed, the ILD layer 370 is patterned to form gate contact openings O9 that extend downward through the ILD layer 370, the ESL 360, and the dielectric cap 340 to the metal cap 330. The resulting structure is shown in Fig. 43. The ILD layer 370 can be patterned using suitable photolithography and etching techniques.

[0108] Next, as in Fig. As illustrated in Figure 44, a patterned mask layer M2 is formed over the substrate 210 to fill the gate contact openings O9. The patterned mask layer M2 has an opening O10 perpendicularly above a source / drain contact 350.

[0109] With reference to Fig. 45, wherein the patterned mask layer M2 is present, a via etch process ET7 is performed to form a via opening O11 extending through the ILD layer 370. The etch duration of the via etch process ET7 is controlled such that the ILD 370 is removed and ends at the MCESL 360. Process details regarding the via etch process ET7 were previously described with respect to the via etch process ET1 and are therefore not repeated herein for brevity.

[0110] With reference to Fig. 46, an etch process ET8 is performed to etch the MCESL 360 and thus recess the via opening O11 downward into the metal oxide region 351 of the source / drain contact 350 and a portion of the oxidized regions 342 of the dielectric cap 340 between the source / drain contact 350 and the patterned mask layer M2. As a result of the etch process ET8, the metal oxide region 351 of the source / drain contact 350 and the oxidized regions 341 of the dielectric cap 340 are exposed at the bottom surfaces of the recessed via openings O11. Process details regarding the etch process ET8 were previously described with respect to the etch process ET2 and are therefore not repeated herein for brevity.

[0111] With reference to the Fig. 47A and Fig. 47B, the structured mask layer M2 (see Fig. 46) is removed from the gate contact openings O9 by ashing and / or wet stripping, and then a butt contact 390 is formed to fill the via opening O9 and the gate contact opening O11. The resulting structure is shown in Fig. 47A or Fig. 47B. The details regarding the materials and manufacturing process of the butt contact 390 are similar to the details regarding the source / drain via openings 150 and are therefore not repeated here for brevity.

[0112] Based on the above description, it can be seen that the present disclosure offers advantages. However, it should be understood that other embodiments may offer additional advantages, not all advantages are necessarily disclosed herein, and no particular advantage is required for all embodiments. One advantage is that the risk of leakage current (e.g., leakage current from the source / drain via to the gate contact and / or gate structure) due to the oxidized region of the dielectric cap may be reduced. Another advantage is that a patterning process for forming the oxidized region of the dielectric cap may be omitted. Another advantage is that the resistance-capacitance (RC) delay may be improved due to a large distance from the source / drain via to a gate contact.Furthermore, due to the doped region, a size of the source / drain via can be increased to reduce the electrical resistance of the source / drain via and further increase the contact area between the source / drain via and the source / drain contact.

[0113] According to some embodiments, a method includes depositing a dielectric cap over a gate structure. A source / drain contact is formed over a source / drain region adjacent to the gate structure. A top surface of the dielectric cap is oxidized. After oxidizing the top surface of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer is deposited over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending through the ILD layer and the etch stop layer. A source / drain via is filled into the via opening.

[0114] In some embodiments, a method includes depositing a source / drain contact over a source / drain region. A top surface of the source / drain contact is oxidized to form a metal oxide region in the source / drain contact. After oxidizing the top surface of the source / drain contact, an interlayer dielectric (ILD) layer is formed to cover the metal oxide region of the source / drain contact. A via opening is formed in the ILD layer to expose the source / drain contact. A source / drain via is filled into the via opening.

[0115] In some embodiments, a device includes a gate structure, a dielectric cap, a source / drain contact, an interlayer dielectric (ILD) layer, and a source / drain via. The dielectric cap is located over the gate structure and has an oxidized region and an unoxidized region between the gate structure and the oxidized region. The source / drain contact is located adjacent to the gate structure. The ILD layer is located over the dielectric cap and the source / drain contact. The source / drain via is located in the ILD layer and is electrically connected to the source / drain contact.

Claims

[1] Method comprising: depositing a dielectric cap (142) over a gate structure (130); Forming a source / drain contact (144) over a source / drain region (122) adjacent to the gate structure (130); oxidizing a top surface of the dielectric cap (142); after oxidizing the top surface of the dielectric cap (142), depositing an etch stop layer (146) over the dielectric cap (142) and an ILD layer (148) over the etch stop layer (146); Etching the ILD layer (148) and the etch stop layer (146) to form a via opening (O1, O2, O3, O4) extending through the ILD layer (148) and the etch stop layer (146); and Filling a source / drain via (150, 152) in the via opening (O1, O2, O3, O4); wherein the source / drain via (150, 152) is in contact with an oxidized region (1421) of the dielectric cap (142). [2] The method of claim 1, wherein the top surface of the dielectric cap 142 is oxidized using an oxygen plasma. [3] The method of claim 2, wherein the oxygen plasma is generated from an O2 gas. [4] The method according to claim 2, wherein the oxygen plasma consists of a gas mixture of an O2 gas and one or more of an Ar gas, a He gas, a Ne gas, a Kr gas, an N2 gas, a CO gas, a CO2 gas, a C x H y F z -gas, an NF3 gas, a carbonyl sulfide (COS) gas, and an SO2 gas, where x, y, and z are greater than zero. [5] A method according to any preceding claim, wherein forming the via opening comprises: performing a first etching process to form the via opening (O1, O3) extending through the ILD layer (148) and to expose a top surface of the etch stop layer; and Performing a second etching process to deepen the via opening such that the via opening (O1, O2, O3, O4) extends through the etch stop layer (146). [6] The method of claim 5, wherein the second etching process uses a different etchant than that used in the first etching process. [7] The method of claim 5 or 6, wherein the first etching process is a plasma etching process using a plasma generated from a hydrogen-free gas mixture. [8] The method according to any one of claims 5 to 7, wherein the second etching process is a plasma etching process using a plasma generated from a hydrogen-containing gas mixture. [9] A method according to any one of the preceding claims, comprising: Oxidizing a top surface of the source / drain contact (144) to form a metal oxide region (1441) in the source / drain contact (144); wherein the filling of the source / drain via (150, 152) is performed such that the source / drain via (150, 152) is in contact with the metal oxide region (1441) of the source / drain contact (144). [10] The method of claim 9, further comprising removing a portion of the metal oxide region (1441) of the source / drain contact (144) after forming the via opening (O1, O3) in the ILD layer. [11] The method of claim 9 or 10, wherein filling the source / drain via (150, 152) is performed such that the source / drain via (150, 152) is in contact with an unoxidized region (1442) of the source / drain contact (144). [12] The method of any one of claims 9 to 11, wherein the etch stop layer (146) and the metal oxide region (1441) of the source / drain contact (144) are made of different materials. [13] The method of any one of claims 9 to 12, wherein the deposition of the etch stop layer (146) is such that the etch stop layer (146) is in contact with the metal oxide region (1441) of the source / drain contact (144). [14] Device comprising: a gate structure (130); a dielectric cap (142) over the gate structure (130) having an oxidized region (1421) and an unoxidized region (1422) between the gate structure (130) and the oxidized region (1421); a source / drain contact (144) adjacent to the gate structure (130); an ILD layer (148) over the dielectric cap (142) and the source / drain contact (144); and a source / drain via (150, 152) in the ILD layer (148) electrically connected to the source / drain contact (144), wherein the source / drain via (150, 152) is in contact with the oxidized region (1421) of the dielectric cap (142). [15] The device of claim 14, wherein the oxidized region (1421) of the dielectric cap (142) has an oxygen concentration gradient. [16] The device according to claim 14 or 15, wherein the oxidized region (1421) of the dielectric cap (142) has an oxygen atom content that decreases in a depth direction from a top surface of the dielectric cap (142). [17] The device of any one of claims 14 to 16, wherein a thickness of the oxidized region (1421) is in a range of about 0.1 nm to about 5 nm.

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