Methods and systems for transposition channel routing

Abstract

Device comprising the following: a printed circuit board (PCB) with an arrangement of contact pads; a plurality of signal lines arranged on the printed circuit board, wherein a portion of the plurality of signal lines comprises an escape route on the printed circuit board; a plurality of routing channels, each routing channel being arranged between a first row of contact pads and a second row of contact pads, each routing channel having a first channel on a first printed circuit board layer and a second transposition channel on a second printed circuit board layer, and wherein a pair of signal lines is routed in the routing channel; and one or more transposition branches arranged within the escape route, each transposition branch having a plurality of pairs of vias arranged in the plurality of routing channels, and each pair of vias being configured to connect the first channel on the first PCB layer to the corresponding second transposition channel on the second PCB layer in such a way that the corresponding pair of signal lines is routed from the first PCB layer to the second PCB layer with reversed relative positions, thus reducing crosstalk between the corresponding pair of signal lines.

Description

Description of the state of the art

[0001] Escape routing generally refers to a pattern and procedure used to route the I / O pads or solder points on a chip (or package) to traces that can escape into the area around the chip to exit the package or its immediate surroundings. In particular, for circuits implementing double data rate (DDR) and quad data rate (QDR) memory circuits, integrated circuit (IC) chips often require high-frequency data transmission links that provide a low bit error rate (BER), high bandwidth, and low on-chip latency.

[0002] Accordingly, escape routing techniques for printed circuit boards (PCBs) implementing memory circuits must consider factors such as increased package size, increased channel bandwidth, lower signal levels, and reduced via and pad spacing. This is in addition to factors commonly considered in the design of conventional escape routing techniques, such as ball pitch, island diameter, number of I / O pins, via type, pad size, trace width / spacing, and the number of layers required for escape routing on the PCB. Brief description of the drawings

[0003] The present disclosure is described in detail according to one or more different embodiments with reference to the following figures. The figures serve only for illustration and represent only typical or exemplary embodiments. Fig. is a diagram of a printed circuit board (PCB) that can implement the disclosed transposition channel routing techniques for improved escape routing according to some embodiments. Fig. is a diagram of an application-specific integrated circuit (ASIC) to ASIC architecture that can implement the disclosed transposition channel routing techniques according to some embodiments. Fig. This is an example of a conventional escape routing pattern. Fig. This is an example of an improved escape routing pattern used in the printed circuit board of Fig. can be implemented, including an example of a transposition channel routing technique, according to some embodiments.

[0004] The illustrations do not claim to be exhaustive and do not limit the present disclosure to the exact form shown. Detailed description

[0005] Several embodiments described herein are directed toward improved escape routing techniques for printed circuit boards (PCBs) implementing electronics requiring high-data-rate channel buses, such as Double Data Rate 5 (DDR5) memory modules. According to these embodiments, several physical properties of the escape route on the PCB can be modified in a way that reduces crosstalk and achieves a significant improvement in signal quality. The improved escape routing techniques may involve adding intermediate connections, such as microvias, to the electrical trace layout, which can be used for the "transposition" of the signal routing channels on the PCB. Transposing channels, as disclosed herein, transposes the relationship between two aggressor signals in a way that reduces the effect coupling coefficients for individual aggressors.Accordingly, the disclosed transposition channel routing techniques can achieve reduced crosstalk by partially eliminating coupled signal lines in a channel that could otherwise cause unwanted signal transmission between channels on the printed circuit board.

[0006] The various mechanisms and techniques of the disclosed embodiments can be referred to here as transposition channel routing. As a general description of the techniques, one or more signal lines can be transposed or repositioned from one routing layer to another by using micro-vias at designated transposition nodes along an escape route. The transposition of signal lines can add a second period to the via crosstalk term, thereby reducing the peak of the accumulated via crosstalk by changing the phase relationship of the accumulated coupled signal. Additionally, an accumulated peak signal can be reduced by implementing the disclosed transposition channel routing techniques.

[0007] Although the transposition channel routing techniques are described for illustrative purposes in relation to escape routing, it should also be noted that the disclosed techniques can be applied to areas on a printed circuit board where space is limited and other attenuation techniques are not feasible. In other words, escape routing is an example of a practical application of the transposition channel routing techniques disclosed here.

[0008] Fig. Figure 104 shows an example configuration for a printed circuit board (PCB) in which the disclosed transposition channel routing can be used. As mentioned herein, a PCB is a structure that mechanically supports and electrically connects electrical (or electronic) components by using conductive traces, pads, and other features etched from sheet layers of conductive material (e.g., copper) laminated onto and / or between sheet layers of a non-conductive substrate. Although PCBs are discussed here for illustrative purposes, it should be understood that the disclosed techniques can also be applied to other types of electrical circuit elements, such as printed circuit assemblies (PCAs), printed circuit board assemblies (PCBAs), circuit board assemblies (CCAs), and the like.In the example, the printed circuit board 104 has a circuit for implementing an electronic device 100 with DDR5 memory modules 102. Background: Electronic devices typically contain memory for storing data and software instructions. Such memory is typically located between a secondary storage device (usually implemented with a disk-based storage device) and the central processing unit (CPU) of the electronic device. The memory can be implemented using dynamic random-access memory (DRAM). There are several types of DRAM, including synchronous DRAM (SDRAM) and double data rate DRAM (DDR) (defined by standards established by JEDEC). The original DDR SDRAM standard has been superseded by later established standards, such as DDR5.

[0009] In the illustrated example, the printed circuit board 104 can be configured to include high-data-rate channels, which are typically required for optimal performance of memory modules such as DDR5. For example, the memory module 120, as DDR5 memory, can support data rates of approximately mega-transfers per second (MT / s) with a base frequency of 2400–3200 MHz, thereby offering increased performance and bandwidth. To accommodate such high-data-rate channels on the printed circuit board 104, the disclosed transposition channel routing techniques can be used as a form of improved escape routing. The channels on the printed circuit board 104 can be particularly affected by the escape routing employed because, unlike other signals, DDR5 channel buses often need to be routed with minimal offset. Escape routing on a printed circuit board with high-data-rate channels, such as...The performance of a printed circuit board (PCB) of 104 can be influenced by several factors in the design of the chips, including, but not limited to: 1) Enlargement of the housing, which extends the channel escape routes out from under the housing; 2) Increased channel bandwidth, reduced signal-to-noise ratio, increased channel losses, and increased lane-to-lane coupling; and 3) Reduced via and pad spacing, which brings the conductor tracks closer together.

[0010] Furthermore, in Fig. It is shown that the printed circuit board 104 can contain several components 112a, 112b, also referred to here as devices (e.g., processors, input / output controllers, memory controllers, bridge devices, etc.), which are mounted on a surface of the printed circuit board 104. The printed circuit board 104 can also include a connector 114 for the memory module 102. As shown, the memory module 102 is designed as a dual in-line memory module (DIMM), which can be used in PCs and servers. A DIMM consists of an array of random-access dynamic integrated memory circuits (ICs). These modules are mounted on the printed circuit board 104 via the connector 114, which is shown as a DIMM connector (in a vertical orientation). One function of the DIMM connector 114 is to keep the DIMMs stable after assembly and to conduct signals vertically between ICs (on the DIMM) and the circuit board 104.In some cases, connector 114 may be connected to the circuit board 104 via an interposer or packaged with a Ball Grid Array (BGA).

[0011] As shown, the memory module 102 can be mounted into the slot 114, which includes a mechanical system, such as a cavity into which an IC fits, and a retention chip or lever system to hold the IC in place. Although the memory module 102 is described as a DDR5 memory module for illustrative purposes, it should be noted that the memory module 102 could also be another type of memory module, such as DDR SDRAM, DDR2, DDR3, DDR4, or a memory module with multiple DRAMs. Accordingly, the transposition channel routing is applicable to various types of technologies that have high data-rate channels on printed circuit boards, such as a PCB. Memory channels, as disclosed above, serve as an example of a specific technology that benefits from the disclosed techniques.

[0012] The memory module 102 can contain memory devices 106 mounted on a first surface 105 of the memory module 102. The memory module 102 also has an opposite surface (on the other side of the memory module 102, which in the view of Fig. (not visible), on which additional storage devices can be mounted. The storage devices 106 can comprise a package, e.g., a flip-chip package, which provides an arrangement of pins (or terminals) for electrical connections. The data input into a storage device 106 is stored in the memory cells of that storage device 106. In one example, the storage devices 106 can have an x4 data pin configuration (where four data pins are used). The data pins of the storage devices 106 are interconnected by conductive lines 108 on the memory module 102. The conductive lines 108 can be implemented as conductor tracks on the memory module 102.

[0013] As indicated above, DDR5 may require that the circuit board 104 have a high density of electrical traces around pin 114 for the IC implementing the memory module 102. For example, some of the traces on the circuit board 104 must carry signals exiting on one side of component 112b (represented as an IC chip) to connect to pin 114 (represented on the opposite side of the circuit board 104). Therefore, the circuit board 104 may require many layers to accommodate traces that intersect under the IC of component 112b and pin 114. For example, component 112b may be an IC chip component (e.g., CPU) with an ASIC and associated chip substrate. A socket may be located beneath the ASIC for component 112b. The combination of the packaged chip and the possible socket for the component 112b can then be mounted on the circuit board 104.A close-up view (indicated by a dashed circle) shows a mounting side of the ASIC (or IC chip) implementing component 112b.

[0014] As seen in the close-up view of Fig. As can be seen, component 112b can be a surface-mount package, wherein one side (e.g., the mounting side) of the package has an array of pads 131 (I / O contacts) on its underside, with a solder ball attached to each pad. The lower pads 131 (e.g., on the BGA) can be arranged in a pattern that corresponds to the pattern of the pads 132 on the printed circuit board 104. The pattern of the lower pads 131 can match the pattern of the upper pads 132 on the printed circuit board 104, so that the lower pads 131 of the package are directly connected to the corresponding upper pads 132 of the printed circuit board 104 by vertical conductive vias. In some cases, the pattern of the lower pads 131 may involve scaling to a larger pitch or contact size than for the pads 132 on the printed circuit board 104, or it may differ from the pattern of the pads 132.In particular, the upper pads 132 of the printed circuit board 104, which are adjacent to each other, can each be connected to the lower pads 131 on the adjacent printed circuit board, such that their respective connection points are also adjacent. The arrangement of the pads 131 (or contacts) establishes electrical connections to corresponding pads in an arrangement on the printed circuit board 104, and a conductive network of vias, traces, or other electrical routings connects the upper contacts to the lower contacts. In this example, the transposition channel routing can be implemented using a pattern of signal lines below component 112b, which are routed out from its immediate vicinity in adjacent layers between terminal 114 and component 112b on the printed circuit board 104.

[0015] The routes on the printed circuit board 104 can begin below component 112b according to the disclosed techniques. The routes can continue to terminal 114, which connects to the memory module 102 (i.e., the DIMM). That is, the transposition channel routing techniques disclosed here can be applied to routes running from component 112b to terminal 114 of the memory module 102 (i.e., the DIMM), and it is in this region of the printed circuit board 104 where the transposition channel routing takes place.

[0016] As indicated above, signals can be routed from below component 112b to the ICs of the memory module 102 and to components 112a on the other side of the printed circuit board 104. For example, signal lines 133 routed between an IC package layer (or socket layer) and the printed circuit board 104 can exit outside the footprint of the IC chip package (or outside the main chip cavity) for component 112b. As will be described in more detail later, the signal lines 133 on the printed circuit board 104 can be arranged as multiple pairs of signal lines (e.g., two parallel signal lines) that are routed, in particular, to use the same channel (either above or below) around adjacent pads 132 in a layer as an escape route. The transposition routing techniques can involve a physical transposition of the signal lines 133, i.e.,A repositioning of signal lines 133 from a routing channel (which, for example, runs in a layer below a pad) to a transposition channel (which, for example, is connected to the routing channel using micro-passages) for at least a portion of the escape route. Details of the transposition signal routing are given with reference to [reference to be inserted here]. Fig. shown and described herein. As mentioned herein, a transposition channel can be a routing channel that serves, in particular, to direct the electrical conductors that have been "transposed" to a different routing channel than their original routing channel in the escape route.

[0017] Furthermore, component 112b, which is an IC socketed on circuit board 104, can communicate with other components (e.g., component 112a) via electrically conductive traces formed in and on circuit board 104. With regard to routing, the area of ​​circuit board 104 beneath component 112b and the connector 114 for memory module 102 can provide space for traces or routings that extend beyond the boundaries of their respective ICs. Accordingly, transposition channel routing techniques can be implemented in areas of circuit board 104 that contain electrical traces connecting component 112b to other devices.

[0018] Fig. Figure 150 shows an example of another circuit configuration, represented as ASICs 151 to 157, in which the disclosed transposition routing techniques can be implemented. In particular, Figure 150 shows Fig. that the transposition signal routing techniques can be implemented in a restricted open field section of the printed circuit board (as opposed to an escape route under a socket, IC chip and the like, as in Fig. shown). In the example shown of Fig. A first ASIC 151 and a second ASIC 157 are shown, arranged at the distal ends of a circuit substrate, represented as PCB 160. Close-up views also show several electrical conductors or signal lines 153 that can be routed from the areas on the PCB 160 where the ASICs 151 and 157 are mounted. In particular, the signal lines 153 are routed as conductors connecting the ASIC 151 on one side of the PCB 160 to the ASIC 157 on the opposite side of the PCB 160. A restricted open field section 155 of the PCB 160 is also shown. As shown, the restricted open field 155 is a section of the open space on the PCB 160 between the ASICs 151 and 157. The signal lines 153 are routed through the restricted open field 155 in such a way that they form conductor tracks which connect the ASICs 151, 157 on the circuit board.For example, the signal lines 153 can be described as running from the ASIC 151 (left) through the forced opening field 155 and ending at the ASIC 157 (right), or vice versa.

[0019] In this configuration, the disclosed transposition channel routing techniques can be implemented within the restricted open field 155. As will be described in more detail below, the signal lines 153 on the printed circuit board 160 can be arranged as multiple pairs of signal lines (e.g., two parallel signal lines) as they traverse the restricted open field 155. Consequently, applying transposition channel routing to the signal lines 153 can transpose the pairs of signal lines 153 from a routing channel 126 to a transposition channel 127 for approximately the length of the conductor tracks through the restricted open field 155. As shown, multiple micro-vias 125 can be used as connections to "transpose" the signal lines 153 from their respective routing channel 126 to a transposition channel 127 (which may be located on a different layer of the printed circuit board 160 than the routing channel 126).This transposition of the signal lines 153 also transposes the relationship between the two aggressor signals in order to partially cancel the coupled signals of the signal line pair and reduce crosstalk. Additionally, the transposition of the signal lines 153 in the area of ​​the forced opening field 155 can change the phase relationship of the accumulated coupled signal (from the interaction of the signal line pairs) on the signal lines 153 up to this point (e.g., the start of the transposition at the transposition junction).

[0020] Fig. shows part of a typical escape routing pattern 200, which is implemented on a substrate, such as a printed circuit board (shown in Fig. , can be arranged. The vertical columns of pattern 200 can represent “layers” of semiconducting components mounted on the printed circuit board (e.g., BGAs, sockets, ICs, etc.), and the horizontal ones can represent “rows” running along the horizontal plane of the printed circuit board, which is also referred to here as the “length” of the escape routing pattern 200. Also shown is an arrangement of various contact points 220. 1a -220 5f , which represent a pattern of solder balls, vias, or conductive pads on the corresponding IC package or substrate. In some cases, the arrangement of the contact points is 220 1a -220 5f configured to match (in number and shape) the corresponding pattern of pads (or spheres) on the IC package onto which it is mounted.

[0021] As can be seen, the signal lines 210a-213b (also referred to as "metal conductors" or "-conductor") emerge from the peripheral contacts 220 1a , 220 2a , 220 3a , 220 4a and 220 5a (on the right side) and the contacts 220 1f , 220 2f , 220 3f , 220 4f and 220 5f(on the left side) that adjoin the outer edges of the escape routing pattern 200. In particular, the signal lines 210a-213b are arranged in pairs in each layer of the pattern 200. Furthermore, these signal line pairs run parallel to each other, following the same path over the entire length of the escape routing pattern 200. In the example shown, for instance, the signal lines 210a and 210b are arranged parallel to each other (with signal line 210a directly above signal line 210b) and run horizontally along the first row (or layer) of the pattern 200 between the contacts 220 1a , 220 1b , 220 1c , 220 1d , 220 1e and 220 1f and 220 2a , 220 2b , 220 2c , 220 2d , 220 2e and 220 2frouted. Conversely, the signal lines 210a and 210b run parallel to each other along the entire length of the escape routing pattern 200 in a guide channel below the contacts 220. 1a , 220 1b , 220 1c , 220 1d , 220 1e and 220 1f and above contacts 220 2a , 220 2b , 220 2c , 220 2d , 220 2e and 220 2f Furthermore, the spacing (i.e., the distance between the centers of the pads) is the same in both the horizontal and vertical directions, although this need not be the case. In some instances, the number of traces that can exit through a layer depth (n=1) is limited by the pitch, the pad dimensions, and the trace width. Therefore, in some embodiments, there can be more than two signal lines running parallel through each layer (or row) in Pattern 200.

[0022] Since the signal line pairs 210a, 210b; 211a, 211b; 212a, 212b; and 213a, 213b are routed together (in parallel) through a routing channel (or routing series), there is some coupling between the signal lines in each of the pairs. In general, as the length (e.g., distance and / or time) of the coupling between the signal line pairs 210a, 210b; 211a, 211b; 212a, 212b; and 213a, 213b increases, the amount of interference between the signals also increases. Consequently, a considerable amount of interference or crosstalk can accumulate on the signal lines, as the signal line pairs 210a, 210b; 211a, 211b; 212a, 212b; and 213a, 213b are coupled together in this pattern 200 over the entire length of the escape route. Furthermore, this pattern 200 can lead to a large accumulation of coupled signal amplitude on the routing channels for escape routing, which can degrade the signal quality (e.g.,(low signal-to-noise ratio, increased channel losses). Accordingly, conventional escape routing techniques, such as those used in... Fig. This has been shown to be particularly unsuitable for circuits where high data rate channels need to be implemented on the printed circuit boards, such as the DDR5 memory circuit (shown in Fig. .

[0023] To achieve escape routing, it is common practice for the outermost rows (e.g., the two to four outermost rows) within the array to contain all the pins requiring escape routing. However, the number of traces on the printed circuit board (PCB) that can be routed between adjacent contacts is limited by the width of the traces, the size (e.g., the diameter) of the contacts, and the associated design rules. As the complexity of connections on modern PCBs (and IC packages) increases, it becomes increasingly difficult to route traces from the internal contacts of the array while maintaining suitable design tolerances for the number of traces that can reasonably fit between adjacent contacts. With an increasing number of pins in ICs, the number of rows and layers required for escape routing increases non-linearly.Furthermore, complex IC designs can lead to larger IC packages, which in turn lengthens the channel escape routes protruding from under the package. These aforementioned challenges can be exacerbated by the implementation of high-data-rate channels on printed circuit boards, particularly in DDR technology. Accordingly, the disclosed transposition channel routing techniques can achieve an improvement over conventional escape routing techniques, such as Pattern 200, by transposing (or repositioning) signal lines from one routing channel to another, such as a transposition channel. Therefore, the disclosed transposition can eliminate the accumulation of coupled signal line pairs along some segments of the escape route length (e.g., reducing the length of the coupled signal lines along any given routing channel).

[0024] Fig. shows part of an escape routing pattern 300, which is printed on a substrate, such as a printed circuit board (shown in Fig. , can be arranged, implementing the disclosed transposition channel guidance techniques. For example, the printed circuit board can contain a plurality of component interface fields, which contain the plurality of component contact fields. 320 1a -320 5f include. For explanatory purposes, the contacts 320 1a -320 5f described as contact pads, but it should be understood that contacts can also be vias or other connections that connect to the 320 contact pads. 1a -320 5f can correspond. For example, a corresponding through-hole can be placed at the same positions as contact pads 3201a-3205f.

[0025] The multiple signal lines, comprising 310a, 310b; 311a, 311b; 312a, 312b; and 313a, 313b, can be arranged on the printed circuit board and have a first end that connects to one of the contact pads 320 1a -320 5f is connected, and a second end is connected to a system interface bus of the printed circuit board. When designing an electrical conductor layout for the printed circuit board, which includes the escape routing pattern 300 with the majority of signal lines and one or more transposition connections for each of the signal line pairs.

[0026] Similar to in Fig. The contacts represent 320 1a -320 5f (also referred to as contact pads) represent a pattern of solder balls or conductive pads on the corresponding IC package or substrate. Additionally, the signal lines 310a-313b emerge from the peripheral contacts 320. 1a , 320 2a , 320 3a , 320 4a and 320 5a(on the right side) and the contacts 320 1l , 320 2k , 320 3l , 320 4k and 320 5l (on the left side) that border the outer edges of the escape routing pattern 300. Additionally, the signal line pairs 310a, 310b; 311a, 311b; 312a, 312b; and 313a, 313b are routed together (in parallel) through a specific routing channel (or row). For example, the signal line pairs 310a, 310b run in parallel in a routing channel around contacts 320 1a , 320 1b , 320 1c for part of the escape route. Thus, for this duration, there is a certain coupling between the signal lines in each of the pairs. In contrast to the escape route in Fig. However, transposition channel routing is applied to the signal line pairs, rerouting them so that they remain parallel (e.g., coupled) to each other in a different channel, represented as the transposition channel, of escape routing pattern 300. That is, in the example shown, both signal lines of the pair can be "transposed" from their original routing channel and run through a different routing channel. As shown, the "transposed" signal lines 310c, 310d; 311c, 311d; 312c, 312d; and 313c, 313d (represented by dashed lines) are located to the left of transposition branch 340. The "transposed" signal lines 310c, 310d; 311c, 311d; 312c, 312d; and 313c, 313d are signal lines that pass through micro-holes 325 1a , 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4bfrom an original routing channel to a transposition channel, thereby adding a second period to the via crosstalk term, which can cancel any accumulation on coupled signal line pairs. It is understood that the transposition channel can be considered to lie in a separate and adjacent layer of the printed circuit board with respect to the initial routing channel. For example, the micro-vias 3251a, 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4b These are blind and / or buried vias on the printed circuit board, consisting of pads in an additional routing layer in the electrical conductor layout, namely the transposition channel. The micro-vias 325 1a , 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4bMicrovias can correspond to positions (in the PCB's transposition channel layer) that are electrically connected by a hole through the PCB to a corresponding contact pad (in the original routing channel layer). As mentioned herein, microvias can be those with a small diameter (approximately 150 micrometers or less) compared to mechanically drilled vias.

[0027] In Fig. are pairs of micro-vias 325 1a , 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4b arranged at a transposition node 340 (point along the length of escape route 300) such that each pair of micro-vias 325 1a , 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4ba corresponding signal line pair 310a, 310b; 311a, 311b; 312a, 312b; and 313a, 313b. In the example shown: signal line pair 310a, 310b is replaced by the micro-via pair 325 1a , 325 1b rerouted to route the “transposed” signal lines 310c, 310d through the transposition channel next to the contact pads 230 1d , 320 1e 320 1f to be routed; signal line pair 311a, 311b is connected by the micro-via pair 325 1a , 325 1b rerouted to route the “transposed” signal lines 311c, 311d through the transposition channel next to the contact pads 230 2d , 320 2e 320 2f to be routed; signal line pair 312a, 312b is connected by the micro-via pair 325 3a , 325 3b rerouted to route the “transposed” signal lines 312c, 312d through the transposition channel next to the contact pads 230 3d , 320 3e 320 3fto conduct; and the signal line pair 313a, 313b is connected by the micro-via pair 325 4a , 325 4b rerouted to carry the “transposed” signal lines 313c, 313d through the transposition channel next to the contact surfaces 230 4d , 320 4e 320 4f to lead.

[0028] By implementing this transposition channel (adding the micro-vias 325 1a , 325 1b 325 2a , 325 2b 325 3a , 325 3b ; and 325 4a , 325 4bTransposing the signal lines changes the position of the relationship, as the lines are routed parallel to each other. For a certain period, while the relationship between two aggressor signals is transposed, this can induce additional noise in the opposite phase (e.g., in the opposite direction), resulting in a cancellation of any interference that may accumulate as the coupled signal pairs traverse the original routing channels. In other words, transposing the relationship of the signals from one plane to another can add a cancellation factor to the interference between the two signals. This also reduces the coupling length for individual aggressors, which reduces crosstalk and limits the frequency content of the coupled signals.As already indicated, position 340 in the escape route length can represent a “transposition node” in the escape routing pattern 300, which can be described as a displacement point (or transposition) of the “transposed” signal lines to another routing channel, namely the transposition channel.

[0029] Although in Fig.Not shown, various combinations of signal lines can be "transposed" in the same manner described above if deemed necessary or appropriate. For example, only one signal line of the signal line pair may be transposed. In another example, one or more signal line pairs (fewer than all signal line pairs in the electrical trace layout) may be transposed. In yet another example, the escape routing pattern may contain more than one transposition node. In a further example, signal line pairs may be "transposed" over a smaller portion of the escape route length (e.g., shorter spacing between transposition branches), thereby increasing the frequency of transposition. In other words, the same signal line pair may be transposed two or more times along the length of the escape routing pattern.Accordingly, in some embodiments of transposition channel routing techniques, the placement of the transposition branches in the escape route, which defines the distance between the offsets (or transitions) of the transposed signal lines, can be varied based on the specific application or a desired degree of crosstalk reduction. As a general concept, it should be understood that reducing the distance between the "transposed" positions of the signal lines, in turn, increases coupling reduction. For example, the total number of transposed connections to be used within an electrical conductor layout can be determined and variably adjusted as a design decision prior to PCB fabrication. The total number of transposition branches in the electrical conductor layout (e.g.,In the escape route section of the printed circuit board, the length of the coupling between signal lines within a given signal pair can be determined. That is, at each transposition branch, the signal pair is transposed by one adjacent channel. Generally, the total number of transposition branches is inversely proportional to the coupling length of a signal pair in a corresponding routing channel. For example, increasing the total number of transposition branches in an escape route adds several periods to the crosstalk term, which can increase the reduction of the accumulated peak crosstalk value.

[0030] The implementation of the disclosed transposition channel routing techniques, illustrated in Escape Routing Pattern 300, can lead to an estimated 50% reduction in coupling at the same Nyquist frequency. It is understood that, due to the use of rerouted or "transposed" routing channels, the disclosed techniques may occasionally require an additional routing channel (e.g., one additional routing channel per 16 lanes at a given layer). Nevertheless, the resulting improved signal-to-noise ratio increases the reliability and information transmission capacity of the channel, both of which are important characteristics in platforms designed for high-performance / high-data-rate applications, such as Application-as-a-Service (AaS) applications and DDR5.

[0031] As used herein, the term "or" can be understood in both an inclusive and an exclusive sense. Furthermore, the singular description of resources, processes, or structures is not to be understood as excluding the plural. Conditional expressions such as "may," "could," "might," or "may" are, unless expressly stated otherwise or understood differently in context, generally to be understood as meaning that certain embodiments include certain features, elements, and / or steps, while other embodiments do not.

[0032] Terms and expressions used in this document, and variations thereof, should be understood as open and not restrictive unless expressly stated otherwise. Adjectives such as "conventional," "traditional," "normal," "standard," "known," and terms of similar meaning are not to be understood as limiting the subject matter described to a particular period or to a subject matter available at a particular point in time, but should be understood as encompassing conventional, traditional, normal, or standard technologies that may be available or known now or at any point in the future.The presence of expansive words and phrases such as "one or more", "at least", "but not limited to" or other similar expressions in some cases is not to be understood as implying that the narrower case is intended or required in cases where such expansive phrases may be absent.

Claims

[1] Device comprising the following: a printed circuit board (PCB) with an arrangement of contact pads; a plurality of signal lines arranged on the printed circuit board, wherein a portion of the plurality of signal lines comprises an escape route on the printed circuit board; a plurality of routing channels, each routing channel being arranged between a first row of contact pads and a second row of contact pads, each routing channel having a first channel on a first printed circuit board layer and a second transposition channel on a second printed circuit board layer, and wherein a pair of signal lines is routed in the routing channel; and one or more transposition branches arranged within the escape route, each transposition branch having a plurality of pairs of vias arranged in the plurality of routing channels, and each pair of vias being configured to connect the first channel on the first PCB layer to the corresponding second transposition channel on the second PCB layer in such a way that the corresponding pair of signal lines is routed from the first PCB layer to the second PCB layer with reversed relative positions, thus reducing crosstalk between the corresponding pair of signal lines. [2] Device according to claim 1, wherein the first channel is located on the same printed circuit board layer as the arrangement of contact pads. [3] Device according to claim 1, wherein the second transposition channel and the arrangement of contact pads are located on separate and adjacent layers. [4] Device according to claim 1, wherein the pair of vias is configured such that the corresponding pair of signal lines is routed from the first printed circuit board layer to the second printed circuit board layer in such a way that a signal relationship between two aggressor signals is transposed. [5] Device according to claim 1, wherein the second transposition channel is adjacent to the first channel and a first signal interference is accumulated according to a coupling of the signal line pair traversing the first channel. [6] Device according to claim 5, wherein the first layer of the printed circuit board is adjacent to the second layer of the printed circuit board and a second signal interference is accumulated in the second transposition channel according to a coupling of the signal line pair traversing the second transposition channel. [7] Device according to claim 6, wherein the second signal interference accumulated in the second transposition channel is generated in an opposite phase to the first signal interference accumulated in the first transposition channel. [8] Device according to claim 7, wherein the second interference that accumulates in the second transposition channel cancels out the first signal interference that accumulates in the first channel. [9] Device according to claim 1, wherein the signal line pair in the second transposition channel is guided from the transposition branch for a remaining length of the escape route. [10] Device according to claim 1, wherein the signal line pair in the second transposition channel is routed from the transposition branch over the length of the escape route to a second transposition branch. [11] Device according to claim 1, wherein the transposition of the signal line pair from the first channel to the second transposition channel over the length of the escape route introduces a second period into a via crosstalk term. [12] Device according to claim 1, wherein the total number of one or more transposition branches arranged within the escape route is variable and adjusts the length of the escape route according to the routing of the signal line pair in the second transposition channel. [13] Device according to claim 1, wherein the multiple pairs of signal lines comprise high data rate signal lines. [14] Device according to claim 1, wherein the printed circuit board comprises an integrated circuit (IC) implementing a second device with high data rate channel buses. [15] Device according to claim 14, wherein the second device comprises a storage module with double the data rate (DDR). [16] Printed circuit board (PCB), comprising: an arrangement of contact pads; a plurality of signal lines arranged on the printed circuit board, wherein a portion of the plurality of signal lines traverses a limited open field on the printed circuit board; wherein the plurality of signal lines are configured to a plurality of routing channels, each routing channel comprising a pair of signal lines, each routing channel comprising a first channel on a first printed circuit board layer and a second transposition channel on a second printed circuit board layer; and one or more transposition branches arranged within the restricted open field on the printed circuit board, each transposition branch having a plurality of pairs of vias arranged in the plurality of routing channels, and each pair of vias being configured to connect the first channel on the first printed circuit board layer to the corresponding second transposition channel on the second printed circuit board layer in such a way that the corresponding pair of signal lines is routed from the first printed circuit board layer to the second printed circuit board layer with reversed relative positions, thus reducing crosstalk between the corresponding pair of signal lines. [17] Printed circuit board (PCB) according to claim 16, wherein the pair of vias is configured to route the corresponding pair of signal lines from the first printed circuit board to an adjacent printed circuit board layer such that a signal relationship between two aggressor signals is transposed. [18] Procedures, including: Specifying a plurality of routing channels, wherein each routing channel has a first channel on a first printed circuit board layer and a second transposition channel on a second printed circuit board layer, and wherein a pair of signal lines is routed in the routing channel; Determining one or more transposition branches arranged along the plurality of routing channels, wherein each transposition branch has a plurality of pairs of vias arranged in the plurality of routing channels, and wherein each pair of vias is configured to connect the first channel on the first printed circuit board layer to the corresponding second transposition channel on the second printed circuit board layer such that the corresponding pair of signal lines is routed from the first printed circuit board layer to the second printed circuit board layer with reversed relative positions; Designing an electrical conductor layout for a printed circuit board (PCB) with a pattern that includes the plurality of routing channels and the one or more transposition branches for each routing channel; and Manufacturing the printed circuit board based on the electrical conductor layout. [19] Method according to claim 18, wherein determining the one or more transposition branches comprises determining a total number of the one or more transposition branches within the electrical conductor layout. [20] Method according to claim 19, wherein the pair of vias is configured such that the corresponding pair of signal lines is redirected from the first printed circuit board layer to an adjacent printed circuit board layer, so that a signal relationship between two aggressor signals is transposed.

Images