Semiconductor package containing an interposer

Abstract

Semiconductor package, comprehensive: a first substrate (100); a processor (200, 800) arranged on the first substrate (100); a first memory (300) arranged on the first substrate (100) and containing a plurality of first memory chips (310, 320, 330, 340, 370, 380); an interposer (400) located above the processor (200, 800) and the first memory (300); and a second memory (500, 700) arranged above the interposer (200, 800), wherein the second memory (500) contains a plurality of second memory chips (510, 520, 530, 540, 570, 580, 710, 720, 730, 740), wherein the processor (200, 800) and the first memory (300) are arranged between the first substrate (100) and the interposer (400); wherein the interposer (400) is arranged between the first memory (300) and the second memory (500, 700), wherein the interposer (400) comprises a first physical layer (440) that transmits and receives a signal between the processor (200, 800) and the first memory (300) and transmits and receives a signal between the processor (200, 800) and the second memory (500, 700), and wherein the processor (200, 800) comprises a second physical layer (210) which is electrically connected to the first substrate (100), and wherein a first silicon via (230, 240) runs vertically through the processor (200, 800) and electrically connects the first physical layer (440) with the second physical layer (210).

Description

TECHNICAL FIELD

[0001] The concept according to the invention relates to a semiconductor package, in particular to a semiconductor package containing an interposer. DISCUSSION OF RELATED TECHNOLOGY

[0002] As the electronics industry progresses, electronic devices are being miniaturized and adapted for a multitude of tasks, thus increasing the speed and capacity of the memory used in electronic devices.

[0003] System-in-Package (SiP) technology was developed to increase the performance and reduce the cost of electronic devices. This technology integrates semiconductor memory devices along with a processing unit into a semiconductor package structure, enabling a single semiconductor package product to perform high-speed operation, massive data processing, and multifunctional functions. Furthermore, High-Bandwidth Memory (HBM) technology was developed to implement high-capacity memory by vertically stacking multiple semiconductor chips within a single package. The various stacked memory devices are interconnected using Through-Silicon Via (TSV) technology.

[0004] HBMs have a structure in which multiple vertically stacked semiconductor chips are interconnected via a TSV (Silicon Transducer) and connected to a processor via a silicon interposer located beneath the semiconductor chips. A semiconductor chip positioned on a bottom layer beneath multiple vertically stacked semiconductor chips can act as a buffer chip, communicating with a processor to send and receive data or to receive various control and voltage signals. Semiconductor chips stacked on top of a buffer chip can act as memory chips, storing data received via the buffer chip.However, as the number of stacked semiconductor chips increases, a physical difference in distance between a memory chip located on a top layer and a memory chip located on a bottom layer causes a misalignment, which creates a problem where a loss of electrical characteristics occurs because the top memory chip is farther from the buffer chip than the bottom memory chip.

[0005] From US patent application 2020 / 0098724A1, a semiconductor package is known that comprises an interposer, a first and a second memory, a processing unit, and a substrate. The first memory is located on the substrate, the interposer on the first memory, and the processing unit and the second memory on the interposer. SUMMARY

[0006] A semiconductor package contains a substrate, a processor mounted on the substrate, a lower memory layer also mounted on the substrate containing multiple vertically stacked first memory chips, an interposer mounted on the processor and lower memory layer, and an upper memory layer mounted on the interposer. The processor and lower memory layer are located between the substrate and the interposer. The upper memory layer contains multiple vertically stacked upper memory chips. The interposer includes a first physical layer (PHY) that transmits and receives signals between the processor and the lower memory layer, and between the processor and the upper memory layer.The processor contains a second PHY that is electrically connected to the first substrate, and a first through-silicon via (TSV) that runs vertically through the processor and electrically connects the first PHY to the second PHY.

[0007] A semiconductor package contains a processor on a substrate, a lower memory located on the substrate containing a plurality of first memory chips stacked vertically on the substrate, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer. The upper memory contains a plurality of upper memory chips stacked vertically. The processor and the lower memory are located between the substrate and the interposer. The interposer contains a first PHY that transmits and receives a signal between the processor and the lower memory, and a power TSV that transmits and receives a signal between the processor and the upper memory. A power TSV passes through the interposer, receives a power signal from the lower memory, and transmits the power signal to the upper memory.A data TSV passes through the interposer, receives a data signal from either the lower or upper memory, and transmits the data signal to the first PHY. The processor contains a second PHY, which is electrically connected to the first substrate, and a TSV that runs vertically through the processor, electrically connecting the first PHY to the second PHY. The first PHY vertically overlaps the second PHY.

[0008] A semiconductor package contains a processor mounted on a substrate, a lower memory mounted on the substrate (100) containing a plurality of lower memory chips stacked vertically on the substrate, an interposer mounted on the processor and the lower memory, and a first upper memory mounted on the interposer. The first upper memory contains a plurality of upper memory chips stacked vertically. The processor and the lower memory are located between the substrate and the interposer.The interposer contains a first PHY electrically connected to the processor, the first upper memory, and the lower memory; a redistribution layer electrically connecting the lower memory to the first PHY and the first upper memory to the first PHY; and a power TSV traversing the interposer, receiving a power signal from the lower memory, and passing the power signal to the first upper memory. The processor contains a second PHY electrically connected to the substrate; a first TSV traversing the processor vertically, electrically connecting the first PHY to the second PHY; and a second TSV that receives a power signal from the substrate and passes the power signal to the power TSV. The first PHY vertically overlaps the second PHY.

[0009] A semiconductor package includes a substrate containing a first cavity and a second cavity, a processor of which at least part is arranged in the first cavity, a lower memory containing a plurality of first memory chips stacked vertically, with at least some of the plurality of lower memory chips arranged in the second cavity, an interposer arranged on the substrate, the processor and the lower memory chip, and an upper memory containing a plurality of upper memory chips stacked vertically on the interposer.

[0010] A semiconductor package contains a base substrate, an interposer positioned above the base substrate, a processor located between the interposer and the base substrate, a first memory stack positioned between the interposer and the base substrate and spaced away from the processor, and a second memory stack positioned above the interposer. The first and second memory stacks communicate with the processor via the interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present revelation and many related aspects is easily attained when it is better understood by reference to the following detailed description, when considered in conjunction with the accompanying drawings, wherein: Fig. Figure 1A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 1B is a schematic top view showing the Fig. Semiconductor package shown in 1A illustrates; Fig. 1C is a block diagram that schematically illustrates an interposer according to one embodiment of the disclosure; Fig. 1D is a top view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 2A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 2B is a schematic top view showing the Fig. Semiconductor package shown in 2A is illustrated; Fig. 3A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 3B is a schematic top view of the in Fig. Semiconductor package shown in 3A; Fig. Figure 4A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 4B is a schematic top view showing the Fig. Semiconductor package shown in 4A illustrates; Fig. Figure 5A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 5B is a schematic top view showing the Fig. The semiconductor package shown in 5A illustrates this; Fig. Figure 6A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 6B is a schematic top view of the in Fig. Semiconductor package shown in 6A; Fig. Figure 7A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 7B is a schematic top view showing the Fig. Semiconductor package shown in 7A is illustrated; Fig. Figure 8A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 8B is a schematic top view showing the Fig. Semiconductor package shown in 8A illustrates; Fig. Figure 9A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 9B is a schematic top view of the in Fig. Semiconductor package shown in 9A; Fig. Figure 10 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. Figure 11 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. Figure 12 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. Figure 13 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. Figure 14 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. Figure 15 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 16 and Fig. Figure 17 are cross-sectional views showing a semiconductor package according to the embodiments of the disclosure; Fig. Figure 18 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; Fig. 19 and Fig. Figure 20 are cross-sectional views showing a semiconductor package according to the embodiments of the disclosure; Fig. Figure 21 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure; and Fig. Figure 22 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. DETAILED DESCRIPTION OF EXAMPLE EXECUTION FORMS

[0012] In the following illustrations, identical reference symbols refer to identical elements, and a description of these elements does not need to be repeated.

[0013] Fig. Figure 1A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 1B is a schematic top view showing the Fig. Semiconductor package shown in 1A is illustrated. Fig. 1C is a block diagram that schematically illustrates an interposer according to one embodiment of the disclosure.

[0014] Referring to Fig. 1A and Fig. 1B the semiconductor package can contain a processor 200, a lower memory 300, an interposer 400 and an upper memory 500, each arranged over a substrate 100.

[0015] The substrate 100 can be a printed circuit board (PCB). A connection terminal 110 can be located beneath the substrate 100. The connection terminal 110 can be a solder bump or a solder ball. The connection terminal 110 can include a data terminal 107, which receives a data signal from an external source, and a plurality of power terminals 105 and 109, which receive a power signal. A plurality of wiring layers 130 and 140, electrically connected to the connection terminal 110, can be formed in the substrate 100. The plurality of wiring layers 130 and 140 can include a first wiring layer 130 and a second wiring layer 140. The first wiring layer 130 can electrically connect the connection port 110 to the processor 200, and the second wiring layer 140 can electrically connect the connection port 110 to the lower memory 300.For example, the data signal and a control signal, each received from data port 107, can be transmitted to processor 200 via first wiring layer 130, and the power signal received from the multiple power ports 105 and 109 can be transmitted to processor 200 via first wiring layer 130 or to lower memory 300 via second wiring layer 140.

[0016] The processor 200 can be located on and above the substrate 100. The processor 200 can be mounted on the substrate 100 via multiple solder pads 205. The processor 200 can be, for example, a host such as a central processing unit (CPU), a graphics processing unit (GPU), or a system-on-a-chip (SoC), and it can also be, for example, an application-specific integrated circuit (ASIC). The multiple solder pads 205 on the substrate 100 can be connected to the first wiring layer 130 formed in the substrate 100, and the processor 200 can be electrically connected via the multiple solder pads 205 and the first wiring layer 130 to multiple connection terminals 110 located beneath the substrate 100.

[0017] The lower memory chip 300 can be arranged on and above the substrate 100, spaced apart from the processor 200. The lower memory chip 300 can be attached to the substrate 100 via the solder pad 305. The lower memory chip 300 can be an HBM (High Bandwidth Memory). The lower memory chip 300 can contain a plurality of lower memory chips 310, 320, 330, and 340, stacked vertically. Each of the plurality of lower memory chips 310, 320, 330, and 340 can contain a memory cell area CELL with a plurality of integrated memory cells. For example, each of the plurality of lower memory chips 310, 320, 330, and 340 can be a dynamic random access memory (DRAM). The majority of the lower memory chips 310, 320, 330, and 340 can be of the same type. In one embodiment, at least one of the majority of lower memory chips 310, 320, 330, and 340 can be a different type of memory chip than the others.

[0018] Each of the plurality of lower memory chips 310, 320, 330, and 340 can contain a lower TSV 350 and a lower contact point 360. The lower TSV 350 can extend through the plurality of lower memory chips 310, 320, 330, and 340. The lower contact point 360 can be electrically connected to an upper and a lower section of the lower TSV 350. The lower contact point 360 can be exposed on surfaces of the plurality of lower memory chips 310, 320, 330, and 340. The solder bump 307 can be located between the plurality of lower memory chips 310, 320, 330, and 340. The solder bump 307 can be in direct contact with the lower contact point 360. The multiple lower memory chips 310, 320, 330 and 340 can be electrically connected to the solder bump 307, the lower contact point 360 and the lower TSV 350.

[0019] The lower memory 300 can contain two, four, or eight lower memory chips, but the disclosure is not limited thereto. In one embodiment, the lower memory 300 can contain a first to fourth lower memory chip 310, 320, 330, and 340, which are stacked sequentially. The first lower memory chip 310 can be arranged at a bottommost section on the substrate 100, and the fourth lower memory chip 340 can be arranged at a topmost section on the substrate 100. It is to be understood that, as used here, “below” and “underneath” are directions measured from the interposer 400 to the substrate 100, and “above” and “over above” are directions measured from the substrate 100 to the interposer 400, and that the lower storage 300 is lower in relation to the interposer 400, while an upper storage 500 is higher in relation to the interposer 400.The height of the top of the fourth lower memory chip 340, which is located at the topmost section, may be essentially the same as that of the top of the processor 200.

[0020] The interposer 400 can be positioned on the processor 200 and the lower memory 300. The interposer 400 can contain a silicon substrate. One side of the interposer 400 (e.g., the left side) can be mounted on the processor 200 via the solder lug 405. The other side of the interposer 400 (e.g., the right side) can be mounted on the lower memory 300 via the solder lug 405.

[0021] The upper memory 500 can be located on top of and above the interposer 400. For example, at least part of the interposer 400 can be located between the upper memory 500 and the lower memory 300. The upper memory 500 can vertically overlap the lower memory 300. The upper memory 500 cannot vertically overlap the processor 200. The upper memory 500 can be an HBM. The upper memory 500 can contain a plurality of upper memory chips 510, 520, 530, and 540 stacked vertically. Each of the plurality of upper memory chips 510, 520, 530, and 540 can contain a memory cell area CELL with a plurality of memory cells integrated within it. For example, each of the plurality of upper memory chips 510, 520, 530, and 540 can be a DRAM. The majority of the top memory chips 510, 520, 530 and 540 may be the same type of memory chip.In one embodiment, at least one of the majority of the upper memory chips 510, 520, 530 and 540 can be a different type of memory chip than the others.

[0022] Each of the plurality of upper memory chips 510, 520, 530, and 540 can contain an upper TSV 550 and an upper contact point 560. The upper TSV 550 can extend through the plurality of upper memory chips 510, 520, 530, and 540. The upper contact point 560 can be electrically connected to an upper and a lower section of the upper TSV 550. The upper contact point 560 can be exposed on the surfaces of the plurality of upper memory chips 510, 520, 530, and 540. The solder lug 507 can be located between the plurality of upper memory chips 510, 520, 530, and 540. The solder lug 507 can be directly connected to the upper contact point 560. The majority of the upper memory chips 510, 520, 530 and 540 can be electrically connected to the solder lug 507, the upper contact point 560 and the upper TSV 550.

[0023] The upper memory 500 can contain two, four, or eight upper memory chips, but the disclosure is not limited thereto. In one embodiment, the upper memory 500 can contain a first to fourth upper memory chip 510, 520, 530, and 540, which are stacked sequentially. The first upper memory chip 510 can be arranged at a bottom section on the interposer 400, and the fourth upper memory chip 540 can be arranged at a top section on the interposer 400.

[0024] The lower TSV 350, contained in each of the majority of lower memory chips 310, 320, 330, and 340, can contain a lower data TSV 351 and a lower power TSV 353. The lower data TSV 351 can be electrically connected to the processor 200 via the interposer 400 and can be a path through which a data signal is transmitted. The lower power TSV 353 can be electrically connected to the second redistribution layer 140 of the substrate 100 and can be a path through which a power signal received via the power connector 109 is transmitted.

[0025] For example, some of the data signals received by the interposer 400 from the lower data TSV 351, contained in the fourth lower memory chip 340, can be transferred to the fourth lower memory chip 340, and the other data signals can be transferred by the lower data TSV 351 to at least one of the first to third lower memory chips 310 to 330. The data signals transferred to the first to fourth lower memory chips 310, 320, 330, and 340 can be stored in the memory cell areas CELL of the first to fourth lower memory chips 310, 320, 330, and 340.The lower-power TSV 353 contained in the first lower memory chip 310 can transmit some of the power signals received via the substrate 100 to the first lower memory chip 310, and the other power signals can be transmitted via the lower-power TSV 353 to at least one of the second to fourth lower memory chips 320 to 340.

[0026] The majority of the upper memory chips 510, 520, 530, and 540 can each contain one upper data TSV 551 and one upper power TSV 553. The upper data TSV 551 can be electrically connected to the processor 200 via the interposer 400 and can be a path through which a data signal is transmitted. The upper power TSV 553 can be electrically connected to the power TSV 353 via the interposer 400 and can be a path through which a power signal received by the lower memory 300 and / or the interposer 400 is transmitted. The upper data TSV 551 can be oriented at a position that corresponds vertically to the lower data TSV 351. The upper power TSV 553 can be oriented at a position that corresponds vertically to the lower data TSV 351.

[0027] In one embodiment, the interposer 400 can include a routing circuit 410, an input / output (I / O) circuit 430, and a first physical layer (PHY) 440 (PHY1). The routing circuit 410 can be arranged vertically between the upper memory 500 and the lower memory 300 and can be electrically connected to the upper memory 500, the lower memory 300, the I / O circuit 430, and / or the first PHY 440. In one embodiment, the routing circuit 410 can include several electrically conductive wiring layers 411 for forwarding the signals received by the processor 200, the upper memory 500, and / or the lower memory 300. The majority of the wiring layers 411 to 413 can be electrically connected to the processor 200, the lower memory 300, and the upper memory 500. The multiple wiring layers 411 to 413 can be arranged in the silicon substrate of the interposer 400.

[0028] In one embodiment, the routing circuit 410 can include a first to third wiring layer 411 to 413. Each of the first wiring layer 411 and the second wiring layer 412 can be a data line through which a data signal travels. The first wiring layer 411 can electrically connect the upper memory 500 to the I / O circuit 430. The first wiring layer 411 can electrically connect the upper memory 500 to the first PHY 440 via the I / O circuit 430. The first wiring layer 411 can be electrically connected to the upper data TSV 551 of the upper memory 500. The second wiring layer 412 can electrically connect the lower memory 300 to the I / O circuit 430. The second wiring layer 412 can electrically connect the lower memory 300 to the first PHY 440 via the I / O circuit 430.The second wiring layer 412 can be electrically connected to the lower data TSV 351 of the lower memory 300. The first wiring layer 411 and the second wiring layer 412 can be electrically isolated from each other. In one embodiment, the first wiring layer 411 and the second wiring layer 412 can be electrically connected.

[0029] The third wiring layer 413 can be a power line through which a power signal travels. The third wiring layer 413 can electrically connect the lower power TSV 353 of the lower memory 300 and the upper power TSV 553 of the upper memory 500. Therefore, a power signal received by the substrate 100 can be transmitted to the upper power TSV 553 via the lower power TSV 353 and the third wiring layer 413 of the interposer 400. The third wiring layer 413 can be electrically connected to the first and second wiring layers 411 and 412, respectively.

[0030] With reference to Fig. In embodiments 1A to 1C, the I / O circuit 430 can be arranged between the routing circuit 410 and the first PHY 440 to electrically connect the routing circuit 410 to the first PHY 440. In one embodiment, the I / O circuit 430 can include a repeater 431 and / or a multiplexer / demultiplexer 433 (MUX / DEMUX). The repeater 431 can compensate for the signal integrity of signals received via the routing circuit 410 and / or the signal integrity of signals received via the first PHY 440. The repeater 431 can be arranged between the routing circuit 410 and the multiplexer / demultiplexer 433 and / or between the first PHY 440 and the multiplexer / demultiplexer 433. The I / O circuit 430 can contain a plurality of repeaters 431.The multiplexer / demultiplexer 433 can multiplex signals received from the routing circuit 410 or signals received via the repeater 431 and transmit the multiplexed signals to the first PHY 440. The multiplexer / demultiplexer 433 can also demultiplex signals received from the first PHY 440 and transmit the demultiplexed signals to the repeater 431 or the routing circuit 410.

[0031] With reference to Fig. 1A and Fig. 1B The first PHY 440 can be located on the processor 200. The first PHY 440 can be a physical layer that allows both the upper memory 500 and the lower memory 300 to communicate with the processor 200. The first PHY 440 can transmit signals received via the I / O circuit 430 and / or the routing circuit 410 to the processor 200 and can transmit signals received by the processor 200 via the I / O circuit 430 or the routing circuit 410 to the upper memory 500 and / or the lower memory 300.

[0032] The first PHY 440 can vertically overlap the processor 200. In one embodiment, the first PHY 440 can be located in a boundary region ED of the processor 200 to vertically overlap the processor 200. The first PHY 440 can be located in a boundary region ED that is near the lower memory 300 and the upper memory 500 of a plurality of boundary regions of the processor 200.

[0033] The processor 200 can contain a second PHY 210 (PHY2) and a TSV 230. The second PHY 210 can be a physical layer electrically connected to the first PHY 440, enabling the processor 200 to communicate with the lower memory 300 and / or the upper memory 500. Additionally, the second PHY 210 can be a physical layer that allows the processor 200 to communicate with external devices connected to the processor 200 via the substrate 100. The second PHY 210 can be located beneath the processor 200 and electrically connected to the substrate 100 via the solder lug 205. For example, the second PHY 210 can be connected to the data port 107 via the first wiring layer 130. The second PHY 210 can also be located in the edge region ED beneath the processor 200.The second PHY 210 can be located in a border region ED, situated near the lower memory 300 and the upper memory 500, within the majority of the processor 200's border regions. Accordingly, the second PHY 210 can vertically overlap the first PHY 440 of the interposer 400.

[0034] The TSV 230 can run vertically through the processor 200 and can be located next to the second PHY 210 within the processor 200. In a top view, the TSV 230 can be located, for example, next to the edge region ED. The first PHY 440 and the TSV 230 can be electrically connected and have a fan-out configuration, and furthermore, the second PHY 210 and the TSV 230 can also be electrically connected and have a fan-out configuration. Therefore, a data signal input via the first wiring layer 130 and the data port 107 of the substrate 100 or a data signal generated by the processor 200 can be transmitted via the second PHY 210 and the TSV 230 to the first PHY 440 of the interposer 400 and supplied to the upper memory 500 and the lower memory 300 via the I / O circuit 430 and / or the routing circuit 410 of the interposer 400.Furthermore, a data signal read from upper memory 500 and lower memory 300 can be transmitted to processor 200 via routing circuit 410, I / O circuit 430, and first PHY 440. Processor 200 can receive the read data signal via second PHY 210 and its TSV 230. First PHY 440 and second PHY 210 can be connected to TSV 230, overlapping vertically. TSV 230 can be located adjacent to first PHY 440 and second PHY 210, thus reducing the signal transmission distance between them and minimizing channel loss.

[0035] Referring to Fig. 1B The upper TSV 550 and the lower TSV 350 can be arranged between a plurality of memory cell regions CELL. In one embodiment, in a top view, the upper data TSV 551 and the lower data TSV 351 can be arranged in a first region R1 relatively close to the processor 200, and the upper power TSV 553 and the lower power TSV 353 can be arranged in a second region R2 relatively far from the processor 200. However, the disclosure is not limited thereto, and the upper data TSV 551 and the upper power TSV 553 can be arranged between the plurality of memory cell regions CELL, and the upper power data TSV 553 and the lower power TSV 353 can be arranged between the plurality of memory cell regions CELL. In Fig. 1A and Fig. 1B shows the upper and lower data TSV 351 and 551 and the upper and lower power TSV 353 and 553 as having the same diameter, but are not limited to this and may have different diameters.

[0036] Fig. Figure 1D is a top view of a semiconductor package according to one embodiment of the disclosure.

[0037] Referring to Fig. In 1D, the second PHY 210 and the TSV 230 of the processor 200 can each be arranged in the edge region ED. The second PHY 210 of the processor 200 can be arranged on one side of the edge region ED, and the TSV 230 can be arranged on one side of the second PHY 210 in the edge region ED. The first PHY 440 of the interposer 400 can vertically overlap the second PHY 210. In one embodiment, the first PHY 440 can vertically overlap the TSV 230 without overlapping the second PHY 210.

[0038] Fig. Figure 2A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 2B is a schematic top view showing the Fig. Semiconductor package shown in 2A is illustrated.

[0039] Referring to Fig. 2A and Fig. 2B, it is possible that the first PHY 440 of an interposer 400 and the second PHY 210 of a processor 200 do not vertically overlap. The second PHY 210 of the processor 200 may be located in a border region ED, and a TSV 230 of the processor 200 may be located next to the second PHY 210, outside the border region ED. The first PHY 440 of the interposer 400 may vertically overlap the TSV 230 of the processor 200. Accordingly, the first PHY 440 may be connected to the TSV 230 and have a fan-in configuration, and the second PHY 210 may be connected to the TSV 230 and have a fan-out configuration.

[0040] Fig. Figure 3A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 3B is a schematic top view showing the Fig. Semiconductor package shown in 3A is illustrated.

[0041] Referring to Fig. 3A and Fig. 3B A second PHY 210 of a processor 200 can be located in a boundary region ED of the processor 200. In a top view, a first PHY 440 of an interposer 400 can be spaced from the boundary region ED and located outside of the boundary region ED. In a top view, a TSV 230 of the processor 200 can be located between the first PHY 440 and the second PHY 210. Accordingly, the first PHY 440 and the second PHY 210 can each be connected to the TSV 230 and have a fan-out configuration.

[0042] Fig. Figure 4A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 4B is a schematic top view showing the Fig. Semiconductor package shown in 4A is illustrated.

[0043] Referring to Fig. 4A and Fig. In one embodiment, shown in a top view, a TSV 230 of a processor 200 may include a first TSV 233 arranged between a first PHY 440 and a second PHY 210, and a second TSV 235 arranged below the first PHY 440. For example, the second TSV 235 may vertically overlap the first PHY 440. The first TSV 233 and the second TSV 235 may each be electrically connected to the first PHY 440. The first TSV 233 may be connected to the first PHY 440 in a fan-out configuration, and the second TSV 235 may be connected to the first PHY 440 in a fan-in configuration. Alternatively, the first TSV 233 and the second TSV 235 may be connected to the second PHY 210 in a fan-out configuration. In one embodiment, the second TSV 235 can be isolated from the second PHY 210.

[0044] Fig. Figure 5A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 5B is a schematic top view showing the Fig. The semiconductor package shown in section 5A is illustrated.

[0045] Referring to Fig. 5A and Fig. 5B A TSV 230 of a processor 200 can be located in a peripheral area ED of a processor 200, and a second PHY 210 of the processor 200 can be located next to the TSV 230, outside the peripheral area ED. A first PHY 440 of an interposer 400 can be located in a position that vertically overlaps the second PHY 210. Both the first PHY 440 and the second PHY 210 can be connected to the TSV 230 and have a fan-out configuration.

[0046] Fig. Figure 6A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 6B is a schematic top view showing the Fig. Semiconductor package shown in 6A is illustrated.

[0047] Referring to Fig. 6A and Fig. 6B A TSV 230 of a processor 200 can be located in a boundary region ED of the processor 200, and a first PHY 440 of an interposer 400 can be located in the boundary region ED of the processor 200. The TSV 230 of the processor 200 can vertically overlap the first PHY 440. A second PHY 210 of the processor 200 can be located next to the TSV 230, outside the boundary region ED. The first PHY 440 can be connected to the TSV 230 and can have a fan-in configuration, and the second PHY 210 can be connected to the TSV 230 and have a fan-out configuration.

[0048] Fig. Figure 7A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 7B is a schematic top view showing the Fig. Semiconductor package shown in 7A is illustrated.

[0049] Referring to Fig. 7A and Fig. 7B A first PHY 440 of an interposer 400 can be located in a boundary region ED of a processor 200. A second PHY 210 of the processor 200 can be spaced from and located outside the boundary region ED. In a top view, a TSV 230 of the processor 200 can be located between the first PHY 440 and the second PHY 210. Both the first PHY 440 and the second PHY 210 can be connected to the TSV 230 and have a fan-out configuration.

[0050] Fig. Figure 8A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 8B is a schematic top view showing the Fig. 8A illustrates the semiconductor package shown.

[0051] Referring to Fig. 8A and Fig. Figure 8B shows that a TSV 230, in a top view, can include a first TSV 233 positioned between a first PHY 440 and a second PHY 210, and a second TSV 235 positioned below the first PHY 440. For example, the second TSV 235 can vertically overlap the first PHY 440. The first TSV 233 and the second TSV 235 can each be electrically connected to the first PHY 440. The first TSV 233 can be connected to the first PHY 440 and have a fan-out configuration, and the second TSV 235 can be connected to the first PHY 440 and have a fan-in configuration. Furthermore, the first TSV 233 and the second TSV 235 can both be connected to the second PHY 210 and have a fan-out configuration. In one embodiment, the second TSV 235 can be isolated from the second PHY 210.

[0052] Fig. Figure 9A is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure. Fig. 9B is a schematic top view showing the Fig. The semiconductor package shown in 9A is illustrated.

[0053] Referring to Fig. 9A and Fig. 9B can contain a TSV 230, a data TSV 240, and a power TSV 260. The data TSV 240 can be a TSV that electrically connects a first PHY 440 to a second PHY 210. The data TSV 240 can have the same configuration and perform the same function as the TSV 230 described above with reference to the Fig. 2A to 8A have been described, and therefore, to the extent that a detailed description of various elements has been omitted, it can be assumed that the omitted description is at least similar to the corresponding elements described elsewhere within the present revelation.

[0054] The power TSV 260 can be spaced from and located outside the edge region ED. The power TSV 260 can be located on one side of each of the data TSV 240, the first PHY 440, and the second PHY 210, and in a top view, it can be located relatively farther from an upper memory 500 and a lower memory 300 than the data TSV 240, the first PHY 440, and the second PHY 210. The power TSV 260 can transmit a power signal received via a power terminal 105 of a substrate 100 to an interposer 400. The power TSV 260 can be isolated from the data TSV 240, the first PHY 440, and the second PHY 210. In one embodiment, the power TSV 260 can be isolated from an I / O circuit 430.The power TSV 260 can be connected to a routing circuit 410 of the interposer 400 and can, for example, be electrically connected to an upper power TSV 553 of the upper memory 500 and a lower power TSV 353 of the lower memory 300 via a wiring layer 419 of the routing circuit 410.

[0055] Fig. Figure 10 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0056] Referring to Fig. 10. In one embodiment, an interposer 400 can include a power TSV 450. The power TSV 450 can be oriented in a position that is vertically aligned with an upper power TSV 553 of an upper memory 500 and a lower power TSV 353 of a lower memory 300. The power TSV 450 can electrically connect the upper memory 500 to the lower memory 300. For example, the power TSV 450 can electrically connect the upper power TSV 553 to the lower power TSV 353. Accordingly, a power signal received by a substrate 100 can be transmitted to a plurality of upper memory chips 510, 520, 530, and 540 via the lower power TSV 353 of the lower memory 300, the power TSV 450 of the interposer 400, and the upper power TSV 553 of the upper memory 500. The power TSV 450 can be electrically isolated from a plurality of wiring layers 411 and 412.

[0057] Fig. Figure 11 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0058] Referring to Fig. 11. In one embodiment, an interposer 400 can include a data TSV 460. The data TSV 460 can be oriented in a position that is vertically aligned with an upper data TSV 551 of an upper memory 500 and a lower data TSV 351 of a lower memory 300. The data TSV 460 can be electrically connected to the upper data TSV 551 of the upper memory 500 and the lower data TSV 351 of the lower memory 300. The data TSV 460 can be electrically isolated from the power TSV 450. A wiring layer 414 can electrically connect the data TSV 460 to an I / O circuit 430. The wiring layer 414 can be connected to a contact point that is connected to the data TSV 460 in order to electrically connect the data TSV 460 to the I / O circuit 430.

[0059] Fig. Figure 12 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0060] Referring to Fig. 12. In one embodiment, an interposer 400 can include a silicon substrate 401 and a redistribution layer 470. An I / O circuit 430 and a first PHY 440 can be arranged in the silicon substrate 401. A plurality of TSVs 450 and 460 can extend through the silicon substrate 401. The multiple TSVs 450 and 460 can be arranged as shown in Fig. 9A, a power TSV 450 and a data TSV 460 are included, which pass through the silicon substrate 401 of the interposer 400.

[0061] The redistribution layer 470 can electrically connect the first PHY 440 to the lower memory 300 and / or the upper memory 500. The redistribution layer 470 can electrically connect the first PHY 440 to the lower memory 300 and / or the upper memory 500 via the I / O circuit 430. The redistribution layer 470 can be arranged on the silicon substrate 401 of the interposer 400. For example, the redistribution layer 470 can be arranged between the silicon substrate 401 of the interposer 400 and the upper memory 500. The redistribution layer 470 can cover one top surface of the silicon substrate 401 of the interposer 400. The redistribution layer 470 can include a plurality of redistribution patterns 471, 473, and 475 and a passivation layer 477. The redistribution layer 470 may further include a contact point 479 which is exposed on a top side of the passivation layer 477.The contact point 479 can be electrically connected to the upper TSV 550 of the upper memory 500 via a solder lug 505. The multiple redistribution patterns 471, 473, and 475 can contain a metal or a metal alloy of at least one metal selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). The passivation layer 477 can contain an insulating material, for example, silicon nitride, silicon oxide, or silicon oxynitride. The passivation layer 477 can, for example, contain a polyimide-based material such as photosensitive polyimide (PSPI).

[0062] The redistribution layer 470 can contain the first through third redistribution patterns 471, 473, and 475. The first redistribution pattern 471 can be connected to the contact point 479 of the redistribution layer 470, can extend into the passivation layer 477, and can be connected to the I / O circuit 430 and electrically connected to the upper memory 500 and the I / O circuit 430. For example, the first redistribution pattern 471 can be a data line through which a data signal travels, and the first redistribution pattern 471 can be connected to the contact point 479, which corresponds to the upper data TSV 551 of the upper memory 500, and it can be electrically connected to the upper data TSV 551.

[0063] The second redistribution pattern 473 can be connected to a contact point of the interposer 400, can extend into the passivation layer 477, and can be connected to the I / O circuit 430 and electrically connected to the lower memory 300 and the I / O circuit 430. For example, the second redistribution pattern 473 can be a data line through which a data signal travels, and the second redistribution pattern 473 can be connected to the contact point corresponding to the lower data TSV 351 of the lower memory 300, and it can be electrically connected to the lower data TSV 351. The second redistribution pattern 473 can be electrically isolated from the first redistribution pattern 471. In one embodiment, the second redistribution pattern 473 can be electrically connected to the first redistribution pattern 471.

[0064] The third redistribution pattern 475 can electrically connect the contact point of the interposer 400 to the contact point 479 of the redistribution layer 470. For example, the third redistribution pattern 475 can be connected to the contact point of the interposer 400 corresponding to the lower power TSV 353 and to the contact point 479 of the redistribution layer 470 corresponding to the upper power TSV 553, thus electrically connecting the lower power TSV 353 to the upper power TSV 553. In one embodiment, the third redistribution pattern 475 can have a linear shape extending vertically and in a straight line.

[0065] Fig. Figure 13 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0066] As in Fig. As shown in Figure 13, an interposer 400 can include a wiring layer 415 that connects a lower data TSV 351 to an I / O circuit 430 of a silicon substrate 401. The interposer 400 can include a redistribution layer 470 arranged on the silicon substrate 401. The redistribution layer 470 can include a first redistribution pattern 471 that connects an upper data TSV 551 to the I / O circuit 430, and a third redistribution pattern 475 that connects an upper power TSV 553 to a lower power TSV 353, and the second redistribution pattern 473, which is described above with reference to Fig. The section described in point 12 can be omitted.

[0067] Fig. Figure 14 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0068] Referring to Fig. 14. A redistribution layer 470 can be arranged beneath a silicon substrate 401 of an interposer 400. For example, the redistribution layer 470 can be arranged between a processor 200 and the silicon substrate 401, and between a lower memory 300 and the silicon substrate 401. In this case, the redistribution layer 470 can also include a redistribution pattern that electrically connects a first PHY 440 to the processor 200.

[0069] Fig. Figure 15 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0070] Referring to Fig. 15. A TSV 230 of a processor 200 can contain a data TSV 240 and a power TSV 260. An interposer 400 can contain a redistribution layer 470, and the redistribution layer 470 can, for example, contain a first redistribution pattern 471 that electrically connects an upper data TSV 551 to an I / O circuit 430 of the interposer 400, a second redistribution pattern 473 that electrically connects the I / O circuit 430 to a lower data TSV 351, and a third redistribution pattern 478 that electrically connects a power TSV 260 of a processor 200 to an upper power TSV 553 and a lower power TSV 353.

[0071] Fig. 16 and Fig. Figure 17 are cross-sectional views showing a semiconductor package according to the embodiments of the disclosure.

[0072] Referring to Fig. 16 and Fig. 17. An interposer 400 can be arranged on a processor 200 and a lower memory 300, and an upper memory 500 can be arranged on the interposer 400. The lower memory 300 can contain a plurality of lower memory chips, and the upper memory 500 can contain a plurality of upper memory chips. In one embodiment, the number of lower memory chips arranged below the interposer 400 can differ from the number of upper memory chips arranged on the interposer 400. For example, as in Fig. 16, the number of lower memory chips 310 and 320 may be less than the number of upper memory chips 510, 520, 530, 540, 570 and 580. Alternatively, as in Fig. 17, the number of lower memory chips 310, 320, 330, 340, 370 and 380 may be greater than the number of upper memory chips 510 and 520. The level of a top of the processor 200 may be essentially the same as the level of a top of each of the lower memory chips 320 and 360, which are arranged on a topmost section of the lower memory 300.

[0073] Fig. Figure 18 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0074] Referring to Fig. 18. A substrate 100 can contain a first cavity CV1 and a second cavity CV2, which are set back from a top surface of the same. At least a portion of a processor 200 can be arranged in the first cavity CV1 and can be secured in the first cavity CV1 by a solder bump 205. A top surface of the processor 200 can be substantially the same as a top surface of the substrate 100. In one embodiment, only a lower portion of the processor 200 can be arranged in the first cavity CV1, and thus an upper portion of the processor 200 can protrude from the substrate 100, and a top surface of the processor 200 can be arranged at a level higher than a top surface of the substrate 100. At least a portion of a lower memory chip 300 can be arranged in the second cavity CV2 and secured in the substrate 100 by a solder bump 305.A top surface of a lower memory chip 320, located at a topmost section in the lower memory 300, can be located at the same level as a top surface of the processor 200. All of a plurality of lower memory chips can be located in the second cavity CV2, or only some of the plurality of lower memory chips can be located in the second cavity CV2 and some other lower memory chips can be located at a level higher than a top surface of the substrate 100.

[0075] Multiple wiring layers 135 and 145 can be arranged beneath the first cavity CV1 and the second cavity CV2 of the substrate 100. A connection terminal 110 arranged beneath the substrate 100 can be electrically connected to the processor 200 via the wiring layers 135 and 145, and the connection terminal 110 can be electrically connected to the lower memory 300. An interposer 400 can be arranged on the substrate 100, the processor 200, and the lower memory 300. The interposer 400 can be mounted on the processor 200 and the lower memory 300 by means of a solder lug 405. An upper memory 500 can be attached to the interposer 400 by means of a solder lug 505. The upper memory 500 can vertically overlap the lower memory 300.

[0076] Fig. 19 and Fig. Figure 20 are cross-sectional views illustrating a semiconductor package according to the embodiments of the disclosure.

[0077] Referring to Fig. 19. A semiconductor package can contain a first upper memory 500 and a second upper memory 600 arranged on an interposer 400. The first upper memory 500 can vertically overlap a lower memory 300, and the second upper memory 600 can vertically overlap a processor 200. The first upper memory 500 can contain a plurality of first upper memory chips 510, 520, 530, and 540 stacked vertically, and the second upper memory 600 can contain a plurality of second upper memory chips 610 and 620 stacked vertically. The plurality of first upper memory chips 510, 520, 530, and 540 and the plurality of second upper memory chips 610 and 620 can be the same memory chips. The number of first upper semiconductor chips can be equal to or different from the number of second upper semiconductor chips.

[0078] Each of the plurality of second upper memory chips 610 and 620 can contain a TSV 650 and a contact point 660. The TSV 650 can contain a data TSV 651 and a power TSV 653. The data TSV 651 of each of the plurality of second upper memory chips 610 and 620 can be electrically connected to an I / O circuit 430 and / or a first PHY 440 of an interposer 400, and the power TSV 651 can be electrically connected to a power TSV 260 of the processor 200 via a redistribution layer or a wiring layer 417 of the interposer 400.

[0079] Referring to Fig. In one embodiment, a semiconductor package 20 can contain a second upper memory chip 700 that vertically overlaps a processor 200. A first upper memory 500 (see Fig. 19) on a lower storage 300 can be omitted.

[0080] Fig. Figure 21 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0081] Referring to Fig. 21 The semiconductor package can contain a plurality of processors 800 and 900. In one embodiment, the semiconductor package can contain a first processor 800 and a second processor 900. The first processor 800 and the second processor 900 can be stacked vertically. An interposer 400 can be mounted on the second processor 900. The level of a top surface of the second processor 900 can be substantially the same as the level of a top surface of a fourth lower memory chip 340, which is arranged at a top section below a plurality of lower memory chips of the lower memory 300. The first processor 800 and the second processor 900 can be the same type of ASIC. In one embodiment, the first processor 800 and the second processor 900 can be different types of ASICs.

[0082] The first processor 800 can contain a second PHY 810 and a first TSV 830, and the second processor 900 can contain a third PHY 910 (PHY3) and a second TSV 930. The first TSV 830 can electrically connect the second PHY 810 to the third PHY 910. The second TSV 930 can electrically connect the first PHY 440 to the third PHY 910. The first TSV 830 can also be electrically connected to the second TSV 930. The first processor 800 and the second processor 900 can communicate with each other via the second PHY 810 and the third PHY 910. The first processor 800 can communicate with an upper memory 500 and / or a lower memory 300 via the first PHY 440 and the second PHY 810. The second processor 900 can communicate with the upper memory 500 and / or the lower memory 300 via the third PHY 910 and the first PHY 440.

[0083] In one embodiment, at least one of the first to third PHY 440, 810, and 910 can be arranged in an edge region of the first and second processors 800 and 900. In one embodiment, the first PHY 440 can vertically overlap at least one second PHY 810 and one third PHY 910.

[0084] Fig. Figure 22 is a cross-sectional view illustrating a semiconductor package according to one embodiment of the disclosure.

[0085] Referring to Fig.22 A plurality of upper memory chips 510, 520, 530, and 540 can be electrically connected to an interposer 400 in a wire-bonded manner. For example, each of the plurality of upper memory chips 510, 520, 530, and 540 can transmit or receive a data signal over a line electrically connected to a first PHY 440 and / or an I / O circuit of the interposer 400. Each of the plurality of upper memory chips 510, 520, 530, and 540 can receive the data signal over an upper data TSV 551, which is electrically connected to a routing circuit 410 of the interposer 400, and can receive a power signal over an upper power TSV 553. In one embodiment, an upper memory 500 can contain the plurality of upper memory chips 510, 520, 530 and 540, and each of the plurality of upper memory chips 510, 520, 530 and 540 could not contain a TSV 530.In this case, the majority of the upper memory chips 510, 520, 530 and 540 can receive the data signal and / or the power signal via the wire connected to the interposer 400.

[0086] The semiconductor package according to one embodiment of the disclosure can be implemented, for example, as a system-in-package, multi-chip package or a single-chip system (system-on-chip), or as a package with a plurality of packages.

[0087] Since, according to the embodiments, an interposer, which fulfills the function of a buffer chip, is arranged between a plurality of vertically stacked memory chips, the physical distance difference between the interposer and each of the memory chips can be minimized, thereby reducing the loss of electrical characteristics. A physical layer contained in the interposer and a physical layer of a processor can be connected to each other by a vertically stacked network (TSV) within a very short distance, thus enabling an electrically optimized topology and improving communication speed between the processor and each memory chip.Since the interposer contains a redistribution layer and a TSV, a wiring process between the processor and each memory chip can be easily carried out, and a loss of electrical properties that occurs during a signal transmission process carried out in the interposer can be minimized.

[0088] Certain embodiments of the disclosure have been described above with reference to the accompanying drawings, but it is understood that the person skilled in the art may modify or amend the embodiments within the scope of protection of the accompanying claims.

Claims

[1] Semiconductor package, comprising: a first substrate (100); a processor (200, 800) arranged on the first substrate (100); a first memory (300) arranged on the first substrate (100) and containing a plurality of first memory chips (310, 320, 330, 340, 370, 380); an interposer (400) located above the processor (200, 800) and the first memory (300); and a second memory (500, 700) arranged above the interposer (200, 800), wherein the second memory (500) contains a plurality of second memory chips (510, 520, 530, 540, 570, 580, 710, 720, 730, 740), wherein the processor (200, 800) and the first memory (300) are arranged between the first substrate (100) and the interposer (400); wherein the interposer (400) is arranged between the first memory (300) and the second memory (500, 700), wherein the interposer (400) comprises a first physical layer (440) that transmits and receives a signal between the processor (200, 800) and the first memory (300) and transmits and receives a signal between the processor (200, 800) and the second memory (500, 700), and wherein the processor (200, 800) comprises a second physical layer (210) which is electrically connected to the first substrate (100), and wherein a first silicon via (230, 240) runs vertically through the processor (200, 800) and electrically connects the first physical layer (440) with the second physical layer (210). [2] Semiconductor package according to claim 1, wherein a number of memory chips of the plurality of first memory chips (310, 320, 330, 340) of the first memory (300) is the same as a number of memory chips of the plurality of second memory chips (510, 520, 530, 540, 710, 720, 730, 740) of the second memory (500, 700). [3] Semiconductor package according to claim 1, wherein a number of memory chips of the plurality of first memory chips (310, 320, 330, 340, 370, 380) of the first memory (300) differs from a number of memory chips of the plurality of second memory chips (510, 520, 530, 540, 570, 580) of the second memory (500). [4] Semiconductor package according to any one of claims 1 to 3, wherein each comprises a plurality of first memory chips (310, 320, 330, 340, 370, 380): a first data silicon via (351) configured to receive a data signal received from the processor (200, 800) via the first physical layer (440); and a first power silicon via (353) configured to receive a power signal from a first substrate (100), and where each comprises the majority of second memory chips (510, 520, 530, 540, 710, 720, 730, 740): a second data silicon via (551) configured to receive a data signal received from the processor via the first physical layer (440); and a second power silicon via (553) which is configured to receive the power signal from the first power silicon via (353). [5] Semiconductor package according to claim 4, wherein the interposer (400) further comprises a power silicon via (450) electrically connecting the first power silicon via (353) to the second power silicon via (553). [6] Semiconductor package according to claim 4 or 5, wherein the interposer (400) further comprises a data silicon via (460) which electrically connects the first data silicon via (351) to the second data silicon via (551). [7] Semiconductor package according to any one of claims 4 to 6, wherein the interposer (400) further comprises: a second substrate (401) containing the first physical layer (440); and a redistribution layer (470) arranged on the second substrate (401), and where the redistribution layer comprises (470): a first redistribution pattern (471) designed to transfer the data signal between the second data silicon via (551) and the first physical layer (440); a second redistribution pattern (473) designed to transfer the data signal between the first data silicon via (351) and the first physical layer (440); a third redistribution pattern (475) configured to transfer the power signal between the first power silicon via (353) and the second power silicon via (553); and a passivation layer (477) that at least partially covers the first redistribution pattern (471), the second redistribution pattern (473) and the third redistribution pattern (475). [8] Semiconductor package according to any one of claims 4 to 7, wherein the processor (200) further comprises a second silicon via (260) configured to receive a power signal through the first substrate (100). [9] Semiconductor package according to claim 8, wherein the second silicon via (260) is configured to transmit the power signal via the interposer (400) to the second power silicon via (553). [10] Semiconductor package according to any one of claims 1 to 9, wherein the interposer (400) further comprises at least one repeater (431) configured to compensate for a loss of signal integrity of the signal. [11] Semiconductor package according to any one of claims 1 to 10, wherein the second physical layer (210) is arranged in an edge region (ED) adjacent to the first memory (300) of the processor (200). [12] Semiconductor package according to claim 11, wherein the first physical layer (440) vertically overlaps the second physical layer (210) at least partially. [13] Semiconductor package according to claim 11 or 12, wherein the first silicon via (230, 240) is arranged adjacent to the second physical layer (210) such that they do not overlap in a top view. [14] Semiconductor package according to claim 13, wherein the first physical layer (440) at least partially vertically overlaps the first silicon via (230, 240). [15] Semiconductor package, comprising: a processor (200) arranged on a substrate (100); a lower memory (300) arranged on the substrate (100) and containing a plurality of lower memory chips (310, 320, 340, 370, 380); an upper storage unit (500) which is arranged on top of the lower storage unit (300) and contains a plurality of upper memory chips (510, 520, 530, 540, 570, 580) stacked vertically; and an interposer (400) located between the lower storage (300) and the upper storage (500), wherein the processor (200) and the lower memory (300) are arranged between the substrate (100) and the interposer (400); the interposer (400) comprises: a first physical layer (440) that sends and receives a signal between the processor (200) and the lower memory (300) and sends and receives a signal between the processor (200) and the upper memory (500); a power silicon via (450) passing through the interposer (400), receiving a power signal from the lower memory (300) and transmitting the power signal to the upper memory (500); and a data silicon via (460) passing through the interposer (400), receives a data signal from the lower memory (300) or the upper memory (500) and transmits the data signal to the first physical layer (440), where the processor comprises (200): a second physical layer (210) that is electrically connected to the first substrate (100); and a silicon via (230) that runs vertically through the processor (200) and electrically connects the first physical layer (440) with the second physical layer (210), and the first physical layer (440) and the second physical layer (210) overlap vertically. [16] Semiconductor package according to claim 15, wherein the interposer (200) further comprises: an interposer substrate (401) containing the first physical layer (440); and a redistribution layer (470) which is arranged on the interposer substrate (401) and electrically connects the first physical layer (440) to the data silicon via (460). [17] Semiconductor package according to claim 16, wherein the redistribution layer (470) is arranged between the interposer substrate (401) and the upper memory (500). [18] Semiconductor package according to claim 16, wherein the redistribution layer (470) is arranged between the interposer substrate (400) and the lower memory (300). [19] Semiconductor package, comprising: a processor (200) arranged on a substrate (100); a lower memory (300) arranged on the substrate (100) and containing a plurality of lower memory chips (310, 320, 330, 340, 370, 380) stacked vertically on the substrate (100); an interposer (400) located on the processor (200) and the lower memory (300); and a first upper memory (500) arranged on the interposer (400), wherein the first upper memory (500) contains a plurality of upper memory chips (510, 520, 530, 540, 570, 580) stacked vertically, wherein the processor (00) and the lower memory (300) are arranged between the substrate (100) and the interposer (400); the interposer (400) comprises: a first physical layer (440) that is electrically connected to the processor (200), the first upper memory (500) and the lower memory (300); a redistribution layer (470) that electrically connects the lower storage (300) to the first physical layer (440) and electrically connects the first upper storage (500) to the first physical layer (440); and a power silicon via (450) passing through the interposer (400), receives a power signal from the lower memory (300) and transmits the power signal to the first upper memory (500), where the processor comprises (200): a second physical layer (210) that is electrically connected to the substrate (100); a first silicon via (240) that runs vertically through the processor (200) and electrically connects the first physical layer (440) to the second physical layer (210); and a second silicon via (260) that receives a power signal from the substrate (100) and transmits the power signal to the power via (450), and where the first physical layer (440) at least partially overlaps the second physical layer (210) vertically. [20] Semiconductor package according to claim 19, wherein the first upper memory (500) at least partially overlaps the lower memory (300) vertically, and The semiconductor package further includes a second upper memory (600) that at least partially overlaps the processor (200) on the interposer (400) vertically.

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