Etching profile control of the gate contact opening

By using an oxide layer with distinct etch selectivity, the etching process for gate contact openings in semiconductor devices is controlled, addressing size variations and enhancing the vertical profile to reduce leakage current and contact resistance.

DE102021110442B4Active Publication Date: 2025-12-31TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102021110442
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-04-09
Filing Date
2021-04-23
Publication Date
2025-12-31
Estimated Expiration
2041-04-23

AI Technical Summary

Technical Problem

The formation of gate contact openings in semiconductor devices can result in varying sizes due to etching inaccuracies, leading to deeper penetration and increased risk of leakage current and contact resistance, particularly in FinFET and GAA transistor structures.

Method used

Incorporating an additional oxide layer with different etch selectivity over the gate dielectric covers to slow down the liner removal etching process, ensuring more vertical gate contact openings and reducing the risk of leakage current and contact resistance.

Benefits of technology

Prevents tiger-tooth-like structures and enhances the vertical profile of gate contact openings, thereby reducing leakage current and increasing contact area, thus improving the performance and reliability of semiconductor devices.

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Abstract

Procedure comprehensive: Forming a gate structure (130) over a semiconductor substrate (12); Etching back the gate structure (130); Forming a gate dielectric cover (142) over the back-etched gate structure (130); Deposition of an etch-resistant layer (145) over the gate dielectric cover (142); Deposition of a contact etch stop layer (146) over the gate dielectric cover (142) and an ILD layer (148) over the contact etch stop layer (146); Performing a first etching process (ET1) to form a gate contact opening (O21, O22) extending through the ILD layer (148) and ending before reaching the etch-resistant layer (145); Performing a second anisotropic etching process (ET2) using a different etchant and / or different etching conditions than the first etching process (ET1) to deepen the gate contact opening (O21, O22), wherein the second etching process (ET2) etches the etch-resistant layer (145) at a slower etch rate than the etching of the contact etch stop layer (146) and the etching of the gate dielectric cover (142); and Forming a gate contact (151, 152) in the recessed gate contact opening (O21, O22), wherein the second anisotropic etching process (ET2) widens lower sections of the gate contact openings (021, O22) laterally during the etching of the etch-resistant layer (145), such that the gate contact openings (021, O22) have increased bottom widths and a vertical sidewall profile, such that the sidewalls of the gate contact openings (021, O22) extend linearly and vertically through an entire thickness of the ILD layer (148), an entire thickness of the contact etch stop layer (146), an entire thickness of the etch-resistant layer (145) and an entire thickness of the gate dielectric cover (142) without a change in inclination.
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Citation Information

Patent Citations

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