Multigate device with air gap spacer and rear rail contact and its manufacturing process

Abstract

Device comprising: having a multi-gate device (200, 200', 200"): a first channel layer (208) and a second channel layer (208) arranged between a source feature (1702A) and a drain feature (1702B), wherein the second channel layer (208) is the channel layer of the multigate device (200, 200', 200") that is closest to a front face of the multigate device (200, 200', 200"); a metal gate (2202-2208) surrounding the first channel layer (208) and the second channel layer (208), a first air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the source feature (1702A), and a second air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the drain feature (1702B); a rear contact (3002) extending to the source feature (1702A); a current-conducting metallization layer (3004) connected to the rear contact (3002); and a residue (1402') of dielectric material next to the first air gap spacer (2702") and adjacent to the second channel layer (208), wherein the first air gap spacer (2702") exposes the first channel layer (208).

Description

BACKGROUND

[0001] The electronics industry is experiencing a growing demand for increasingly smaller and faster electronic devices capable of handling a greater number of increasingly complex and demanding functions. To meet these demands, the integrated circuit (IC) industry has a continuing trend toward manufacturing cost-effective, high-performance, and energy-efficient ICs. To date, these goals have largely been achieved by reducing IC dimensions (for example, minimum IC feature size), thereby improving production efficiency and reducing associated costs. However, such scaling has also led to more complex IC manufacturing processes. Therefore, further advancements in IC devices and their performance require similar progress in IC manufacturing processes and technology.

[0002] Recently, multigate devices have been introduced to improve gate control. It has been shown that multigate devices increase gate-channel coupling, reduce off-state current, and / or mitigate short-channel effects (SCEs). One such multigate device is the gate-all-around (GAA) device, which features a gate structure that can partially or completely surround a channel area to provide access to the channel area from at least two sides. GAA devices enable aggressive miniaturization of IC technologies while maintaining gate control and suppressing SCEs, and they integrate seamlessly into conventional IC fabrication processes. However, further scaling of GAA devices presents challenges in achieving the desired gate density and performance.For example, miniaturizing devices can lead to increased resistance due to smaller conductive features, while smaller dielectric features can result in higher capacitance, both of which negatively impact device performance. Therefore, existing GAA devices and manufacturing processes for such devices are generally suitable for their intended purposes, but not entirely satisfactory.

[0003] Multigate devices are known, for example, from US 2018 / 0 331 232 A1. US 2019 / 0 157 310 A1 describes techniques for back-contacting semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, the various features are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be enlarged or reduced as desired for the sake of clarity. Fig. Figure 1 is a flowchart of a process for manufacturing a multigate device according to various aspects of the present disclosure. Fig. 2, Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A and Fig. Figure 10A are fragmentary cross-sectional views of the multigate device in parts or in its entirety at various stages of manufacture (for example, those associated with the process in Fig. 1) according to various aspects of the present revelation. Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A, Fig. 22B, Fig. 23, Fig. 24, Fig. 25, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29 and Fig. 30A are fragmentary perspective views of a multigate device, in parts or as a whole, at various stages of manufacture (for example, those associated with the process in Fig. 1) according to various aspects of the present revelation. Fig. 26B, Fig. 27B, Fig. 28B, Fig. 30B and Fig. Figures 30C are fragmentary cross-sectional views of a portion of the multigate device according to the aspects of Fig. 26A, Fig. 27A, Fig. 28A and Fig. 30A. Fig. 31A, Fig. 31B and Fig. Figure 31C are a fragmentary perspective view and fragmentary cross-sectional views of another multigate device, in part or as a whole, which may be manufactured according to various aspects of the present disclosure. Fig. 32A, Fig. 32B and Fig. Figures 32C are a fragmentary perspective view and fragmentary cross-sectional views of another multigate device, in part or as a whole, which may be manufactured according to various aspects of the present disclosure. Fig. Figure 33 is an outline drawing of an implementation of a device according to one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure relates generally to integrated circuit devices and, in particular, techniques for their fabrication and resulting multigate devices. The present invention provides devices with the features of claim 1 and 8, as well as a method with the features of claim 13. Exemplary embodiments are given in the dependent claims.

[0006] The following disclosure provides many different embodiments and examples of the implementation of various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the embodiment of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, spatially relative terms, such as "below," "above," "horizontal," "vertical," "above," "over," "below," "under," "upward," "downward," "front," "back," etc., are used.as well as derivatives thereof (for example, "downwards," "upwards," etc.) are used to simplify the present disclosure of the relationship of one feature to another feature. The spatially relative terms are intended to encompass various orientations of the device that incorporates the features. Furthermore, when a number or range of numbers is described by "approximately," "about," or the like, the term is intended to encompass numbers that lie within a reasonable range, taking into account variations that naturally occur during manufacturing, as understood by a person skilled in the art. For example, the number or range of numbers encompasses a reasonable range including the described number, such as within + / -10% of the described number, based on known manufacturing tolerances in connection with the manufacture of a feature that has a property associated with the number.For example, a material layer with a thickness of "about 5 nm" may have a dimensional range of 4.5 nm to 5.5 nm, wherein manufacturing tolerances associated with the application of the material layer are known to a person skilled in the art and amount to + / -10%. Furthermore, reference numerals may be repeated in the various examples presented in this disclosure. This repetition serves for simplicity and clarity and does not necessarily imply any relationship between the various embodiments and / or configurations discussed.

[0007] As device dimensions decrease, the resistance of the associated metal interconnect lines can increase. One technique for reducing metallization line resistance, presented below, involves placing the routing on the back of the device, thereby freeing up additional space and allowing for larger metallization lines. One metal routing feature that can benefit from such a configuration is a power rail. Configuring the device's power rail on the back also allows for higher gate density (e.g., more densely packed gates on the device) due to the additional routing space. Furthermore, the width of the power rail metallization line can be increased when located on the back of the device.This is because the power rail is not constrained by the M0 routing of the front of the device. In some implementations, the width of the rear power rail can be more than twice that of a similarly configured front power rail. The greater the width of the metallization line, the lower its resistance, which affects the IR drop and consequently the circuit performance.

[0008] Further improvements, described herein in one or more embodiments, provide an air gap between the gate structure and the source / drain region. This air gap can enable a reduction in capacitance compared to other configurations with internal spacers, since the dielectric constant of air is approximately 1. The internal air gap spacer can provide improvements in device performance, enabling AC reduction and speed improvements for the resulting device.

[0009] The present disclosure therefore proposes methods and devices that provide an internal spacer formed at least partially from an air gap and / or a backside metallization routing (for example, a busbar routing). In some implementations, the internal air gap spacer is formed during the backside machining of the device. During the backside machining of the device, in some implementations, some or all of the internal spacers formed during the fabrication of the device features (for example, gate, source / drain) are selectively removed. The previous internal spacers are replaced by air, which has a dielectric constant close to 1, thus advantageously reducing the capacitance of the device, as explained above.In some embodiments, the methods include forming a dielectric fin that separates a first GAA device (in particular, a first metal gate of the first GAA device) from a second GAA device (in particular, a second metal gate of the second GAA device). Furthermore, internal air gap spacers can be provided between a gate and the dielectric fin, which also offer the advantages of a low dielectric constant within the space. Details of the internal air gap spacers and rear connections for busbar techniques for manufacturing GAA devices and resulting GAA devices as proposed herein are described with reference to the following pages and / or drawings.It should be noted that, while a multigate device incorporating GAA transistors is used for the following explanation, it is conceivable that other device types, such as fin-type field-effect transistors (FinFETs), could also be provided by the present methods and apparatus. Furthermore, the GAA devices described herein may include n-type field-effect transistors (NFETs) and / or p-type field-effect transistors (PFETs).

[0010] Fig. Figure 1 is a flowchart of an embodiment of a method 100 for manufacturing a multigate device according to various aspects of the present disclosure. In some embodiments, the method 100 manufactures a device comprising multiple gate all-around transistors (GAAs). The method 100 is only exemplary and is not intended to limit the present disclosure to its explicit description. Additional steps may be provided before, during, and after the method 100, and some steps described herein may be substituted, eliminated, or rearranged for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. In addition to what is explicitly shown in the drawings of the present disclosure, the semiconductor device 200 may include additional transistors, bipolar transistors, resistors, capacitors, diodes, fuses, etc.The multigate device 200, or a part thereof, may be contained in a microprocessor, a memory device, and / or another IC device. In some embodiments, the multigate device 200 is part of an IC chip, a system-on-a-chip (SoC), or a part thereof. The exemplary drawings of the multigate 200 have been simplified for clarity to better illustrate the inventive concepts of this disclosure. Additional features may be added to the multigate device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the multigate device 200. Except for the specifically noted differences of exemplary devices 200, 200', 200", and 200''', a description of one of the devices applies to the other exemplary devices.Throughout this disclosure, identical reference numerals denote identical / similar features unless otherwise specified or described.

[0011] Method 100 begins at block 102, where a substrate with several fin structures formed on it is obtained. Referring to the example of Fig. 2 A substrate 202 is provided. In one embodiment, the substrate 202 can be a silicon substrate (Si substrate). In some other embodiments, the substrate 202 can contain other semiconductors such as germanium (Ge), silicon-germanium (SiGe), or a III-V semiconductor material. Exemplary III-V semiconductor materials can include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 can also contain an insulating layer such as a silicon oxide layer to obtain a SOI (silicon-on-insulator) structure or a GOI (germanium-on-insulator) structure.In some embodiments, the substrate 202 can have one or more well regions, such as n-well regions doped with an n-dopant (e.g., phosphorus (P) or arsenic (As)) or p-well regions doped with a p-dopant (e.g., boron (B)), to form different types of devices. An ion implantation process, a diffusion process, and / or another suitable doping process can be carried out to form the different doped regions.

[0012] With further reference to Fig. 2. A stack 204 of epitaxial layers can be arranged on the substrate 202. The stack 204 can contain several semiconductor layers 208 nested with several sacrificial layers 206. As explained in more detail below, the semiconductor layers 208, or parts thereof, form channel regions of the multigate device 200 and are therefore referred to as channel layers 208. The channel layers 208 and the sacrificial layers 206 can have different semiconductor compositions. The sacrificial layers 206 and the channel layers 208 are deposited alternately to form the stack 204. In some implementations, the channel layers 208 are made of silicon (Si) and the sacrificial layers 206 are made of silicon germanium (SiGe).In some embodiments, the additional germanium content in the sacrificial layers 206 allows for selective removal or recession of the sacrificial layers 206 without significant damage to the channel layers 208, as explained below. In some embodiments, the stack 204 comprising the sacrificial layers 206 and the channel layers 208 can be formed using an epitaxial deposition technique. Exemplary techniques include, but are not limited to, CVD deposition techniques (for example, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV CVD)), molecular beam epitaxy (MBE), and / or other suitable methods. It should be noted that four (4) layers of the sacrificial layers 206 and four (4) layers of the channel layers 208 are shown in the representation of . Fig. 2 are arranged alternately and vertically. However, this is for illustrative purposes only and is not intended to restrict the wording of the claims. The number of layers depends on the desired number of channel elements for the semiconductor device 200. In some embodiments, the number of channel layers 208 is 2 to 10. The channel layers 208 and / or the sacrificial layers 206 can have a constant thickness or vary in thickness. The thickness can be selected based on the performance of the device 200, including the channel dimensions (layers 208), the gate height (layers 206), and the desired height of the inner air gap spacer (see below).

[0013] A buried etch stop layer 210 can also be arranged in the substrate. The buried etch stop layer 210 can also be epitaxially grown or formed by implantation into the substrate. In some embodiments, the buried etch stop layer 210 has the same composition as the sacrificial layers 206. In one embodiment, the buried etch stop layer 210 contains silicon germanium (SiGe). Additional substrate material 202 is formed above the buried etch stop layer 210.

[0014] Referring now to the examples in Fig. 3A and Fig. 3B several fin structures 212 are separated from the substrate 202 and the stack 204 of Fig. 2 formed. The fin structures 212 each extend essentially parallel to each other along a y-direction and have a length defined in the y-direction, a width defined in an x-direction, and a height defined in a z-direction. The fin structures 212 each define an active area on the substrate. With reference to the example of Fig. 2. The fin structures 212 are formed by the epitaxial stack 204. While the exemplary drawings show two (2) or four (4) fin structures, this is for illustrative purposes only and is not intended to limit the wording of the claims. The fin structures 212 comprise the epitaxial stack 204 and also a portion of the underlying substrate, designated 202A. It is noted again that the section 202A above the buried etch stop layer 210 can be an epitaxially grown layer of the substrate 202. In some implementations, the section 202A is silicon.

[0015] For structuring purposes, a hard mask layer 216 can be arranged over the stack 204. The hard mask layer 216 can be a single layer or a multiple layer. In one embodiment, the hard mask layer 216 comprises a silicon oxide layer and a silicon nitride layer. In some embodiments, a lithography and / or etching process is performed to structure a semiconductor layer stack to form fins 212. The lithography process can include: forming a resist layer over the semiconductor layer stack 204 (for example, by spin coating), performing a firing process before exposure, performing an exposure process using a mask, performing a firing process after exposure, and performing a development process.During the exposure process, the resist layer is exposed to radiant energy (e.g., UV light, DUV light (deep ultraviolet), or EUV light (extreme ultraviolet)). Depending on the mask's structure and / or type (e.g., binary mask, phase-shift mask, or EUV mask), the mask blocks, transmits, and / or reflects radiation onto the resist layer, projecting an image onto the resist layer that corresponds to the mask structure. Because the resist layer is sensitive to radiant energy, exposed areas of the resist layer undergo chemical changes. During the development process, exposed (or unexposed) areas of the resist layer dissolve, depending on the properties of the resist layer and the properties of the developing solution used. After development, the structured resist layer comprises a resist structure that matches the mask.The etching process removes sections of the semiconductor layer stack 204 using the structured resist layer and / or the hard mask layer 216 as an etch mask. The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After the etching process, the structured resist layer is removed, for example, by a resist stripping process or another suitable process.Alternatively, the fin structures 212 are formed by a multiple structuring process, such as a DPL process (Double Patterning Lithography) (such as a LELE process (Lithography-Etch-Lithography-Etch), a SADP process (Self-Aligned Double Patterning), a SID-SADP process (Spacer-Is-Dielectric-SADP), another double structuring process or combinations thereof), a triple structuring process (such as a LELELE process (Lithography-Etch-Lithography-Etch-Lithography-Etch), a SATP process (Self-Aligned Triple Patterning), another triple structuring process or combinations thereof), another multiple structuring process (such as a SAQP process (Self-Aligned Quadruple Patterning)) or combinations thereof. Such processes can also provide fin structures 212 with hard mask layer 216, semiconductor layer stack 204 and fin section 202A, as in . Fig. 3A, Fig. Figure 3B illustrates this. In some embodiments, DAS (Directed Self-Assembly) techniques are used for structuring the semiconductor layer stack 204. Furthermore, in some embodiments, the exposure process can implement maskless lithography, electron beam (E-beam) etching, and / or ion beam etching for structuring the resist layer. The fin structure 212 is arranged between grooves 214 formed by the corresponding etching process.

[0016] Method 100 continues with block 104, in which insulation features such as STI (Shallow Trench Isolation) features are formed between the fin structures. Referring to the example of Fig. 4A, Fig. 4B, Fig. 5A and Fig. In 5B, shallow trench insulation features 402 are arranged in the trench 214. In one embodiment, the insulation material is, for example, multilayered, including a lining layer and an overlying layer, such as an oxide material. In some embodiments, the oxide material is deposited by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable oxide material (e.g., in a liquid state) over the multigate device 200 and converting the flowable oxide material into a solid oxide material by an annealing process. The flowable oxide material can flow into the trenches 214 and conform to the exposed surfaces of the multigate device 200, which in some implementations enables void-free filling of the trenches 214.

[0017] In some embodiments, the insulating material forming the insulating layer 402 can comprise SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable, conventional materials. In various examples, the dielectric material can be deposited by a CVD process, a SACVD (subatomospheric CVD) process, a FCVD (flowable CVD) process, an ALD process, a PVD process, or another suitable process. The deposition process can overfill trenches 214 (not shown) so that the thickness of the material for the insulating features 402 is greater than the height of the fins 212. After the deposition process, a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed on the materials, thereby reducing the thickness. This planarization forms a surface as shown in Fig. 4A and Fig. Figure 4B shows that in one embodiment the planarization process is carried out with an etching stop of the hard mask layer 216.

[0018] The formation of the insulating features can then continue to spare the deposited (and planarized) insulating material(s) to form the STI structures, so that the fin structures extend over the STI structures. Referring to the example of Fig. 5A and Fig. 5B The insulating material(s) can then be recessed so that the fin structures 212 extend (protrude) between the etched insulating features 402. The etching process for recessing the insulating material is configured such that material (e.g., oxide) is selectively removed with respect to the fin structure 212. Thus, the insulating features 402 fill the lower portions of the grooves 214 between the fin structure 212. In some embodiments, a field oxide, a LOCOS feature, and / or other suitable insulating features can additionally or alternatively be implemented on and / or within the substrate.

[0019] Process 100 then continues with block 106, in which a mantle layer is formed over the fin structure. The mantle layer can be a sacrificial layer and can be formed over any fin structure. According to the example of Fig. 6A and Fig. In 6B, a shell layer 602 is formed on each fin element 212. In some embodiments, the shell layer 602 may have a composition similar to that of the sacrificial layers 206. In one embodiment, the shell layer 602 is made of silicon germanium (SiGe). In some embodiments, the shell layer 602 and the sacrificial layers 206 have a composition that allows for the selective removal of the sacrificial layers 206 and the shell layer 602 during the release of the channel layers 208 in a subsequent process by a single etching process, as explained in more detail below.In one embodiment, the cladding layer 602 can be epitaxially grown using gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), or formed by a deposition process such as a CVD process, a subatmospheric CVD process (SACVD), a flowable CVD process, an ALD process, a PVD process, or another suitable process. In some embodiments, the operations in Block 106, following conformal deposition of the material for the cladding layer 602, may include a back-etching process to remove material of the cladding layer 602 from portions of the insulation feature 402 between the fins. In some implementations, Block 106 may be omitted. It should be noted that other lining layers may be formed in addition to, or instead of, the cladding layer 602 over the fin structures 212, before or after the formation of the insulation features in Block 104.In some embodiments, an oxide lining and / or a silicon lining can be formed over the fin structure 212 before the formation of the insulation features 402.

[0020] Method 100 then proceeds to Block 108, in which separating structures, also known as dielectric fins, are formed between the upper sections of the fin structures, thereby separating the adjacent active regions and later serving to separate adjacent gate structures formed over the active regions, if desired. The dielectric fins can comprise a multilayer structure that fills the gap between the fin structures and is positioned over the STI features of Block 104. Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A and Fig. Figure 10B illustrates one embodiment of the formation of a multilayer separating structure or dielectric fins between active areas. Referring to the example of Fig. 7A, Fig. In step 7B, a first dielectric layer 702 is deposited over the device 200. In one embodiment, the first dielectric layer 702 is a high-k dielectric. In another embodiment, the first dielectric layer 702 can be silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof. In some embodiments, the dielectric layer 702 contains HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, another suitable high-k dielectric material, or combinations thereof. A second dielectric layer, such as an oxide layer, 704 can then be formed over the first dielectric layer 702.In some embodiments, the oxide layer 704 can be deposited by a flowable CVD, HARP, and / or other process that provides suitable gap-filling properties. In some embodiments, the trenches 214 can be overfilled with the oxide layer, and after deposition of the oxide layer 704, a CMP process can be performed, resulting in a substantially flat top surface, as shown in [reference]. Fig. 7A and Fig. Figure 7B shows that in one embodiment, the cladding layer 602 provides an etching stop for this planarization process.

[0021] Further in the course of the production of the dielectric fins and with reference to Fig. 8A and Fig. In 8B, layers 702 and / or 704 are etched back, forming an opening 802. In one embodiment, the oxide layer 704 is removed to form the opening 802, which has sidewalls defined by the first dielectric layer 702 and is bounded by the grooves 214. In another embodiment, layers 702 and 704 are each removed to form the opening 802, as shown in Fig. 8A, Fig. Figure 8B shows the etching process for forming the opening 802. This process can be a dry etching process, a wet etching process, or a combination thereof.

[0022] As in Fig. 9A and Fig. As shown in Figure 9B, a third dielectric material 902 of the dielectric fin is formed within the openings 802. The dielectric material 902 can be deposited to overfill the opening 802, and subsequently, excess material is removed by a planarization process. In one embodiment, the dielectric material 902 is a high-k dielectric. In some embodiments, the dielectric material 902 is essentially the same composition as the first dielectric layer 702. In one embodiment, the dielectric material 902 can be silicon nitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or combinations thereof.In some embodiments, the dielectric layer 702 comprises HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3, (Ba,Sr)TiO3, HfO2-Al2O3, another suitable high-k dielectric material, or combinations thereof. The dielectric material 902 can be deposited by a suitable process, such as a SACVD process, an FCVD process, another CVD process, an ALD process, a PVD process, or another suitable process. In some implementations, a planarization process is performed following deposition, thereby thinning the deposited dielectric material 902 to obtain a flat surface. In some embodiments, the planarization process can terminate at the hard mask 216.

[0023] The dielectric layers 702, 704, and 902, as described above, together form the separating structure, which is referred to as a dielectric fin 904. The dielectric fin 904 extends between adjacent active regions, the fin structures 212, and in particular between sections of the cladding layer 602 that are arranged on the aforementioned adjacent fin structures 212. The dielectric fin 904 is so named because the dielectric fins 904, like the fin structures 212, extend vertically (in the Z direction) above the substrate 202 (in particular above the insulating structure 402) and longitudinally along the Y direction from the substrate 202, and are spaced apart in the X direction from the adjacent dielectric fin 904.

[0024] In some embodiments, after the formation of the dielectric fin 904 and before the formation of the dummy gate, the hard mask 216 and the adjacent cladding layers 602 are etched to form an opening 1002, as shown in Fig. 10A and Fig. Figure 10B illustrates this. In some embodiments, an upper surface of a top channel region 208 is exposed by etching, on which the gate structure can be formed, as described below. The etching is carried out selectively on the hard mask 216 and the cladding layers 602, either by using a selective etching agent or by using masking elements, so that the dielectric fins 904 are preserved.

[0025] Procedure 100 then continues with block 110, in which a dummy gate structure is formed over the fin structures. Referring to the example of Fig. 11. Dummy gate structures 1102 are formed over sections of the fins 212 and the dielectric fins 904. The dummy gate structures 1102 fill parts of the openings 1002, are arranged on the uppermost channel layer 208, and can extend over the dielectric fins 904. The dummy gate structures 1102 extend longitudinally in a direction different from the longitudinal direction of the fin structures 212 (for example, perpendicular to it). For example, the dummy gate structures 1102 extend substantially parallel to each other along the x-direction and have a length defined in the x-direction, a width defined in the y-direction, and a height defined in the z-direction. The dummy gate structures 1102 are arranged above channel areas of the fins 212 of the multigate device 200 and between source / drain areas (S / D areas) of the fin structures 212 of the multigate device 200.The dummy gate structures 1102 can each extend over one or more fin structures 212.

[0026] The dummy gate structures 1102 each comprise a dummy gate dielectric 1104 and a dummy gate electrode 1106. The dummy gate dielectric 1104 contains a dielectric material, such as silicon oxide, a high-k dielectric, another suitable dielectric material, or combinations thereof. In some embodiments, the dummy gate dielectric 1104 comprises an interface layer (for example, silicon oxide) and a high-k dielectric layer arranged above the interface layer. The dummy gate electrode 1106 contains a suitable dummy gate material, such as polysilicon. In some embodiments, the dummy gate structures 1102 comprise numerous additional layers, such as hard mask layers, cover layers, interface layers, diffusion layers, barrier layers, or combinations thereof. In one implementation, the hard mask layer comprises a silicon oxide layer and a silicon nitride layer.The dummy gate structures 1102 are formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, a first deposition process is performed to form a dielectric dummy gate layer over the multigate device 200, and a second deposition process is performed to form a dummy gate electrode layer over the dielectric dummy gate layer. The deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof. A lithographic structuring and etching process is then carried out to structure the hard mask layer, the dummy gate electrode layer and the dummy gate dielectric layer to form dummy gate structures 1102 comprising the dummy gate dielectric 1104 and the dummy gate electrode 1106, as shown in . Fig. Figure 11 illustrates the lithographic structuring processes. These include coating the resist (e.g., spin coating), soft firing, mask alignment, exposure, post-exposure firing, resist development, rinsing, drying (e.g., hard firing), other suitable lithographic processes, or combinations thereof. Etching processes include dry etching, wet etching, other etching processes, or combinations thereof.

[0027] The dummy gate structures 1102 can further include gate spacers 1202 arranged on the side walls. Referring to the example of Fig. 12. Gate spacers 1202 are formed along the side walls of the dummy gate stacks 1102. The gate spacers 1202 can contain a suitable dielectric material. The dielectric material can contain silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon oxycarbide, and / or silicon oxycarbonitride). In some embodiments, the gate spacers 1202 comprise a multilayer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide. In some embodiments, more than one set of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, is formed alongside the dummy gate structures 1102.

[0028] Procedure 100 then continues with block 112, in which the source / drain regions of the fin structure(s) are omitted to prepare for the formation of source / drain features. Referring to the example in Fig. 12. Sections of the fin structures 212 in the source / drain regions of the multigate device 200 (i.e., source / drain regions of the fin structures 212 that are not covered by the gate structures 1102) are at least partially removed or recessed to form source / drain recesses or grooves 1204. In the illustrated embodiment, the semiconductor layer stacks 204 in the source / drain regions of the multigate device 200 are completely removed by an etching process, thereby exposing the fin sections 202A in the source / drain regions. In embodiments, sections of the cladding layer 602 that are adjacent to the source / drain regions of the fin structures 212 are also completely removed by the etching process.In the illustrated embodiment, each source / drain recess 1204 thus has a side wall defined by a corresponding dielectric fin 904 and a bottom surface defined by a corresponding fin section 202A and a corresponding insulating feature 402. The etching process may comprise a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the etching process is a multi-stage etching process. In some embodiments, the recess removes an upper section of the dielectric fin 904 (for example, a section of a dielectric layer 902).

[0029] Procedure 100 then continues with block 114, in which internal spacers are provided between the respective source / drain area and the gate structure. Fig. 13, Fig. 14 and Fig. Figure 15 illustrates exemplary steps for forming multi-layered inner spacers. Referring first to Fig. In some embodiments, block 114 comprises slight (lateral) etching of sacrificial layers 206 to form recesses 1302 (for example, vertically beneath the gate structure 1102 and including the gate spacers 1202). The recesses 1302 are formed between hanging end regions of the channel layers 208. In one embodiment, the recesses 1302 are formed by selective etching of the silicon germanium (SiGe). In some embodiments, the channel layers 208 are slightly etched, thereby reducing their thickness at the recesses 1302. In one embodiment, the recesses 1302 have a height h1 of about 5 nm (nanometers) to about 15 nm. In one embodiment, the recesses 1302 have an inner edge (such as the nearest channel) which is substantially aligned (flanked) with an inner edge (such as the nearest gate) of the gate spacers 1202.In one embodiment, the recesses 1302 have a width w1 of approximately 2 nm to approximately 15 nm. The width and height of the recesses 1302 can define the dimensions of the subsequently formed air gap, as explained in more detail below, whereby the choice of thickness t1 and width w1 influences the performance of the device with respect to capacitance and affects the manufacture of the device. It should be noted that in some embodiments, the recesses 1302 extend to the dielectric fin 904. The sheath layer 602 can be etched simultaneously with the sacrificial layers 206, thereby creating part of the recess 1302 between the end of the channel layer 208 and the dielectric fin 904.

[0030] Further details will follow regarding the formation of the inner spacers and with reference to the example of Fig. 14. A first inner spacer 1402 is formed in each of the recesses 1302. In one embodiment, the first inner spacer 1402 is a dielectric material. Exemplary materials for the first inner spacer 1402 include nitride (for example, SiN, SiON). In another embodiment, the first inner spacer 1402 comprises a different type of material that provides selectivity with respect to the surrounding materials. In one embodiment, the first inner spacer 1402 may be referred to as a dummy spacer or dummy dielectric, since it is a sacrificial material that is subsequently removed to form the air gap features or parts thereof, as explained below. The first inner spacer 1402 extends between adjacent hanging regions of the channel layers 208 and between a bottommost channel layer 208 and section 202A.The first inner spacer 1402 also extends between one end of the channel layers and the dielectric fin 904.

[0031] In one embodiment, the thickness t1 of the second inner spacer is approximately 1 nm to approximately 10 nm. The thickness t1 may be less than the width w1 of the recess 1302. In some embodiments, dielectric material is deposited (for example, conformally) over the device 200 and subsequently back-etched to provide the first inner spacer 1402, which is contained within the recesses 1302. The first inner spacers 1402 each extend the height h1 of the recess 1302. In some embodiments, the thickness t1 of the inner spacer is selected to determine the dimensions of the air gap. If the thickness t1 is too large, the air gap may allow subsequently deposited layers (see block 130) to intrude into the air gap. If the thickness t1 is too small, the provided air gap is so large that the performance of the device is not sufficiently improved by the resulting air gap, as explained below.

[0032] The first inner spacer abuts the stack 204, which comprises the sacrificial layers 206; the first inner spacer may abut the perimeter of the side wall of the sacrificial layer 206. Due to the slight etching of the channel layers 208 during the formation of the recesses 1302, in some embodiments a small area of ​​the side wall of the channel layer 208 may be contacted, in addition to the boundaries formed by the upper and lower surfaces of the channel layers 208. In other embodiments, the etching of the recesses 1302 does not affect the channel layer 208, and the first inner spacer layer 1402 abuts only an upper and / or a lower surface of the channel layers 208. The first inner spacer layer 1402 further abuts the dielectric fin 904 as described above.Similarly, the first spacer layer can contact a part (for example, the lower surface) of the gate spacer 1202 and a part (for example, the upper surface) of the isolation feature 402 where the cladding layer was previously removed.

[0033] Continuing with the formation of internal spacers and with reference to the example of Fig. In 15, a second inner spacer 1502 is formed in each of the recesses 1302, which abuts the first inner spacer 1402. In one embodiment, the second inner spacer 1502 is a low-k material. Examples of materials for the second inner spacer 1502 include SiOC, SiCN, SiOCN, or combinations thereof.

[0034] In some implementations, the low-k material of the second inner spacer 1502 is deposited over the device 200 and subsequently back-etched to provide the second inner spacer 1502 within the recesses 1302. The deposition methods for the material of the second inner spacer include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, and / or other suitable methods. In some embodiments, the thickness t2 of the second inner spacer 1502 is less than the thickness t1 of the first inner spacer 1402. The thicknesses t1 and t2 affect the dielectric constant of the region between the source / drain feature and the subsequently formed metal gate, and thus the capacitance of the device, as described below.

[0035] In one embodiment, the thickness of the second inner spacer t2 is approximately 1 nm to approximately 5 nm. The thickness t2 can be less than the width w1 of the recess 1302. In some embodiments, t1 plus t2 is essentially equal to the width w1 of the recess 1302. Each of the second inner spacers 1502 increases the height h1 of the recess 1302. Thus, the height of the second inner spacers 1502 is approximately 5 nm to 15 nm in some embodiments. In some implementations, such as in the device 200', the thickness of the second inner spacers t2 is chosen to define part of the inner air gap spacer dimensions. In some implementations, the thickness of the second inner spacers t2 is controlled so that it is not too large, which can lead to an increase in the device's capacity (for example, by reducing the dimensions of an air gap).In some implementations, the thickness of the device of the second inner spacer t2 is chosen to be sufficient to protect the source / drain feature during the removal of the first inner spacer 1402 to form the air gap, as explained below.

[0036] The second inner spacer 1502 borders the first inner spacer 1402 and an upper / lower surface of the channel layers 208. The second inner spacer layer 1502 further borders the dielectric fin 904 and, in particular, the first dielectric layer 702. In some embodiments, this interface is located in the area where the cladding layer 206 has been removed. In one embodiment, the first dielectric layer 702 may have the same composition as the second inner spacer layer 1502. The second spacer layer may further border a section (for example, the lower surface) of the gate spacer 1202 and a section (for example, the upper surface) of the insulating feature 402 where the cladding layer has previously been removed. The second inner spacer 1502 also borders the source / drain region and, if present, the source / drain feature.

[0037] In some implementations, the inner spacers 1402 / 1502 are slightly recessed along the y-direction relative to the semiconductor layers 208, so that the spacers 1402 / 1502 do not cover the entirety of the upper and / or lower surfaces of the semiconductor layers 208, and a semiconductor layer 208 can be observed extending from above / below the inner spacers 1402 / 1502. In other words, the recess 1302 may not be completely filled in some embodiments. In other embodiments, the inner spacers 1402 / 1502 do cover the entirety of the upper and / or lower surfaces of the semiconductor layers 208. In other words, an outer surface of the second inner spacer 1502 is vertically aligned with an outer edge of the channel layer 208 in some embodiments.

[0038] Method 100 then proceeds to Block 116, in which etching is performed at a terminal of the GAA transistor(s) of the device. In some embodiments, further etching is performed on one of the source sides or one of the drain sides of the device. In one embodiment, etching of the substrate is performed beneath the source side of the device(s). The etching can be performed at a terminal (for example, source / drain) where a back-side contact is to be formed, as further explained below. With reference to the example of Fig. In step 16, a source-side recess 1602 is etched into the source / drain region of the device 200, and in particular into the fin 212. The source-side recess 1602 adjoins the recess 1204. In some implementations, a masking element 1604 is positioned over the device 200 to form the recess 1602, providing an opening above the source side of the etched back fin structure 212. Within the opening, the depth of the recess 1604 is extended by an etching process, either on the source side or the drain side. The recess 1602 can be selectively etched by a suitable wet or dry etching process suitable for etching the composition of the substrate 202 (for example, silicon), while minimizing or avoiding the etching of adjacent dielectric materials, including the second inner spacers 1502, the dielectric fin 904 and the insulating feature 402.The source-side recess 1602 can end above the buried etch stop layer 210.

[0039] Procedure 100 then continues with block 118, in which source / drain features for the device are grown. Referring to the example in Fig. Source / drain features 1702 are formed. The source / drain features are designated as a source feature 1702A and a drain feature 1702B, although other configurations are also possible. The source feature 1702A and the drain feature 1702B are collectively referred to as source / drain features 1702. In one embodiment, the source feature 1702A and the drain feature 1702B are of the same type (for example, NFET, PFET). To form the source / drain features 1702, a semiconductor material is epitaxially grown from exposed nucleation sites (such as fin sections 202A of the substrate 202) within the recesses 1204 and 1602. In some embodiments, the semiconductor layers 208 exposed by the source / drain recesses 1204 are also nucleation areas for the epitaxial material, the growth rate of which may differ from the upper surface of the fin sections 202A.In some embodiments, the epitaxial source / drain features 1702 completely fill the respective source / drain recesses, such that the upper surfaces of the epitaxial source / drain features 1702 are essentially planar with a bottom surface of the gate structure 1102. An epitaxial process can employ CVD deposition techniques (e.g., LPCVD, VPE, and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth methods, or combinations thereof. The epitaxial process can utilize gaseous and / or liquid precursors that interact with the composition of the fin sections 202A and / or the semiconductor layers 208. The epitaxial source / drain features 1702 are doped with n-type and / or p-type dopants.In some embodiments with n-transistors, the epitaxial source / drain features 1702 comprise silicon, which may be doped with carbon, phosphorus, arsenic, other n-dopants, or combinations thereof (so that, for example, epitaxial Si:C source / drain features, epitaxial Si:P source / drain features, or epitaxial Si:C:P source / drain features are formed). In some embodiments with p-transistors, the epitaxial source / drain features 1702A / B comprise silicon germanium or germanium, which may be doped with boron, another p-dopant, or combinations thereof (so that, for example, Si:Ge:B epitaxial source / drain features are formed). In some embodiments, the epitaxial source / drain features 1702 comprise more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may have the same or different materials and / or dopant concentrations.In some embodiments, the epitaxial source / drain features 1702 contain materials and / or dopants that generate a desired tensile and / or compressive stress in the respective channel regions of the n-transistors and / or the p-transistors. In some embodiments, the epitaxial source / drain features 1702 are doped during deposition by adding impurities to a starting material of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain features 1702 are doped by an ion implantation process following a deposition process.In some embodiments, annealing processes (e.g., rapid thermal annealing and / or laser annealing) are performed to activate dopants in epitaxial source / drain features 1702 and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain regions (LDD)). In some embodiments, certain epitaxial source / drain features 1702 of the device 200 are formed in separate processing sequences, which, for example, include one transistor region when epitaxial source / drain features 1702 are formed in another transistor region.

[0040] It should be noted that due to the lack of significant growth of the epitaxial material of the source / drain features 1702, a gap may form next to an exposed upper surface of the insulation structure 402. In some implementations, this gap may border the second inner spacer 1502 (for example, adjacent to the lower channel region of the device).

[0041] In some implementations, isolating layers are formed over the source / drain epitaxy features after their creation. Referring to the example in Fig. 18. Deposition processes (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof) are carried out to form a lower contact etch stop layer (B-CESL) 1802 and an inter-level dielectric (ILD) layer 1804 over the multi-gate device 200. A CMP process and / or another planarization process is carried out until the upper sections (or the upper surfaces) of the dummy gate stack 1102 are reached (exposed). In some embodiments, the ILD layer 1804 is formed by FCVD, HARP, HDP, or combinations thereof. In some embodiments, the planarization process removes the hard mask layer(s) of the dummy gate structure 1102 to expose underlying dummy gate electrodes 1106 of the dummy gate structure 1102, such as polysilicon gate electrodes.The B-CESL layer 1802 and / or the ILD layer 1804 are arranged over the epitaxial source / drain features 1702 and the dielectric fins 904 adjacent to the source / drain regions of the multigate device 200. The ILD layer 1804 is further arranged between adjacent gate structures 1102. The ILD layer 1804 contains a dielectric material, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BSG, BPSG, FSG, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric material, or combinations thereof.In some embodiments, the ILD layer 1804 contains a dielectric material with a dielectric constant that is less than that of silicon dioxide (for example, k < 3.9). In some embodiments, the ILD layer 1804 contains a dielectric material with a dielectric constant that is less than about 2.5 (i.e., an ELK (Extreme Low-k) dielectric material, such as SiO2 (for example, porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxide (for example, a SiCOH-based material (with, for example, Si-CH3 bonds)), each of which is designed / configured to have a dielectric constant of less than about 2.5. The ILD layer 1804 can have a multilayer structure with several dielectric materials.In some embodiments, the B-CESL 1802 is arranged between the ILD layer 1804 and the epitaxial source / drain features 1702, the dielectric layers 902 (the dielectric fins 904), and the gate spacers 1202. The CESL 1802 contains a different material than the ILD layer 1804, for example, a dielectric material different from that of the ILD layer 1804. For instance, if the ILD layer 1804 contains a dielectric material containing silicon and oxygen and having a dielectric constant lower than, say, that of silicon dioxide, the CESL 1802 can contain silicon and nitrogen, such as silicon nitride or silicon oxynitride.

[0042] In one embodiment, the CESL 1802 is arranged on epitaxial source / drain features 1702 and physically contacts them. The ILD layer 1804 and the CESL 1802 are part of a multilayer interconnect (MLI) feature formed above them. In some embodiments, the ILD layer 1804 and the CESL 1802 form a bottom layer of the MLI feature (for example, an ILD0). An MLI feature electrically couples different devices (such as p-transistors and / or n-transistors of the Multigate Device 200, resistors, capacitors and / or inductors) and / or components (such as gate electrodes and / or epitaxial source / drain features of p-transistors and / or n-transistors of the Multigate Device 200) so that the different devices and / or components can operate according to the design requirements of the Multigate Device 200.An MLI feature comprises a combination of dielectric layers and electrically conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as device-level contacts and / or device-level vias, and / or horizontal interconnect features, such as conductive traces. Vertical interconnect features typically connect horizontal interconnect features in different layers (or different levels) of the MLI feature. During operation, the interconnect features are configured to carry signals between the devices and / or components of the Multigate Device 200 and / or to distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to the devices and / or components of the Multigate Device 200.In one embodiment, a contact element extends through the CESL 1802 and the ILD 1804 over the drain feature 1702B to establish electrical contact with the drain feature 1702B, as shown below. In another embodiment, contact with the source feature 1702A is made via a rear contact as described below, and thus the CESL 1802 and the ILD 1804 provide insulation for the source feature 1702.

[0043] Procedure 100 then proceeds to Block 120, in which a gate replacement process is performed to replace the dummy gate structure of Block 110 with a metal gate structure. In some implementations, Block 120 further includes performing a cut metal gate process in which certain areas are defined to provide gate separation features of the dielectric fins, and certain other gate structures are defined to be connected to adjacent gates. For example, in some implementations, an etching process is performed that removes the dummy gate electrodes 1106 until the dielectric layers 902 of the dielectric fins 904 are exposed between the remaining portions of the dummy gate electrodes 1106. See Fig. 19. The exposed dielectric layers 902 are then removed from this area of ​​the dielectric fins 904, forming the opening 1904, while a masking element 1902 protects other areas. In this way, the dielectric fins 904 spanning certain device areas are retained to provide insulation between adjacent features (e.g., gate structures) and thus provide a cut-metal gate area, while sections of the dielectric fins 904 spanning certain device areas are (partially) removed so that the subsequently formed metal gate is continuous across the area. With reference to Fig. 19, Fig. 20A and Fig. In 20B, the dielectric fin 904 is retained under the masking element 1902, creating a cut-gate area, while the dielectric fin 904 on the right side of the drawing is partially removed (so that, for example, the dielectric layer 902 is recessed), forming the opening 1904.

[0044] In the further course of the gate replacement process and with reference to the example of Fig. 20A and Fig. In 20B, a remnant of the dummy gate structures 1102 is then removed. For example, the dummy gate electrodes 1106 and 1104 are completely removed by an etching process to expose an upper channel layer 208. The etching process can be a selective dry etching process, a wet etching process, or a combination thereof. The removal of the dummy gate structure forms part of the opening 2102 (for example, above the uppermost channel layer).

[0045] In the further course of the gate replacement process and with reference to the example of Fig. 21A and Fig. 21B A channel release process can be performed which leads to the removal of the sacrificial layers 206 in the channel region, thereby forming hanging semiconductor layers 208 in the channel region, separated from each other and / or from the fin sections 202A by gaps. The etching process that releases the channel layers 208 can be a selective dry etching process, a wet etching process, or a combination thereof. The channel release process can further include the removal of the cladding layer 602 in the channel region, for example, to form a gap between one end of the channel layer 208 and the dielectric fin 904. The channel release process can include an etching process selectively for a composition (for example, silicon-germanium) of the cladding layer 602 and / or the sacrificial layers 206, while no or only minimal etching of the channel layers 208 takes place.Releasing the channel layers, removing the dummy gate structure and / or removing the jacket layer 602 creates corresponding openings 2102 in the channel areas of the device 200 as shown in . Fig. 21A and Fig. Figure 21B illustrates this. A distance s1 is defined between the channel layers 208 along the z-direction, and a distance s2 is defined between the end of the channel layers 208 and the dielectric fins 904 along the x-direction. The distance s1 can be from 5 to 15 nm. In some embodiments, the distance s1 can be substantially equal to the height h1. The distance s1 can be provided such that sufficient clearance is given to form a gate structure of sufficient height for adequate performance. If the distance s1 is too large, this can cause the capacitance of the device to increase to a point where performance deteriorates. In some embodiments, the distance s2 is approximately 5 to 20 nm. If the distance s2 is too large, this can cause the capacitance of the device to increase to a point where performance deteriorates.If the spacing s2 is too small, it may not be sufficient to form the gate structure, as explained above. In some embodiments, each channel layer 208 has dimensions in the nanometer range and can be referred to individually or collectively as "nanostructures." In some embodiments, the channel layers 208 have cylindrical profiles (e.g., nanowires), rectangular profiles (e.g., nanorods), sheet-shaped profiles (e.g., nanosheets (i.e., the dimensions in the XY plane are larger than the dimensions in the XZ and YZ planes to form sheet-like structures)), or any other suitably shaped profile.

[0046] In some embodiments, the etching process for releasing the channel layers 208 partially, but minimally, etches the channel layers 208, the fin sections 202A, and / or the insulation features 402. In other embodiments, the etching process is sufficiently selective such that the channel layers 208, the fin sections 202A, and / or the insulation area 402 are minimally or not at all etched.

[0047] Block 120 of the process 100 then proceeds to fill the openings 2102 formed by removing the dummy gate structure and releasing the channel layers with a metal gate structure. The metal gate structure can be the functional gate(s) of the GAA device of the apparatus 200. With reference to Fig. 22A and Fig. 22B are metal gate structures 2202 (also referred to as metal gates and / or high-k / metal gates) formed in gate openings 2102. The metal gate structures 2202 are configured to achieve the desired functionality according to the design requirements of the multigate device 200. The metal gate structures 2202 each comprise a gate dielectric 2204 (for example, a high-k gate dielectric layer) and a gate electrode 2206 (for example, an exit working layer and a bulk conductor layer). The metal gate structures 2202 can have numerous other layers, such as cover layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof.In some embodiments, the formation of metal gate structures 2202 comprises depositing a gate dielectric layer over the multigate device 200, wherein the gate dielectric layer partially fills the gate openings 2102, depositing a gate electrode layer over the gate electrode layer, wherein the gate electrode layer fills a remainder of the gate openings 2102, and performing a planarization process to remove excess gate material from the multigate device 200. The gate dielectrics 2204 comprise a high-k dielectric layer containing a high-k dielectric material, which, for the purposes of the metal gate structure 2202, refers to a dielectric material with a dielectric constant greater than that of silicon dioxide (k ≈ 3.9).The high-k dielectric layer contains, for example, HfO₂, HfSiO₂, HfSiO₄, HfSiON, HfLaO, HfTaO, HfTiO₂, HfZrO, HfAlOx, ZrO, ZrO₂, ZrSiO₂, AlO, AlSiO₂, Al₂O₃, TiO, TiO₂, LaO, LaSiO₂, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO, BaTiO₃ (BTO), (Ba,Sr)TiO₃ (BST), Si₃N₄, hafnium dioxide-aluminum oxide (HfO₂-Al₂O₃) alloy, other suitable high-k dielectric material for metal gate stacks, or combinations thereof. The high-k dielectric layer is formed by one of the processes described here, such as ALD, CVD, PVD, oxidation-based deposition, other suitable processes, or combinations thereof. In some embodiments, the gate structure 2202 comprises an interface layer 2208 arranged between the high-k dielectric layer and the channel layers 208.The interface layer 2208 contains a dielectric material, such as SiO2, HfSiO, SiON, another silicon-containing dielectric material, another suitable dielectric material, or combinations thereof. The interface layer is formed by one of the processes described here, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof.

[0048] Gate electrodes 2206 are formed over the gate dielectrics 2204 / 2208 and fill a remainder of the gate openings 2102. The gate electrodes 2206 contain a conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, another conductive material, or combinations thereof. In some embodiments, the gate electrodes 2206 comprise a work function layer and a bulk conductive layer. The work function layer is a conductive layer configured to exhibit a desired work function (for example, an n-work function or a p-work function), and the bulk conductive layer is a conductive layer formed over the work function layer.In some embodiments, the exit layer contains n-exit work materials, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-exit work materials, or combinations thereof. In some embodiments, the exit layer contains a p-exit work material, such as ruthenium, Mo, Al, TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-exit work materials, or combinations thereof. The bulk conductor layer (or filler conductor layer) contains a suitable conductive material, such as Al, W, Ti, Ta, polysilicon, Cu, metal alloys, other suitable materials, or combinations thereof. The gate electrodes 2206 are formed by one of the processes described herein, for example, ALD, CVD, PVD, coating, other suitable processes, or combinations thereof.

[0049] After the deposition of the materials of the metal gate structure 2202, in some implementations the deposited materials are back-etched so that sections of the dielectric fin 904 extend over the gate structure, thereby providing a self-aligned metal gate cutting process as described above. The back-etching process is a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. After back-etching, the dielectric fin 904 separates and isolates certain metal gates from other metal gates, as illustrated by the left gate of Fig. Figure 22A shows that, as depicted there, the gate electrodes 2206 no longer extend continuously from a first transistor region to a second transistor region (not shown) after the etching process. Furthermore, certain gate electrodes 2006 remain on the right side of the diagram after the etching process. Fig. 22A, and as in Fig. 22B are visible and extend over the previously back-etched dielectric fins 904 (see metal gate 2202 and high-k dielectric 2204, which contact the upper surfaces of the dielectric layers 702, 704). As explained in the preceding description of method 100, the metal gate cutting process is referred to as "self-aligned" because the gate insulating structures (here, the dielectric fins 904) are aligned between the metal gates without the need for a lithography process after the formation of the metal gate stack 2206. The self-aligned arrangement of the gate insulating structures (the dielectric fins 904) provides electrical insulation between different devices, such as transistors, of the multi-gate device 200.

[0050] Method 100 then proceeds to Block 122, in which further fabrication is carried out on the front face of the device 200, comprising forming the remaining parts of an MLI. The fabrication steps may include forming various contacts, such as gate contacts and certain source / drain contacts, to facilitate the operation of the transistors of the multigate device 200. Referring to the example of Fig. Gate contacts 2302 are formed at the metal gates 2202. The gate contacts 2302 provide an electrical connection to a metallization layer 2304 (for example, metal-0 or M0), which is part of a multi-layer interconnect (MLI) 2310 formed on the front face of the device 200. Source / drain contacts 2306 can also be formed at epitaxial source / drain features 1702 A / B. In some embodiments, a source / drain contact 2306 to the source feature 1704A is not electrically connected to the MLI 2310 on the front face of the device. In some embodiments, a source / drain contact 2306 to the drain feature 1704B is electrically connected to the MLI, which has metallization layers formed above the front face of the device.The source / drain contacts and / or gate contacts can then be provided with one or more electrically conductive materials, such as tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, another metallic component with low resistivity, alloys thereof, or combinations thereof. The conductive material(s) can be deposited by PVD, CVD, ALD, electroplating, electroless plating, other suitable deposition processes, or combinations thereof. The contacts can have a multilayer structure, such as a barrier layer, a bonding layer, a bulk layer, and / or other suitable layers. Various dielectric layers, such as ILD layers, are placed between the contacts and the metallization layers.An MLI electrically couples various devices (for example, p-transistors and / or n-transistors of the Multigate Device 200, resistors, capacitors, and / or inductors) and / or components (for example, gate electrodes and / or epitaxial source / drain features of p-transistors and / or n-transistors) so that the various devices and / or components can operate according to the design requirements of the Multigate Device 200. An MLI feature typically comprises a combination of dielectric layers and electrically conductive layers (for example, metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features such as device-level contacts and / or device-level vias, and / or horizontal interconnect features such as conductive traces.Vertical interconnect features typically connect horizontal interconnect features in different layers (or levels) of the MLI. During operation, the interconnect features are configured to carry signals between the devices and / or components of the Multigate Device 200 and / or to distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or components of the Multigate Device 200. The MLI 2310 is formed on the front of the Device 200.

[0051] Method 100 then proceeds to block 124, in which the device is flipped for processing on the back side. In some embodiments, a carrier wafer is attached to the front of the device and the device is flipped. In the example of Fig. 23. A carrier wafer 2308 is attached to the front of the device above the MLI. It should be noted that the carrier wafer can be bonded to the device 200 with a removable adhesive material and can be retained or removed for each of the following processing steps. Fig. Figure 24 and the following drawings show that the device 200 is turned over so that the back is on the “top” of the device.

[0052] Method 100 then proceeds to block 126, in which the structure is thinned by removing substrate material from the back of the device. In some embodiments, the thinning is performed by attaching the front of the device 200 to a support while the back of the structure is thinned. According to the example in Fig. In step 23, a carrier wafer 2308 is attached to the front of the device 200. In the further course of the process, and with reference to Fig. 24. The device 200 is reversed for backside processing of the thinning of the device 200 by removing the substrate 202 from the back of the structure until the semiconductor fin section 202A, the adjacent insulation structure 402, and the source feature 1702A are exposed from the back of the device 200. The resulting thinned device is in Fig. Figure 25 illustrates the thinning process. The thinning process can involve multi-stage processing, for example, a mechanical grinding process followed by a chemical thinning process.

[0053] In some implementations, block 126 of process 100 continues after thinning the device 200 to remove additional fin and substrate material to expose the GAA features from the back. Referring to the example of Fig. In 26A, portions of the fin 212 are removed, forming an opening 2602. The underside of the opening exposes the first inner spacer 1402 and the second inner spacer 1502. The opening 2602 further exposes the adjacent metal gate structure 2202. In some embodiments, a dielectric layer, such as the interface layer 2208, is exposed. The drain feature 1702B is also exposed, as is a side wall of the source feature 1702A. The removal of the silicon material can be a selective etching process, such as selective wet etching or dry etching, targeting the composition of the fin 212, for example, silicon, while the source / drain features and dielectric compositions (for example, the interface layer 2208, the gate dielectric 2204, the insulating region 402, the first inner spacer 1402, and the second inner spacer 1502) remain essentially unetched. Fig. Figure 26B shows a detailed cross-sectional view of part of the device 200 along the Y-axis.

[0054] Method 100 then proceeds to block 128, in which the inner spacer, or a portion thereof, is removed to form an air gap. In one embodiment, the inner spacer, or a portion thereof, is removed by a wet or dry etching process. The removal of the inner spacer can be accomplished by a selective etching process. In some embodiments, the etchant contains H3PO4, NaOH, combinations thereof, or other suitable etchants. For example, in some methods where the first inner spacer 1402 is a nitride, an etchant consisting of at least one of H3PO4 or NaOH can be used to selectively etch the nitride with respect to the surrounding layers. It should be noted that the inner spacer, or a portion thereof, is removed from the rear of the device (for example, from the side opposite the gate structure). In other words, the etchant enters the device from the rear.Referring to the example of . Fig. 27A and Fig. In 27B, the first inner spacer 1402 has been selectively removed to form the openings or air gaps 2702. In some embodiments, the first inner spacer 1402 is completely removed. In another embodiment, the second inner spacer 1502 is retained on the device 200. The etchant can be selective for the material of the inner spacer 1402 and substantially not etch the second inner spacer 1502, the interface layer 2208 (if present), the gate dielectric 2204, the channel layers 208, the dielectric fin 904, and / or the insulating feature 402, which may also be exposed during the etching process. The first inner spacer 1402 is removed from between each channel region 208 and also from the space between the channel region 208 and the dielectric fin 904.In some embodiments, the etching process continues until the etchant removes the first inner spacer 1402 adjacent to the gate spacer 1202 and the uppermost channel layer 208 - i.e., the channel layer 208 closest to the front of the device (for example, the bottom layer in the Fig. (orientation shown in 27A). In some other implementations, parts of the first inner spacer 1402 remain on the device 200. For example, the etching process can be stopped before the gate spacer 1202 is exposed, leaving a remnant of the inner spacer next to the gate spacer 1202 and the top channel layer 208. Fig. Figures 32A-32C are examples of such an embodiment. In some embodiments, the second inner spacer 1502 is also removed from the device 200 in the same or a subsequent etching process (see Figure 32A-32C). Fig. 31A-31C). Similarly, in another embodiment of a process that etches both the first and second inner spacers, a residue of the second inner spacer 1502 and / or the first inner spacer 1402 may remain on the device 200. For example, the etching process may be stopped before the gate spacer 1202 is exposed, leaving a residue of the first inner spacer 1402 and the second inner spacer 1502 next to the gate spacer 1202 and the top channel layer 208.

[0055] Method 100 then proceeds to block 130, in which an insulating material is deposited. The insulating material can provide a seal for at least one air gap formed by removing the inner spacer(s) or part thereof, as described above with reference to block 128. With reference to the example of Fig. 28A and Fig. In 28B, an insulating material layer 2802 is formed on the device 200. In some embodiments, the insulating material forming the insulating material layer 2802 can comprise SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable, conventionally known materials. In one embodiment, the insulating material layer 2802 contains a composition also provided in the insulating structure 402. In one embodiment, the insulating material layer 2802 is a multilayer feature. In various examples, the dielectric material can be deposited by a CVD process, a subatmospheric CVD process (SACVD), a flowable CVD process, an ALD process, a PVD process, or another suitable process.Following the deposition process, a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed on the materials, reducing their thickness. This planarization creates a surface as shown in [reference to relevant image]. Fig. 28A shown. The insulating material layer 2802, as shown in the detailed cross-sectional view of Fig. Figure 28B provides a cover or seal for the air gap 2702. Depending on the width of the air gap 2702, the insulating material layer 2802 may extend slightly into the air gap 2702. For example, the greater the width of the air gap 2702, the more material from the insulating material layer 2802 may be present in the upper part of the air gap 2702.

[0056] Procedure 100 then proceeds to block 132, in which the backside interconnect features are formed. In some implementations, block 132 involves etching the backside of the device by back-etching a terminal, for example, the source side, of a GAA transistor of the device. Referring to the example of Fig. In 29, the source side is recessed to provide an opening 2902. In one embodiment, the opening 2902 is provided by a selective etching process that targets the semiconductor material of the source feature 1702A, while the surrounding insulating layers, such as the insulating feature 402 and the insulating material layer 2802, are only minimally etched. The insulating material layer 2802 and the insulating structure 402 provide protection for the device, for example, the channel area. Thus, a self-aligned via for contacting the source feature 1702A is enabled due to the selectivity of the source feature 1702A compared to the surrounding dielectric.

[0057] After etching the back side of the device 200 to form the opening, conductive material can be deposited into the opening 2902 to establish contact with the associated source feature. Referring to the example in Fig. On the rear side of device 200, a contact via 3002 is formed, which contacts the source feature 1702A. The contact via 3002 can establish an electrical connection to the source feature 1702A. It should be noted that in some embodiments a conductive via is formed from the front side to the source feature 1702A, but this conductive via may not be connected to any other conductor, so that no electrical connection from the front side to the source feature 1702A is provided.

[0058] An additional backside metallization can be formed adjacent to the contact via 3002, providing an electrical connection to the source feature 2702B. In one embodiment, a busbar metallization line 3004 is formed over the contact via 3002. It should be noted that, due to the topography of the backside of the device 200, which includes the insulating layer 2802 and the insulating structure 402, the busbar metallization line 3004 may be wider than the metallization features formed on the frontside of the device 200. In some implementations, the busbar metallization line 3004 contains Cu, Al, Co, W, Ti, Ta, Ru, and / or combinations thereof.During operation, the metallization line 3004 and the contact via 3002, in conjunction with the other elements of the MLI 3006 described below, provide the routing of current (Vdd) or ground (Vss).

[0059] The contact via 3002 and / or the metallization line 3004 can have a multilayer structure, such as a barrier layer, an adhesive layer, a volume layer, and / or other suitable layers. The contact via 3002 and / or the metallization line 3004 can be components of the MLI 3006 formed on the back side of the device. In some embodiments, additional metallization lines, vias, and corresponding dielectric layers can be formed above the busbar metallization line 3004 to provide parts of the back-side MLI structure 3006.In the MLI 3006, various dielectric layers are located between the vertical interconnect features, such as the contact via 3002, and the metallization layers, such as the metallization conductor 3004, whereby the various dielectric layers may have ILD layers.

[0060] Thus, with reference to Fig. 30A, Fig. 30B and Fig. Figure 30C shows an embodiment of the device 200, which is manufactured according to one or more steps of the method 100 as explained above. The device 200 of Fig. 30A, Fig. 30B, Fig. 30C comprises an air gap 2702 formed by removing the first inner spacer 1402, in some embodiments entirely. The air gap 2702 extends from the second inner spacer 1502 to an edge of the gate structure 2202, and in particular the high-k gate dielectric 2204 and / or the interface layer 2008, in the y-direction. The air gap 2702 has a width w2 in the y-direction, where w2 can be approximately 1 nm to 10 nm. The air gap 2702 has a height h2 between the channel layers 208, where h2 is approximately 5 nm to 15 nm.

[0061] The air gap 2702 is also arranged between the dielectric fin 904 and the ends of the channel layers 208. The air gap extends in the x-direction from the end of the channel layers 208 to the first dielectric layer 702 of the dielectric fin 904. The air gap 2702 has a width w3 of approximately 5 nm to 20 nm in this x-direction. The air gap 2702 has a height h3 in the z-direction adjacent to the ends of the channel layers 208. The height h3 depends on the number of channel layers 208 of the GAA device. It should be noted that the cross-section of Fig. 30C is recorded through the air gap, so that the adjacent second inner spacer 1502 is not shown.

[0062] In one embodiment, the dimensions of the air gap 2702 are selected to provide the appropriate performance with respect to the device's capacity, taking into account trade-offs due to manufacturing process challenges. In one embodiment, the insulating material layer 2802 may undesirably penetrate the air gap 2702 if the air gap width (w2) is too large. If the insulating material layer 2802 penetrates the air gap 2702, the resistance may increase compared to air due to the properties of the insulating material (e.g., dielectric constant). In another embodiment, if the air gap width (w2) is too small, insufficient air volume is provided, and the device's capacity may be greater than desired. In yet another embodiment, the device's capacity can be increased if the air gap height (h2) is too large.In one embodiment, if the air gap height (h2) is too small, processing, such as performing the replacement gate process, can be made more difficult. Similarly, in one embodiment, the capacity of the device can be increased if the air gap width (w3) to the dielectric fin 904 is too large. If, in another embodiment, the air gap width (w3) to the dielectric fin 904 is too small, processing, such as performing the replacement gate process, can be made more difficult.

[0063] The second inner spacer 1502 may have a height essentially equal to h2 as described above. The second inner spacer 1502 may have a width (t2, see above) of approximately 1 to 5 nm. In some embodiments, if the width of the second inner spacer 1502 is too large, the capacity of the device may increase. In some embodiments, if the width of the second inner spacer 1502 is too narrow, it may be insufficient to protect the source / drain feature 1702 during the removal of the first inner spacer 1402 to form the air gap 2702.

[0064] In another embodiment of method 100, a device 200' is provided as shown in Fig. 31A, Fig. 31B and Fig. Figure 31C illustrates the device 200'. The device 200' is essentially similar to the device 200, except that in forming the air gap as described above with reference to block 128, both the first inner spacer 1402 and the second inner spacer 1502 are removed to form an air gap 2702'. The air gap 2702' extends from the source / drain feature 1702 to the gate structure 2202. In one embodiment, the air gap 2702' has a width w4 of about 2 nm to 15 nm. The air gap 2702' also extends from the ends of the channel layers 208 of the dielectric fin 904 substantially by the width w3 as explained above.The device 200' with the air gap 2702' can enable a further reduction in capacity, thereby improving the performance of the device 200', but can also cause the side walls of the source / drain features 1702 to be exposed during the removal process, which may pose an additional risk of damage.

[0065] In some embodiments, one or more etching processes can be carried out to form the device 200' at block 128 of method 100 in order to selectively remove the first spacer element 1402 and the second spacer element 1502 simultaneously or sequentially. In some embodiments, the first inner spacer 1402 and the second inner spacer 1502 are completely removed. In other embodiments, a remnant of the first inner spacer 1402 or of the second inner spacer 1502, or both, may remain on the device, as explained below with reference to the device 200''.

[0066] In another embodiment of method 100, a device 200'' is provided, as shown in Fig. 32A, Fig. 32B and Fig. 32C. The device 200'' is essentially similar to the device 200, except that in forming the air gap, as described above with reference to Block 128 of the method 100, only a portion (for example, less than the entirety) of the first inner spacer 1402 is removed to form the air gap 2702'', while a portion of the first inner spacer, shown as a remainder 1402', remains in the device. In some embodiments, the remainder 1402' remains near the uppermost channel layer 208, i.e., the channel section closest to the front of the device 200. This is because the etching agent is introduced from the rear of the device (see opening 2602 in Fig. 26A) and the material furthest from the etchant inlet is etched last, thus forming the remainder 1402'. In one embodiment, the remainder 1402' has a thickness of height (h4) from about 0 nm to about 30 nm. The device 200' with the air gap 2702' may lead to reduced performance of the device (such as increased capacity), but it may also reduce the likelihood of damage from the etching process of block 128, shorten the processing time of block 128, and / or provide additional structural stiffness. It should be noted that in some embodiments, a surface of the topmost channel layer 208 may be completely covered, or a portion of the surface of the channel layer 208 may be exposed in the y-direction or the x-direction.

[0067] Fig.Figure 34 is an outline drawing of the multigate device 200 with multiple gate structures 2202 and source / drain features 1702, shown in layout and cross-sectional view. As shown, certain source / drain features 1702 are connected to a contact via 3002 on the back side, which is connected to a metallization 3004 that provides a bus bar in some implementations. In comparison, the metallization 3004 with a width M0 (e.g., the bottom metal conduction layer) of the front-side MLI 2310 is provided on the front side of the device. The metallization layer 3004 can be part of the rear MLI 3006 and can be connected to a MIM induction device 3302 and / or a rear I / O pad (input-output), a rear Vdd pad and / or rear ground pads (GND) 3304 formed on the rear of the device.In one embodiment, the metallization 3004 contains Cu, Al, Co, W, Ti, Ta, Ru and / or combinations thereof.

[0068] Thus, methods and devices are provided which, in some implementations, enable reduced capacitance while simultaneously providing a rear-side metallization scheme (for example, a current conductor) that experiences reduced resistance by increasing the width of the metal conductor. The methods and devices enable the creation of an air gap adjacent to the channel area, thereby reducing the dielectric constant of the insulating material to that of air. It is evident from the foregoing description that the multigate devices described herein offer advantages over conventional multigate devices. However, it is understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, nor is any particular advantage required for all embodiments.The present disclosure provides for many different embodiments.

[0069] An exemplary device described herein comprises a multigate device having: a channel layer arranged between a source feature and a drain feature, a metal gate surrounding the channel layer, and a first air gap spacer separating the metal gate and the source feature, and a second air gap spacer separating the metal gate and the drain feature. A rear contact extends to the source feature. A busbar metallization layer is connected to the rear contact.

[0070] In another embodiment, the device includes a dielectric fin between the metal gate and another metal gate. In one embodiment, the first air gap spacer extends from a dielectric gate layer of the metal gate to the dielectric fin. In another embodiment, the device further includes a low-k dielectric layer between the metal gate and the dielectric fin and adjacent to the first air gap spacer. In some embodiments, a front-side contact is formed with the drain feature. In one embodiment, the device includes a residue of dielectric material adjacent to the first air gap spacer and adjoining a second channel layer, with the metal gate surrounding the second channel layer. In another embodiment, the residue adjoins spacer elements on the side walls of the metal gate.In one embodiment, the width of the first air gap spacer between the source feature and the metal gate is approximately 1 nm to 10 nm.

[0071] In another, broader embodiment, a device is provided comprising an insulating feature arranged over a substrate. The insulating feature is located between a first fin section and a second fin section extending from the substrate. A dielectric gate insulating fin is arranged over the insulating feature, with the dielectric gate insulating fin and a first gate structure arranged around a first channel layer and a second channel layer above the first channel layer. The first channel layer and the second channel layer are arranged over the first fin section and extend between a first source feature and a first drain feature. The device includes gate spacers that abut the side walls of a section of the first gate structure. The gate spacers are arranged on the second channel layer.An air gap is located between the second channel layer and the first channel layer, and between the first gate structure and the first source feature. A residue of dielectric material lies between the first and second channel layers, adjacent to the air gap.

[0072] In another embodiment, the first gate structure of the device is formed around a third channel layer below the first channel layer, and the air gap extends from the first channel layer to the third channel layer. In one embodiment, the device includes a low-k dielectric material in addition to the rest of the dielectric material. The low-k dielectric material is located between the air gap and the first source feature. In another embodiment, the device further comprises a dielectric fin with a first surface section that abuts the first gate structure and a second surface section that abuts the air gap.In one embodiment, the device comprises a first contact element to the first source feature from a rear side of the device, a second contact element to the first drain feature from a front side of the device, and a busbar metallization line connected to the first contact element.

[0073] In another of the broader embodiments described herein, a method is provided comprising: providing a structure with a front and a back. On the front of the structure, a gate-all-around (GAA) device is formed. Forming the GAA device includes etching several alternating layers to form a fin structure; forming internal spacers containing a dielectric dummy material and a low-k dielectric material between the channel layers of the fin structures; epitaxially growing a source / drain feature adjacent to a first side of the internal spacers; releasing the channel layers in a channel region of the fin structure adjacent to a second side of the internal spacers, the second side facing the first side; and forming a metal gate structure between the channel layers.After the GAA device is formed, the structure is inverted to remove a portion of the substrate, exposing the dielectric dummy material. The dummy dielectric is removed to create an air gap. An insulating layer is deposited on the back side of the structure over the air gap.

[0074] In another embodiment, the method further comprises: removing the low-k dielectric material after forming the GAA device to form part of the air gap. In one embodiment, after removing the dielectric dummy material to form the air gap, a portion of the dielectric dummy material remains adjacent to the air gap. In some embodiments, this portion of the dielectric dummy material is adjacent to gate spacers. In one embodiment, the method comprises: forming a contact to the source / drain feature from the rear side of the device after forming the air gap. The method may include forming the contact, creating a via adjacent to a metallization layer formed on the rear side of the structure, and connecting the metallization layer to a power source.In some embodiments, forming the metal gate structure includes forming a high-k dielectric adjacent to the dummy dielectric.

Claims

[1] comprising a device: having a multi-gate device (200, 200', 200"): a first channel layer (208) and a second channel layer (208) arranged between a source feature (1702A) and a drain feature (1702B), wherein the second channel layer (208) is the channel layer of the multigate device (200, 200', 200") that is closest to a front face of the multigate device (200, 200', 200"); a metal gate (2202-2208) surrounding the first channel layer (208) and the second channel layer (208), a first air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the source feature (1702A), and a second air gap spacer (2702, 2702', 2702") located between the metal gate (2202-2208) and the drain feature (1702B); a rear contact (3002) extending to the source feature (1702A); a current-conducting metallization layer (3004) connected to the rear contact (3002); and a residue (1402') of dielectric material next to the first air gap spacer (2702") and adjacent to the second channel layer (208), wherein the first air gap spacer (2702") exposes the first channel layer (208). [2] Device according to claim 1, further comprising: a dielectric fin (904) between the metal gate (2202-2208) and another metal gate. [3] Device according to claim 2, wherein the first air gap spacer (2702, 2702', 2702") extends from a gate dielectric layer (2204) of the metal gate (2202-2208) to the dielectric fin (904). [4] Device according to claim 2 or 3, further comprising: a low-k dielectric layer (1502) between the metal gate (2202-2208) and the dielectric fin (904) next to the first air gap spacer (2702, 2702', 2702"). [5] Device according to one of the preceding claims, further comprising: a front contact (2306) to the drain feature (1702B). [6] Device according to any one of claims 1 to 5, wherein the remainder (1402') of dielectric material adjoins spacer elements on side walls of the metal gate (2202-2208). [7] Device according to one of the preceding claims, wherein the width of the first air gap spacer (2702, 2702', 2702") between the source feature (1702A) and the metal gate (2202-2208) is about 1 nm to 10 nm. [8] Device (200") comprising: an insulation feature (402) arranged over a substrate (202), wherein the insulation feature (402) is arranged between a first fin section (202A) and a second fin section (202A) extending from the substrate (202); a dielectric gate insulation fin (904) arranged above the insulation feature (402); a first gate structure (2202-2208) around a first channel layer (208) and a second channel layer (208) above the first channel layer (208), wherein the first channel layer (208) and the second channel layer (208) are arranged above the first fin section (202A) and extend between a first source feature (1702A) and a first drain feature (1702B); Gate spacers (1202) adjoining side walls of part of the first gate structure (2202-2208), wherein the gate spacers (1202) are arranged on the second channel layer (208); an air gap (2702") between the second channel layer (208) and the first channel layer (208) and between the first gate structure (2202-2208) and the first source feature (1702A); and a dielectric material residue (1402') between the first channel layer (208) and the second channel layer (208) next to the air gap (2702"), wherein the air gap (2702") exposes the first channel layer (208) and the dielectric material residue (1402') covers a surface of the second channel layer (208). [9] Device (200") according to claim 8, wherein the first gate structure (2202-2208) is formed around a third channel layer (208) below the first channel layer (208) and the air gap (2702") extends from the first channel layer (208) to the third channel layer (208). [10] Device (200'') according to claim 8 or 9, further comprising: a low-k dielectric material (1502) next to the dielectric material residue (1402'), wherein the low-k dielectric material (1502) is located between the air gap (2702'') and the first source feature (1702A). [11] Device (200'') according to one of claims 8 to 10, wherein the dielectric gate insulation fin (904) has a first section of a surface adjacent to the first gate structure (2202-2208) and a second section of the surface adjacent to the air gap (2702''). [12] Device (200'') according to any one of claims 8 to 11, further comprising: a first contact element (3002) from a rear side of the device (200'') to the first source feature (1702A); a second contact element (2306) from a front side of the device (200'') to the first drain feature (1702B); a busbar metallization conductor (3004) adjacent to the first contact element (3002). [13] Procedure (100) comprising: Providing a structure (200) having a front and a back; Forming a GAA device on the front of the structure, wherein forming the GAA device includes: - Etching of several alternating layers (206, 208) to form a fin structure (212); - Forming internal spacers (1402, 1502) containing a dielectric dummy material (1402) and a low-k dielectric material (1502) between the channel layers (208) of the fin structures (212); - epitaxial growth of a source / drain feature (1702, 1702A) next to a first side of the inner spacers (1402, 1502); - Releasing the channel layers (208) in a channel area of ​​the fin structure (212) adjacent to a second side of the inner spacers (1402, 1502), the second side being opposite the first side; and - Forming a metal gate structure (2202-2208) between the channel layers (208); and After forming the GAA device, the structure is inverted to remove part of the substrate (202), thereby exposing the dummy dielectric material (1402); Removing the dummy dielectric material (1402) to form an air gap (2702, 2702', 2702"); and Deposition of an insulating layer (2802) on the back side of the structure over the air gap (2702, 2702', 2702"). [14] Method (100) according to claim 13, further comprising: Removing the low-k dielectric material (1502) after forming the GAA device to form part of the air gap (2702, 2702', 2702"). [15] Method (100) according to claim 13 or 14, wherein after removing the dummy dielectric material (1402) to form the air gap (2702"), a part of the dummy dielectric material (1402') remains next to the air gap (2702"). [16] Method (100) according to claim 15, wherein the part of the dummy dielectric material (1402) contacts the gate spacer (1202). [17] Method (100) according to any one of claims 13 to 16, further comprising: Forming a contact (3002) from a rear side of the device (200, 200', 200") to the source / drain feature (1702, 1702A) after forming the air gap (2702, 2702', 2702"). [18] Method (100) according to claim 17, wherein forming the contact comprises: Forming a through-hole (3002) to adjoin a metallization layer (3004) formed on the back side of the structure; and Connecting the metallization layer (3004) to a power source. [19] Method (100) according to any one of claims 13 to 18, comprising forming the metal gate structure (2202-2208): Forming a high-k dielectric (2204) adjacent to the dummy dielectric material (1402).

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