MANUFACTURING METHOD OF AN UNDOTATED AREA UNDER A SOURCE / DRAIN AREA

Abstract

Procedure with the following steps: Forming (206) a semiconductor fin (36) that protrudes higher than an upper surface (24TS) of an insulation region (24), wherein the semiconductor fin (36) overlaps a semiconductor strip (26) and the semiconductor strip (26) contacts the insulation region (24); Forming (208) a gate stack (38) on a side wall and an upper surface of a first part of the semiconductor fin (36); Etching (210) of the semiconductor fin (36) and the semiconductor strip (26) to form a trench (50), wherein the trench (50) has an upper part in the semiconductor fin (36) and a lower part in the semiconductor strip (26); Growing (212) a semiconductor region (56) in the lower part of the trench (50), wherein the semiconductor region (56) is grown to have a concave top surface, wherein process gases used for growing the semiconductor region (56) are free of n-doped and p-doped gases; and Growth (214) of a source / drain region (60) in the upper part of the trench (50) on the semiconductor region (56), wherein the source / drain region (60) contains a p-doped or an n-doped wherein the top of the semiconductor area (56) is lower than a lower surface (24TS) of the semiconductor fin (36).

Description

BACKGROUND

[0001] In the manufacturing of integrated circuits, deep source / drain regions are created for transistors to reduce channel resistance. This can improve the performance of the corresponding transistors. However, creating these deep source / drain regions can lead to an increase in leakage currents.

[0002] A method for manufacturing a FETS is known from US 2016 / 0056290 A1. Further manufacturing methods are known from US 2015 / 0303118 A1 and US 2020 / 0006548 A1, and a semiconductor structure from US 2015 / 0295089 A1. Another method is known from US 2020 / 0303521 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1 to 4, 5A, 5B, 6A, 6B, 6C, 7A, 7B, 8A, 8B, 9A, 9B, 10, 11A, 11B, 12, 13A and 13B show sectional views of intermediate stages in the manufacture of fin field-effect transistors (FinFETs) according to some embodiments. Fig. Figure 14 shows a process flow for manufacturing a FinFET according to some embodiments. DETAILED DESCRIPTION

[0004] The following description provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] A fin field-effect transistor (FinFET) and a method for its fabrication are provided. According to some embodiments of the present disclosure, a semiconductor fin on which a gate stack is fabricated is etched to create a trench. The trench extends deep into a semiconductor strip beneath the semiconductor fin, such that an upper portion of the trench in the semiconductor fin has a more vertically oriented sidewall and is closer to a channel region of the FinFET. On a bottom side of the trench, a semiconductor region is epitaxially grown, which is undoped or unintentionally doped. The semiconductor region may have a top surface that is (within process variations) level with or slightly lower than the bottom surface of the semiconductor fin. Then, a doped source / drain region is epitaxially grown on the semiconductor region.By creating a semiconductor region with no or only a low doping concentration, the leakage current between adjacent source / drain regions is reduced. The embodiments discussed herein are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure. In all illustrations and explanatory embodiments, similar reference numerals are used to designate similar components. While some method embodiments may be discussed as being carried out in a particular sequence, other method embodiments may be carried out in any logical order.

[0007] The Fig. Figures 1 to 4, 5A, 5B, 6A, 6B, 6C, 7A, 7B, 8A, 8B, 9A, 9B, 10, 11A, 11B, 12, 13A and 13B show sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments of the present disclosure. The corresponding steps are also schematically indicated in the process flow 200, which is presented in Fig. 14 is shown.

[0008] In Fig. 1. A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The semiconductor substrate 20 can be part of a wafer 10, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise: silicon; germanium; a compound semiconductor, such as carbon-doped silicon, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. According to some embodiments, the substrate 20 is doped with a p- or an n-doped compound. The concentration of the p-doped compound (or n-doped compound), which may be intentionally or unintentionally doped, may be approximately 1 × 10⁻¹⁷ / cm³. 3 up to about 1E18 / cm 3 According to some embodiments, a top surface of the semiconductor substrate 20 is located on a (100) surface plane of this crystalline substrate.

[0009] Let's stay with Fig. 1. A trough area 22 is created in the substrate 20. The corresponding step is specified as step 202 in the process flow 200, which is in Fig. Figure 14 shows that in some embodiments of the present disclosure, the trough region 22 is a p-trough region produced by implanting a p-doping agent, such as boron, indium, or the like, into the substrate 20. In other embodiments of the present disclosure, the trough region 22 is an n-trough region produced by implanting an n-doping agent, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. The resulting trough region 22 may extend to the top surface of the substrate 20. The n- or p-doping concentration in the trough region 22 may be equal to or less than 1 × 10⁻⁸ / cm². 3 be, e.g., about 1E18 / cm² 3 up to about 1E19 / cm 3 be.

[0010] In Fig. 2 Insulation zones 24 are created such that they extend from the top of the substrate 20 into the substrate 20. The insulation zones 24 are subsequently referred to alternatively as STI zones (STI: shallow trench insulation). The corresponding step is specified as step 204 in the process flow 200, which is described in Fig. Figure 14 shows that portions of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To fabricate the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are produced on the semiconductor substrate 20 and subsequently patterned. The pad oxide layer 28 can be a thin layer made of silicon oxide. In some embodiments of the present disclosure, the pad oxide layer 28 is produced in a thermal oxidation process in which a surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesive layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also act as an etch stop layer for etching the hard mask layer 30.In some embodiments of the present disclosure, the silicon nitride hard mask layer 30 is produced, for example, by atomic layer deposition (ALD), low-pressure gravure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. A photoresist (not shown) is produced on the hard mask layer 30 and subsequently patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to produce hard masks 30, as shown in [reference]. Fig. 2 is shown.

[0011] The structured hard mask layer 30 is then used as an etching mask for etching the pad oxide layer 28 and the substrate 20. Subsequently, the resulting trenches in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as a CMP process (CMP: chemical-mechanical polishing) or a mechanical grinding process, is then performed to remove excess dielectric materials. The remaining dielectric materials are the STI regions 24. The STI regions 24 may have a dielectric coating (not shown), which may be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20.The dielectric coating can also be a deposited silicon oxide layer, silicon nitride layer, or the like, produced, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or chemical vapor deposition (CVD). The STI areas 24 can also have a dielectric material over the oxide coating, wherein the dielectric material can be deposited by flowable chemical vapor deposition (FCVD), spin coating, or the like. In some embodiments, the dielectric material over the dielectric coating can be silicon oxide.

[0012] Semiconductor strips 26 are located between adjacent STI regions 24. In some embodiments of the present disclosure, the semiconductor strips 26 are parts of the original substrate 20 and the trough region 22, and therefore the material of the semiconductor strips 26 is the same as that of the substrate 20. In alternative embodiments of the present disclosure, the semiconductor strips 26 are substitute strips produced by etching the portions of the substrate 20 between the STI regions 24 to create recesses and performing an epitaxial growth process to grow further semiconductor material in the recesses. Accordingly, the semiconductor strips 26 are produced from a semiconductor material different from that of the substrate 20. In some embodiments, the semiconductor strips 26 are produced from silicon germanium, silicon-carbon, or a III-V compound semiconductor material.

[0013] In Fig. 3. The STI areas 24 are left out so that upper parts of the semiconductor strips 26 protrude over top surfaces 24TS of the remaining parts of the STI areas 24, forming protruding fins 36. The corresponding step is specified as step 206 in the process sequence 200, which is described in Fig. Figure 14 shows that the etching can be carried out using a dry etching process, in which, for example, HF and NF3 are used as etching gases. A plasma can be generated during the etching process. Argon can also be used. In alternative embodiments of the present disclosure, the masking of the STI areas 24 can be carried out using a wet etching process. For example, diluted HF can be used as the etching chemical.

[0014] In the embodiments described above, the fins can be structured using any suitable method. For example, the fins can be structured using one or more photolithography processes, such as dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers, or thorns, can then be used to structure the fins.

[0015] In Fig. 4. Dummy gate stacks 38 are manufactured such that they extend onto the surfaces and sidewalls of the (protruding) fins 36. The corresponding step is specified as step 208 in the process flow 200, which is described in Fig. 14 is shown. The dummy gate stacks 38 can be dummy gate dielectrics 40 ( Fig. 7A) and dummy gate electrodes 42 over the dummy gate dielectrics 40. The dummy gate electrodes 42 can be made, for example, using polysilicon, but other materials, such as amorphous silicon or amorphous carbon, can also be used. The dummy gate stacks 38 can each comprise one or more hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 can be made of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stacks 38 can extend over one or more of the projecting fins 36 and / or the STI regions 24. The dummy gate stacks 38 also have longitudinal directions that are perpendicular to the longitudinal directions of the projecting fins 36.

[0016] Then, gate spacers 46 are manufactured on the side walls of the dummy gate stacks 38. The corresponding step is also specified as step 208 in process flow 200, which is described in Fig. Figure 14 shows that in some embodiments of the present disclosure, the gate spacers 46 are made of one or more dielectric materials, such as silicon nitride, silicon carbonitride, silicon oxide carbonitride, or the like, and they can have a single-layer structure or a multi-layer structure with a plurality of dielectric layers. Simultaneously with the gate spacers 46, fin spacers (not shown) can also be manufactured on the side walls of the projecting fins 36.

[0017] In some embodiments, an implantation process is used to create source / drain expansion areas 51 (see Fig. 5B). The implantation process may include oblique implantation steps such that the source / drain expansion regions 51 extend into areas directly beneath the gate spacers 46 and are created on opposite sides of channel regions 53 of the resulting FinFET. The source / drain expansion regions 51 have the same conductivity type (p or n) as subsequently fabricated source / drain regions 60 and a lower doping concentration than these. In some embodiments, the source / drain expansion regions 51 have a p or n doping concentration lower than approximately 1 × 10⁹ / cm². 3 is, for example, about 5E17 / cm² 3 up to about 1E19 / cm 3 In alternative embodiments, the source / drain extension areas 51 can be generated in a later process, for example after epitaxy processes to generate the epitaxy areas 60.

[0018] Then an etching process is carried out to etch the parts of the protruding fins 36 that are not covered by the dummy gate stacks 38 and the gate spacers 46, so that the in the Fig. 5A and Fig. The structure shown in 5B is created. The corresponding step is indicated as step 210 in process flow 200, which is in Fig. Figure 14 shows planes of top surfaces 24TS and bottom surfaces 24BS. The recess can be anisotropic, and therefore the portions of the fins 36 directly beneath the dummy gate stacks 38 and the gate spacers 46 are protected and are not etched. In some embodiments, the top surfaces of the recessed semiconductor strips 26 can be lower than the top surfaces 24TS of the STI areas 24 and can be higher than the bottom surfaces 24BS of the STI areas 24. This creates trenches 50. The trenches 50 comprise parts located on opposite sides of the dummy gate stacks 38 and parts between remaining portions of the projecting fins 36. The etching can be carried out using a dry etching process, which can be performed using process gases such as C2F6, CF4, SO2, a mixture of HF and ozone, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CF2, etc., or the like. The etching can be anisotropic.

[0019] In Fig. 5B, which has a reference cross-section 5B - 5B of Fig. As shown in Figure 5A, the trenches 50 are deep trenches with bottom surfaces 50BOT that are lower than the top surfaces 24TS of the STI areas 24. Since the top surfaces 24TS of the STI areas 24 are on the same plane as the bottom surfaces of the projecting fins 36, the trenches 50 also extend to a plane that is lower than that of the bottom surfaces of the projecting fins 36. In some embodiments, a depth D1, measured from the bottom surface of the projecting fins 36 to the bottom surface of the trenches 50, can be greater than about 2 nm and can range from about 2 nm to about 4 nm. In some embodiments, the side walls 50SW of the trenches 50 have straight and vertical upper portions. Close to the bottom of the trenches 50, the lower parts of the side walls 50SW begin to become conical and curved, thus forming a U-shaped or V-shaped bottom (with curved side walls and bottoms).

[0020] In some embodiments, the vertical and straight upper parts of the side walls 50SW extend to the lower plane of the projecting fins 36, wherein the vertical and straight side wall in Fig. 5B is shown by dashed lines 50SW'. In some embodiments, the connection points between the upper parts of the vertical and straight side wall and the curved lower parts are located on a top surface 24TS, which is also the bottom surface of the projecting fins 36. In alternative embodiments, the curved side wall parts start on a plane that is higher than the top surface 24TS, as shown in Fig. Figure 5B shows that by creating deep trenches 50, it can be ensured that important parts of the sidewalls 50SW, or the entire sidewalls 50SW, are vertical and straight in the projecting fins 36. A bottom-side clearance S1, which is a lateral distance from the channel regions 53 (of the resulting FinFET) to the nearest source / drain regions 60, is small. However, if the trenches 50 are created as shallow trenches, where, for example, the bottom side is on the same plane as the bottom surface of the projecting fins 36, the bottom-side clearance increases to a value S2 that is greater than S1. Since the clearance S1 or S2 is located in regions (source / drain extension regions 51) with a low doping concentration, the resistance of these regions is high.Accordingly, by creating deep trenches, the channel resistance and the resistance between source and drain regions can be reduced, thus improving the performance of the resulting FinFET.

[0021] However, widening the trenches 50 deep into the semiconductor strips 26 can lead to the leakage current between adjacent source / drain regions 60 ( Fig. 13A) adversely increases. In some embodiments, semiconductor regions 56 that are undoped, unintentionally doped, or intentionally doped with n- or p-dopeds are generated, as in the Fig. 6A, Fig. 6B and Fig. 6C is shown.

[0022] In some embodiments, the semiconductor regions 56 are produced by a selective epitaxy process. The selective epitaxy process is also a bottom-up deposition process. The corresponding step is specified as step 212 in the process sequence 200, which is described in Fig. Figure 14 shows that the semiconductor regions 56 can be silicon (without Ge, C, or the like), SiGe, carbon-doped silicon (SiC), or the like. For example, if the resulting FinFET is an n-FinFET, the semiconductor regions 56 can be silicon or carbon-doped silicon. If the resulting FinFET is a p-FinFET, the semiconductor regions 56 can be silicon, SiGe, or germanium.

[0023] Deposition can be achieved by reduced-pressure chemical vapor deposition (RPCVD), PECVD, or similar processes. A silicon-containing gas such as silane, disilane (Si₂H₆), dichlorosilane (DCS), or similar can be used as the process gas for depositing the semiconductor regions 56. If the resulting semiconductor regions 56 are to contain germanium, the silicon-containing gas can be mixed with a germanium-containing gas such as monogerman (GeH₄), digerman (Ge₂H₆), or similar. The process gases are mixed with an etching gas such as HCl to achieve selective deposition on the semiconductor but not on the dielectric. The process gas can also contain one or more carrier gases such as H₂ and / or N₂. Bottom-up deposition can be achieved by adjusting process conditions, such as the process gas flow rate ratio.For example, the ratio of the flow rates of one or more Si / Ge-containing gases to the flow rate of the etching gas can be adjusted. The growth rates for semiconductor regions 56 on different surface levels are different. For example, growth on the (100) surface (which is the area of ​​the semiconductor strips 26 on the bottom surfaces of the trenches 50) is faster than on the (110) surface (the sidewall surfaces of the substrate 20 and the projecting fins 36). With the correct flow rate, it can be ensured that the semiconductor grown on the (110) surface is etched and completely removed, while the semiconductor grown on the (100) surface is only partially etched. Therefore, the semiconductor region grows on the (100) surfaces (the top surfaces of the semiconductor on the bottom surfaces of the trenches) but not on the (110) surfaces (the sidewall surfaces in the trenches 50).Accordingly, growth occurs from the bottom up.

[0024] In some embodiments, the process gases used to generate the semiconductor regions 56 contain neither gas with an n-doped element nor gas with a p-doped element. Accordingly, the semiconductor regions 56 can be intrinsic. The process chamber used to grow the semiconductor regions 56 may or may not contain residues. Depending on what was previously grown in the process chamber and whether / how the process chamber was cleaned, the residues may contain p-doped elements, such as boron and / or indium, and / or n-doped elements, such as phosphorus, arsenic, antimony, and / or the like. Other dopants, such as oxygen (O), may also remain in the process chamber. These residues are doped into the semiconductor regions 56. Since, in these embodiments, these dopants are not intended to be doped into the semiconductor regions 56, they are referred to as unintentionally doped dopants.The unintentionally doped dotandes can be n- or p-dotandes, regardless of whether the later grown source / drain areas are 60 (. Fig. 7A) are p- or n-type. In some embodiments, the unintentionally doped dopants have concentrations that may be less than about 1 × 10¹⁸ / cm³. 3 , smaller than approximately 1E17 / cm 3 , smaller than approximately 1E16 / cm 3 or smaller than approximately 1 x 15 cm² 3 is or approximately 1E17 / cm 3 up to about 1E18 / cm 3 The amount is [value missing]. After deposition, the semiconductor regions 56 cannot contain any unintentionally doped dopants, and are therefore intrinsic.

[0025] In some embodiments, the semiconductor regions 56 are intentionally doped in situ during epitaxy with the same conductivity type as the underlying source / drain regions 60. The in-situ doping is performed by introducing a dopant-containing gas into the process chamber. For example, if the source / drain regions 60 are p-type, boron and / or indium can be doped into the semiconductor regions 56. If the source / drain regions 60 are n-type, phosphorus, arsenic, and / or antimony can be doped into the semiconductor regions 56. For example, the semiconductor regions 56 can be intentionally doped to a concentration of less than approximately 1 × 10⁻⁷ / cm³. 3 can be doped, with the doping concentration also being lower than approximately 1E16 / cm². 3 , approximately 1E15 / cm 3 or approximately 1E14 / cm 3 may be.

[0026] In alternative embodiments, the semiconductor regions 56 are intentionally counter-doped in situ during epitaxy so that they have a conductivity type opposite to that of the source / drain regions 60 located above them. Accordingly, the dopant has the same conductivity type as the well region 22. The in-situ doping is carried out by introducing a dopant-containing process gas. For example, if the source / drain regions 60 are n-type, boron and / or indium can be doped into the semiconductor regions 56. If the source / drain regions 60 are p-type, phosphorus, arsenic, and / or antimony can be counter-doped into the semiconductor regions 56. For example, the semiconductor regions 56 can be intentionally doped to a concentration of less than approximately 1 × 10⁻⁷ / cm³. 3 can be doped, with the doping concentration also being lower than approximately 1E16 / cm². 3 , approximately 1E15 / cm 3 or approximately 1E14 / cm 3may be.

[0027] If the semiconductor areas 56 are intentionally doped, the doping concentration can be controlled (by reducing the throughput of the dopant-containing process gas) so that it is lower than the doping concentrations in the well area 22 (and thus the channel areas 53), the source / drain extension areas 51 and the source / drain areas 60 ( Fig. 7A) in total. For example, the semiconductor regions 56 (after deposition) can be doped in situ such that their doping concentration is at least one or two orders of magnitude lower than the doping concentrations in the well region 22, the source / drain extension regions 51, and the source / drain regions 60. The intentionally doped dopant can have a concentration of the same order of magnitude as the original semiconductor substrate 20 (before doping the well region 22).

[0028] Fig. Figure 6A shows a profile of semiconductor regions 56 according to some embodiments, in which the top surfaces of the semiconductor regions 56 are planar or substantially planar, for example with a height variation of less than about 1 nm or less than about 0.5 nm (5 Å). Within process variations, the top surfaces of the semiconductor regions 56 may also be on the same plane as the bottom surfaces of the projecting fins 36, for example with a height difference of less than 1 nm or less than about 0.5 nm (5 Å). The top surfaces of the semiconductor regions 56 may also be slightly lower than the bottom surfaces of the projecting fins 36, for example with a height difference (within process variations) of about 1 nm to about 2 nm. Fig. Figure 6B shows a profile of semiconductor areas 56 according to alternative embodiments, in which the upper surfaces of the semiconductor areas 56 are concave. The upper corners of the semiconductor areas 56 can be located on the same plane as the lower surfaces of the projecting fins 36. Fig. Figure 6C shows a profile of semiconductor regions 56 according to further alternative embodiments, in which thin layers of the semiconductor regions 56 are formed on the sidewalls of the projecting fins 36, for example by incomplete etching of the semiconductor regions 56 from the sidewalls of the projecting fins 36. The thickness of the sidewall parts can be less than about 1 nm.

[0029] The top surfaces of the semiconductor regions 56 can be at the same level as the bottom surfaces of the projecting fins 36 to achieve a higher current and reduced leakage loss. If the top surfaces of the semiconductor regions 56 are higher than the bottom surfaces of the projecting fins 36, the bottom surfaces of the subsequently fabricated source / drain regions 60 ( Fig. 7A) does not extend to the underside of the protruding fins, and therefore the lower parts of the channel regions are not effectively utilized, resulting in a reduction of the FinFET's saturation current. If the tops of the semiconductor regions 56 are lower than the undersides of the protruding fins 36, the leakage current increases.

[0030] In the Fig. 7A and Fig. 7B Epitaxial regions (source / drain regions) 60 are generated by selective growth of a semiconductor material in the trenches 50. The corresponding step is specified as step 214 in the process flow 200, which is described in Fig. 14 is shown. Fig. Figure 7B shows a perspective view, and Fig. 7A shows a reference cross-section 7A - 7A of Fig. 7B. Depending on whether the resulting FinFET is a p- or an n-FinFET, a p- or an n-doper can be in situ doped during epitaxy. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, if the resulting FinFET is an n-FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) can be grown. In alternative embodiments of the present disclosure, the epitaxial regions comprise 60 III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the trenches 50 have been filled with the epitaxial areas 60, the further epitaxial growth of the epitaxial areas 60 causes them to expand horizontally, and bevels may form.Furthermore, as the epitaxial areas 60 continue to grow, adjacent epitaxial areas 60 can fuse together. This can result in the formation of cavities (air gaps) 61.

[0031] In some embodiments, the source / drain regions 60 have a plurality of sublayers designated 60A, 60B and 60C ( Fig. 7A). Sublayers 60A, 60B, and 60C can have different compositions. For example, the germanium or carbon (if present) in sublayers 60A, 60B, and 60C can differ. The n-type dopant (if the FinFET is an n-type FinFET) in sublayers 60A, 60B, and 60C can have different concentrations. The p-type dopant (if the FinFET is a p-type FinFET) in sublayers 60A, 60B, and 60C can also have different concentrations. For example, if the source / drain regions are 60n regions, sublayer 60A can contain SiAs, while sublayers 60B and 60C can contain SiP. Sublayer 60B can also have an n-doping concentration that is higher than the n-doping concentration in sublayers 60A and 60C if the source / drain regions are 60 n regions.Conversely, sublayer 60B can also have a p-doping concentration higher than the p-doping concentration in sublayers 60A and 60C if the source / drain regions 60 are p-regions. In some embodiments, the source / drain regions 60 have an n- or p-doping concentration of approximately 5 × 10²⁰ / cm². 3 up to about 5E21 / cm 3 In some embodiments, after epitaxy of the source / drain regions 60, no implantation process is carried out to implant an n or p dopant, so that the doping concentration in the semiconductor regions 56 remains low.

[0032] The Fig. 8A and Fig. Figure 8B shows a perspective view of the structure after the fabrication of a contact etch stop layer (CESL) 62 and an interlayer dielectric (ILD) 64. The corresponding step is indicated as step 216 in the process flow 200, which is described in Fig. 14 is shown. Fig. Figure 8B shows a perspective view, and Fig. 8A shows a reference cross-section 8A - 8A of Fig. 8B. The CESL 62 can be fabricated from silicon oxide, silicon nitride, silicon carbon nitride, or the like by CVD, ALD, or the like. The ILD 64 can be a dielectric material deposited, for example, by FCVD, spin coating, CVD, or another deposition process. The ILD 64 can be fabricated from an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, can be performed to bring the top surfaces of the ILD 64, the dummy gate stack 38, and the gate spacer 46 to the same height.

[0033] Then the dummy gate stacks 38, comprising the hard mask layers 44, the dummy gate electrodes 42, and the dummy gate dielectrics 40, are etched so that grooves 66 are formed between the gate spacers 46, as shown in the Fig. 9A and Fig. 9B is shown. The corresponding step is indicated as step 218 in process flow 200, which is shown in Fig. Figure 14 shows that the upper surfaces and side walls of the projecting fins 36 are exposed towards the trenches 66. Fig. Figure 9B shows a perspective view, and Fig. 9A shows a reference cross-section 9A - 9A of Fig. 9B.

[0034] As in Fig. As shown in 10, replacement gate stacks 84 will then be placed in trenches 66 ( Fig. 9A and Fig. 9B). The corresponding step is specified as step 220 in process flow 200, which is in Fig. Figure 14 shows that the replacement gate stacks 84 comprise gate dielectrics 72 and corresponding gate electrodes 82. In some embodiments of the present disclosure, a gate dielectric 72 comprises an interface layer (IL) 68 as its lower part, as shown in Figure 14. Fig. Figure 9A shows that the IL 68 is produced on the exposed surfaces of the protruding fins 36. The IL 68 can be an oxide layer, such as a silicon oxide layer, produced by thermal oxidation of the protruding fins 36, a chemical oxidation process, or a deposition process. The gate dielectric 72 can have a high-k dielectric layer 70 deposited over the IL 68. The high-k dielectric layer 70 comprises a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (k-value) of the high-k dielectric material is greater than 3.9 and can be greater than approximately 7.0 or even higher. The dielectric high-k layer 70 is produced as a conformal layer and extends to the side walls of the projecting fins 36 and the top and side walls of the gate spacers 46.In some embodiments of the present disclosure, the dielectric high-k layer 70 is produced by ALD, CVD, PECVD, molecular beam deposition (MBD) or the like.

[0035] Let's stay with Fig. 10. Gate electrodes 82 are fabricated on the gate dielectrics 72. The gate electrodes 82 can have a plurality of stacked layers 74, 76, and 78, which can be fabricated as conformal layers, and filler metal regions 80 that fill the remaining trenches not yet filled by the plurality of stacked layers 74, 76, and 78. The multiple stacked layers 74, 76, and 78 can each have the shape of a basin with a bottom and sidewall portions that form a ring and are connected to the bottom. A fabrication process for the gate stacks 84 is briefly described below. It is understood that the layers mentioned are merely an example and other layer schemes can also be used.

[0036] In some embodiments, an adhesive layer 74 (which is also a diffusion barrier layer) is produced over the dielectric high-k layer 70. The adhesive layer 74 can be made of or comprise TiN or titanium silicon nitride (TiSiN). The TiN layer can be produced by ALD or CVD, and the TiSiN layer can comprise alternating deposited TiN and SiN layers, produced, for example, by ALD. Because the TiN and SiN layers are very thin, these layers may not be distinguishable from one another, and therefore they are referred to as a single TiSiN layer.

[0037] An exit work layer 76 is fabricated above the adhesive layer 74. The exit work layer 76 determines the exit function of a gate and comprises at least one layer or multiple layers made of different materials. The material for the exit work layer 76 is selected depending on whether the FinFET is an n- or p-FET. For example, if the FinFET is an n-FinFET, the exit work layer 76 can consist of TiC, TaC, TiAl, TiAlC, Ti, Al, Sc, Y, Er, La, Hf, alloys thereof, and / or multilayers thereof. If the FinFET is a p-FinFET, the exit work layer 76 can consist of TiN, TaN, TiAlN, TiSiN, WCN, MOCN, Pt, Pd, Ni, Au, alloys thereof, and / or multilayers thereof.

[0038] In some embodiments of the present disclosure, a capping layer 78 is produced above the exit working layer 76. In some embodiments, the capping layer 78 can be made of TiN, but other materials, such as TaN, can also be used. In some embodiments, the capping layer 78 is produced by ALD, CVD, or the like.

[0039] A filler metal region 80 is also produced above the capping layer 78. In some embodiments, the filler metal region 80 is produced from tungsten, cobalt, aluminum, or the like, or alloys thereof, which can be deposited by CVD, plating, or the like. In some embodiments, WF6, WCl5, WCl6, SiH4, H2, or the like, or combinations thereof, can be used as process gases for depositing tungsten. After the production of the filler metal region 80, a planarization process can be carried out to remove excess portions of the deposited layers, which comprise the dielectric high-k layer 70, the stacked layers 74, 76, and 78, and the filler metal region 80. The remaining portions of these layers are the gate stacks 84, which are Fig. 10 are shown.

[0040] In Fig. In 11A, the gate stacks 84 are recessed to create trenches (spaces occupied by hard masks 86). The etching process can be a wet etching process, a dry etching process, or a combination thereof. The hard masks 86 are manufactured to fill the trenches. The corresponding step is specified as step 222 in process flow 200, which is described in Fig. 14 is shown. Fig. 11A and Fig. Figure 11B shows a sectional view or a perspective view, where Fig. 11A a reference cross-section 11A - 11A of Fig. Figure 11B shows that in some embodiments of the present disclosure, the fabrication of the hard masks 86 comprises a deposition process for depositing a dielectric protective material and a planarization process for removing excess dielectric material over the gate spacers 46 and the ILD 64. The hard masks 86 can be made, for example, from silicon nitride, silicon oxide nitride, or silicon carbonitride, or from other similar dielectric materials.

[0041] Fig. Figure 12 shows the production of lower source / drain contact pins 88 and source / drain silicide areas 90. The corresponding step is indicated as step 224 in process flow 200, which is described in Fig. Figure 14 shows that in some embodiments of the present disclosure, the manufacturing process comprises the following: etching the ILD 64 and the CESL 62 to create source / drain contact openings; depositing a metal layer (such as a titanium layer, a cobalt layer, or the like) such that it extends into the source / drain contact openings; depositing a barrier layer (such as a titanium nitride layer); and performing an annealing process such that a lower portion of the metal layer reacts with the source / drain regions 60 to create silicide regions 90. The barrier layer and the remaining sidewall portions of the metal layer may be removed or retained. A further barrier layer, such as a titanium nitride layer, may also be deposited. The remaining source / drain contact openings may be filled with a metallic material, such as cobalt, tungsten, other suitable metals, or alloys thereof.Then a planarization process, such as a CMP process or a mechanical grinding process, is carried out to remove excess material and bring the top of the contact pins 88 to the same level as the top of the ILD 64.

[0042] The Fig. 13A and Fig. Figure 13B shows the fabrication of an etch stop layer (ESL) 92 and a dielectric layer 94 (which can also be an ILD) over the ESL 92. The corresponding step is indicated as step 226 in the process flow 200, which is described in Fig. Figure 14 shows that the ESL 92 can be made of or comprise silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, aluminum oxide, aluminum nitride, or the like, or multilayers thereof. The dielectric layer 94 can be made of or comprise silicon dioxide, a dielectric low-k material, silicon oxide nitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOC, spin-on glass, spin-on polymer, or the like. The ESL 92 and the dielectric layer 94 can be deposited by spin coating, CVD, ALD, LPCVD, PECVD, or the like.

[0043] Then gate contact pins 96 and upper source / drain contact pins 98 are manufactured. The corresponding step is specified as step 228 in process flow 200, which is described in Fig.Figure 14 shows that the fabrication process may include: etching the dielectric layer 94 and the ESL 92 to create openings until the gate electrodes 82 and the source / drain contact pins 88 are exposed; filling the openings with one or more conductive layers; and performing a planarization process to remove excess portions of the conductive layers. This results in a FinFET 102.

[0044] In some embodiments, the distance S1 on the underside of the projecting fins 36 is reduced, for example, to approximately 6 nm to approximately 12 nm. As explained above, the reduction of the distance S1 is achieved by creating deeper trenches. However, the deeper trenches can lead to an increase in leakage currents between adjacent source / drain regions. In some embodiments of the present disclosure, the semiconductor regions 56 are designed to have no or only low p / n doping in order to reduce the leakage currents. The following explains how the semiconductor regions 56 can reduce the leakage current. The discussion uses n-FinFETs as an example. It is understood that the discussion also applies to p-FinFETs.

[0045] The source / drain regions 60 of the n-FinFETs are n-type, and the well region 22 of the n-FinFETs is p-type. Through unintentional doping, intentional doping, or intentional counter-doping, the semiconductor regions 56 can be n- or p-type. The semiconductor regions 56 can also be intrinsic, without being p- or n-doped. The n-type dopant in the source / drain regions 60 and the p-type dopant in the well region 22 can diffuse into the semiconductor regions 56. Thus, if the semiconductor regions 56 are intrinsic or n-type during epitaxy, their portions closer to the respective source / drain regions 60 above them are n-type, and their portions closer to the well region 22 are p-type. Depletion zones form in the areas close to the interfaces between the n-conducting parts and the p-conducting parts.When the semiconductor regions 56 are counter-doped with p-type materials, depletion regions are formed at the interfaces between n-type source / drain regions 60 and p-type semiconductor regions 56.

[0046] Due to the low concentrations of dopants in the semiconductor regions 56, the depletion regions are wider than in conventional FinFETs, in which no semiconductor region 56 is created, and the source / drain regions 60 are in contact with the well region 22. This reduces leakage currents.

[0047] The embodiments of the present disclosure have several advantages. By creating trenches (used to generate source regions) deeper into the semiconductor strips, the convex undersides of the openings extend to deeper positions, and the spacing (the distance from the source / drain region to the corresponding channel regions) is reduced. However, creating deeper trenches can lead to an increase in leakage currents. According to some embodiments of the present disclosure, the lower parts of the trenches are filled with semiconductor regions that are either undoped or doped (intentionally and / or intentionally) such that they have a low doping concentration. This increases the widths of the resulting depletion regions and reduces the undesired increase in leakage current.

[0048] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims.

Claims

[1] Procedure with the following steps: Forming (206) a semiconductor fin (36) that protrudes higher than an upper surface (24TS) of an insulation region (24), wherein the semiconductor fin (36) overlaps a semiconductor strip (26) and the semiconductor strip (26) contacts the insulation region (24); Forming (208) a gate stack (38) on a side wall and an upper surface of a first part of the semiconductor fin (36); Etching (210) of the semiconductor fin (36) and the semiconductor strip (26) to form a trench (50), wherein the trench (50) has an upper part in the semiconductor fin (36) and a lower part in the semiconductor strip (26); Growing (212) a semiconductor region (56) in the lower part of the trench (50), wherein the semiconductor region (56) is grown to have a concave top surface, wherein process gases used for growing the semiconductor region (56) are free of n-doped and p-doped gases; and Growth (214) of a source / drain region (60) in the upper part of the trench (50) on the semiconductor region (56), wherein the source / drain region (60) contains a p-doped or an n-doped wherein the top of the semiconductor area (56) is lower than a lower surface (24TS) of the semiconductor fin (36). [2] Method according to claim 1, wherein the semiconductor area (56) is grown using a bottom-up deposition process. [3] Method according to claim 2, wherein the semiconductor area (56) is grown on a bottom surface (50BOT) of the trench (50), but not on side wall surfaces of the trench (50). [4] Method according to any of the preceding claims, wherein the lower part of the trench (50) has a depth of about 2 nm to about 4 nm. [5] Method according to any of the preceding claims, wherein the semiconductor region (56) is doped such that it has a first conductivity type which is opposite to a second conductivity type of the source / drain region (60). [6] Method according to any one of claims 1 to 4, wherein the semiconductor region (56) is doped to have the same conductivity type as the source / drain region (60). [7] Method according to any of the preceding claims, wherein the semiconductor fin (36) has a first side wall (50SW) facing the upper part of the trench (50), and the semiconductor strip (26) has a second side wall (50SW') facing the lower part of the trench (50), wherein the first side wall (50SW) is vertical and straight and the second side wall (50SW') is curved. [8] Method according to claim 7, wherein the first side wall (50SW) and the second side wall (50SW') meet at a position that is at the same level as or lower than a bottom surface (24TS) of the semiconductor fin (36). [9] Method according to any of the preceding claims, wherein the semiconductor region (56) has a doping concentration of less than 1E18 / cm² 3 , preferably smaller than 1E17 / cm 3 exhibits. [10] Method according to any of the preceding claims, wherein the doping concentration of the semiconductor region (56) is at least one order of magnitude, preferably at least two orders of magnitude, lower than the doping concentration in the source / drain region (60). [11] Method according to one of the preceding claims, wherein during the growth (212) of the semiconductor area (56) the semiconductor area (56) remains exposed towards the upper part of the trench (50). [12] Procedure encompassing: Forming (206) a semiconductor fin (36) that protrudes higher than an upper surface (24TS) of an isolation region (24); Forming (208) a gate stack (38) on the semiconductor fin (36); Etching (210) of the semiconductor fin (36) to form a trench (50), the trench (50) extending further into a semiconductor strip (26) located below the semiconductor fin (36) and extending into a trough area (22); Growing (212) a semiconductor region (56) in a lower part of the trench (50), wherein the semiconductor region (56) is grown such that it has a concave top surface, the top surface of the semiconductor region (56) being lower than a lower surface (24TS) of the semiconductor fin (36), and a first doping concentration of the semiconductor region (56) being lower than a second doping concentration of the trough region (22), wherein the first doping concentration and the second doping concentration are doping concentrations of an n dopant and a p dopant, respectively; and Growth (214) of a source / drain region (60) over the semiconductor region (56). [13] Method according to claim 12, wherein the semiconductor region (56) is an intrinsic region. [14] Method according to claim 12 or 13, wherein the growth (212) of the semiconductor region (56) is carried out using process gases that are free of n-doped and p-doped gases. [15] Method according to claim 12, wherein the growth (212) of the semiconductor region (56) is carried out using process gases containing an n-doped gas or a p-doped gas. [16] Method according to claim 15, wherein the semiconductor region (56) and the source / drain region (60) have opposite conductivity types. [17] Method according to any one of claims 12 to 16, further comprising: Creating a source / drain expansion region (51) in the semiconductor fin (36), wherein the first doping concentration remains lower than a third doping concentration in the source / drain expansion region (51). [18] Procedure encompassing: Forming (202) a trough area (22) in a semiconductor substrate (20); Forming (204) isolation areas (24) extending into the tub area (22); Recess (206) of the insulation areas (24), wherein a part of the basin area (22) protrudes higher than the insulation areas (24) to form a semiconductor fin (36), wherein a part of the basin area (22) is arranged between the insulation areas (24) as a semiconductor strip (26); Growing (212) a semiconductor region (56) in the semiconductor strip (26), wherein the semiconductor region (56) is grown to have a concave top surface, wherein process gases for growing the semiconductor region (56) are free of p-doped and n-dopeds, and wherein the top surface of the semiconductor region (56) is lower than a lower surface (24TS) of the semiconductor fin (36); and Generating (214) a source / drain region (60) above the semiconductor region (56), wherein the semiconductor region (56) has a first doping concentration that is lower than a second doping concentration of the well region (22) and than a third doping concentration of the source / drain region (60). [19] Method according to claim 18, wherein the semiconductor region (56) is doped with a p-residue or an n-residue that has remained in a process chamber which is used to grow (212) the semiconductor region (56) with the first doping concentration. [20] Method according to one of the preceding claims 18 or 19, wherein the semiconductor region (56) has a doping concentration of less than 1E18 / cm² 3 , preferably smaller than 1E17 / cm 3 exhibits .

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