Method for producing a power semiconductor device and power semiconductor device

Abstract

A method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device (1), the method comprising: providing a semiconductor body (10); implanting a dopant to form a doped region (101) in the semiconductor body (10); providing, above the doped region (101), a mask layer (210), wherein the mask layer (210) has a first portion (211) and a second portion (212), wherein the first portion (211) has a first thickness along a vertical direction (Z); the second portion (212) has a second thickness along the vertical direction (Z), wherein the second thickness is different from the first thickness; subjecting the doped region (101) and both mask portions (211, 212) to a laser thermal annealing processing step (200), hereinafter LTA processing step called;- the first mask layer section (211) has a first reflectance that is different from a second reflectance of the second mask layer section (212); and - the first reflectance is above 50% and the second reflectance is below 35%.

Description

TECHNICAL FIELD

[0001] The present document relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, the present document relates to embodiments of a power semiconductor device with a specific dopant profile in a doped semiconductor region and corresponding embodiments of a method for manufacturing a power semiconductor device. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor switches. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including, but not limited to, switches in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.

[0004] Furthermore, in the case of a controllable power semiconductor device, e.g., a transistor, the load current path can be controlled by means of an insulated electrode, commonly referred to as a gate or control electrode. For example, upon receiving a corresponding control signal, e.g., from a driver unit, the control electrode can place the power semiconductor device into a forward conducting state and a blocking state. In some cases, the gate electrode can be contained in a trench of the power semiconductor switch, wherein the trench can have a stripe configuration or a needle configuration.

[0005] To provide the specific properties of the power semiconductor device, the semiconductor body is configured with doped regions, such as a front side, a source region, a body region, a body contact subregion, or emitter regions on a back side of the semiconductor body. As relevant feature sizes become ever smaller, the dimensions of such doped regions must decrease accordingly.

[0006] Accordingly, it is desirable to provide local doped semiconductor regions with a clearly defined size and a specific dopant concentration profile.

[0007] The documents US 2008 / 0 044 988 A1, US 2015 / 0 255 602 A1, US 6 812 106 B1 and US 5 401 666 A provide further information on the technical background of the present disclosure. SUMMARY

[0008] According to one embodiment, a method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device comprises: providing a semiconductor body; implanting a dopant to form a doped region in the semiconductor body; providing, over the doped region, a mask layer, wherein the mask layer has a first portion and a second portion, wherein the first portion has a first thickness along a vertical direction and wherein the second portion has a second thickness along the vertical direction, wherein the second thickness is different from the first thickness; and subjecting the doped region and both mask portions to an LTA (laser thermal annealing) processing step.

[0009] According to one embodiment, a method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device comprises: providing a semiconductor body; providing, on the semiconductor body, a mask layer, wherein the mask layer has a first portion and a second portion, wherein the first portion has a first thickness along a vertical direction and wherein the second portion has a second thickness along the vertical direction, wherein the second thickness is different from the first thickness; implanting a dopant to form a doped region in the semiconductor body; and subjecting the doped region and both mask portions to an LTA processing step (LTA - laser thermal annealing).

[0010] In the above embodiments, it is provided that the first mask layer section has a first reflectance which is different from a second reflectance of the second mask layer section, wherein the first reflectance is above 50% and the second reflectance is below 35%.

[0011] According to one embodiment, a power semiconductor device comprises a semiconductor body having a surface and a first load terminal on the surface, wherein the semiconductor body includes an electrically activated region in a doped region, wherein the electrically activated region forms part of the surface and has a laterally varying dopant concentration profile, which in a change region has a dopant concentration gradient along a first lateral direction of at least 5*10 21 cm -3 / 50 nm.

[0012] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The parts in the figures are not necessarily to scale, but emphasis is placed on illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: Fig. 1 schematically and exemplarily, based on a portion of a vertical cross-section of a power semiconductor device, a method according to one or more embodiments; Fig. 2 schematically and exemplarily shows a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 3 schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor device according to some embodiments; and Fig. 4 schematically and exemplarily shows a portion of a vertical cross-section of a power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0014] The term "horizontal" as used in this document is intended to describe an orientation substantially parallel to a central horizontal surface of a semiconductor substrate or semiconductor structure. This can be, for example, the surface of a semiconductor wafer, a die, or a chip. For example, both the first lateral direction X and the second lateral direction Y mentioned here can be horizontal directions, and the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0015] The term "vertical" as used herein is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the vertical direction Z mentioned herein may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0016] In this document, n-doped is referred to as the "first conductivity type," while p-doped is referred to as the "second conductivity type." Alternatively, reversed doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0017] For the purposes of this specification, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe that a low-resistance electrical connection or a low-resistance current path exists between two regions, sections, zones, areas, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and an area or part of a semiconductor device. Furthermore, for the purposes of this specification, the term "in contact" is intended to describe that a direct physical connection exists between two elements of the respective semiconductor device; e.g., a junction between two elements in contact with each other does not comprise any further intermediate element or the like.

[0018] Furthermore, unless otherwise stated, the term "electrical isolation" is used in the context of this document in its generally accepted sense and is intended to describe that two or more components are positioned separately from one another and that there is no ohmic connection connecting these components. However, components that are electrically isolated from one another can nevertheless be coupled to one another, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled. To give an example, two electrodes of a capacitor can be electrically isolated from one another and simultaneously mechanically and capacitively coupled to one another, for example, by means of insulation, e.g., a dielectric.

[0019] Specific embodiments described in this document relate to a power semiconductor device, such as an IGBT, an RC-IGBT, a MOSFET, a diode, or derivatives thereof, e.g., a power semiconductor device for use within a power converter or a power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be supplied to a load or provided by a power source, respectively. For example, the power semiconductor device may comprise a plurality of power semiconductor cells, such as monolithically integrated diode cells, derivatives of a monolithically integrated diode cell, monolithically integrated MOSFET or IGBT cells, and / or derivatives thereof. Such diode / transistor cells may be integrated in a power semiconductor module.Several such cells can form a cell array arranged in an active region of the power semiconductor device.

[0020] The term "power semiconductor device" as used in this document is intended to describe a single-chip power semiconductor device with capabilities for blocking a high voltage and / or conducting a high current. In other words, embodiments of the power semiconductor device described herein are single-chip power semiconductor devices configured for high current, typically in the ampere range, for example, up to several amperes or several tens or hundreds of amperes, and / or high voltages, typically 200 V and above, for example, up to at least over 400 V or even more, for example, up to at least 3 kV or even up to 10 kV or more.

[0021] For example, the power semiconductor device described below may be a single-chip power semiconductor device configured to be used as a power component in a low, medium, and / or high voltage application. Multiple single-chip power semiconductor devices may be integrated into a module to form a power semiconductor device module, for example, for installation and use in a low, medium, and / or high voltage application, such as a large household appliance, a general-purpose drive, an electric drive train, a servo drive, a traction device, (higher) power transmission devices, etc.

[0022] For example, the term “power semiconductor device” as used in this document does not refer to a logic semiconductor device used, for example, for storing data, computing data, and / or other types of semiconductor-based data processing.

[0023] Each of the Fig. 1 to 4 schematically and exemplarily shows a section of a vertical cross section of embodiments of a power semiconductor device 1. Based on the illustration in Fig. 1, embodiments of a method for producing such power semiconductor devices 1 will first be described:

[0024] In one embodiment, a method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device 1 is presented. The method comprises the step of providing a semiconductor body 10 and the step of implanting a dopant to form a doped region 101 in the semiconductor body 10. Next, the step of providing, over the doped region 101, a mask layer 210 is performed, wherein the mask layer 210 has a first portion 211 and a second portion 212. The first portion 211 has a first thickness along the vertical direction Z, and the second portion 212 has a second thickness along the vertical direction Z, wherein the second thickness is different from the first thickness.Then the step of subjecting the doped region 101 and both mask sections 211 and 212 to an LTA processing step (LTA - laser thermal annealing).

[0025] With further reference to Fig. 1, in another embodiment, the order of the processing steps may be different. For example, after providing the semiconductor body 10 (and before implantation), the mask layer 210 is provided. Then, the step of implanting the dopant to form the doped region 101 in the semiconductor body 10 is performed. Thereafter, the step of applying the LTA processing step to the doped region 101 and both mask portions 211 and 212 is performed. Then, the mask layer 210 is already used during the implantation, resulting in a self-aligned process stage.

[0026] In another embodiment, the embodiments described in the two previous sections are combined. For example, after a first implantation processing step, the mask layer 210 is provided. Then, a second implantation processing step is performed. After that, the LTA processing step can be performed.

[0027] Fig. 1 illustrates that the processing steps described above are directed toward a front side 110 of the semiconductor body 10. However, the processing steps described above may additionally or alternatively be directed toward a back side 120 of the semiconductor body 10, which will be described further below.

[0028] The mask layer 210 may comprise a third portion 213 and a fourth portion 214, wherein the third portion 213 and the fourth portion 214 may have different thicknesses or no different thicknesses along the vertical direction Z. In the schematic representation of Fig. 1, the third portion 213 is illustrated as having the same thickness as the second portion 212, and the fourth portion 214 is illustrated as having the same thickness as the first portion 211. At the same time, the vertical extent of an electrically activated region 102 (see description below) beneath the third and fourth portions 213, 214 may be different from the vertical extent of the electrically activated region 102 beneath the first and second portions 211, 212, e.g., due to a difference in the reflectance of the first and / or second portions 211, 212 and the reflectance of the third and / or fourth portions 213, 214. Such differences in reflectance may be achieved based on the use of a first material for forming the portions 211, 212 and a different material for forming the portions 213, 214.Or the same material may be used, and the third and / or fourth portion 213, 214 may be provided with a respective thickness that is different from the thickness of the first and / or second portion 211, 212.

[0029] In one embodiment, each portion 211 to 214 of the mask layer 214 is made of the same material (an example of which is described below).

[0030] The second mask portion 212 of the mask layer 210 may adjoin the first portion 211. Likewise, the third mask portion 213 of the mask layer 210 may adjoin the fourth portion 214. The first and second mask portions 211, 212 of the mask layer 210 may form a continuous first part (i.e., a monolithic first part) of the mask layer 210, and the third and fourth mask portions 213, 214 of the mask layer 210 may form a continuous second part (i.e., a monolithic second part) of the mask layer 210. The first part of the mask layer 210 may be separated from the second part of the mask layer 210, so that a mask opening is produced, as in Fig. 1 is shown.

[0031] The mask layer 210, e.g., the first and second mask portions 211, 212, and if present, also the third and fourth portions 213, 214, may be made of a mask material including at least one of silicon oxide, SiO2, silicon nitride, Si3N4, and amorphous silicon.

[0032] According to the invention, the first mask layer section 211 has a first reflectance that is different from a second reflectance of the second mask layer section 212. Furthermore, the third mask layer section 213 can have a third reflectance that is different from a fourth reflectance of the fourth mask layer section 214. According to the invention, the first reflectance is above 50%, and the second reflectance is below 35%. Both the third and fourth reflectances can also be above 50%. For example, the first and fourth mask sections 211, 214 can be configured identically with regard to reflectance and / or thickness, and the second and third mask sections 212, 213 can be configured identically with regard to reflectance and / or thickness. Depending on the specific configuration of the doped semiconductor region 101, another approach can also be used, for examplethe third and fourth mask sections 213 and 214 are configured differently compared to the first and second mask sections 211 and 212.

[0033] The configuration of the mask layer 210 and the LTA processing step 200 can be adapted with respect to one another. For example, the first reflectance and the second reflectance are present at a specific wavelength of a laser light emitted during the LTA processing step 200. Furthermore, the third reflectance and the fourth reflectance can be present at a specific wavelength of a laser light emitted during the LTA processing step 200. Furthermore, the first thickness and the second thickness can be selected depending on the wavelength of the laser light emitted during the LTA processing step 200. Furthermore, the third thickness and the fourth thickness can be selected depending on the wavelength of the laser light emitted during the LTA processing step 200.

[0034] In one embodiment, the laser light emitted during LTA processing step 200 has a wavelength in the range of 150 nm to 1100 nm. Various lasers may be used, such as an arF excimer laser operating at a wavelength of 193 nm, or an XeF excimer laser operating at a wavelength of 308 nm, or an Nd:YAG laser operating at a wavelength of 1064 nm, for example.

[0035] The LTA processing step 200 may consist of a single laser shot, e.g., a single laser shot with a duration in the range of 1 ns to 1000 ns, e.g., in the range of 20 ns to 200 ns.

[0036] In one embodiment, the first mask layer portion 211 acts as a laser light reflector (not shown), and the second mask layer portion 212 acts as a laser light absorber (e.g., as an anti-reflection layer). Based on having a reflectance of over 50%, the first mask layer portion 211 acts, for example, as a laser light reflector. Based on having a reflectance of under 35%, the first mask layer portion 211 acts, for example, as a laser light absorber. In another embodiment, as in Fig. 1, both mask layer sections 211 and 212 act as laser light absorbers.

[0037] In one embodiment, the laser energy coupled into the doped region 101 may vary such that the doped region 102 either has a short melting phase or remains in a solid state configuration.

[0038] The corresponding laser energy density threshold for substrate melting is primarily determined by the combination of the substrate material and configuration, crystal damage extent, properties of the surface layers, laser processing conditions (e.g., laser wavelength, pulse duration, repetition frequency), and external wafer heating. Depending on the time over which the doped region 102 exceeds a threshold temperature required for dopant activation, the ratio of electrically activated concentration vs. implanted dopants concentration can be adjusted to achieve, for example, at least 5%, at least 10%, or at least 30% (i.e., at least 5% or at least 30% of the implanted dopants can be electrically activated).

[0039] Depending on the configuration of the respective mask section, the laser radiation may be melting or non-melting. Furthermore, since the mask layer 210 may act locally as an anti-reflection layer, i.e., an absorber layer, the duration and / or energy of the LTA processing step 200 may be reduced. Based on the configuration of the LTA processing step 200 and based on the configuration of the mask layer 210, a portion of the doped region 101 may thus be electrically activated, while a directly adjacent portion is not electrically activated or is at least electrically activated to a lesser extent.

[0040] The LTA processing step 200 may be performed to at least partially electrically activate the implanted dopant, thereby forming an electrically activated region 102 in the doped region 101. As shown in Fig. 1, the different configuration of the mask sections 211 to 214 is accordingly observed in the configuration of the electrically activated region 102: the second mask section 212 has the lowest reflectance, the first mask section 211 the second lowest reflectance; these two sections 211 and 212 act more like anti-reflective layers, which accordingly result in the longest vertical extensions of the electrically activated region 102 below these sections 211 and 212. In particular, due to the configuration of the first and second mask sections 211 and 212, the vertical extension of the electrically activated region 102 below these sections 211 and 212 is larger compared to the part of the electrically activated region 102 below the mask opening.Further along the first lateral direction X, the vertical extension of the electrically activated region 102 below the mask sections 213 and 214 is then even smaller compared to the part of the electrically activated region 102 below the mask opening, since the mask sections 213 and 214 can have a comparatively high degree of reflection and act, for example, as a Bragg reflector layer.

[0041] Based on the preceding description of an embodiment, it becomes clear that, based on the laterally varying configuration of the mask layer 210, a correspondingly laterally varying dopant concentration profile can be provided in the electrically activated region 102 beneath the mask layer 210. For example, in a change region 1029, which corresponds to a vertical projection of the transition between the first mask portion 211 and the second mask portion 212, the electrically activated region 102 has a dopant concentration gradient along a first lateral direction X of at least 5*10 21 cm -3 / 50 nm. This dopant concentration gradient refers to the electrically activated dopants in the electrically activated region 102.

[0042] According to embodiments described herein, it is therefore possible to create a shallow electrically activated region 102 in the immediate vicinity of a surface of the semiconductor body 10 on the front side 110 and / or the back side 120, which region has a laterally strongly varying dopant concentration profile.

[0043] The implanted dopant includes, for example, one of boron fluorine (BF2), boron (B), gallium (Ga), aluminum (Al), nitrogen (N), arsenic (As), phosphorus (P), and antimony (Sb). The dopant can be implanted at an energy range of 10 keV to 1000 keV, or even at lower or higher energies depending on the specific configuration. For example, a maximum concentration of the implanted dopant is in the range of 10 nm to 1000 nm.

[0044] The method may further comprise the step of implanting a non-dopant, e.g., a heavy metal (e.g., platinum (Pt), palladium (Pd), gold (Au)), into the doped region 101. In this embodiment, the region created by subjecting the doped region 101 to the LTA processing step 200 may act as a recombination zone in the semiconductor body 10.

[0045] Forming the mask layer 210 may include depositing the mask material, e.g., based on plasma-assisted deposition; performing a lithographic processing step; and performing an etching processing step. This may result in the formation of the variously configured mask portions 211 to 214. Forming the mask layer 210 may be performed before or after implanting the dopant(s) or the dopants, or after forming the doped region 101. In the latter case, the mask layer 210 may also be used as a mask for forming the doped region 101, resulting, for example, in a masked implantation process.

[0046] The embodiments described above can be used to form various power semiconductor devices.

[0047] With reference to Fig. 2, a power semiconductor device 1 comprises a semiconductor body 10 and, coupled thereto, a first load terminal 11 and a second load terminal (in Fig. 2 not shown). The power semiconductor device 1 is configured to carry a load current between the first load terminal 11 and the second load terminal. The first load terminal 11 can be arranged on a first side 110 of the semiconductor body 10, wherein the first side 110 can be a front side. The second load terminal can also be arranged on a first side 110 of the semiconductor body 10 or alternatively, as in Fig. 3 and Fig. 4, may be arranged on a second side 120 of the semiconductor body 10, wherein the second side 120 may be a rear side.

[0048] The semiconductor body 10 may have any configuration, such as a diode configuration, a MOSFET configuration, an IGBT configuration, or a derivative thereof. Depending on the configuration, the semiconductor body 10 may comprise a plurality of doped regions. These configurations are largely known to those skilled in the art and are therefore not described in more detail here.

[0049] Fig. 2, for example, illustrates a trench-based MOS structure on the front side. Such a structure may, for example, belong to an IGBT, an RC-IGBT, or a MOSFET, or the like. A contact plug 111 extends from the first load terminal 11, e.g., a source terminal or an emitter terminal, along the vertical direction Z to electrically contact a source trench electrode 161 as well as a source region 103 and a body contact sub-region 10022 in a mesa 18. The mesa 18 is laterally delimited by a control trench 14, which receives a control trench electrode 141, and a source trench 16, which receives the source trench electrode 161. Both trench electrodes 141 and 161 are separated from the semiconductor body 10 by respective trench insulators 142, 162. An insulating layer 191 separates the trench electrodes 141 and 161 from the first load terminal 11.A body region 102 is of the second conductivity type and isolates the source region 103 of the first conductivity type from a portion of the drift region 100 of the first conductivity type. The control electrode 141 is configured to generate an inversion channel in a channel region 190 of the body region 102 when subjected to a corresponding control signal (e.g., a gate-source voltage).

[0050] A further mesa 19 may be formed between the source trench and another trench 15, which accommodates a further trench electrode 151 separated from the semiconductor body 10 by the trench insulators 152. For example, no source region is provided in the further mesa 14, but rather a region 104 of the second conductivity type, which is electrically connected to the first load terminal 11 via a contact 112.

[0051] To ensure a good electrical connection between the body region 102 and the contact plug 111, the body contact sub-region 1022 may be formed in the body region 102. The body contact sub-region 1022 may have a much higher dopant concentration compared to the rest of the body region 102. At the same time, it may be ensured that the body contact sub-region 1022 is sufficiently offset from the channel region 190, namely based on a correspondingly configured dopant concentration profile that varies laterally along the first lateral direction X, such as in the right part of Fig. 2 is shown schematically. The diagram shown therein represents the dopant concentration in the first lateral direction X along line AA'. For example, the maximum dopant concentration of the part of the body region 102 forming the channel region 190 amounts to at least 1*10 17 cm -3 up to 1*10 18 cm -3. The dopant concentration of the part of the body region 102 forming the body contact sub-region 1022 may be more than 2*10 18 cm -3 amount to.

[0052] Thus, the body region 102 may be configured with the above-described modification region 1029. That is, the body region 102 may be formed according to an embodiment of the processing methods described above; accordingly, the body region 102 may correspond to the above-described electrically activated region 102. Furthermore, the body region 102 is part of a doped region 101, and the doped region 101 forms a part of the surface at the front side 110 of the semiconductor body 10, where, for example, the contact plug 111 contacts the body contact sub-region 1022.

[0053] The dopant of the doped region 101 can include one of boron fluorine, boron, gallium, aluminum, nitrogen, arsenic, phosphorus, and antimony. Such a material can thus also be observed in the body region 102 (and in the body contact subregion 1022).

[0054] Based on the foregoing description, it can be seen that the electrically activated region 102 with such a change region 1029 can be provided in various power semiconductor devices.

[0055] When considering, for example, Fig. 3 shows two examples (1) and (2) for a diode. The first example (1) shows a merged PIN Schottky (MPS) configuration of a diode. There, a Schottky contact is formed at a junction between the first load terminal 11 and the drift region 100. Two electrically activated regions 102 are provided adjacent to the junction, each of which has a respective change region 1029. There, the electrically activated regions 102 can form body regions of the second conductivity type. The drift region 100 of the first conductivity type extends along the vertical direction Z to the adjacent region 108, e.g., an emitter region of the first conductivity type. The region 108 is electrically connected to the second load terminal 12 at the rear side 120 and has a higher dopant concentration than the drift region 100. The first load terminal 11 may be an anode terminal, and the second load terminal 12 may be a cathode terminal.

[0056] The Fig. The second example (2) for a diode shown in Figure 3 shows a so-called IDEE configuration (Inverse Injection Dependency of the Emitter Efficiency). There, regions 107 of the second conductivity type are formed at a distance from one another on the rear side 120 above the region 108 (e.g., an emitter region of the first conductivity type) so that part of the region 100' can border the field stop region 108. The region 100' is of the same conductivity type as the drift region 100, but has a higher dopant concentration. On the front side 120, the electrically activated regions 102 can form body regions of the second conductivity type, which are electrically connected to the first load terminal 11. Highly doped subregions 103 of the first conductivity type are also electrically connected to the first load terminal 11 and, as shown, separate the electrically activated regions 102 from one another.

[0057] As mentioned above, the electrically activated region 102 may be formed not only on the front side 110, but additionally or alternatively on the back side 120. Some examples of this will now be described with reference to Fig. 4 described:

[0058] Fig. 4 shows three examples (1) to (3) of a configuration of a lower part of a semiconductor body 10 belonging, for example, to an IGBT or RC-IGBT.

[0059] For example, with reference to all three examples, the drift region 100 of the first conductivity type extends along the vertical direction Z until it borders a field stop region 108 of the first conductivity type. The field stop region 108 has a higher dopant concentration than the drift region 100 and borders an emitter structure electrically connected to the second load terminal 12 (e.g., a collector terminal). According to the three examples (1) to (3), the electrically activated region 102 forms the backside emitter structure of an IGBT / RC-IGBT. The modification region 1029, for example, separates the backside emitter structure into a locally enhanced backside emitter (LEBE) part 1022 and a "normal" emitter part 1028. Such a separation can, for example,Based on appropriately configuring the mask layer 210, the first and second mask portions 211 and 212 may be provided once (Example (1)) or multiple times (Examples (2) and (3)). In view of the above, the mask layer 210 may also be provided with a third portion 213 different from the first and second mask portions 211 and 212 to form further emitter portions 1023 having a further different dopant concentration than the LEBE portions 1022 and normal portions 1028.

[0060] According to the embodiments described above, it is possible to provide a doped region with a smaller vertical extent and minimal lateral diffusion and, furthermore, to provide, adjacent thereto, another doped region with a small but different vertical extent and minimal lateral diffusion and a different concentration of electrically activated dopants. Such concepts can be applied in particular to semiconductor regions that are electrically connected to a terminal of the power semiconductor device. For example, it can be ensured that lateral diffusion of (e.g., implanted) dopants of a doped region into critical neighboring regions, for example, a channel region, is avoided. The generated region with the laterally varying dopant concentration profile can also be configured to form a recombination zone of the power semiconductor device.

[0061] Embodiments relating to a power semiconductor device and corresponding manufacturing methods have been explained above. For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body 10 and its regions / zones, e.g., regions, etc., may be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used. For example, the values ​​of the dopant concentrations and dopants described above relate to embodiments in which Si is selected as the material of the semiconductor body 10.

[0062] However, it should be appreciated that the semiconductor body 10 and its regions / zones may be made of any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include elemental semiconductor materials, such as silicon (Si) or germanium (Ge), Group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), and aluminum indium nitride (AlInN). For power semiconductor switch applications, Si, SiC, GaAs, and GaN materials are currently primarily used.

[0063] For example, in embodiments where SiC is selected as the material of the semiconductor body 10, the dopant concentrations and dopants described above may need to be adjusted. For SiC, compared to the doses and concentrations described above, the dopant concentrations are increased, for example, by a factor of ten or a factor of 100, and the dopant doses are increased by a factor of between three and ten.

[0064] Spatial terms such as "below," "beneath," "lower," "above," "upper," and the like are used for convenience of description to describe the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the respective device, in addition to orientations different from those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0065] As used herein, the terms “have,” “contain,” “include,” “comprise,” “have,” and the like are open-ended terms and indicate the presence of the specified elements or features, but do not preclude additional elements or features.

Claims

[1] A method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device (1), the method comprising: Providing a semiconductor body (10); implanting a dopant to form a doped region (101) in the semiconductor body (10); Providing, over the doped region (101), a mask layer (210), wherein the mask layer (210) has a first portion (211) and a second portion (212), wherein - the first portion (211) has a first thickness along a vertical direction (Z); - the second portion (212) has a second thickness along the vertical direction (Z), the second thickness being different from the first thickness; Subjecting the doped region (101) and both mask sections (211, 212) to a laser thermal annealing processing step (200), hereinafter referred to as LTA processing step; - the first mask layer section (211) has a first reflectance which is different from a second reflectance of the second mask layer section (212); and - the first reflectance is above 50% and the second reflectance is below 35%. [2] A method for forming a laterally varying dopant concentration profile of an electrically activated dopant in a power semiconductor device (1), the method comprising: Providing a semiconductor body (10); Providing a mask layer (210) on the semiconductor body (10), wherein the mask layer (210) has a first portion (211) and a second portion (212), wherein - the first portion (211) has a first thickness along a vertical direction (Z); and - the second portion (212) has a second thickness along the vertical direction (Z), the second thickness being different from the first thickness; implanting a dopant to form a doped region (101) in the semiconductor body (10); Subjecting the doped region (101) and both mask sections (211, 212) to a laser thermal annealing processing step (200), hereinafter referred to as LTA processing step; - the first mask layer section (211) has a first reflectance which is different from a second reflectance of the second mask layer section (212); and - the first reflectance is above 50% and the second reflectance is below 35%. [3] The method of claim 1, wherein the second mask portion (212) of the mask layer (210) is adjacent to the first portion (211). [4] The method according to any one of the preceding claims, wherein the mask layer (210) is made of a mask material including at least one of silicon oxide, SiO2, silicon nitride, Si3N4 and amorphous silicon. [5] A method according to any one of the preceding claims, wherein the first reflectance and the second reflectance are at a particular wavelength of a laser light emitted during the LTA processing step (200). [6] A method according to any one of the preceding claims, wherein the laser light emitted during the LTA processing step (200) has a wavelength in the range of 150 nm to 1100 nm. [7] A method according to any one of the preceding claims, wherein the first thickness and the second thickness are selected depending on the wavelength of the laser light emitted during the LTA processing step (200). [8] Method according to one of the preceding claims, wherein the first mask layer portion (211) acts as a laser light reflector and the second mask layer portion (212) acts as a laser light absorber, or wherein both the first mask layer portion (211) and the second mask layer portion (212) act as laser light absorbers. [9] The method of any preceding claim, wherein the LTA processing step (200) is performed to at least partially electrically activate the implanted dopant, thereby forming an electrically activated region (102) in the doped region (101). [10] The method according to claim 9, wherein the electrically activated region (102) in a change region (1029) corresponding to a vertical projection of the transition between the first mask portion (211) and the second mask portion (212) has a dopant concentration gradient along a first lateral direction (X) of at least (1*10 20 cm -3 - 1*10 17 cm -3 ) / 50 nm. [11] A method according to any one of the preceding claims, wherein the implanted dopant comprises one of boron-fluorine, boron, gallium, aluminum, nitrogen, arsenic, phosphorus and antimony. [12] Method according to one of the preceding claims, wherein the dopant is implanted with an energy in the range of 10 keV to 1000 keV, and / or wherein a maximum concentration of the implanted dopant is in the range of 10 nm to 1000 nm. [13] The method of any preceding claim, further comprising implanting a non-dopant into the doped region (101). [14] A method according to any one of the preceding claims, wherein forming the mask layer (210) includes: Deposition of the mask material, e.g. based on plasma-assisted deposition; performing a lithographic processing step; and Performing an etching processing step. [15] Power semiconductor device (1), comprising a semiconductor body (10) having a surface (110) and a first load terminal (11) on the surface (110; 120), wherein the semiconductor body (10) includes an electrically activated region (102) in a doped region (101), wherein the electrically activated region (102) forms part of the surface (110; 120) and has a laterally varying dopant concentration profile, which in a change region (1029) has a dopant concentration gradient along a first lateral direction (X) of at least 5*10 21 cm -3 / 50 nm. [16] The power semiconductor device (1) according to claim 17, wherein the dopant of the doped region (101) includes one of boron fluorine, boron, gallium, aluminum, nitrogen, arsenic, phosphorus, and antimony. [17] The power semiconductor device (1) according to claim 15 or 16, wherein the power semiconductor device (1) has one of an IGBT or a MOSFET configuration; the first load terminal (11) is an emitter terminal or a source terminal; the electrically activated region (102) is a body region (102) of p-conductivity type, which isolates a source region (103) of n-conductivity type from a drift region (100) of the power semiconductor device (1); and the dopant concentration gradient along the first lateral direction (X) of at least 5*10 21 cm -3 / 50 nm at a transition between a body contact sub-region (1022) of the body region (102) and a remaining part of the body region (102). [18] The power semiconductor device (1) according to claim 15 or 16, wherein the power semiconductor device (1) has an IGBT configuration; the first load terminal (11) is a collector terminal; the electrically activated region (102) is an emitter region (102) of p-conductivity type and is electrically connected to the collector terminal. [19] The power semiconductor device (1) according to claim 15 or 16, wherein the power semiconductor device (1) has a diode configuration; the first load terminal (11) is an anode terminal; the electrically activated region (102) is a body region (102) of p-conductivity type and is electrically connected to the anode terminal. [20] Power semiconductor device (1) according to one of the preceding claims 15 to 19, wherein the electrically activated region (102) has a total lateral extent of less than 200 nm along the first lateral direction (X).

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